1d52c454aSMarc-André Lureau /* 2d52c454aSMarc-André Lureau * Virtio vhost-user GPU Device 3d52c454aSMarc-André Lureau * 4d52c454aSMarc-André Lureau * Copyright Red Hat, Inc. 2013-2018 5d52c454aSMarc-André Lureau * 6d52c454aSMarc-André Lureau * Authors: 7d52c454aSMarc-André Lureau * Dave Airlie <airlied@redhat.com> 8d52c454aSMarc-André Lureau * Gerd Hoffmann <kraxel@redhat.com> 9d52c454aSMarc-André Lureau * Marc-André Lureau <marcandre.lureau@redhat.com> 10d52c454aSMarc-André Lureau * 11d52c454aSMarc-André Lureau * This work is licensed under the terms of the GNU GPL, version 2 or later. 12d52c454aSMarc-André Lureau * See the COPYING file in the top-level directory. 13d52c454aSMarc-André Lureau */ 14d52c454aSMarc-André Lureau 154bd802b2SMarkus Armbruster #include "qemu/osdep.h" 16d52c454aSMarc-André Lureau #include <virglrenderer.h> 17d52c454aSMarc-André Lureau #include "virgl.h" 18d52c454aSMarc-André Lureau 190c27b9c5SMarc-André Lureau #include <epoxy/gl.h> 200c27b9c5SMarc-André Lureau 21d52c454aSMarc-André Lureau void 22d52c454aSMarc-André Lureau vg_virgl_update_cursor_data(VuGpu *g, uint32_t resource_id, 23d52c454aSMarc-André Lureau gpointer data) 24d52c454aSMarc-André Lureau { 25d52c454aSMarc-André Lureau uint32_t width, height; 26d52c454aSMarc-André Lureau uint32_t *cursor; 27d52c454aSMarc-André Lureau 28d52c454aSMarc-André Lureau cursor = virgl_renderer_get_cursor_data(resource_id, &width, &height); 29d52c454aSMarc-André Lureau g_return_if_fail(cursor != NULL); 30d52c454aSMarc-André Lureau g_return_if_fail(width == 64); 31d52c454aSMarc-André Lureau g_return_if_fail(height == 64); 32d52c454aSMarc-André Lureau 33d52c454aSMarc-André Lureau memcpy(data, cursor, 64 * 64 * sizeof(uint32_t)); 34d52c454aSMarc-André Lureau free(cursor); 35d52c454aSMarc-André Lureau } 36d52c454aSMarc-André Lureau 37d52c454aSMarc-André Lureau static void 38d52c454aSMarc-André Lureau virgl_cmd_context_create(VuGpu *g, 39d52c454aSMarc-André Lureau struct virtio_gpu_ctrl_command *cmd) 40d52c454aSMarc-André Lureau { 41d52c454aSMarc-André Lureau struct virtio_gpu_ctx_create cc; 42d52c454aSMarc-André Lureau 43d52c454aSMarc-André Lureau VUGPU_FILL_CMD(cc); 44d52c454aSMarc-André Lureau 45d52c454aSMarc-André Lureau virgl_renderer_context_create(cc.hdr.ctx_id, cc.nlen, 46d52c454aSMarc-André Lureau cc.debug_name); 47d52c454aSMarc-André Lureau } 48d52c454aSMarc-André Lureau 49d52c454aSMarc-André Lureau static void 50d52c454aSMarc-André Lureau virgl_cmd_context_destroy(VuGpu *g, 51d52c454aSMarc-André Lureau struct virtio_gpu_ctrl_command *cmd) 52d52c454aSMarc-André Lureau { 53d52c454aSMarc-André Lureau struct virtio_gpu_ctx_destroy cd; 54d52c454aSMarc-André Lureau 55d52c454aSMarc-André Lureau VUGPU_FILL_CMD(cd); 56d52c454aSMarc-André Lureau 57d52c454aSMarc-André Lureau virgl_renderer_context_destroy(cd.hdr.ctx_id); 58d52c454aSMarc-André Lureau } 59d52c454aSMarc-André Lureau 60d52c454aSMarc-André Lureau static void 61d52c454aSMarc-André Lureau virgl_cmd_create_resource_2d(VuGpu *g, 62d52c454aSMarc-André Lureau struct virtio_gpu_ctrl_command *cmd) 63d52c454aSMarc-André Lureau { 64d52c454aSMarc-André Lureau struct virtio_gpu_resource_create_2d c2d; 65d52c454aSMarc-André Lureau struct virgl_renderer_resource_create_args args; 66d52c454aSMarc-André Lureau 67d52c454aSMarc-André Lureau VUGPU_FILL_CMD(c2d); 68d52c454aSMarc-André Lureau 69d52c454aSMarc-André Lureau args.handle = c2d.resource_id; 70d52c454aSMarc-André Lureau args.target = 2; 71d52c454aSMarc-André Lureau args.format = c2d.format; 72d52c454aSMarc-André Lureau args.bind = (1 << 1); 73d52c454aSMarc-André Lureau args.width = c2d.width; 74d52c454aSMarc-André Lureau args.height = c2d.height; 75d52c454aSMarc-André Lureau args.depth = 1; 76d52c454aSMarc-André Lureau args.array_size = 1; 77d52c454aSMarc-André Lureau args.last_level = 0; 78d52c454aSMarc-André Lureau args.nr_samples = 0; 79d52c454aSMarc-André Lureau args.flags = VIRTIO_GPU_RESOURCE_FLAG_Y_0_TOP; 80d52c454aSMarc-André Lureau virgl_renderer_resource_create(&args, NULL, 0); 81d52c454aSMarc-André Lureau } 82d52c454aSMarc-André Lureau 83d52c454aSMarc-André Lureau static void 84d52c454aSMarc-André Lureau virgl_cmd_create_resource_3d(VuGpu *g, 85d52c454aSMarc-André Lureau struct virtio_gpu_ctrl_command *cmd) 86d52c454aSMarc-André Lureau { 87d52c454aSMarc-André Lureau struct virtio_gpu_resource_create_3d c3d; 88d52c454aSMarc-André Lureau struct virgl_renderer_resource_create_args args; 89d52c454aSMarc-André Lureau 90d52c454aSMarc-André Lureau VUGPU_FILL_CMD(c3d); 91d52c454aSMarc-André Lureau 92d52c454aSMarc-André Lureau args.handle = c3d.resource_id; 93d52c454aSMarc-André Lureau args.target = c3d.target; 94d52c454aSMarc-André Lureau args.format = c3d.format; 95d52c454aSMarc-André Lureau args.bind = c3d.bind; 96d52c454aSMarc-André Lureau args.width = c3d.width; 97d52c454aSMarc-André Lureau args.height = c3d.height; 98d52c454aSMarc-André Lureau args.depth = c3d.depth; 99d52c454aSMarc-André Lureau args.array_size = c3d.array_size; 100d52c454aSMarc-André Lureau args.last_level = c3d.last_level; 101d52c454aSMarc-André Lureau args.nr_samples = c3d.nr_samples; 102d52c454aSMarc-André Lureau args.flags = c3d.flags; 103d52c454aSMarc-André Lureau virgl_renderer_resource_create(&args, NULL, 0); 104d52c454aSMarc-André Lureau } 105d52c454aSMarc-André Lureau 106d52c454aSMarc-André Lureau static void 107d52c454aSMarc-André Lureau virgl_cmd_resource_unref(VuGpu *g, 108d52c454aSMarc-André Lureau struct virtio_gpu_ctrl_command *cmd) 109d52c454aSMarc-André Lureau { 110d52c454aSMarc-André Lureau struct virtio_gpu_resource_unref unref; 111f6091d86SLi Qiang struct iovec *res_iovs = NULL; 112f6091d86SLi Qiang int num_iovs = 0; 113d52c454aSMarc-André Lureau 114d52c454aSMarc-André Lureau VUGPU_FILL_CMD(unref); 115d52c454aSMarc-André Lureau 116f6091d86SLi Qiang virgl_renderer_resource_detach_iov(unref.resource_id, 117f6091d86SLi Qiang &res_iovs, 118f6091d86SLi Qiang &num_iovs); 119f6091d86SLi Qiang g_free(res_iovs); 120f6091d86SLi Qiang 121d52c454aSMarc-André Lureau virgl_renderer_resource_unref(unref.resource_id); 122d52c454aSMarc-André Lureau } 123d52c454aSMarc-André Lureau 124d52c454aSMarc-André Lureau /* Not yet(?) defined in standard-headers, remove when possible */ 125d52c454aSMarc-André Lureau #ifndef VIRTIO_GPU_CAPSET_VIRGL2 126d52c454aSMarc-André Lureau #define VIRTIO_GPU_CAPSET_VIRGL2 2 127d52c454aSMarc-André Lureau #endif 128d52c454aSMarc-André Lureau 129d52c454aSMarc-André Lureau static void 130d52c454aSMarc-André Lureau virgl_cmd_get_capset_info(VuGpu *g, 131d52c454aSMarc-André Lureau struct virtio_gpu_ctrl_command *cmd) 132d52c454aSMarc-André Lureau { 133d52c454aSMarc-André Lureau struct virtio_gpu_get_capset_info info; 134d52c454aSMarc-André Lureau struct virtio_gpu_resp_capset_info resp; 135d52c454aSMarc-André Lureau 136d52c454aSMarc-André Lureau VUGPU_FILL_CMD(info); 137d52c454aSMarc-André Lureau 138121841b2SLi Qiang memset(&resp, 0, sizeof(resp)); 139d52c454aSMarc-André Lureau if (info.capset_index == 0) { 140d52c454aSMarc-André Lureau resp.capset_id = VIRTIO_GPU_CAPSET_VIRGL; 141d52c454aSMarc-André Lureau virgl_renderer_get_cap_set(resp.capset_id, 142d52c454aSMarc-André Lureau &resp.capset_max_version, 143d52c454aSMarc-André Lureau &resp.capset_max_size); 144d52c454aSMarc-André Lureau } else if (info.capset_index == 1) { 145d52c454aSMarc-André Lureau resp.capset_id = VIRTIO_GPU_CAPSET_VIRGL2; 146d52c454aSMarc-André Lureau virgl_renderer_get_cap_set(resp.capset_id, 147d52c454aSMarc-André Lureau &resp.capset_max_version, 148d52c454aSMarc-André Lureau &resp.capset_max_size); 149d52c454aSMarc-André Lureau } else { 150d52c454aSMarc-André Lureau resp.capset_max_version = 0; 151d52c454aSMarc-André Lureau resp.capset_max_size = 0; 152d52c454aSMarc-André Lureau } 153d52c454aSMarc-André Lureau resp.hdr.type = VIRTIO_GPU_RESP_OK_CAPSET_INFO; 154d52c454aSMarc-André Lureau vg_ctrl_response(g, cmd, &resp.hdr, sizeof(resp)); 155d52c454aSMarc-André Lureau } 156d52c454aSMarc-André Lureau 157d52c454aSMarc-André Lureau uint32_t 158d52c454aSMarc-André Lureau vg_virgl_get_num_capsets(void) 159d52c454aSMarc-André Lureau { 160d52c454aSMarc-André Lureau uint32_t capset2_max_ver, capset2_max_size; 161d52c454aSMarc-André Lureau virgl_renderer_get_cap_set(VIRTIO_GPU_CAPSET_VIRGL2, 162d52c454aSMarc-André Lureau &capset2_max_ver, 163d52c454aSMarc-André Lureau &capset2_max_size); 164d52c454aSMarc-André Lureau 165d52c454aSMarc-André Lureau return capset2_max_ver ? 2 : 1; 166d52c454aSMarc-André Lureau } 167d52c454aSMarc-André Lureau 168d52c454aSMarc-André Lureau static void 169d52c454aSMarc-André Lureau virgl_cmd_get_capset(VuGpu *g, 170d52c454aSMarc-André Lureau struct virtio_gpu_ctrl_command *cmd) 171d52c454aSMarc-André Lureau { 172d52c454aSMarc-André Lureau struct virtio_gpu_get_capset gc; 173d52c454aSMarc-André Lureau struct virtio_gpu_resp_capset *resp; 174d52c454aSMarc-André Lureau uint32_t max_ver, max_size; 175d52c454aSMarc-André Lureau 176d52c454aSMarc-André Lureau VUGPU_FILL_CMD(gc); 177d52c454aSMarc-André Lureau 178d52c454aSMarc-André Lureau virgl_renderer_get_cap_set(gc.capset_id, &max_ver, 179d52c454aSMarc-André Lureau &max_size); 180d52c454aSMarc-André Lureau resp = g_malloc0(sizeof(*resp) + max_size); 181d52c454aSMarc-André Lureau 182d52c454aSMarc-André Lureau resp->hdr.type = VIRTIO_GPU_RESP_OK_CAPSET; 183d52c454aSMarc-André Lureau virgl_renderer_fill_caps(gc.capset_id, 184d52c454aSMarc-André Lureau gc.capset_version, 185d52c454aSMarc-André Lureau (void *)resp->capset_data); 186d52c454aSMarc-André Lureau vg_ctrl_response(g, cmd, &resp->hdr, sizeof(*resp) + max_size); 187d52c454aSMarc-André Lureau g_free(resp); 188d52c454aSMarc-André Lureau } 189d52c454aSMarc-André Lureau 190d52c454aSMarc-André Lureau static void 191d52c454aSMarc-André Lureau virgl_cmd_submit_3d(VuGpu *g, 192d52c454aSMarc-André Lureau struct virtio_gpu_ctrl_command *cmd) 193d52c454aSMarc-André Lureau { 194d52c454aSMarc-André Lureau struct virtio_gpu_cmd_submit cs; 195d52c454aSMarc-André Lureau void *buf; 196d52c454aSMarc-André Lureau size_t s; 197d52c454aSMarc-André Lureau 198d52c454aSMarc-André Lureau VUGPU_FILL_CMD(cs); 199d52c454aSMarc-André Lureau 200d52c454aSMarc-André Lureau buf = g_malloc(cs.size); 201d52c454aSMarc-André Lureau s = iov_to_buf(cmd->elem.out_sg, cmd->elem.out_num, 202d52c454aSMarc-André Lureau sizeof(cs), buf, cs.size); 203d52c454aSMarc-André Lureau if (s != cs.size) { 204d52c454aSMarc-André Lureau g_critical("%s: size mismatch (%zd/%d)", __func__, s, cs.size); 205d52c454aSMarc-André Lureau cmd->error = VIRTIO_GPU_RESP_ERR_INVALID_PARAMETER; 206d52c454aSMarc-André Lureau goto out; 207d52c454aSMarc-André Lureau } 208d52c454aSMarc-André Lureau 209d52c454aSMarc-André Lureau virgl_renderer_submit_cmd(buf, cs.hdr.ctx_id, cs.size / 4); 210d52c454aSMarc-André Lureau 211d52c454aSMarc-André Lureau out: 212d52c454aSMarc-André Lureau g_free(buf); 213d52c454aSMarc-André Lureau } 214d52c454aSMarc-André Lureau 215d52c454aSMarc-André Lureau static void 216d52c454aSMarc-André Lureau virgl_cmd_transfer_to_host_2d(VuGpu *g, 217d52c454aSMarc-André Lureau struct virtio_gpu_ctrl_command *cmd) 218d52c454aSMarc-André Lureau { 219d52c454aSMarc-André Lureau struct virtio_gpu_transfer_to_host_2d t2d; 220d52c454aSMarc-André Lureau struct virtio_gpu_box box; 221d52c454aSMarc-André Lureau 222d52c454aSMarc-André Lureau VUGPU_FILL_CMD(t2d); 223d52c454aSMarc-André Lureau 224d52c454aSMarc-André Lureau box.x = t2d.r.x; 225d52c454aSMarc-André Lureau box.y = t2d.r.y; 226d52c454aSMarc-André Lureau box.z = 0; 227d52c454aSMarc-André Lureau box.w = t2d.r.width; 228d52c454aSMarc-André Lureau box.h = t2d.r.height; 229d52c454aSMarc-André Lureau box.d = 1; 230d52c454aSMarc-André Lureau 231d52c454aSMarc-André Lureau virgl_renderer_transfer_write_iov(t2d.resource_id, 232d52c454aSMarc-André Lureau 0, 233d52c454aSMarc-André Lureau 0, 234d52c454aSMarc-André Lureau 0, 235d52c454aSMarc-André Lureau 0, 236d52c454aSMarc-André Lureau (struct virgl_box *)&box, 237d52c454aSMarc-André Lureau t2d.offset, NULL, 0); 238d52c454aSMarc-André Lureau } 239d52c454aSMarc-André Lureau 240d52c454aSMarc-André Lureau static void 241d52c454aSMarc-André Lureau virgl_cmd_transfer_to_host_3d(VuGpu *g, 242d52c454aSMarc-André Lureau struct virtio_gpu_ctrl_command *cmd) 243d52c454aSMarc-André Lureau { 244d52c454aSMarc-André Lureau struct virtio_gpu_transfer_host_3d t3d; 245d52c454aSMarc-André Lureau 246d52c454aSMarc-André Lureau VUGPU_FILL_CMD(t3d); 247d52c454aSMarc-André Lureau 248d52c454aSMarc-André Lureau virgl_renderer_transfer_write_iov(t3d.resource_id, 249d52c454aSMarc-André Lureau t3d.hdr.ctx_id, 250d52c454aSMarc-André Lureau t3d.level, 251d52c454aSMarc-André Lureau t3d.stride, 252d52c454aSMarc-André Lureau t3d.layer_stride, 253d52c454aSMarc-André Lureau (struct virgl_box *)&t3d.box, 254d52c454aSMarc-André Lureau t3d.offset, NULL, 0); 255d52c454aSMarc-André Lureau } 256d52c454aSMarc-André Lureau 257d52c454aSMarc-André Lureau static void 258d52c454aSMarc-André Lureau virgl_cmd_transfer_from_host_3d(VuGpu *g, 259d52c454aSMarc-André Lureau struct virtio_gpu_ctrl_command *cmd) 260d52c454aSMarc-André Lureau { 261d52c454aSMarc-André Lureau struct virtio_gpu_transfer_host_3d tf3d; 262d52c454aSMarc-André Lureau 263d52c454aSMarc-André Lureau VUGPU_FILL_CMD(tf3d); 264d52c454aSMarc-André Lureau 265d52c454aSMarc-André Lureau virgl_renderer_transfer_read_iov(tf3d.resource_id, 266d52c454aSMarc-André Lureau tf3d.hdr.ctx_id, 267d52c454aSMarc-André Lureau tf3d.level, 268d52c454aSMarc-André Lureau tf3d.stride, 269d52c454aSMarc-André Lureau tf3d.layer_stride, 270d52c454aSMarc-André Lureau (struct virgl_box *)&tf3d.box, 271d52c454aSMarc-André Lureau tf3d.offset, NULL, 0); 272d52c454aSMarc-André Lureau } 273d52c454aSMarc-André Lureau 274d52c454aSMarc-André Lureau static void 275d52c454aSMarc-André Lureau virgl_resource_attach_backing(VuGpu *g, 276d52c454aSMarc-André Lureau struct virtio_gpu_ctrl_command *cmd) 277d52c454aSMarc-André Lureau { 278d52c454aSMarc-André Lureau struct virtio_gpu_resource_attach_backing att_rb; 279d52c454aSMarc-André Lureau struct iovec *res_iovs; 280d52c454aSMarc-André Lureau int ret; 281d52c454aSMarc-André Lureau 282d52c454aSMarc-André Lureau VUGPU_FILL_CMD(att_rb); 283d52c454aSMarc-André Lureau 284d52c454aSMarc-André Lureau ret = vg_create_mapping_iov(g, &att_rb, cmd, &res_iovs); 285d52c454aSMarc-André Lureau if (ret != 0) { 286d52c454aSMarc-André Lureau cmd->error = VIRTIO_GPU_RESP_ERR_UNSPEC; 287d52c454aSMarc-André Lureau return; 288d52c454aSMarc-André Lureau } 289d52c454aSMarc-André Lureau 290*63736af5SLi Qiang ret = virgl_renderer_resource_attach_iov(att_rb.resource_id, 291d52c454aSMarc-André Lureau res_iovs, att_rb.nr_entries); 292*63736af5SLi Qiang if (ret != 0) { 293*63736af5SLi Qiang g_free(res_iovs); 294*63736af5SLi Qiang } 295d52c454aSMarc-André Lureau } 296d52c454aSMarc-André Lureau 297d52c454aSMarc-André Lureau static void 298d52c454aSMarc-André Lureau virgl_resource_detach_backing(VuGpu *g, 299d52c454aSMarc-André Lureau struct virtio_gpu_ctrl_command *cmd) 300d52c454aSMarc-André Lureau { 301d52c454aSMarc-André Lureau struct virtio_gpu_resource_detach_backing detach_rb; 302d52c454aSMarc-André Lureau struct iovec *res_iovs = NULL; 303d52c454aSMarc-André Lureau int num_iovs = 0; 304d52c454aSMarc-André Lureau 305d52c454aSMarc-André Lureau VUGPU_FILL_CMD(detach_rb); 306d52c454aSMarc-André Lureau 307d52c454aSMarc-André Lureau virgl_renderer_resource_detach_iov(detach_rb.resource_id, 308d52c454aSMarc-André Lureau &res_iovs, 309d52c454aSMarc-André Lureau &num_iovs); 310d52c454aSMarc-André Lureau if (res_iovs == NULL || num_iovs == 0) { 311d52c454aSMarc-André Lureau return; 312d52c454aSMarc-André Lureau } 313d52c454aSMarc-André Lureau g_free(res_iovs); 314d52c454aSMarc-André Lureau } 315d52c454aSMarc-André Lureau 316d52c454aSMarc-André Lureau static void 317d52c454aSMarc-André Lureau virgl_cmd_set_scanout(VuGpu *g, 318d52c454aSMarc-André Lureau struct virtio_gpu_ctrl_command *cmd) 319d52c454aSMarc-André Lureau { 320d52c454aSMarc-André Lureau struct virtio_gpu_set_scanout ss; 321d52c454aSMarc-André Lureau struct virgl_renderer_resource_info info; 322d52c454aSMarc-André Lureau int ret; 323d52c454aSMarc-André Lureau 324d52c454aSMarc-André Lureau VUGPU_FILL_CMD(ss); 325d52c454aSMarc-André Lureau 326d52c454aSMarc-André Lureau if (ss.scanout_id >= VIRTIO_GPU_MAX_SCANOUTS) { 327d52c454aSMarc-André Lureau g_critical("%s: illegal scanout id specified %d", 328d52c454aSMarc-André Lureau __func__, ss.scanout_id); 329d52c454aSMarc-André Lureau cmd->error = VIRTIO_GPU_RESP_ERR_INVALID_SCANOUT_ID; 330d52c454aSMarc-André Lureau return; 331d52c454aSMarc-André Lureau } 332d52c454aSMarc-André Lureau 333d52c454aSMarc-André Lureau memset(&info, 0, sizeof(info)); 334d52c454aSMarc-André Lureau 335d52c454aSMarc-André Lureau if (ss.resource_id && ss.r.width && ss.r.height) { 336d52c454aSMarc-André Lureau ret = virgl_renderer_resource_get_info(ss.resource_id, &info); 337d52c454aSMarc-André Lureau if (ret == -1) { 338d52c454aSMarc-André Lureau g_critical("%s: illegal resource specified %d\n", 339d52c454aSMarc-André Lureau __func__, ss.resource_id); 340d52c454aSMarc-André Lureau cmd->error = VIRTIO_GPU_RESP_ERR_INVALID_RESOURCE_ID; 341d52c454aSMarc-André Lureau return; 342d52c454aSMarc-André Lureau } 343d52c454aSMarc-André Lureau 344d52c454aSMarc-André Lureau int fd = -1; 345d52c454aSMarc-André Lureau if (virgl_renderer_get_fd_for_texture(info.tex_id, &fd) < 0) { 346d52c454aSMarc-André Lureau g_critical("%s: failed to get fd for texture\n", __func__); 347d52c454aSMarc-André Lureau cmd->error = VIRTIO_GPU_RESP_ERR_INVALID_RESOURCE_ID; 348d52c454aSMarc-André Lureau return; 349d52c454aSMarc-André Lureau } 350d52c454aSMarc-André Lureau assert(fd >= 0); 351d52c454aSMarc-André Lureau VhostUserGpuMsg msg = { 352d52c454aSMarc-André Lureau .request = VHOST_USER_GPU_DMABUF_SCANOUT, 353d52c454aSMarc-André Lureau .size = sizeof(VhostUserGpuDMABUFScanout), 354d52c454aSMarc-André Lureau .payload.dmabuf_scanout.scanout_id = ss.scanout_id, 355d52c454aSMarc-André Lureau .payload.dmabuf_scanout.x = ss.r.x, 356d52c454aSMarc-André Lureau .payload.dmabuf_scanout.y = ss.r.y, 357d52c454aSMarc-André Lureau .payload.dmabuf_scanout.width = ss.r.width, 358d52c454aSMarc-André Lureau .payload.dmabuf_scanout.height = ss.r.height, 359d52c454aSMarc-André Lureau .payload.dmabuf_scanout.fd_width = info.width, 360d52c454aSMarc-André Lureau .payload.dmabuf_scanout.fd_height = info.height, 361d52c454aSMarc-André Lureau .payload.dmabuf_scanout.fd_stride = info.stride, 362d52c454aSMarc-André Lureau .payload.dmabuf_scanout.fd_flags = info.flags, 363d52c454aSMarc-André Lureau .payload.dmabuf_scanout.fd_drm_fourcc = info.drm_fourcc 364d52c454aSMarc-André Lureau }; 365d52c454aSMarc-André Lureau vg_send_msg(g, &msg, fd); 366d52c454aSMarc-André Lureau close(fd); 367d52c454aSMarc-André Lureau } else { 368d52c454aSMarc-André Lureau VhostUserGpuMsg msg = { 369d52c454aSMarc-André Lureau .request = VHOST_USER_GPU_DMABUF_SCANOUT, 370d52c454aSMarc-André Lureau .size = sizeof(VhostUserGpuDMABUFScanout), 371d52c454aSMarc-André Lureau .payload.dmabuf_scanout.scanout_id = ss.scanout_id, 372d52c454aSMarc-André Lureau }; 373d52c454aSMarc-André Lureau g_debug("disable scanout"); 374d52c454aSMarc-André Lureau vg_send_msg(g, &msg, -1); 375d52c454aSMarc-André Lureau } 376d52c454aSMarc-André Lureau g->scanout[ss.scanout_id].resource_id = ss.resource_id; 377d52c454aSMarc-André Lureau } 378d52c454aSMarc-André Lureau 379d52c454aSMarc-André Lureau static void 380d52c454aSMarc-André Lureau virgl_cmd_resource_flush(VuGpu *g, 381d52c454aSMarc-André Lureau struct virtio_gpu_ctrl_command *cmd) 382d52c454aSMarc-André Lureau { 383d52c454aSMarc-André Lureau struct virtio_gpu_resource_flush rf; 384d52c454aSMarc-André Lureau int i; 385d52c454aSMarc-André Lureau 386d52c454aSMarc-André Lureau VUGPU_FILL_CMD(rf); 387d52c454aSMarc-André Lureau 3880c27b9c5SMarc-André Lureau glFlush(); 389d52c454aSMarc-André Lureau if (!rf.resource_id) { 390d52c454aSMarc-André Lureau g_debug("bad resource id for flush..?"); 391d52c454aSMarc-André Lureau return; 392d52c454aSMarc-André Lureau } 393d52c454aSMarc-André Lureau for (i = 0; i < VIRTIO_GPU_MAX_SCANOUTS; i++) { 394d52c454aSMarc-André Lureau if (g->scanout[i].resource_id != rf.resource_id) { 395d52c454aSMarc-André Lureau continue; 396d52c454aSMarc-André Lureau } 397d52c454aSMarc-André Lureau VhostUserGpuMsg msg = { 398d52c454aSMarc-André Lureau .request = VHOST_USER_GPU_DMABUF_UPDATE, 399d52c454aSMarc-André Lureau .size = sizeof(VhostUserGpuUpdate), 400d52c454aSMarc-André Lureau .payload.update.scanout_id = i, 401d52c454aSMarc-André Lureau .payload.update.x = rf.r.x, 402d52c454aSMarc-André Lureau .payload.update.y = rf.r.y, 403d52c454aSMarc-André Lureau .payload.update.width = rf.r.width, 404d52c454aSMarc-André Lureau .payload.update.height = rf.r.height 405d52c454aSMarc-André Lureau }; 406d52c454aSMarc-André Lureau vg_send_msg(g, &msg, -1); 407d52c454aSMarc-André Lureau vg_wait_ok(g); 408d52c454aSMarc-André Lureau } 409d52c454aSMarc-André Lureau } 410d52c454aSMarc-André Lureau 411d52c454aSMarc-André Lureau static void 412d52c454aSMarc-André Lureau virgl_cmd_ctx_attach_resource(VuGpu *g, 413d52c454aSMarc-André Lureau struct virtio_gpu_ctrl_command *cmd) 414d52c454aSMarc-André Lureau { 415d52c454aSMarc-André Lureau struct virtio_gpu_ctx_resource att_res; 416d52c454aSMarc-André Lureau 417d52c454aSMarc-André Lureau VUGPU_FILL_CMD(att_res); 418d52c454aSMarc-André Lureau 419d52c454aSMarc-André Lureau virgl_renderer_ctx_attach_resource(att_res.hdr.ctx_id, att_res.resource_id); 420d52c454aSMarc-André Lureau } 421d52c454aSMarc-André Lureau 422d52c454aSMarc-André Lureau static void 423d52c454aSMarc-André Lureau virgl_cmd_ctx_detach_resource(VuGpu *g, 424d52c454aSMarc-André Lureau struct virtio_gpu_ctrl_command *cmd) 425d52c454aSMarc-André Lureau { 426d52c454aSMarc-André Lureau struct virtio_gpu_ctx_resource det_res; 427d52c454aSMarc-André Lureau 428d52c454aSMarc-André Lureau VUGPU_FILL_CMD(det_res); 429d52c454aSMarc-André Lureau 430d52c454aSMarc-André Lureau virgl_renderer_ctx_detach_resource(det_res.hdr.ctx_id, det_res.resource_id); 431d52c454aSMarc-André Lureau } 432d52c454aSMarc-André Lureau 433d52c454aSMarc-André Lureau void vg_virgl_process_cmd(VuGpu *g, struct virtio_gpu_ctrl_command *cmd) 434d52c454aSMarc-André Lureau { 435d52c454aSMarc-André Lureau virgl_renderer_force_ctx_0(); 436d52c454aSMarc-André Lureau switch (cmd->cmd_hdr.type) { 437d52c454aSMarc-André Lureau case VIRTIO_GPU_CMD_CTX_CREATE: 438d52c454aSMarc-André Lureau virgl_cmd_context_create(g, cmd); 439d52c454aSMarc-André Lureau break; 440d52c454aSMarc-André Lureau case VIRTIO_GPU_CMD_CTX_DESTROY: 441d52c454aSMarc-André Lureau virgl_cmd_context_destroy(g, cmd); 442d52c454aSMarc-André Lureau break; 443d52c454aSMarc-André Lureau case VIRTIO_GPU_CMD_RESOURCE_CREATE_2D: 444d52c454aSMarc-André Lureau virgl_cmd_create_resource_2d(g, cmd); 445d52c454aSMarc-André Lureau break; 446d52c454aSMarc-André Lureau case VIRTIO_GPU_CMD_RESOURCE_CREATE_3D: 447d52c454aSMarc-André Lureau virgl_cmd_create_resource_3d(g, cmd); 448d52c454aSMarc-André Lureau break; 449d52c454aSMarc-André Lureau case VIRTIO_GPU_CMD_SUBMIT_3D: 450d52c454aSMarc-André Lureau virgl_cmd_submit_3d(g, cmd); 451d52c454aSMarc-André Lureau break; 452d52c454aSMarc-André Lureau case VIRTIO_GPU_CMD_TRANSFER_TO_HOST_2D: 453d52c454aSMarc-André Lureau virgl_cmd_transfer_to_host_2d(g, cmd); 454d52c454aSMarc-André Lureau break; 455d52c454aSMarc-André Lureau case VIRTIO_GPU_CMD_TRANSFER_TO_HOST_3D: 456d52c454aSMarc-André Lureau virgl_cmd_transfer_to_host_3d(g, cmd); 457d52c454aSMarc-André Lureau break; 458d52c454aSMarc-André Lureau case VIRTIO_GPU_CMD_TRANSFER_FROM_HOST_3D: 459d52c454aSMarc-André Lureau virgl_cmd_transfer_from_host_3d(g, cmd); 460d52c454aSMarc-André Lureau break; 461d52c454aSMarc-André Lureau case VIRTIO_GPU_CMD_RESOURCE_ATTACH_BACKING: 462d52c454aSMarc-André Lureau virgl_resource_attach_backing(g, cmd); 463d52c454aSMarc-André Lureau break; 464d52c454aSMarc-André Lureau case VIRTIO_GPU_CMD_RESOURCE_DETACH_BACKING: 465d52c454aSMarc-André Lureau virgl_resource_detach_backing(g, cmd); 466d52c454aSMarc-André Lureau break; 467d52c454aSMarc-André Lureau case VIRTIO_GPU_CMD_SET_SCANOUT: 468d52c454aSMarc-André Lureau virgl_cmd_set_scanout(g, cmd); 469d52c454aSMarc-André Lureau break; 470d52c454aSMarc-André Lureau case VIRTIO_GPU_CMD_RESOURCE_FLUSH: 471d52c454aSMarc-André Lureau virgl_cmd_resource_flush(g, cmd); 472d52c454aSMarc-André Lureau break; 473d52c454aSMarc-André Lureau case VIRTIO_GPU_CMD_RESOURCE_UNREF: 474d52c454aSMarc-André Lureau virgl_cmd_resource_unref(g, cmd); 475d52c454aSMarc-André Lureau break; 476d52c454aSMarc-André Lureau case VIRTIO_GPU_CMD_CTX_ATTACH_RESOURCE: 477d52c454aSMarc-André Lureau /* TODO add security */ 478d52c454aSMarc-André Lureau virgl_cmd_ctx_attach_resource(g, cmd); 479d52c454aSMarc-André Lureau break; 480d52c454aSMarc-André Lureau case VIRTIO_GPU_CMD_CTX_DETACH_RESOURCE: 481d52c454aSMarc-André Lureau /* TODO add security */ 482d52c454aSMarc-André Lureau virgl_cmd_ctx_detach_resource(g, cmd); 483d52c454aSMarc-André Lureau break; 484d52c454aSMarc-André Lureau case VIRTIO_GPU_CMD_GET_CAPSET_INFO: 485d52c454aSMarc-André Lureau virgl_cmd_get_capset_info(g, cmd); 486d52c454aSMarc-André Lureau break; 487d52c454aSMarc-André Lureau case VIRTIO_GPU_CMD_GET_CAPSET: 488d52c454aSMarc-André Lureau virgl_cmd_get_capset(g, cmd); 489d52c454aSMarc-André Lureau break; 490d52c454aSMarc-André Lureau case VIRTIO_GPU_CMD_GET_DISPLAY_INFO: 491d52c454aSMarc-André Lureau vg_get_display_info(g, cmd); 492d52c454aSMarc-André Lureau break; 493d52c454aSMarc-André Lureau default: 494d52c454aSMarc-André Lureau g_debug("TODO handle ctrl %x\n", cmd->cmd_hdr.type); 495d52c454aSMarc-André Lureau cmd->error = VIRTIO_GPU_RESP_ERR_UNSPEC; 496d52c454aSMarc-André Lureau break; 497d52c454aSMarc-André Lureau } 498d52c454aSMarc-André Lureau 49972e631c6SMarc-André Lureau if (cmd->state != VG_CMD_STATE_NEW) { 500d52c454aSMarc-André Lureau return; 501d52c454aSMarc-André Lureau } 502d52c454aSMarc-André Lureau 503d52c454aSMarc-André Lureau if (cmd->error) { 504d52c454aSMarc-André Lureau g_warning("%s: ctrl 0x%x, error 0x%x\n", __func__, 505d52c454aSMarc-André Lureau cmd->cmd_hdr.type, cmd->error); 506d52c454aSMarc-André Lureau vg_ctrl_response_nodata(g, cmd, cmd->error); 507d52c454aSMarc-André Lureau return; 508d52c454aSMarc-André Lureau } 509d52c454aSMarc-André Lureau 510d52c454aSMarc-André Lureau if (!(cmd->cmd_hdr.flags & VIRTIO_GPU_FLAG_FENCE)) { 511d52c454aSMarc-André Lureau vg_ctrl_response_nodata(g, cmd, VIRTIO_GPU_RESP_OK_NODATA); 512d52c454aSMarc-André Lureau return; 513d52c454aSMarc-André Lureau } 514d52c454aSMarc-André Lureau 515d52c454aSMarc-André Lureau g_debug("Creating fence id:%" PRId64 " type:%d", 516d52c454aSMarc-André Lureau cmd->cmd_hdr.fence_id, cmd->cmd_hdr.type); 517d52c454aSMarc-André Lureau virgl_renderer_create_fence(cmd->cmd_hdr.fence_id, cmd->cmd_hdr.type); 518d52c454aSMarc-André Lureau } 519d52c454aSMarc-André Lureau 520d52c454aSMarc-André Lureau static void 521d52c454aSMarc-André Lureau virgl_write_fence(void *opaque, uint32_t fence) 522d52c454aSMarc-André Lureau { 523d52c454aSMarc-André Lureau VuGpu *g = opaque; 524d52c454aSMarc-André Lureau struct virtio_gpu_ctrl_command *cmd, *tmp; 525d52c454aSMarc-André Lureau 526d52c454aSMarc-André Lureau QTAILQ_FOREACH_SAFE(cmd, &g->fenceq, next, tmp) { 527d52c454aSMarc-André Lureau /* 528d52c454aSMarc-André Lureau * the guest can end up emitting fences out of order 529d52c454aSMarc-André Lureau * so we should check all fenced cmds not just the first one. 530d52c454aSMarc-André Lureau */ 531d52c454aSMarc-André Lureau if (cmd->cmd_hdr.fence_id > fence) { 532d52c454aSMarc-André Lureau continue; 533d52c454aSMarc-André Lureau } 534d52c454aSMarc-André Lureau g_debug("FENCE %" PRIu64, cmd->cmd_hdr.fence_id); 535d52c454aSMarc-André Lureau vg_ctrl_response_nodata(g, cmd, VIRTIO_GPU_RESP_OK_NODATA); 536d52c454aSMarc-André Lureau QTAILQ_REMOVE(&g->fenceq, cmd, next); 5374ff97121SPhilippe Mathieu-Daudé free(cmd); 538d52c454aSMarc-André Lureau g->inflight--; 539d52c454aSMarc-André Lureau } 540d52c454aSMarc-André Lureau } 541d52c454aSMarc-André Lureau 542d52c454aSMarc-André Lureau #if defined(VIRGL_RENDERER_CALLBACKS_VERSION) && \ 543d52c454aSMarc-André Lureau VIRGL_RENDERER_CALLBACKS_VERSION >= 2 544d52c454aSMarc-André Lureau static int 545d52c454aSMarc-André Lureau virgl_get_drm_fd(void *opaque) 546d52c454aSMarc-André Lureau { 547d52c454aSMarc-André Lureau VuGpu *g = opaque; 548d52c454aSMarc-André Lureau 549d52c454aSMarc-André Lureau return g->drm_rnode_fd; 550d52c454aSMarc-André Lureau } 551d52c454aSMarc-André Lureau #endif 552d52c454aSMarc-André Lureau 553d52c454aSMarc-André Lureau static struct virgl_renderer_callbacks virgl_cbs = { 554d52c454aSMarc-André Lureau #if defined(VIRGL_RENDERER_CALLBACKS_VERSION) && \ 555d52c454aSMarc-André Lureau VIRGL_RENDERER_CALLBACKS_VERSION >= 2 556d52c454aSMarc-André Lureau .get_drm_fd = virgl_get_drm_fd, 557d52c454aSMarc-André Lureau .version = 2, 558d52c454aSMarc-André Lureau #else 559d52c454aSMarc-André Lureau .version = 1, 560d52c454aSMarc-André Lureau #endif 561d52c454aSMarc-André Lureau .write_fence = virgl_write_fence, 562d52c454aSMarc-André Lureau }; 563d52c454aSMarc-André Lureau 564d52c454aSMarc-André Lureau static void 565d52c454aSMarc-André Lureau vg_virgl_poll(VuDev *dev, int condition, void *data) 566d52c454aSMarc-André Lureau { 567d52c454aSMarc-André Lureau virgl_renderer_poll(); 568d52c454aSMarc-André Lureau } 569d52c454aSMarc-André Lureau 570d52c454aSMarc-André Lureau bool 571d52c454aSMarc-André Lureau vg_virgl_init(VuGpu *g) 572d52c454aSMarc-André Lureau { 573d52c454aSMarc-André Lureau int ret; 574d52c454aSMarc-André Lureau 575d52c454aSMarc-André Lureau if (g->drm_rnode_fd && virgl_cbs.version == 1) { 576d52c454aSMarc-André Lureau g_warning("virgl will use the default rendernode"); 577d52c454aSMarc-André Lureau } 578d52c454aSMarc-André Lureau 579d52c454aSMarc-André Lureau ret = virgl_renderer_init(g, 580d52c454aSMarc-André Lureau VIRGL_RENDERER_USE_EGL | 581d52c454aSMarc-André Lureau VIRGL_RENDERER_THREAD_SYNC, 582d52c454aSMarc-André Lureau &virgl_cbs); 583d52c454aSMarc-André Lureau if (ret != 0) { 584d52c454aSMarc-André Lureau return false; 585d52c454aSMarc-André Lureau } 586d52c454aSMarc-André Lureau 587d52c454aSMarc-André Lureau ret = virgl_renderer_get_poll_fd(); 588d52c454aSMarc-André Lureau if (ret != -1) { 589d52c454aSMarc-André Lureau g->renderer_source = 590d52c454aSMarc-André Lureau vug_source_new(&g->dev, ret, G_IO_IN, vg_virgl_poll, g); 591d52c454aSMarc-André Lureau } 592d52c454aSMarc-André Lureau 593d52c454aSMarc-André Lureau return true; 594d52c454aSMarc-André Lureau } 595