xref: /qemu/disas/nanomips.c (revision c3bef3b4) 
1 /*
2  *  Source file for nanoMIPS disassembler component of QEMU
3  *
4  *  Copyright (C) 2018  Wave Computing, Inc.
5  *  Copyright (C) 2018  Matthew Fortune <matthew.fortune@mips.com>
6  *  Copyright (C) 2018  Aleksandar Markovic <amarkovic@wavecomp.com>
7  *
8  *  This program is free software: you can redistribute it and/or modify
9  *  it under the terms of the GNU General Public License as published by
10  *  the Free Software Foundation, either version 2 of the License, or
11  *  (at your option) any later version.
12  *
13  *  This program is distributed in the hope that it will be useful,
14  *  but WITHOUT ANY WARRANTY; without even the implied warranty of
15  *  MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
16  *  GNU General Public License for more details.
17  *
18  *  You should have received a copy of the GNU General Public License
19  *  along with this program.  If not, see <https://www.gnu.org/licenses/>.
20  *
21  */
22 
23 /*
24  *  Documentation used while implementing this component:
25  *
26  *  [1] "MIPS® Architecture Base: nanoMIPS32(tm) Instruction Set Technical
27  *      Reference Manual", Revision 01.01, April 27, 2018
28  */
29 
30 #include "qemu/osdep.h"
31 #include "disas/dis-asm.h"
32 
33 typedef int64_t int64;
34 typedef uint64_t uint64;
35 typedef uint32_t uint32;
36 typedef uint16_t uint16;
37 typedef uint64_t img_address;
38 
39 typedef enum  {
40     instruction,
41     call_instruction,
42     branch_instruction,
43     return_instruction,
44     reserved_block,
45     pool,
46 } TABLE_ENTRY_TYPE;
47 
48 typedef enum {
49     MIPS64_    = 0x00000001,
50     XNP_       = 0x00000002,
51     XMMS_      = 0x00000004,
52     EVA_       = 0x00000008,
53     DSP_       = 0x00000010,
54     MT_        = 0x00000020,
55     EJTAG_     = 0x00000040,
56     TLBINV_    = 0x00000080,
57     CP0_       = 0x00000100,
58     CP1_       = 0x00000200,
59     CP2_       = 0x00000400,
60     UDI_       = 0x00000800,
61     MCU_       = 0x00001000,
62     VZ_        = 0x00002000,
63     TLB_       = 0x00004000,
64     MVH_       = 0x00008000,
65     ALL_ATTRIBUTES = 0xffffffffull,
66 } TABLE_ATTRIBUTE_TYPE;
67 
68 typedef struct Dis_info {
69   img_address m_pc;
70   fprintf_function fprintf_func;
71   FILE *stream;
72   sigjmp_buf buf;
73 } Dis_info;
74 
75 typedef bool (*conditional_function)(uint64 instruction);
76 typedef char * (*disassembly_function)(uint64 instruction,
77                                             Dis_info *info);
78 
79 typedef struct Pool {
80     TABLE_ENTRY_TYPE     type;
81     const struct Pool    *next_table;
82     int                  next_table_size;
83     int                  instructions_size;
84     uint64               mask;
85     uint64               value;
86     disassembly_function disassembly;
87     conditional_function condition;
88     uint64               attributes;
89 } Pool;
90 
91 #define IMGASSERTONCE(test)
92 
93 
94 static char * G_GNUC_PRINTF(1, 2) img_format(const char *format, ...)
95 {
96     char *buffer;
97     va_list args;
98     va_start(args, format);
99     buffer = g_strdup_vprintf(format, args);
100     va_end(args);
101     return buffer;
102 }
103 
104 
105 static char *to_string(img_address a)
106 {
107     return g_strdup_printf("0x%" PRIx64, a);
108 }
109 
110 
111 static uint64 extract_bits(uint64 data, uint32 bit_offset, uint32 bit_size)
112 {
113     return (data << (64 - (bit_size + bit_offset))) >> (64 - bit_size);
114 }
115 
116 
117 static int64 sign_extend(int64 data, int msb)
118 {
119     uint64 shift = 63 - msb;
120     return (data << shift) >> shift;
121 }
122 
123 
124 static uint64 renumber_registers(uint64 index, uint64 *register_list,
125                                size_t register_list_size, Dis_info *info)
126 {
127     if (index < register_list_size) {
128         return register_list[index];
129     }
130 
131     info->fprintf_func(info->stream, "Invalid register mapping index %" PRIu64
132                        ", size of list = %zu", index, register_list_size);
133     siglongjmp(info->buf, 1);
134 }
135 
136 
137 /*
138  * decode_gpr_gpr4() - decoder for 'gpr4' gpr encoding type
139  *
140  *   Map a 4-bit code to the 5-bit register space according to this pattern:
141  *
142  *                              1                   0
143  *                    5 4 3 2 1 0 9 8 7 6 5 4 3 2 1 0
144  *                    | | | | | | | | | | | | | | | |
145  *                    | | | | | | | | | | | | | | | |
146  *                    | | | | | | | | | | | └---------------┐
147  *                    | | | | | | | | | | └---------------┐ |
148  *                    | | | | | | | | | └---------------┐ | |
149  *                    | | | | | | | | └---------------┐ | | |
150  *                    | | | | | | | |         | | | | | | | |
151  *                    | | | | | | | |         | | | | | | | |
152  *    1 0 9 8 7 6 5 4 3 2 1 0 9 8 7 6 5 4 3 2 1 0 9 8 7 6 5 4 3 2 1 0
153  *      3                   2                   1                   0
154  *
155  *   Used in handling following instructions:
156  *
157  *     - ADDU[4X4]
158  *     - LW[4X4]
159  *     - MOVEP[REV]
160  *     - MUL[4X4]
161  *     - SW[4X4]
162  */
163 static uint64 decode_gpr_gpr4(uint64 d, Dis_info *info)
164 {
165     static uint64 register_list[] = {  8,  9, 10, 11,  4,  5,  6,  7,
166                                       16, 17, 18, 19, 20, 21, 22, 23 };
167     return renumber_registers(d, register_list,
168                sizeof(register_list) / sizeof(register_list[0]), info);
169 }
170 
171 
172 /*
173  * decode_gpr_gpr4_zero() - decoder for 'gpr4.zero' gpr encoding type
174  *
175  *   Map a 4-bit code to the 5-bit register space according to this pattern:
176  *
177  *                              1                   0
178  *                    5 4 3 2 1 0 9 8 7 6 5 4 3 2 1 0
179  *                    | | | | | | | | | | | | | | | |
180  *                    | | | | | | | | | | | | └---------------------┐
181  *                    | | | | | | | | | | | └---------------┐       |
182  *                    | | | | | | | | | | └---------------┐ |       |
183  *                    | | | | | | | | | └---------------┐ | |       |
184  *                    | | | | | | | | └---------------┐ | | |       |
185  *                    | | | | | | | |           | | | | | | |       |
186  *                    | | | | | | | |           | | | | | | |       |
187  *    1 0 9 8 7 6 5 4 3 2 1 0 9 8 7 6 5 4 3 2 1 0 9 8 7 6 5 4 3 2 1 0
188  *      3                   2                   1                   0
189  *
190  *   This pattern is the same one used for 'gpr4' gpr encoding type, except for
191  * the input value 3, that is mapped to the output value 0 instead of 11.
192  *
193  *   Used in handling following instructions:
194  *
195  *     - MOVE.BALC
196  *     - MOVEP
197  *     - SW[4X4]
198  */
199 static uint64 decode_gpr_gpr4_zero(uint64 d, Dis_info *info)
200 {
201     static uint64 register_list[] = {  8,  9, 10,  0,  4,  5,  6,  7,
202                                       16, 17, 18, 19, 20, 21, 22, 23 };
203     return renumber_registers(d, register_list,
204                sizeof(register_list) / sizeof(register_list[0]), info);
205 }
206 
207 
208 /*
209  * decode_gpr_gpr3() - decoder for 'gpr3' gpr encoding type
210  *
211  *   Map a 3-bit code to the 5-bit register space according to this pattern:
212  *
213  *                            7 6 5 4 3 2 1 0
214  *                            | | | | | | | |
215  *                            | | | | | | | |
216  *                            | | | └-----------------------┐
217  *                            | | └-----------------------┐ |
218  *                            | └-----------------------┐ | |
219  *                            └-----------------------┐ | | |
220  *                                    | | | |         | | | |
221  *                            ┌-------┘ | | |         | | | |
222  *                            | ┌-------┘ | |         | | | |
223  *                            | | ┌-------┘ |         | | | |
224  *                            | | | ┌-------┘         | | | |
225  *                            | | | |                 | | | |
226  *    1 0 9 8 7 6 5 4 3 2 1 0 9 8 7 6 5 4 3 2 1 0 9 8 7 6 5 4 3 2 1 0
227  *      3                   2                   1                   0
228  *
229  *   Used in handling following instructions:
230  *
231  *     - ADDIU[R1.SP]
232  *     - ADDIU[R2]
233  *     - ADDU[16]
234  *     - AND[16]
235  *     - ANDI[16]
236  *     - BEQC[16]
237  *     - BEQZC[16]
238  *     - BNEC[16]
239  *     - BNEZC[16]
240  *     - LB[16]
241  *     - LBU[16]
242  *     - LH[16]
243  *     - LHU[16]
244  *     - LI[16]
245  *     - LW[16]
246  *     - LW[GP16]
247  *     - LWXS[16]
248  *     - NOT[16]
249  *     - OR[16]
250  *     - SB[16]
251  *     - SH[16]
252  *     - SLL[16]
253  *     - SRL[16]
254  *     - SUBU[16]
255  *     - SW[16]
256  *     - XOR[16]
257  */
258 static uint64 decode_gpr_gpr3(uint64 d, Dis_info *info)
259 {
260     static uint64 register_list[] = { 16, 17, 18, 19,  4,  5,  6,  7 };
261     return renumber_registers(d, register_list,
262                sizeof(register_list) / sizeof(register_list[0]), info);
263 }
264 
265 
266 /*
267  * decode_gpr_gpr3_src_store() - decoder for 'gpr3.src.store' gpr encoding
268  *     type
269  *
270  *   Map a 3-bit code to the 5-bit register space according to this pattern:
271  *
272  *                            7 6 5 4 3 2 1 0
273  *                            | | | | | | | |
274  *                            | | | | | | | └-----------------------┐
275  *                            | | | └-----------------------┐       |
276  *                            | | └-----------------------┐ |       |
277  *                            | └-----------------------┐ | |       |
278  *                            └-----------------------┐ | | |       |
279  *                                    | | |           | | | |       |
280  *                            ┌-------┘ | |           | | | |       |
281  *                            | ┌-------┘ |           | | | |       |
282  *                            | | ┌-------┘           | | | |       |
283  *                            | | |                   | | | |       |
284  *                            | | |                   | | | |       |
285  *    1 0 9 8 7 6 5 4 3 2 1 0 9 8 7 6 5 4 3 2 1 0 9 8 7 6 5 4 3 2 1 0
286  *      3                   2                   1                   0
287  *
288  *   This pattern is the same one used for 'gpr3' gpr encoding type, except for
289  * the input value 0, that is mapped to the output value 0 instead of 16.
290  *
291  *   Used in handling following instructions:
292  *
293  *     - SB[16]
294  *     - SH[16]
295  *     - SW[16]
296  *     - SW[GP16]
297  */
298 static uint64 decode_gpr_gpr3_src_store(uint64 d, Dis_info *info)
299 {
300     static uint64 register_list[] = {  0, 17, 18, 19,  4,  5,  6,  7 };
301     return renumber_registers(d, register_list,
302                sizeof(register_list) / sizeof(register_list[0]), info);
303 }
304 
305 
306 /*
307  * decode_gpr_gpr2_reg1() - decoder for 'gpr2.reg1' gpr encoding type
308  *
309  *   Map a 2-bit code to the 5-bit register space according to this pattern:
310  *
311  *                                3 2 1 0
312  *                                | | | |
313  *                                | | | |
314  *                                | | | └-------------------┐
315  *                                | | └-------------------┐ |
316  *                                | └-------------------┐ | |
317  *                                └-------------------┐ | | |
318  *                                                    | | | |
319  *                                                    | | | |
320  *    1 0 9 8 7 6 5 4 3 2 1 0 9 8 7 6 5 4 3 2 1 0 9 8 7 6 5 4 3 2 1 0
321  *      3                   2                   1                   0
322  *
323  *   Used in handling following instructions:
324  *
325  *     - MOVEP
326  *     - MOVEP[REV]
327  */
328 static uint64 decode_gpr_gpr2_reg1(uint64 d, Dis_info *info)
329 {
330     static uint64 register_list[] = {  4,  5,  6,  7 };
331     return renumber_registers(d, register_list,
332                sizeof(register_list) / sizeof(register_list[0]), info);
333 }
334 
335 
336 /*
337  * decode_gpr_gpr2_reg2() - decoder for 'gpr2.reg2' gpr encoding type
338  *
339  *   Map a 2-bit code to the 5-bit register space according to this pattern:
340  *
341  *                                3 2 1 0
342  *                                | | | |
343  *                                | | | |
344  *                                | | | └-----------------┐
345  *                                | | └-----------------┐ |
346  *                                | └-----------------┐ | |
347  *                                └-----------------┐ | | |
348  *                                                  | | | |
349  *                                                  | | | |
350  *    1 0 9 8 7 6 5 4 3 2 1 0 9 8 7 6 5 4 3 2 1 0 9 8 7 6 5 4 3 2 1 0
351  *      3                   2                   1                   0
352  *
353  *   Used in handling following instructions:
354  *
355  *     - MOVEP
356  *     - MOVEP[REV]
357  */
358 static uint64 decode_gpr_gpr2_reg2(uint64 d, Dis_info *info)
359 {
360     static uint64 register_list[] = {  5,  6,  7,  8 };
361     return renumber_registers(d, register_list,
362                sizeof(register_list) / sizeof(register_list[0]), info);
363 }
364 
365 
366 /*
367  * decode_gpr_gpr1() - decoder for 'gpr1' gpr encoding type
368  *
369  *   Map a 1-bit code to the 5-bit register space according to this pattern:
370  *
371  *                                  1 0
372  *                                  | |
373  *                                  | |
374  *                                  | └---------------------┐
375  *                                  └---------------------┐ |
376  *                                                        | |
377  *                                                        | |
378  *                                                        | |
379  *                                                        | |
380  *    1 0 9 8 7 6 5 4 3 2 1 0 9 8 7 6 5 4 3 2 1 0 9 8 7 6 5 4 3 2 1 0
381  *      3                   2                   1                   0
382  *
383  *   Used in handling following instruction:
384  *
385  *     - MOVE.BALC
386  */
387 static uint64 decode_gpr_gpr1(uint64 d, Dis_info *info)
388 {
389     static uint64 register_list[] = {  4,  5 };
390     return renumber_registers(d, register_list,
391                sizeof(register_list) / sizeof(register_list[0]), info);
392 }
393 
394 
395 static int64 neg_copy(uint64 d)
396 {
397     return 0ll - d;
398 }
399 
400 
401 static uint64 encode_count3_from_count(uint64 d)
402 {
403     IMGASSERTONCE(d < 8);
404     return d == 0ull ? 8ull : d;
405 }
406 
407 
408 static uint64 encode_shift3_from_shift(uint64 d)
409 {
410     IMGASSERTONCE(d < 8);
411     return d == 0ull ? 8ull : d;
412 }
413 
414 
415 /* special value for load literal */
416 static int64 encode_eu_from_s_li16(uint64 d)
417 {
418     IMGASSERTONCE(d < 128);
419     return d == 127 ? -1 : (int64)d;
420 }
421 
422 
423 static uint64 encode_msbd_from_size(uint64 d)
424 {
425     IMGASSERTONCE(d < 32);
426     return d + 1;
427 }
428 
429 
430 static uint64 encode_eu_from_u_andi16(uint64 d)
431 {
432     IMGASSERTONCE(d < 16);
433     if (d == 12) {
434         return 0x00ffull;
435     }
436     if (d == 13) {
437         return 0xffffull;
438     }
439     return d;
440 }
441 
442 
443 /* save16 / restore16   ???? */
444 static uint64 encode_rt1_from_rt(uint64 d)
445 {
446     return d ? 31 : 30;
447 }
448 
449 
450 static const char *GPR(uint64 reg, Dis_info *info)
451 {
452     static const char *gpr_reg[32] = {
453         "zero", "at",   "v0",   "v1",   "a0",   "a1",   "a2",   "a3",
454         "a4",   "a5",   "a6",   "a7",   "r12",  "r13",  "r14",  "r15",
455         "s0",   "s1",   "s2",   "s3",   "s4",   "s5",   "s6",   "s7",
456         "r24",  "r25",  "k0",   "k1",   "gp",   "sp",   "fp",   "ra"
457     };
458 
459     if (reg < 32) {
460         return gpr_reg[reg];
461     }
462 
463     info->fprintf_func(info->stream, "Invalid GPR register index %" PRIu64,
464                        reg);
465     siglongjmp(info->buf, 1);
466 }
467 
468 
469 static char *save_restore_list(uint64 rt, uint64 count, uint64 gp,
470                                Dis_info *info)
471 {
472     char *reg_list[34];
473     reg_list[0] = (char *)"";
474 
475     assert(count <= 32);
476     for (uint64 counter = 0; counter != count; counter++) {
477         bool use_gp = gp && (counter == count - 1);
478         uint64 this_rt = use_gp ? 28 : ((rt & 0x10) | (rt + counter)) & 0x1f;
479         /* glib usage below requires casting away const */
480         reg_list[counter + 1] = (char *)GPR(this_rt, info);
481     }
482     reg_list[count + 1] = NULL;
483 
484     return g_strjoinv(",", reg_list);
485 }
486 
487 
488 static const char *FPR(uint64 reg, Dis_info *info)
489 {
490     static const char *fpr_reg[32] = {
491         "f0",  "f1",  "f2",  "f3",  "f4",  "f5",  "f6",  "f7",
492         "f8",  "f9",  "f10", "f11", "f12", "f13", "f14", "f15",
493         "f16", "f17", "f18", "f19", "f20", "f21", "f22", "f23",
494         "f24", "f25", "f26", "f27", "f28", "f29", "f30", "f31"
495     };
496 
497     if (reg < 32) {
498         return fpr_reg[reg];
499     }
500 
501     info->fprintf_func(info->stream, "Invalid FPR register index %" PRIu64,
502                        reg);
503     siglongjmp(info->buf, 1);
504 }
505 
506 
507 static const char *AC(uint64 reg, Dis_info *info)
508 {
509     static const char *ac_reg[4] = {
510         "ac0",  "ac1",  "ac2",  "ac3"
511     };
512 
513     if (reg < 4) {
514         return ac_reg[reg];
515     }
516 
517     info->fprintf_func(info->stream, "Invalid AC register index %" PRIu64,
518                        reg);
519     siglongjmp(info->buf, 1);
520 }
521 
522 
523 static char *ADDRESS(uint64 value, int instruction_size, Dis_info *info)
524 {
525     /* token for string replace */
526     img_address address = info->m_pc + value + instruction_size;
527     /* symbol replacement */
528     return to_string(address);
529 }
530 
531 
532 static uint64 extract_op_code_value(const uint16 *data, int size)
533 {
534     switch (size) {
535     case 16:
536         return data[0];
537     case 32:
538         return ((uint64)data[0] << 16) | data[1];
539     case 48:
540         return ((uint64)data[0] << 32) | ((uint64)data[1] << 16) | data[2];
541     default:
542         return data[0];
543     }
544 }
545 
546 
547 /*
548  * Recurse through tables until the instruction is found then return
549  * the string and size
550  *
551  * inputs:
552  *      pointer to a word stream,
553  *      disassember table and size
554  * returns:
555  *      instruction size    - negative is error
556  *      disassembly string  - on error will constain error string
557  */
558 static int Disassemble(const uint16 *data, char **dis,
559                      TABLE_ENTRY_TYPE *type, const Pool *table,
560                      int table_size, Dis_info *info)
561 {
562     for (int i = 0; i < table_size; i++) {
563         uint64 op_code = extract_op_code_value(data,
564                              table[i].instructions_size);
565         if ((op_code & table[i].mask) == table[i].value) {
566             /* possible match */
567             conditional_function cond = table[i].condition;
568             if ((cond == NULL) || cond(op_code)) {
569                 if (table[i].type == pool) {
570                     return Disassemble(data, dis, type,
571                                        table[i].next_table,
572                                        table[i].next_table_size,
573                                        info);
574                 } else if ((table[i].type == instruction) ||
575                            (table[i].type == call_instruction) ||
576                            (table[i].type == branch_instruction) ||
577                            (table[i].type == return_instruction)) {
578                     disassembly_function dis_fn = table[i].disassembly;
579                     if (dis_fn == 0) {
580                         *dis = g_strdup(
581                             "disassembler failure - bad table entry");
582                         return -6;
583                     }
584                     *type = table[i].type;
585                     *dis = dis_fn(op_code, info);
586                     return table[i].instructions_size;
587                 } else {
588                     *dis = g_strdup("reserved instruction");
589                     return -2;
590                 }
591             }
592         }
593     }
594     *dis = g_strdup("failed to disassemble");
595     return -1;      /* failed to disassemble        */
596 }
597 
598 
599 static uint64 extract_code_18_to_0(uint64 instruction)
600 {
601     uint64 value = 0;
602     value |= extract_bits(instruction, 0, 19);
603     return value;
604 }
605 
606 
607 static uint64 extract_shift3_2_1_0(uint64 instruction)
608 {
609     uint64 value = 0;
610     value |= extract_bits(instruction, 0, 3);
611     return value;
612 }
613 
614 
615 static uint64 extract_u_11_10_9_8_7_6_5_4_3__s3(uint64 instruction)
616 {
617     uint64 value = 0;
618     value |= extract_bits(instruction, 3, 9) << 3;
619     return value;
620 }
621 
622 
623 static uint64 extract_count_3_2_1_0(uint64 instruction)
624 {
625     uint64 value = 0;
626     value |= extract_bits(instruction, 0, 4);
627     return value;
628 }
629 
630 
631 static uint64 extract_rtz3_9_8_7(uint64 instruction)
632 {
633     uint64 value = 0;
634     value |= extract_bits(instruction, 7, 3);
635     return value;
636 }
637 
638 
639 static uint64 extract_u_17_to_1__s1(uint64 instruction)
640 {
641     uint64 value = 0;
642     value |= extract_bits(instruction, 1, 17) << 1;
643     return value;
644 }
645 
646 
647 static int64 extract_s__se9_20_19_18_17_16_15_14_13_12_11(uint64 instruction)
648 {
649     int64 value = 0;
650     value |= extract_bits(instruction, 11, 10);
651     value = sign_extend(value, 9);
652     return value;
653 }
654 
655 
656 static int64 extract_s__se11_0_10_9_8_7_6_5_4_3_2_1_0_s1(uint64 instruction)
657 {
658     int64 value = 0;
659     value |= extract_bits(instruction, 0, 1) << 11;
660     value |= extract_bits(instruction, 1, 10) << 1;
661     value = sign_extend(value, 11);
662     return value;
663 }
664 
665 
666 static uint64 extract_u_10(uint64 instruction)
667 {
668     uint64 value = 0;
669     value |= extract_bits(instruction, 10, 1);
670     return value;
671 }
672 
673 
674 static uint64 extract_rtz4_27_26_25_23_22_21(uint64 instruction)
675 {
676     uint64 value = 0;
677     value |= extract_bits(instruction, 21, 3);
678     value |= extract_bits(instruction, 25, 1) << 3;
679     return value;
680 }
681 
682 
683 static uint64 extract_sa_15_14_13_12_11(uint64 instruction)
684 {
685     uint64 value = 0;
686     value |= extract_bits(instruction, 11, 5);
687     return value;
688 }
689 
690 
691 static uint64 extract_shift_4_3_2_1_0(uint64 instruction)
692 {
693     uint64 value = 0;
694     value |= extract_bits(instruction, 0, 5);
695     return value;
696 }
697 
698 
699 static uint64 extract_shiftx_10_9_8_7__s1(uint64 instruction)
700 {
701     uint64 value = 0;
702     value |= extract_bits(instruction, 7, 4) << 1;
703     return value;
704 }
705 
706 
707 static uint64 extract_hint_25_24_23_22_21(uint64 instruction)
708 {
709     uint64 value = 0;
710     value |= extract_bits(instruction, 21, 5);
711     return value;
712 }
713 
714 
715 static uint64 extract_count3_14_13_12(uint64 instruction)
716 {
717     uint64 value = 0;
718     value |= extract_bits(instruction, 12, 3);
719     return value;
720 }
721 
722 
723 static int64 extract_s__se31_0_11_to_2_20_to_12_s12(uint64 instruction)
724 {
725     int64 value = 0;
726     value |= extract_bits(instruction, 0, 1) << 31;
727     value |= extract_bits(instruction, 2, 10) << 21;
728     value |= extract_bits(instruction, 12, 9) << 12;
729     value = sign_extend(value, 31);
730     return value;
731 }
732 
733 
734 static int64 extract_s__se7_0_6_5_4_3_2_1_s1(uint64 instruction)
735 {
736     int64 value = 0;
737     value |= extract_bits(instruction, 0, 1) << 7;
738     value |= extract_bits(instruction, 1, 6) << 1;
739     value = sign_extend(value, 7);
740     return value;
741 }
742 
743 
744 static uint64 extract_u2_10_9(uint64 instruction)
745 {
746     uint64 value = 0;
747     value |= extract_bits(instruction, 9, 2);
748     return value;
749 }
750 
751 
752 static uint64 extract_code_25_24_23_22_21_20_19_18_17_16(uint64 instruction)
753 {
754     uint64 value = 0;
755     value |= extract_bits(instruction, 16, 10);
756     return value;
757 }
758 
759 
760 static uint64 extract_rs_20_19_18_17_16(uint64 instruction)
761 {
762     uint64 value = 0;
763     value |= extract_bits(instruction, 16, 5);
764     return value;
765 }
766 
767 
768 static uint64 extract_u_2_1__s1(uint64 instruction)
769 {
770     uint64 value = 0;
771     value |= extract_bits(instruction, 1, 2) << 1;
772     return value;
773 }
774 
775 
776 static uint64 extract_stripe_6(uint64 instruction)
777 {
778     uint64 value = 0;
779     value |= extract_bits(instruction, 6, 1);
780     return value;
781 }
782 
783 
784 static uint64 extract_ac_15_14(uint64 instruction)
785 {
786     uint64 value = 0;
787     value |= extract_bits(instruction, 14, 2);
788     return value;
789 }
790 
791 
792 static uint64 extract_shift_20_19_18_17_16(uint64 instruction)
793 {
794     uint64 value = 0;
795     value |= extract_bits(instruction, 16, 5);
796     return value;
797 }
798 
799 
800 static uint64 extract_rdl_25_24(uint64 instruction)
801 {
802     uint64 value = 0;
803     value |= extract_bits(instruction, 24, 1);
804     return value;
805 }
806 
807 
808 static int64 extract_s__se10_0_9_8_7_6_5_4_3_2_1_s1(uint64 instruction)
809 {
810     int64 value = 0;
811     value |= extract_bits(instruction, 0, 1) << 10;
812     value |= extract_bits(instruction, 1, 9) << 1;
813     value = sign_extend(value, 10);
814     return value;
815 }
816 
817 
818 static uint64 extract_eu_6_5_4_3_2_1_0(uint64 instruction)
819 {
820     uint64 value = 0;
821     value |= extract_bits(instruction, 0, 7);
822     return value;
823 }
824 
825 
826 static uint64 extract_shift_5_4_3_2_1_0(uint64 instruction)
827 {
828     uint64 value = 0;
829     value |= extract_bits(instruction, 0, 6);
830     return value;
831 }
832 
833 
834 static uint64 extract_count_19_18_17_16(uint64 instruction)
835 {
836     uint64 value = 0;
837     value |= extract_bits(instruction, 16, 4);
838     return value;
839 }
840 
841 
842 static uint64 extract_code_2_1_0(uint64 instruction)
843 {
844     uint64 value = 0;
845     value |= extract_bits(instruction, 0, 3);
846     return value;
847 }
848 
849 
850 static uint64 extract_u_11_10_9_8_7_6_5_4_3_2_1_0(uint64 instruction)
851 {
852     uint64 value = 0;
853     value |= extract_bits(instruction, 0, 12);
854     return value;
855 }
856 
857 
858 static uint64 extract_rs_4_3_2_1_0(uint64 instruction)
859 {
860     uint64 value = 0;
861     value |= extract_bits(instruction, 0, 5);
862     return value;
863 }
864 
865 
866 static uint64 extract_u_20_to_3__s3(uint64 instruction)
867 {
868     uint64 value = 0;
869     value |= extract_bits(instruction, 3, 18) << 3;
870     return value;
871 }
872 
873 
874 static uint64 extract_u_3_2_1_0__s2(uint64 instruction)
875 {
876     uint64 value = 0;
877     value |= extract_bits(instruction, 0, 4) << 2;
878     return value;
879 }
880 
881 
882 static uint64 extract_cofun_25_24_23(uint64 instruction)
883 {
884     uint64 value = 0;
885     value |= extract_bits(instruction, 3, 23);
886     return value;
887 }
888 
889 
890 static uint64 extract_u_2_1_0__s2(uint64 instruction)
891 {
892     uint64 value = 0;
893     value |= extract_bits(instruction, 0, 3) << 2;
894     return value;
895 }
896 
897 
898 static uint64 extract_rd3_3_2_1(uint64 instruction)
899 {
900     uint64 value = 0;
901     value |= extract_bits(instruction, 1, 3);
902     return value;
903 }
904 
905 
906 static uint64 extract_sa_15_14_13_12(uint64 instruction)
907 {
908     uint64 value = 0;
909     value |= extract_bits(instruction, 12, 4);
910     return value;
911 }
912 
913 
914 static uint64 extract_rt_25_24_23_22_21(uint64 instruction)
915 {
916     uint64 value = 0;
917     value |= extract_bits(instruction, 21, 5);
918     return value;
919 }
920 
921 
922 static uint64 extract_ru_7_6_5_4_3(uint64 instruction)
923 {
924     uint64 value = 0;
925     value |= extract_bits(instruction, 3, 5);
926     return value;
927 }
928 
929 
930 static uint64 extract_u_17_to_0(uint64 instruction)
931 {
932     uint64 value = 0;
933     value |= extract_bits(instruction, 0, 18);
934     return value;
935 }
936 
937 
938 static uint64 extract_rsz4_4_2_1_0(uint64 instruction)
939 {
940     uint64 value = 0;
941     value |= extract_bits(instruction, 0, 3);
942     value |= extract_bits(instruction, 4, 1) << 3;
943     return value;
944 }
945 
946 
947 static int64 extract_s__se21_0_20_to_1_s1(uint64 instruction)
948 {
949     int64 value = 0;
950     value |= extract_bits(instruction, 0, 1) << 21;
951     value |= extract_bits(instruction, 1, 20) << 1;
952     value = sign_extend(value, 21);
953     return value;
954 }
955 
956 
957 static uint64 extract_op_25_to_3(uint64 instruction)
958 {
959     uint64 value = 0;
960     value |= extract_bits(instruction, 3, 23);
961     return value;
962 }
963 
964 
965 static uint64 extract_rs4_4_2_1_0(uint64 instruction)
966 {
967     uint64 value = 0;
968     value |= extract_bits(instruction, 0, 3);
969     value |= extract_bits(instruction, 4, 1) << 3;
970     return value;
971 }
972 
973 
974 static uint64 extract_bit_23_22_21(uint64 instruction)
975 {
976     uint64 value = 0;
977     value |= extract_bits(instruction, 21, 3);
978     return value;
979 }
980 
981 
982 static uint64 extract_rt_41_40_39_38_37(uint64 instruction)
983 {
984     uint64 value = 0;
985     value |= extract_bits(instruction, 37, 5);
986     return value;
987 }
988 
989 
990 static int64 extract_shift__se5_21_20_19_18_17_16(uint64 instruction)
991 {
992     int64 value = 0;
993     value |= extract_bits(instruction, 16, 6);
994     value = sign_extend(value, 5);
995     return value;
996 }
997 
998 
999 static uint64 extract_rd2_3_8(uint64 instruction)
1000 {
1001     uint64 value = 0;
1002     value |= extract_bits(instruction, 3, 1) << 1;
1003     value |= extract_bits(instruction, 8, 1);
1004     return value;
1005 }
1006 
1007 
1008 static uint64 extract_code_17_to_0(uint64 instruction)
1009 {
1010     uint64 value = 0;
1011     value |= extract_bits(instruction, 0, 18);
1012     return value;
1013 }
1014 
1015 
1016 static uint64 extract_size_20_19_18_17_16(uint64 instruction)
1017 {
1018     uint64 value = 0;
1019     value |= extract_bits(instruction, 16, 5);
1020     return value;
1021 }
1022 
1023 
1024 static int64 extract_s__se8_15_7_6_5_4_3_2_s2(uint64 instruction)
1025 {
1026     int64 value = 0;
1027     value |= extract_bits(instruction, 2, 6) << 2;
1028     value |= extract_bits(instruction, 15, 1) << 8;
1029     value = sign_extend(value, 8);
1030     return value;
1031 }
1032 
1033 
1034 static uint64 extract_u_15_to_0(uint64 instruction)
1035 {
1036     uint64 value = 0;
1037     value |= extract_bits(instruction, 0, 16);
1038     return value;
1039 }
1040 
1041 
1042 static uint64 extract_fs_20_19_18_17_16(uint64 instruction)
1043 {
1044     uint64 value = 0;
1045     value |= extract_bits(instruction, 16, 5);
1046     return value;
1047 }
1048 
1049 
1050 static int64 extract_s__se8_15_7_6_5_4_3_2_1_0(uint64 instruction)
1051 {
1052     int64 value = 0;
1053     value |= extract_bits(instruction, 0, 8);
1054     value |= extract_bits(instruction, 15, 1) << 8;
1055     value = sign_extend(value, 8);
1056     return value;
1057 }
1058 
1059 
1060 static uint64 extract_stype_20_19_18_17_16(uint64 instruction)
1061 {
1062     uint64 value = 0;
1063     value |= extract_bits(instruction, 16, 5);
1064     return value;
1065 }
1066 
1067 
1068 static uint64 extract_rtl_11(uint64 instruction)
1069 {
1070     uint64 value = 0;
1071     value |= extract_bits(instruction, 9, 1);
1072     return value;
1073 }
1074 
1075 
1076 static uint64 extract_hs_20_19_18_17_16(uint64 instruction)
1077 {
1078     uint64 value = 0;
1079     value |= extract_bits(instruction, 16, 5);
1080     return value;
1081 }
1082 
1083 
1084 static uint64 extract_sel_13_12_11(uint64 instruction)
1085 {
1086     uint64 value = 0;
1087     value |= extract_bits(instruction, 11, 3);
1088     return value;
1089 }
1090 
1091 
1092 static uint64 extract_lsb_4_3_2_1_0(uint64 instruction)
1093 {
1094     uint64 value = 0;
1095     value |= extract_bits(instruction, 0, 5);
1096     return value;
1097 }
1098 
1099 
1100 static uint64 extract_gp_2(uint64 instruction)
1101 {
1102     uint64 value = 0;
1103     value |= extract_bits(instruction, 2, 1);
1104     return value;
1105 }
1106 
1107 
1108 static uint64 extract_rt3_9_8_7(uint64 instruction)
1109 {
1110     uint64 value = 0;
1111     value |= extract_bits(instruction, 7, 3);
1112     return value;
1113 }
1114 
1115 
1116 static uint64 extract_ft_25_24_23_22_21(uint64 instruction)
1117 {
1118     uint64 value = 0;
1119     value |= extract_bits(instruction, 21, 5);
1120     return value;
1121 }
1122 
1123 
1124 static uint64 extract_u_17_16_15_14_13_12_11(uint64 instruction)
1125 {
1126     uint64 value = 0;
1127     value |= extract_bits(instruction, 11, 7);
1128     return value;
1129 }
1130 
1131 
1132 static uint64 extract_cs_20_19_18_17_16(uint64 instruction)
1133 {
1134     uint64 value = 0;
1135     value |= extract_bits(instruction, 16, 5);
1136     return value;
1137 }
1138 
1139 
1140 static uint64 extract_rt4_9_7_6_5(uint64 instruction)
1141 {
1142     uint64 value = 0;
1143     value |= extract_bits(instruction, 5, 3);
1144     value |= extract_bits(instruction, 9, 1) << 3;
1145     return value;
1146 }
1147 
1148 
1149 static uint64 extract_msbt_10_9_8_7_6(uint64 instruction)
1150 {
1151     uint64 value = 0;
1152     value |= extract_bits(instruction, 6, 5);
1153     return value;
1154 }
1155 
1156 
1157 static uint64 extract_u_5_4_3_2_1_0__s2(uint64 instruction)
1158 {
1159     uint64 value = 0;
1160     value |= extract_bits(instruction, 0, 6) << 2;
1161     return value;
1162 }
1163 
1164 
1165 static uint64 extract_sa_15_14_13(uint64 instruction)
1166 {
1167     uint64 value = 0;
1168     value |= extract_bits(instruction, 13, 3);
1169     return value;
1170 }
1171 
1172 
1173 static int64 extract_s__se14_0_13_to_1_s1(uint64 instruction)
1174 {
1175     int64 value = 0;
1176     value |= extract_bits(instruction, 0, 1) << 14;
1177     value |= extract_bits(instruction, 1, 13) << 1;
1178     value = sign_extend(value, 14);
1179     return value;
1180 }
1181 
1182 
1183 static uint64 extract_rs3_6_5_4(uint64 instruction)
1184 {
1185     uint64 value = 0;
1186     value |= extract_bits(instruction, 4, 3);
1187     return value;
1188 }
1189 
1190 
1191 static uint64 extract_u_31_to_0__s32(uint64 instruction)
1192 {
1193     uint64 value = 0;
1194     value |= extract_bits(instruction, 0, 32) << 32;
1195     return value;
1196 }
1197 
1198 
1199 static uint64 extract_shift_10_9_8_7_6(uint64 instruction)
1200 {
1201     uint64 value = 0;
1202     value |= extract_bits(instruction, 6, 5);
1203     return value;
1204 }
1205 
1206 
1207 static uint64 extract_cs_25_24_23_22_21(uint64 instruction)
1208 {
1209     uint64 value = 0;
1210     value |= extract_bits(instruction, 21, 5);
1211     return value;
1212 }
1213 
1214 
1215 static uint64 extract_shiftx_11_10_9_8_7_6(uint64 instruction)
1216 {
1217     uint64 value = 0;
1218     value |= extract_bits(instruction, 6, 6);
1219     return value;
1220 }
1221 
1222 
1223 static uint64 extract_rt_9_8_7_6_5(uint64 instruction)
1224 {
1225     uint64 value = 0;
1226     value |= extract_bits(instruction, 5, 5);
1227     return value;
1228 }
1229 
1230 
1231 static uint64 extract_op_25_24_23_22_21(uint64 instruction)
1232 {
1233     uint64 value = 0;
1234     value |= extract_bits(instruction, 21, 5);
1235     return value;
1236 }
1237 
1238 
1239 static uint64 extract_u_6_5_4_3_2_1_0__s2(uint64 instruction)
1240 {
1241     uint64 value = 0;
1242     value |= extract_bits(instruction, 0, 7) << 2;
1243     return value;
1244 }
1245 
1246 
1247 static uint64 extract_bit_16_15_14_13_12_11(uint64 instruction)
1248 {
1249     uint64 value = 0;
1250     value |= extract_bits(instruction, 11, 6);
1251     return value;
1252 }
1253 
1254 
1255 static uint64 extract_mask_20_19_18_17_16_15_14(uint64 instruction)
1256 {
1257     uint64 value = 0;
1258     value |= extract_bits(instruction, 14, 7);
1259     return value;
1260 }
1261 
1262 
1263 static uint64 extract_eu_3_2_1_0(uint64 instruction)
1264 {
1265     uint64 value = 0;
1266     value |= extract_bits(instruction, 0, 4);
1267     return value;
1268 }
1269 
1270 
1271 static uint64 extract_u_7_6_5_4__s4(uint64 instruction)
1272 {
1273     uint64 value = 0;
1274     value |= extract_bits(instruction, 4, 4) << 4;
1275     return value;
1276 }
1277 
1278 
1279 static int64 extract_s__se8_15_7_6_5_4_3_s3(uint64 instruction)
1280 {
1281     int64 value = 0;
1282     value |= extract_bits(instruction, 3, 5) << 3;
1283     value |= extract_bits(instruction, 15, 1) << 8;
1284     value = sign_extend(value, 8);
1285     return value;
1286 }
1287 
1288 
1289 static uint64 extract_ft_15_14_13_12_11(uint64 instruction)
1290 {
1291     uint64 value = 0;
1292     value |= extract_bits(instruction, 11, 5);
1293     return value;
1294 }
1295 
1296 
1297 static int64 extract_s__se31_15_to_0_31_to_16(uint64 instruction)
1298 {
1299     int64 value = 0;
1300     value |= extract_bits(instruction, 0, 16) << 16;
1301     value |= extract_bits(instruction, 16, 16);
1302     value = sign_extend(value, 31);
1303     return value;
1304 }
1305 
1306 
1307 static uint64 extract_u_20_19_18_17_16_15_14_13(uint64 instruction)
1308 {
1309     uint64 value = 0;
1310     value |= extract_bits(instruction, 13, 8);
1311     return value;
1312 }
1313 
1314 
1315 static uint64 extract_u_17_to_2__s2(uint64 instruction)
1316 {
1317     uint64 value = 0;
1318     value |= extract_bits(instruction, 2, 16) << 2;
1319     return value;
1320 }
1321 
1322 
1323 static uint64 extract_rd_15_14_13_12_11(uint64 instruction)
1324 {
1325     uint64 value = 0;
1326     value |= extract_bits(instruction, 11, 5);
1327     return value;
1328 }
1329 
1330 
1331 static uint64 extract_c0s_20_19_18_17_16(uint64 instruction)
1332 {
1333     uint64 value = 0;
1334     value |= extract_bits(instruction, 16, 5);
1335     return value;
1336 }
1337 
1338 
1339 static uint64 extract_code_1_0(uint64 instruction)
1340 {
1341     uint64 value = 0;
1342     value |= extract_bits(instruction, 0, 2);
1343     return value;
1344 }
1345 
1346 
1347 static int64 extract_s__se25_0_24_to_1_s1(uint64 instruction)
1348 {
1349     int64 value = 0;
1350     value |= extract_bits(instruction, 0, 1) << 25;
1351     value |= extract_bits(instruction, 1, 24) << 1;
1352     value = sign_extend(value, 25);
1353     return value;
1354 }
1355 
1356 
1357 static uint64 extract_u_1_0(uint64 instruction)
1358 {
1359     uint64 value = 0;
1360     value |= extract_bits(instruction, 0, 2);
1361     return value;
1362 }
1363 
1364 
1365 static uint64 extract_u_3_8__s2(uint64 instruction)
1366 {
1367     uint64 value = 0;
1368     value |= extract_bits(instruction, 3, 1) << 3;
1369     value |= extract_bits(instruction, 8, 1) << 2;
1370     return value;
1371 }
1372 
1373 
1374 static uint64 extract_fd_15_14_13_12_11(uint64 instruction)
1375 {
1376     uint64 value = 0;
1377     value |= extract_bits(instruction, 11, 5);
1378     return value;
1379 }
1380 
1381 
1382 static uint64 extract_u_4_3_2_1_0__s2(uint64 instruction)
1383 {
1384     uint64 value = 0;
1385     value |= extract_bits(instruction, 0, 5) << 2;
1386     return value;
1387 }
1388 
1389 
1390 static uint64 extract_rtz4_9_7_6_5(uint64 instruction)
1391 {
1392     uint64 value = 0;
1393     value |= extract_bits(instruction, 5, 3);
1394     value |= extract_bits(instruction, 9, 1) << 3;
1395     return value;
1396 }
1397 
1398 
1399 static uint64 extract_sel_15_14_13_12_11(uint64 instruction)
1400 {
1401     uint64 value = 0;
1402     value |= extract_bits(instruction, 11, 5);
1403     return value;
1404 }
1405 
1406 
1407 static uint64 extract_ct_25_24_23_22_21(uint64 instruction)
1408 {
1409     uint64 value = 0;
1410     value |= extract_bits(instruction, 21, 5);
1411     return value;
1412 }
1413 
1414 
1415 static uint64 extract_u_20_to_2__s2(uint64 instruction)
1416 {
1417     uint64 value = 0;
1418     value |= extract_bits(instruction, 2, 19) << 2;
1419     return value;
1420 }
1421 
1422 
1423 static int64 extract_s__se3_4_2_1_0(uint64 instruction)
1424 {
1425     int64 value = 0;
1426     value |= extract_bits(instruction, 0, 3);
1427     value |= extract_bits(instruction, 4, 1) << 3;
1428     value = sign_extend(value, 3);
1429     return value;
1430 }
1431 
1432 
1433 static uint64 extract_u_3_2_1_0__s1(uint64 instruction)
1434 {
1435     uint64 value = 0;
1436     value |= extract_bits(instruction, 0, 4) << 1;
1437     return value;
1438 }
1439 
1440 
1441 
1442 static bool ADDIU_32__cond(uint64 instruction)
1443 {
1444     uint64 rt = extract_rt_25_24_23_22_21(instruction);
1445     return rt != 0;
1446 }
1447 
1448 
1449 static bool ADDIU_RS5__cond(uint64 instruction)
1450 {
1451     uint64 rt = extract_rt_9_8_7_6_5(instruction);
1452     return rt != 0;
1453 }
1454 
1455 
1456 static bool BALRSC_cond(uint64 instruction)
1457 {
1458     uint64 rt = extract_rt_25_24_23_22_21(instruction);
1459     return rt != 0;
1460 }
1461 
1462 
1463 static bool BEQC_16__cond(uint64 instruction)
1464 {
1465     uint64 rs3 = extract_rs3_6_5_4(instruction);
1466     uint64 rt3 = extract_rt3_9_8_7(instruction);
1467     uint64 u = extract_u_3_2_1_0__s1(instruction);
1468     return rs3 < rt3 && u != 0;
1469 }
1470 
1471 
1472 static bool BNEC_16__cond(uint64 instruction)
1473 {
1474     uint64 rs3 = extract_rs3_6_5_4(instruction);
1475     uint64 rt3 = extract_rt3_9_8_7(instruction);
1476     uint64 u = extract_u_3_2_1_0__s1(instruction);
1477     return rs3 >= rt3 && u != 0;
1478 }
1479 
1480 
1481 static bool MOVE_cond(uint64 instruction)
1482 {
1483     uint64 rt = extract_rt_9_8_7_6_5(instruction);
1484     return rt != 0;
1485 }
1486 
1487 
1488 static bool P16_BR1_cond(uint64 instruction)
1489 {
1490     uint64 u = extract_u_3_2_1_0__s1(instruction);
1491     return u != 0;
1492 }
1493 
1494 
1495 static bool PREF_S9__cond(uint64 instruction)
1496 {
1497     uint64 hint = extract_hint_25_24_23_22_21(instruction);
1498     return hint != 31;
1499 }
1500 
1501 
1502 static bool PREFE_cond(uint64 instruction)
1503 {
1504     uint64 hint = extract_hint_25_24_23_22_21(instruction);
1505     return hint != 31;
1506 }
1507 
1508 
1509 static bool SLTU_cond(uint64 instruction)
1510 {
1511     uint64 rd = extract_rd_15_14_13_12_11(instruction);
1512     return rd != 0;
1513 }
1514 
1515 
1516 
1517 /*
1518  * ABS.D fd, fs - Floating Point Absolute Value
1519  *
1520  *   3         2         1
1521  *  10987654321098765432109876543210
1522  *  010001     00000          000101
1523  *    fmt -----
1524  *               fs -----
1525  *                    fd -----
1526  */
1527 static char *ABS_D(uint64 instruction, Dis_info *info)
1528 {
1529     uint64 fd_value = extract_ft_25_24_23_22_21(instruction);
1530     uint64 fs_value = extract_fs_20_19_18_17_16(instruction);
1531 
1532     const char *fs = FPR(fs_value, info);
1533     const char *fd = FPR(fd_value, info);
1534 
1535     return img_format("ABS.D %s, %s", fd, fs);
1536 }
1537 
1538 
1539 /*
1540  * ABS.S fd, fs - Floating Point Absolute Value
1541  *
1542  *   3         2         1
1543  *  10987654321098765432109876543210
1544  *  010001     00000          000101
1545  *    fmt -----
1546  *               fd -----
1547  *                    fs -----
1548  */
1549 static char *ABS_S(uint64 instruction, Dis_info *info)
1550 {
1551     uint64 fd_value = extract_ft_25_24_23_22_21(instruction);
1552     uint64 fs_value = extract_fs_20_19_18_17_16(instruction);
1553 
1554     const char *fs = FPR(fs_value, info);
1555     const char *fd = FPR(fd_value, info);
1556 
1557     return img_format("ABS.S %s, %s", fd, fs);
1558 }
1559 
1560 
1561 /*
1562  * [DSP] ABSQ_S.PH rt, rs - Find absolute value of two fractional halfwords
1563  *         with 16-bit saturation
1564  *
1565  *   3         2         1
1566  *  10987654321098765432109876543210
1567  *  001000          0001000100111111
1568  *     rt -----
1569  *          rs -----
1570  */
1571 static char *ABSQ_S_PH(uint64 instruction, Dis_info *info)
1572 {
1573     uint64 rt_value = extract_rt_25_24_23_22_21(instruction);
1574     uint64 rs_value = extract_rs_20_19_18_17_16(instruction);
1575 
1576     const char *rt = GPR(rt_value, info);
1577     const char *rs = GPR(rs_value, info);
1578 
1579     return img_format("ABSQ_S.PH %s, %s", rt, rs);
1580 }
1581 
1582 
1583 /*
1584  * [DSP] ABSQ_S.QB rt, rs - Find absolute value of four fractional byte values
1585  *         with 8-bit saturation
1586  *
1587  *   3         2         1
1588  *  10987654321098765432109876543210
1589  *  001000          0000000100111111
1590  *     rt -----
1591  *          rs -----
1592  */
1593 static char *ABSQ_S_QB(uint64 instruction, Dis_info *info)
1594 {
1595     uint64 rt_value = extract_rt_25_24_23_22_21(instruction);
1596     uint64 rs_value = extract_rs_20_19_18_17_16(instruction);
1597 
1598     const char *rt = GPR(rt_value, info);
1599     const char *rs = GPR(rs_value, info);
1600 
1601     return img_format("ABSQ_S.QB %s, %s", rt, rs);
1602 }
1603 
1604 
1605 /*
1606  * [DSP] ABSQ_S.W rt, rs - Find absolute value of fractional word with 32-bit
1607  *         saturation
1608  *
1609  *   3         2         1
1610  *  10987654321098765432109876543210
1611  *  001000          0010000100111111
1612  *     rt -----
1613  *          rs -----
1614  */
1615 static char *ABSQ_S_W(uint64 instruction, Dis_info *info)
1616 {
1617     uint64 rt_value = extract_rt_25_24_23_22_21(instruction);
1618     uint64 rs_value = extract_rs_20_19_18_17_16(instruction);
1619 
1620     const char *rt = GPR(rt_value, info);
1621     const char *rs = GPR(rs_value, info);
1622 
1623     return img_format("ABSQ_S.W %s, %s", rt, rs);
1624 }
1625 
1626 
1627 /*
1628  *
1629  *
1630  *   3         2         1
1631  *  10987654321098765432109876543210
1632  *  001000          0010000100111111
1633  *     rt -----
1634  *          rs -----
1635  */
1636 static char *ACLR(uint64 instruction, Dis_info *info)
1637 {
1638     uint64 bit_value = extract_bit_23_22_21(instruction);
1639     uint64 rs_value = extract_rs_20_19_18_17_16(instruction);
1640     int64 s_value = extract_s__se8_15_7_6_5_4_3_2_1_0(instruction);
1641 
1642     const char *rs = GPR(rs_value, info);
1643 
1644     return img_format("ACLR 0x%" PRIx64 ", %" PRId64 "(%s)",
1645                       bit_value, s_value, rs);
1646 }
1647 
1648 
1649 /*
1650  *
1651  *
1652  *   3         2         1
1653  *  10987654321098765432109876543210
1654  *  001000          0010000100111111
1655  *     rt -----
1656  *          rs -----
1657  */
1658 static char *ADD(uint64 instruction, Dis_info *info)
1659 {
1660     uint64 rt_value = extract_rt_25_24_23_22_21(instruction);
1661     uint64 rs_value = extract_rs_20_19_18_17_16(instruction);
1662     uint64 rd_value = extract_rd_15_14_13_12_11(instruction);
1663 
1664     const char *rd = GPR(rd_value, info);
1665     const char *rs = GPR(rs_value, info);
1666     const char *rt = GPR(rt_value, info);
1667 
1668     return img_format("ADD %s, %s, %s", rd, rs, rt);
1669 }
1670 
1671 
1672 /*
1673  * ADD.D fd, fs, ft - Floating Point Add
1674  *
1675  *   3         2         1
1676  *  10987654321098765432109876543210
1677  *  010001                    000101
1678  *    fmt -----
1679  *          ft -----
1680  *               fs -----
1681  *                    fd -----
1682  */
1683 static char *ADD_D(uint64 instruction, Dis_info *info)
1684 {
1685     uint64 ft_value = extract_ft_25_24_23_22_21(instruction);
1686     uint64 fs_value = extract_fs_20_19_18_17_16(instruction);
1687     uint64 fd_value = extract_fd_15_14_13_12_11(instruction);
1688 
1689     const char *ft = FPR(ft_value, info);
1690     const char *fs = FPR(fs_value, info);
1691     const char *fd = FPR(fd_value, info);
1692 
1693     return img_format("ADD.D %s, %s, %s", fd, fs, ft);
1694 }
1695 
1696 
1697 /*
1698  * ADD.S fd, fs, ft - Floating Point Add
1699  *
1700  *   3         2         1
1701  *  10987654321098765432109876543210
1702  *  010001                    000101
1703  *    fmt -----
1704  *          ft -----
1705  *               fs -----
1706  *                    fd -----
1707  */
1708 static char *ADD_S(uint64 instruction, Dis_info *info)
1709 {
1710     uint64 ft_value = extract_ft_25_24_23_22_21(instruction);
1711     uint64 fs_value = extract_fs_20_19_18_17_16(instruction);
1712     uint64 fd_value = extract_fd_15_14_13_12_11(instruction);
1713 
1714     const char *ft = FPR(ft_value, info);
1715     const char *fs = FPR(fs_value, info);
1716     const char *fd = FPR(fd_value, info);
1717 
1718     return img_format("ADD.S %s, %s, %s", fd, fs, ft);
1719 }
1720 
1721 
1722 /*
1723  *
1724  *
1725  *   3         2         1
1726  *  10987654321098765432109876543210
1727  *  001000          0010000100111111
1728  *     rt -----
1729  *          rs -----
1730  */
1731 static char *ADDIU_32_(uint64 instruction, Dis_info *info)
1732 {
1733     uint64 rt_value = extract_rt_25_24_23_22_21(instruction);
1734     uint64 rs_value = extract_rs_20_19_18_17_16(instruction);
1735     uint64 u_value = extract_u_15_to_0(instruction);
1736 
1737     const char *rt = GPR(rt_value, info);
1738     const char *rs = GPR(rs_value, info);
1739 
1740     return img_format("ADDIU %s, %s, 0x%" PRIx64, rt, rs, u_value);
1741 }
1742 
1743 
1744 /*
1745  *
1746  *
1747  *   3         2         1
1748  *  10987654321098765432109876543210
1749  *  001000          0010000100111111
1750  *     rt -----
1751  *          rs -----
1752  */
1753 static char *ADDIU_48_(uint64 instruction, Dis_info *info)
1754 {
1755     uint64 rt_value = extract_rt_41_40_39_38_37(instruction);
1756     int64 s_value = extract_s__se31_15_to_0_31_to_16(instruction);
1757 
1758     const char *rt = GPR(rt_value, info);
1759 
1760     return img_format("ADDIU %s, %" PRId64, rt, s_value);
1761 }
1762 
1763 
1764 /*
1765  *
1766  *
1767  *   3         2         1
1768  *  10987654321098765432109876543210
1769  *  001000          0010000100111111
1770  *     rt -----
1771  *          rs -----
1772  */
1773 static char *ADDIU_GP48_(uint64 instruction, Dis_info *info)
1774 {
1775     uint64 rt_value = extract_rt_41_40_39_38_37(instruction);
1776     int64 s_value = extract_s__se31_15_to_0_31_to_16(instruction);
1777 
1778     const char *rt = GPR(rt_value, info);
1779 
1780     return img_format("ADDIU %s, $%d, %" PRId64, rt, 28, s_value);
1781 }
1782 
1783 
1784 /*
1785  *
1786  *
1787  *   3         2         1
1788  *  10987654321098765432109876543210
1789  *  001000          0010000100111111
1790  *     rt -----
1791  *          rs -----
1792  */
1793 static char *ADDIU_GP_B_(uint64 instruction, Dis_info *info)
1794 {
1795     uint64 rt_value = extract_rt_25_24_23_22_21(instruction);
1796     uint64 u_value = extract_u_17_to_0(instruction);
1797 
1798     const char *rt = GPR(rt_value, info);
1799 
1800     return img_format("ADDIU %s, $%d, 0x%" PRIx64, rt, 28, u_value);
1801 }
1802 
1803 
1804 /*
1805  *
1806  *
1807  *   3         2         1
1808  *  10987654321098765432109876543210
1809  *  001000          0010000100111111
1810  *     rt -----
1811  *          rs -----
1812  */
1813 static char *ADDIU_GP_W_(uint64 instruction, Dis_info *info)
1814 {
1815     uint64 rt_value = extract_rt_25_24_23_22_21(instruction);
1816     uint64 u_value = extract_u_20_to_2__s2(instruction);
1817 
1818     const char *rt = GPR(rt_value, info);
1819 
1820     return img_format("ADDIU %s, $%d, 0x%" PRIx64, rt, 28, u_value);
1821 }
1822 
1823 
1824 /*
1825  *
1826  *
1827  *   3         2         1
1828  *  10987654321098765432109876543210
1829  *  001000          0010000100111111
1830  *     rt -----
1831  *          rs -----
1832  */
1833 static char *ADDIU_NEG_(uint64 instruction, Dis_info *info)
1834 {
1835     uint64 rt_value = extract_rt_25_24_23_22_21(instruction);
1836     uint64 rs_value = extract_rs_20_19_18_17_16(instruction);
1837     uint64 u_value = extract_u_11_10_9_8_7_6_5_4_3_2_1_0(instruction);
1838 
1839     const char *rt = GPR(rt_value, info);
1840     const char *rs = GPR(rs_value, info);
1841     int64 u = neg_copy(u_value);
1842 
1843     return img_format("ADDIU %s, %s, %" PRId64, rt, rs, u);
1844 }
1845 
1846 
1847 /*
1848  *
1849  *
1850  *   3         2         1
1851  *  10987654321098765432109876543210
1852  *  001000          0010000100111111
1853  *     rt -----
1854  *          rs -----
1855  */
1856 static char *ADDIU_R1_SP_(uint64 instruction, Dis_info *info)
1857 {
1858     uint64 u_value = extract_u_5_4_3_2_1_0__s2(instruction);
1859     uint64 rt3_value = extract_rt3_9_8_7(instruction);
1860 
1861     const char *rt3 = GPR(decode_gpr_gpr3(rt3_value, info), info);
1862 
1863     return img_format("ADDIU %s, $%d, 0x%" PRIx64, rt3, 29, u_value);
1864 }
1865 
1866 
1867 /*
1868  *
1869  *
1870  *   3         2         1
1871  *  10987654321098765432109876543210
1872  *  001000          0010000100111111
1873  *     rt -----
1874  *          rs -----
1875  */
1876 static char *ADDIU_R2_(uint64 instruction, Dis_info *info)
1877 {
1878     uint64 rt3_value = extract_rt3_9_8_7(instruction);
1879     uint64 rs3_value = extract_rs3_6_5_4(instruction);
1880     uint64 u_value = extract_u_2_1_0__s2(instruction);
1881 
1882     const char *rt3 = GPR(decode_gpr_gpr3(rt3_value, info), info);
1883     const char *rs3 = GPR(decode_gpr_gpr3(rs3_value, info), info);
1884 
1885     return img_format("ADDIU %s, %s, 0x%" PRIx64, rt3, rs3, u_value);
1886 }
1887 
1888 
1889 /*
1890  * ADDIU[RS5] rt, s5 - Add Signed Word and Set Carry Bit
1891  *
1892  *  5432109876543210
1893  *  100100      1
1894  *     rt -----
1895  *           s - ---
1896  */
1897 static char *ADDIU_RS5_(uint64 instruction, Dis_info *info)
1898 {
1899     uint64 rt_value = extract_rt_9_8_7_6_5(instruction);
1900     int64 s_value = extract_s__se3_4_2_1_0(instruction);
1901 
1902     const char *rt = GPR(rt_value, info);
1903 
1904     return img_format("ADDIU %s, %" PRId64, rt, s_value);
1905 }
1906 
1907 
1908 /*
1909  *
1910  *
1911  *   3         2         1
1912  *  10987654321098765432109876543210
1913  *  001000               x1110000101
1914  *     rt -----
1915  *          rs -----
1916  *               rd -----
1917  */
1918 static char *ADDIUPC_32_(uint64 instruction, Dis_info *info)
1919 {
1920     uint64 rt_value = extract_rt_25_24_23_22_21(instruction);
1921     int64 s_value = extract_s__se21_0_20_to_1_s1(instruction);
1922 
1923     const char *rt = GPR(rt_value, info);
1924     g_autofree char *s = ADDRESS(s_value, 4, info);
1925 
1926     return img_format("ADDIUPC %s, %s", rt, s);
1927 }
1928 
1929 
1930 /*
1931  *
1932  *
1933  *   3         2         1
1934  *  10987654321098765432109876543210
1935  *  001000               x1110000101
1936  *     rt -----
1937  *          rs -----
1938  *               rd -----
1939  */
1940 static char *ADDIUPC_48_(uint64 instruction, Dis_info *info)
1941 {
1942     uint64 rt_value = extract_rt_41_40_39_38_37(instruction);
1943     int64 s_value = extract_s__se31_15_to_0_31_to_16(instruction);
1944 
1945     const char *rt = GPR(rt_value, info);
1946     g_autofree char *s = ADDRESS(s_value, 6, info);
1947 
1948     return img_format("ADDIUPC %s, %s", rt, s);
1949 }
1950 
1951 
1952 /*
1953  * [DSP] ADDQ.PH rd, rt, rs - Add fractional halfword vectors
1954  *
1955  *   3         2         1
1956  *  10987654321098765432109876543210
1957  *  001000               00000001101
1958  *     rt -----
1959  *          rs -----
1960  *               rd -----
1961  */
1962 static char *ADDQ_PH(uint64 instruction, Dis_info *info)
1963 {
1964     uint64 rt_value = extract_rt_25_24_23_22_21(instruction);
1965     uint64 rs_value = extract_rs_20_19_18_17_16(instruction);
1966     uint64 rd_value = extract_rd_15_14_13_12_11(instruction);
1967 
1968     const char *rd = GPR(rd_value, info);
1969     const char *rs = GPR(rs_value, info);
1970     const char *rt = GPR(rt_value, info);
1971 
1972     return img_format("ADDQ.PH %s, %s, %s", rd, rs, rt);
1973 }
1974 
1975 
1976 /*
1977  * [DSP] ADDQ_S.PH rd, rt, rs - Add fractional halfword vectors with 16-bit
1978  *         saturation
1979  *
1980  *   3         2         1
1981  *  10987654321098765432109876543210
1982  *  001000               10000001101
1983  *     rt -----
1984  *          rs -----
1985  *               rd -----
1986  */
1987 static char *ADDQ_S_PH(uint64 instruction, Dis_info *info)
1988 {
1989     uint64 rt_value = extract_rt_25_24_23_22_21(instruction);
1990     uint64 rs_value = extract_rs_20_19_18_17_16(instruction);
1991     uint64 rd_value = extract_rd_15_14_13_12_11(instruction);
1992 
1993     const char *rd = GPR(rd_value, info);
1994     const char *rs = GPR(rs_value, info);
1995     const char *rt = GPR(rt_value, info);
1996 
1997     return img_format("ADDQ_S.PH %s, %s, %s", rd, rs, rt);
1998 }
1999 
2000 
2001 /*
2002  * [DSP] ADDQ_S.W rd, rt, rs - Add fractional words with 32-bit saturation
2003  *
2004  *   3         2         1
2005  *  10987654321098765432109876543210
2006  *  001000               x1100000101
2007  *     rt -----
2008  *          rs -----
2009  *               rd -----
2010  */
2011 static char *ADDQ_S_W(uint64 instruction, Dis_info *info)
2012 {
2013     uint64 rt_value = extract_rt_25_24_23_22_21(instruction);
2014     uint64 rs_value = extract_rs_20_19_18_17_16(instruction);
2015     uint64 rd_value = extract_rd_15_14_13_12_11(instruction);
2016 
2017     const char *rd = GPR(rd_value, info);
2018     const char *rs = GPR(rs_value, info);
2019     const char *rt = GPR(rt_value, info);
2020 
2021     return img_format("ADDQ_S.W %s, %s, %s", rd, rs, rt);
2022 }
2023 
2024 
2025 /*
2026  * [DSP] ADDQH.PH rd, rt, rs - Add fractional halfword vectors and shift
2027  *         right to halve results
2028  *
2029  *   3         2         1
2030  *  10987654321098765432109876543210
2031  *  001000               00001001101
2032  *     rt -----
2033  *          rs -----
2034  *               rd -----
2035  */
2036 static char *ADDQH_PH(uint64 instruction, Dis_info *info)
2037 {
2038     uint64 rt_value = extract_rt_25_24_23_22_21(instruction);
2039     uint64 rs_value = extract_rs_20_19_18_17_16(instruction);
2040     uint64 rd_value = extract_rd_15_14_13_12_11(instruction);
2041 
2042     const char *rd = GPR(rd_value, info);
2043     const char *rs = GPR(rs_value, info);
2044     const char *rt = GPR(rt_value, info);
2045 
2046     return img_format("ADDQH.PH %s, %s, %s", rd, rs, rt);
2047 }
2048 
2049 
2050 /*
2051  * [DSP] ADDQH_R.PH rd, rt, rs - Add fractional halfword vectors and shift
2052  *         right to halve results with rounding
2053  *
2054  *   3         2         1
2055  *  10987654321098765432109876543210
2056  *  001000               10001001101
2057  *     rt -----
2058  *          rs -----
2059  *               rd -----
2060  */
2061 static char *ADDQH_R_PH(uint64 instruction, Dis_info *info)
2062 {
2063     uint64 rt_value = extract_rt_25_24_23_22_21(instruction);
2064     uint64 rs_value = extract_rs_20_19_18_17_16(instruction);
2065     uint64 rd_value = extract_rd_15_14_13_12_11(instruction);
2066 
2067     const char *rd = GPR(rd_value, info);
2068     const char *rs = GPR(rs_value, info);
2069     const char *rt = GPR(rt_value, info);
2070 
2071     return img_format("ADDQH_R.PH %s, %s, %s", rd, rs, rt);
2072 }
2073 
2074 
2075 /*
2076  * [DSP] ADDQH_R.W rd, rt, rs - Add fractional words and shift right to halve
2077  *         results with rounding
2078  *
2079  *   3         2         1
2080  *  10987654321098765432109876543210
2081  *  001000               00010001101
2082  *     rt -----
2083  *          rs -----
2084  *               rd -----
2085  */
2086 static char *ADDQH_R_W(uint64 instruction, Dis_info *info)
2087 {
2088     uint64 rt_value = extract_rt_25_24_23_22_21(instruction);
2089     uint64 rs_value = extract_rs_20_19_18_17_16(instruction);
2090     uint64 rd_value = extract_rd_15_14_13_12_11(instruction);
2091 
2092     const char *rd = GPR(rd_value, info);
2093     const char *rs = GPR(rs_value, info);
2094     const char *rt = GPR(rt_value, info);
2095 
2096     return img_format("ADDQH_R.W %s, %s, %s", rd, rs, rt);
2097 }
2098 
2099 
2100 /*
2101  * [DSP] ADDQH.W rd, rt, rs - Add fractional words and shift right to halve
2102  *         results
2103  *
2104  *   3         2         1
2105  *  10987654321098765432109876543210
2106  *  001000               10010001101
2107  *     rt -----
2108  *          rs -----
2109  *               rd -----
2110  */
2111 static char *ADDQH_W(uint64 instruction, Dis_info *info)
2112 {
2113     uint64 rt_value = extract_rt_25_24_23_22_21(instruction);
2114     uint64 rs_value = extract_rs_20_19_18_17_16(instruction);
2115     uint64 rd_value = extract_rd_15_14_13_12_11(instruction);
2116 
2117     const char *rd = GPR(rd_value, info);
2118     const char *rs = GPR(rs_value, info);
2119     const char *rt = GPR(rt_value, info);
2120 
2121     return img_format("ADDQH.W %s, %s, %s", rd, rs, rt);
2122 }
2123 
2124 
2125 /*
2126  * [DSP] ADDSC rd, rt, rs - Add two signed words and set carry bit
2127  *
2128  *   3         2         1
2129  *  10987654321098765432109876543210
2130  *  001000               x1110000101
2131  *     rt -----
2132  *          rs -----
2133  *               rd -----
2134  */
2135 static char *ADDSC(uint64 instruction, Dis_info *info)
2136 {
2137     uint64 rt_value = extract_rt_25_24_23_22_21(instruction);
2138     uint64 rs_value = extract_rs_20_19_18_17_16(instruction);
2139     uint64 rd_value = extract_rd_15_14_13_12_11(instruction);
2140 
2141     const char *rd = GPR(rd_value, info);
2142     const char *rs = GPR(rs_value, info);
2143     const char *rt = GPR(rt_value, info);
2144 
2145     return img_format("ADDSC %s, %s, %s", rd, rs, rt);
2146 }
2147 
2148 
2149 /*
2150  * ADDU[16] rd3, rs3, rt3 -
2151  *
2152  *  5432109876543210
2153  *  101100         0
2154  *    rt3 ---
2155  *       rs3 ---
2156  *          rd3 ---
2157  */
2158 static char *ADDU_16_(uint64 instruction, Dis_info *info)
2159 {
2160     uint64 rt3_value = extract_rt3_9_8_7(instruction);
2161     uint64 rs3_value = extract_rs3_6_5_4(instruction);
2162     uint64 rd3_value = extract_rd3_3_2_1(instruction);
2163 
2164     const char *rt3 = GPR(decode_gpr_gpr3(rt3_value, info), info);
2165     const char *rs3 = GPR(decode_gpr_gpr3(rs3_value, info), info);
2166     const char *rd3 = GPR(decode_gpr_gpr3(rd3_value, info), info);
2167 
2168     return img_format("ADDU %s, %s, %s", rd3, rs3, rt3);
2169 }
2170 
2171 
2172 /*
2173  *
2174  *
2175  *   3         2         1
2176  *  10987654321098765432109876543210
2177  *  001000               x1110000101
2178  *     rt -----
2179  *          rs -----
2180  *               rd -----
2181  */
2182 static char *ADDU_32_(uint64 instruction, Dis_info *info)
2183 {
2184     uint64 rt_value = extract_rt_25_24_23_22_21(instruction);
2185     uint64 rs_value = extract_rs_20_19_18_17_16(instruction);
2186     uint64 rd_value = extract_rd_15_14_13_12_11(instruction);
2187 
2188     const char *rd = GPR(rd_value, info);
2189     const char *rs = GPR(rs_value, info);
2190     const char *rt = GPR(rt_value, info);
2191 
2192     return img_format("ADDU %s, %s, %s", rd, rs, rt);
2193 }
2194 
2195 
2196 /*
2197  *
2198  *
2199  *   3         2         1
2200  *  10987654321098765432109876543210
2201  *  001000               x1110000101
2202  *     rt -----
2203  *          rs -----
2204  *               rd -----
2205  */
2206 static char *ADDU_4X4_(uint64 instruction, Dis_info *info)
2207 {
2208     uint64 rt4_value = extract_rt4_9_7_6_5(instruction);
2209     uint64 rs4_value = extract_rs4_4_2_1_0(instruction);
2210 
2211     const char *rs4 = GPR(decode_gpr_gpr4(rs4_value, info), info);
2212     const char *rt4 = GPR(decode_gpr_gpr4(rt4_value, info), info);
2213 
2214     return img_format("ADDU %s, %s", rs4, rt4);
2215 }
2216 
2217 
2218 /*
2219  * [DSP] ADDU.PH rd, rt, rs - Add two pairs of unsigned halfwords
2220  *
2221  *   3         2         1
2222  *  10987654321098765432109876543210
2223  *  001000               00100001101
2224  *     rt -----
2225  *          rs -----
2226  *               rd -----
2227  */
2228 static char *ADDU_PH(uint64 instruction, Dis_info *info)
2229 {
2230     uint64 rt_value = extract_rt_25_24_23_22_21(instruction);
2231     uint64 rs_value = extract_rs_20_19_18_17_16(instruction);
2232     uint64 rd_value = extract_rd_15_14_13_12_11(instruction);
2233 
2234     const char *rd = GPR(rd_value, info);
2235     const char *rs = GPR(rs_value, info);
2236     const char *rt = GPR(rt_value, info);
2237 
2238     return img_format("ADDU.PH %s, %s, %s", rd, rs, rt);
2239 }
2240 
2241 
2242 /*
2243  * ADDU.QB rd, rt, rs - Unsigned Add Quad Byte Vectors
2244  *
2245  *   3         2         1
2246  *  10987654321098765432109876543210
2247  *  001000               00011001101
2248  *     rt -----
2249  *          rs -----
2250  *               rd -----
2251  */
2252 static char *ADDU_QB(uint64 instruction, Dis_info *info)
2253 {
2254     uint64 rt_value = extract_rt_25_24_23_22_21(instruction);
2255     uint64 rs_value = extract_rs_20_19_18_17_16(instruction);
2256     uint64 rd_value = extract_rd_15_14_13_12_11(instruction);
2257 
2258     const char *rd = GPR(rd_value, info);
2259     const char *rs = GPR(rs_value, info);
2260     const char *rt = GPR(rt_value, info);
2261 
2262     return img_format("ADDU.QB %s, %s, %s", rd, rs, rt);
2263 }
2264 
2265 
2266 /*
2267  * [DSP] ADDU_S.PH rd, rt, rs - Add two pairs of unsigned halfwords with 16-bit
2268  *         saturation
2269  *
2270  *   3         2         1
2271  *  10987654321098765432109876543210
2272  *  001000               10100001101
2273  *     rt -----
2274  *          rs -----
2275  *               rd -----
2276  */
2277 static char *ADDU_S_PH(uint64 instruction, Dis_info *info)
2278 {
2279     uint64 rt_value = extract_rt_25_24_23_22_21(instruction);
2280     uint64 rs_value = extract_rs_20_19_18_17_16(instruction);
2281     uint64 rd_value = extract_rd_15_14_13_12_11(instruction);
2282 
2283     const char *rd = GPR(rd_value, info);
2284     const char *rs = GPR(rs_value, info);
2285     const char *rt = GPR(rt_value, info);
2286 
2287     return img_format("ADDU_S.PH %s, %s, %s", rd, rs, rt);
2288 }
2289 
2290 
2291 /*
2292  * ADDU_S.QB rd, rt, rs - Unsigned Add Quad Byte Vectors
2293  *
2294  *   3         2         1
2295  *  10987654321098765432109876543210
2296  *  001000               10011001101
2297  *     rt -----
2298  *          rs -----
2299  *               rd -----
2300  */
2301 static char *ADDU_S_QB(uint64 instruction, Dis_info *info)
2302 {
2303     uint64 rt_value = extract_rt_25_24_23_22_21(instruction);
2304     uint64 rs_value = extract_rs_20_19_18_17_16(instruction);
2305     uint64 rd_value = extract_rd_15_14_13_12_11(instruction);
2306 
2307     const char *rd = GPR(rd_value, info);
2308     const char *rs = GPR(rs_value, info);
2309     const char *rt = GPR(rt_value, info);
2310 
2311     return img_format("ADDU_S.QB %s, %s, %s", rd, rs, rt);
2312 }
2313 
2314 
2315 /*
2316  * ADDUH.QB rd, rt, rs - Unsigned Add Vector Quad-Bytes And Right Shift
2317  *                       to Halve Results
2318  *
2319  *   3         2         1
2320  *  10987654321098765432109876543210
2321  *  001000               00101001101
2322  *     rt -----
2323  *          rs -----
2324  *               rd -----
2325  */
2326 static char *ADDUH_QB(uint64 instruction, Dis_info *info)
2327 {
2328     uint64 rt_value = extract_rt_25_24_23_22_21(instruction);
2329     uint64 rs_value = extract_rs_20_19_18_17_16(instruction);
2330     uint64 rd_value = extract_rd_15_14_13_12_11(instruction);
2331 
2332     const char *rd = GPR(rd_value, info);
2333     const char *rs = GPR(rs_value, info);
2334     const char *rt = GPR(rt_value, info);
2335 
2336     return img_format("ADDUH.QB %s, %s, %s", rd, rs, rt);
2337 }
2338 
2339 
2340 /*
2341  * ADDUH_R.QB rd, rt, rs - Unsigned Add Vector Quad-Bytes And Right Shift
2342  *                         to Halve Results
2343  *
2344  *   3         2         1
2345  *  10987654321098765432109876543210
2346  *  001000               10101001101
2347  *     rt -----
2348  *          rs -----
2349  *               rd -----
2350  */
2351 static char *ADDUH_R_QB(uint64 instruction, Dis_info *info)
2352 {
2353     uint64 rt_value = extract_rt_25_24_23_22_21(instruction);
2354     uint64 rs_value = extract_rs_20_19_18_17_16(instruction);
2355     uint64 rd_value = extract_rd_15_14_13_12_11(instruction);
2356 
2357     const char *rd = GPR(rd_value, info);
2358     const char *rs = GPR(rs_value, info);
2359     const char *rt = GPR(rt_value, info);
2360 
2361     return img_format("ADDUH_R.QB %s, %s, %s", rd, rs, rt);
2362 }
2363 
2364 /*
2365  * ADDWC rd, rt, rs - Add Word with Carry Bit
2366  *
2367  *   3         2         1
2368  *  10987654321098765432109876543210
2369  *  001000               x1111000101
2370  *     rt -----
2371  *          rs -----
2372  *               rd -----
2373  */
2374 static char *ADDWC(uint64 instruction, Dis_info *info)
2375 {
2376     uint64 rt_value = extract_rt_25_24_23_22_21(instruction);
2377     uint64 rs_value = extract_rs_20_19_18_17_16(instruction);
2378     uint64 rd_value = extract_rd_15_14_13_12_11(instruction);
2379 
2380     const char *rd = GPR(rd_value, info);
2381     const char *rs = GPR(rs_value, info);
2382     const char *rt = GPR(rt_value, info);
2383 
2384     return img_format("ADDWC %s, %s, %s", rd, rs, rt);
2385 }
2386 
2387 
2388 /*
2389  *
2390  *
2391  *   3         2         1
2392  *  10987654321098765432109876543210
2393  *  001000               x1110000101
2394  *     rt -----
2395  *          rs -----
2396  *               rd -----
2397  */
2398 static char *ALUIPC(uint64 instruction, Dis_info *info)
2399 {
2400     uint64 rt_value = extract_rt_25_24_23_22_21(instruction);
2401     int64 s_value = extract_s__se31_0_11_to_2_20_to_12_s12(instruction);
2402 
2403     const char *rt = GPR(rt_value, info);
2404     g_autofree char *s = ADDRESS(s_value, 4, info);
2405 
2406     return img_format("ALUIPC %s, %%pcrel_hi(%s)", rt, s);
2407 }
2408 
2409 
2410 /*
2411  * AND[16] rt3, rs3 -
2412  *
2413  *  5432109876543210
2414  *  101100
2415  *    rt3 ---
2416  *       rs3 ---
2417  *           eu ----
2418  */
2419 static char *AND_16_(uint64 instruction, Dis_info *info)
2420 {
2421     uint64 rt3_value = extract_rt3_9_8_7(instruction);
2422     uint64 rs3_value = extract_rs3_6_5_4(instruction);
2423 
2424     const char *rt3 = GPR(decode_gpr_gpr3(rt3_value, info), info);
2425     const char *rs3 = GPR(decode_gpr_gpr3(rs3_value, info), info);
2426 
2427     return img_format("AND %s, %s", rs3, rt3);
2428 }
2429 
2430 
2431 /*
2432  *
2433  *
2434  *   3         2         1
2435  *  10987654321098765432109876543210
2436  *  001000               x1110000101
2437  *     rt -----
2438  *          rs -----
2439  *               rd -----
2440  */
2441 static char *AND_32_(uint64 instruction, Dis_info *info)
2442 {
2443     uint64 rt_value = extract_rt_25_24_23_22_21(instruction);
2444     uint64 rs_value = extract_rs_20_19_18_17_16(instruction);
2445     uint64 rd_value = extract_rd_15_14_13_12_11(instruction);
2446 
2447     const char *rd = GPR(rd_value, info);
2448     const char *rs = GPR(rs_value, info);
2449     const char *rt = GPR(rt_value, info);
2450 
2451     return img_format("AND %s, %s, %s", rd, rs, rt);
2452 }
2453 
2454 
2455 /*
2456  * ANDI rt, rs, u -
2457  *
2458  *  5432109876543210
2459  *  101100
2460  *    rt3 ---
2461  *       rs3 ---
2462  *           eu ----
2463  */
2464 static char *ANDI_16_(uint64 instruction, Dis_info *info)
2465 {
2466     uint64 rt3_value = extract_rt3_9_8_7(instruction);
2467     uint64 rs3_value = extract_rs3_6_5_4(instruction);
2468     uint64 eu_value = extract_eu_3_2_1_0(instruction);
2469 
2470     const char *rt3 = GPR(decode_gpr_gpr3(rt3_value, info), info);
2471     const char *rs3 = GPR(decode_gpr_gpr3(rs3_value, info), info);
2472     uint64 eu = encode_eu_from_u_andi16(eu_value);
2473 
2474     return img_format("ANDI %s, %s, 0x%" PRIx64, rt3, rs3, eu);
2475 }
2476 
2477 
2478 /*
2479  *
2480  *
2481  *   3         2         1
2482  *  10987654321098765432109876543210
2483  *  001000               x1110000101
2484  *     rt -----
2485  *          rs -----
2486  *               rd -----
2487  */
2488 static char *ANDI_32_(uint64 instruction, Dis_info *info)
2489 {
2490     uint64 rt_value = extract_rt_25_24_23_22_21(instruction);
2491     uint64 rs_value = extract_rs_20_19_18_17_16(instruction);
2492     uint64 u_value = extract_u_11_10_9_8_7_6_5_4_3_2_1_0(instruction);
2493 
2494     const char *rt = GPR(rt_value, info);
2495     const char *rs = GPR(rs_value, info);
2496 
2497     return img_format("ANDI %s, %s, 0x%" PRIx64, rt, rs, u_value);
2498 }
2499 
2500 
2501 /*
2502  *
2503  *
2504  *   3         2         1
2505  *  10987654321098765432109876543210
2506  *  001000               x1110000101
2507  *     rt -----
2508  *          rs -----
2509  *               rd -----
2510  */
2511 static char *APPEND(uint64 instruction, Dis_info *info)
2512 {
2513     uint64 rt_value = extract_rt_25_24_23_22_21(instruction);
2514     uint64 rs_value = extract_rs_20_19_18_17_16(instruction);
2515     uint64 sa_value = extract_sa_15_14_13_12_11(instruction);
2516 
2517     const char *rt = GPR(rt_value, info);
2518     const char *rs = GPR(rs_value, info);
2519 
2520     return img_format("APPEND %s, %s, 0x%" PRIx64, rt, rs, sa_value);
2521 }
2522 
2523 
2524 /*
2525  *
2526  *
2527  *   3         2         1
2528  *  10987654321098765432109876543210
2529  *  001000               x1110000101
2530  *     rt -----
2531  *          rs -----
2532  *               rd -----
2533  */
2534 static char *ASET(uint64 instruction, Dis_info *info)
2535 {
2536     uint64 bit_value = extract_bit_23_22_21(instruction);
2537     uint64 rs_value = extract_rs_20_19_18_17_16(instruction);
2538     int64 s_value = extract_s__se8_15_7_6_5_4_3_2_1_0(instruction);
2539 
2540     const char *rs = GPR(rs_value, info);
2541 
2542     return img_format("ASET 0x%" PRIx64 ", %" PRId64 "(%s)",
2543                       bit_value, s_value, rs);
2544 }
2545 
2546 
2547 /*
2548  *
2549  *
2550  *   3         2         1
2551  *  10987654321098765432109876543210
2552  *  001000               x1110000101
2553  *     rt -----
2554  *          rs -----
2555  *               rd -----
2556  */
2557 static char *BALC_16_(uint64 instruction, Dis_info *info)
2558 {
2559     int64 s_value = extract_s__se10_0_9_8_7_6_5_4_3_2_1_s1(instruction);
2560 
2561     g_autofree char *s = ADDRESS(s_value, 2, info);
2562 
2563     return img_format("BALC %s", s);
2564 }
2565 
2566 
2567 /*
2568  *
2569  *
2570  *   3         2         1
2571  *  10987654321098765432109876543210
2572  *  001000               x1110000101
2573  *     rt -----
2574  *          rs -----
2575  *               rd -----
2576  */
2577 static char *BALC_32_(uint64 instruction, Dis_info *info)
2578 {
2579     int64 s_value = extract_s__se25_0_24_to_1_s1(instruction);
2580 
2581     g_autofree char *s = ADDRESS(s_value, 4, info);
2582 
2583     return img_format("BALC %s", s);
2584 }
2585 
2586 
2587 /*
2588  *
2589  *
2590  *   3         2         1
2591  *  10987654321098765432109876543210
2592  *  001000               x1110000101
2593  *     rt -----
2594  *          rs -----
2595  *               rd -----
2596  */
2597 static char *BALRSC(uint64 instruction, Dis_info *info)
2598 {
2599     uint64 rt_value = extract_rt_25_24_23_22_21(instruction);
2600     uint64 rs_value = extract_rs_20_19_18_17_16(instruction);
2601 
2602     const char *rt = GPR(rt_value, info);
2603     const char *rs = GPR(rs_value, info);
2604 
2605     return img_format("BALRSC %s, %s", rt, rs);
2606 }
2607 
2608 
2609 /*
2610  *
2611  *
2612  *   3         2         1
2613  *  10987654321098765432109876543210
2614  *  001000               x1110000101
2615  *     rt -----
2616  *          rs -----
2617  *               rd -----
2618  */
2619 static char *BBEQZC(uint64 instruction, Dis_info *info)
2620 {
2621     uint64 rt_value = extract_rt_25_24_23_22_21(instruction);
2622     uint64 bit_value = extract_bit_16_15_14_13_12_11(instruction);
2623     int64 s_value = extract_s__se11_0_10_9_8_7_6_5_4_3_2_1_0_s1(instruction);
2624 
2625     const char *rt = GPR(rt_value, info);
2626     g_autofree char *s = ADDRESS(s_value, 4, info);
2627 
2628     return img_format("BBEQZC %s, 0x%" PRIx64 ", %s", rt, bit_value, s);
2629 }
2630 
2631 
2632 /*
2633  *
2634  *
2635  *   3         2         1
2636  *  10987654321098765432109876543210
2637  *  001000               x1110000101
2638  *     rt -----
2639  *          rs -----
2640  *               rd -----
2641  */
2642 static char *BBNEZC(uint64 instruction, Dis_info *info)
2643 {
2644     uint64 rt_value = extract_rt_25_24_23_22_21(instruction);
2645     uint64 bit_value = extract_bit_16_15_14_13_12_11(instruction);
2646     int64 s_value = extract_s__se11_0_10_9_8_7_6_5_4_3_2_1_0_s1(instruction);
2647 
2648     const char *rt = GPR(rt_value, info);
2649     g_autofree char *s = ADDRESS(s_value, 4, info);
2650 
2651     return img_format("BBNEZC %s, 0x%" PRIx64 ", %s", rt, bit_value, s);
2652 }
2653 
2654 
2655 /*
2656  *
2657  *
2658  *   3         2         1
2659  *  10987654321098765432109876543210
2660  *  001000               x1110000101
2661  *     rt -----
2662  *          rs -----
2663  *               rd -----
2664  */
2665 static char *BC_16_(uint64 instruction, Dis_info *info)
2666 {
2667     int64 s_value = extract_s__se10_0_9_8_7_6_5_4_3_2_1_s1(instruction);
2668 
2669     g_autofree char *s = ADDRESS(s_value, 2, info);
2670 
2671     return img_format("BC %s", s);
2672 }
2673 
2674 
2675 /*
2676  *
2677  *
2678  *   3         2         1
2679  *  10987654321098765432109876543210
2680  *  001000               x1110000101
2681  *     rt -----
2682  *          rs -----
2683  *               rd -----
2684  */
2685 static char *BC_32_(uint64 instruction, Dis_info *info)
2686 {
2687     int64 s_value = extract_s__se25_0_24_to_1_s1(instruction);
2688 
2689     g_autofree char *s = ADDRESS(s_value, 4, info);
2690 
2691     return img_format("BC %s", s);
2692 }
2693 
2694 
2695 /*
2696  *
2697  *
2698  *   3         2         1
2699  *  10987654321098765432109876543210
2700  *  001000               x1110000101
2701  *     rt -----
2702  *          rs -----
2703  *               rd -----
2704  */
2705 static char *BC1EQZC(uint64 instruction, Dis_info *info)
2706 {
2707     uint64 ft_value = extract_ft_25_24_23_22_21(instruction);
2708     int64 s_value = extract_s__se14_0_13_to_1_s1(instruction);
2709 
2710     const char *ft = FPR(ft_value, info);
2711     g_autofree char *s = ADDRESS(s_value, 4, info);
2712 
2713     return img_format("BC1EQZC %s, %s", ft, s);
2714 }
2715 
2716 
2717 /*
2718  *
2719  *
2720  *   3         2         1
2721  *  10987654321098765432109876543210
2722  *  001000               x1110000101
2723  *     rt -----
2724  *          rs -----
2725  *               rd -----
2726  */
2727 static char *BC1NEZC(uint64 instruction, Dis_info *info)
2728 {
2729     uint64 ft_value = extract_ft_25_24_23_22_21(instruction);
2730     int64 s_value = extract_s__se14_0_13_to_1_s1(instruction);
2731 
2732     const char *ft = FPR(ft_value, info);
2733     g_autofree char *s = ADDRESS(s_value, 4, info);
2734 
2735     return img_format("BC1NEZC %s, %s", ft, s);
2736 }
2737 
2738 
2739 /*
2740  *
2741  *
2742  *   3         2         1
2743  *  10987654321098765432109876543210
2744  *  001000               x1110000101
2745  *     rt -----
2746  *          rs -----
2747  *               rd -----
2748  */
2749 static char *BC2EQZC(uint64 instruction, Dis_info *info)
2750 {
2751     uint64 ct_value = extract_ct_25_24_23_22_21(instruction);
2752     int64 s_value = extract_s__se14_0_13_to_1_s1(instruction);
2753 
2754     g_autofree char *s = ADDRESS(s_value, 4, info);
2755 
2756     return img_format("BC2EQZC CP%" PRIu64 ", %s", ct_value, s);
2757 }
2758 
2759 
2760 /*
2761  *
2762  *
2763  *   3         2         1
2764  *  10987654321098765432109876543210
2765  *  001000               x1110000101
2766  *     rt -----
2767  *          rs -----
2768  *               rd -----
2769  */
2770 static char *BC2NEZC(uint64 instruction, Dis_info *info)
2771 {
2772     uint64 ct_value = extract_ct_25_24_23_22_21(instruction);
2773     int64 s_value = extract_s__se14_0_13_to_1_s1(instruction);
2774 
2775     g_autofree char *s = ADDRESS(s_value, 4, info);
2776 
2777     return img_format("BC2NEZC CP%" PRIu64 ", %s", ct_value, s);
2778 }
2779 
2780 
2781 /*
2782  *
2783  *
2784  *   3         2         1
2785  *  10987654321098765432109876543210
2786  *  001000               x1110000101
2787  *     rt -----
2788  *          rs -----
2789  *               rd -----
2790  */
2791 static char *BEQC_16_(uint64 instruction, Dis_info *info)
2792 {
2793     uint64 rt3_value = extract_rt3_9_8_7(instruction);
2794     uint64 rs3_value = extract_rs3_6_5_4(instruction);
2795     uint64 u_value = extract_u_3_2_1_0__s1(instruction);
2796 
2797     const char *rs3 = GPR(decode_gpr_gpr3(rs3_value, info), info);
2798     const char *rt3 = GPR(decode_gpr_gpr3(rt3_value, info), info);
2799     g_autofree char *u = ADDRESS(u_value, 2, info);
2800 
2801     return img_format("BEQC %s, %s, %s", rs3, rt3, u);
2802 }
2803 
2804 
2805 /*
2806  *
2807  *
2808  *   3         2         1
2809  *  10987654321098765432109876543210
2810  *  001000               x1110000101
2811  *     rt -----
2812  *          rs -----
2813  *               rd -----
2814  */
2815 static char *BEQC_32_(uint64 instruction, Dis_info *info)
2816 {
2817     uint64 rt_value = extract_rt_25_24_23_22_21(instruction);
2818     uint64 rs_value = extract_rs_20_19_18_17_16(instruction);
2819     int64 s_value = extract_s__se14_0_13_to_1_s1(instruction);
2820 
2821     const char *rs = GPR(rs_value, info);
2822     const char *rt = GPR(rt_value, info);
2823     g_autofree char *s = ADDRESS(s_value, 4, info);
2824 
2825     return img_format("BEQC %s, %s, %s", rs, rt, s);
2826 }
2827 
2828 
2829 /*
2830  *
2831  *
2832  *   3         2         1
2833  *  10987654321098765432109876543210
2834  *  001000               x1110000101
2835  *     rt -----
2836  *          rs -----
2837  *               rd -----
2838  */
2839 static char *BEQIC(uint64 instruction, Dis_info *info)
2840 {
2841     uint64 rt_value = extract_rt_25_24_23_22_21(instruction);
2842     uint64 u_value = extract_u_17_16_15_14_13_12_11(instruction);
2843     int64 s_value = extract_s__se11_0_10_9_8_7_6_5_4_3_2_1_0_s1(instruction);
2844 
2845     const char *rt = GPR(rt_value, info);
2846     g_autofree char *s = ADDRESS(s_value, 4, info);
2847 
2848     return img_format("BEQIC %s, 0x%" PRIx64 ", %s", rt, u_value, s);
2849 }
2850 
2851 
2852 /*
2853  *
2854  *
2855  *   3         2         1
2856  *  10987654321098765432109876543210
2857  *  001000               x1110000101
2858  *     rt -----
2859  *          rs -----
2860  *               rd -----
2861  */
2862 static char *BEQZC_16_(uint64 instruction, Dis_info *info)
2863 {
2864     uint64 rt3_value = extract_rt3_9_8_7(instruction);
2865     int64 s_value = extract_s__se7_0_6_5_4_3_2_1_s1(instruction);
2866 
2867     const char *rt3 = GPR(decode_gpr_gpr3(rt3_value, info), info);
2868     g_autofree char *s = ADDRESS(s_value, 2, info);
2869 
2870     return img_format("BEQZC %s, %s", rt3, s);
2871 }
2872 
2873 
2874 /*
2875  *
2876  *
2877  *   3         2         1
2878  *  10987654321098765432109876543210
2879  *  001000               x1110000101
2880  *     rt -----
2881  *          rs -----
2882  *               rd -----
2883  */
2884 static char *BGEC(uint64 instruction, Dis_info *info)
2885 {
2886     uint64 rt_value = extract_rt_25_24_23_22_21(instruction);
2887     uint64 rs_value = extract_rs_20_19_18_17_16(instruction);
2888     int64 s_value = extract_s__se14_0_13_to_1_s1(instruction);
2889 
2890     const char *rs = GPR(rs_value, info);
2891     const char *rt = GPR(rt_value, info);
2892     g_autofree char *s = ADDRESS(s_value, 4, info);
2893 
2894     return img_format("BGEC %s, %s, %s", rs, rt, s);
2895 }
2896 
2897 
2898 /*
2899  *
2900  *
2901  *   3         2         1
2902  *  10987654321098765432109876543210
2903  *  001000               x1110000101
2904  *     rt -----
2905  *          rs -----
2906  *               rd -----
2907  */
2908 static char *BGEIC(uint64 instruction, Dis_info *info)
2909 {
2910     uint64 rt_value = extract_rt_25_24_23_22_21(instruction);
2911     uint64 u_value = extract_u_17_16_15_14_13_12_11(instruction);
2912     int64 s_value = extract_s__se11_0_10_9_8_7_6_5_4_3_2_1_0_s1(instruction);
2913 
2914     const char *rt = GPR(rt_value, info);
2915     g_autofree char *s = ADDRESS(s_value, 4, info);
2916 
2917     return img_format("BGEIC %s, 0x%" PRIx64 ", %s", rt, u_value, s);
2918 }
2919 
2920 
2921 /*
2922  *
2923  *
2924  *   3         2         1
2925  *  10987654321098765432109876543210
2926  *  001000               x1110000101
2927  *     rt -----
2928  *          rs -----
2929  *               rd -----
2930  */
2931 static char *BGEIUC(uint64 instruction, Dis_info *info)
2932 {
2933     uint64 rt_value = extract_rt_25_24_23_22_21(instruction);
2934     uint64 u_value = extract_u_17_16_15_14_13_12_11(instruction);
2935     int64 s_value = extract_s__se11_0_10_9_8_7_6_5_4_3_2_1_0_s1(instruction);
2936 
2937     const char *rt = GPR(rt_value, info);
2938     g_autofree char *s = ADDRESS(s_value, 4, info);
2939 
2940     return img_format("BGEIUC %s, 0x%" PRIx64 ", %s", rt, u_value, s);
2941 }
2942 
2943 
2944 /*
2945  *
2946  *
2947  *   3         2         1
2948  *  10987654321098765432109876543210
2949  *  001000               x1110000101
2950  *     rt -----
2951  *          rs -----
2952  *               rd -----
2953  */
2954 static char *BGEUC(uint64 instruction, Dis_info *info)
2955 {
2956     uint64 rt_value = extract_rt_25_24_23_22_21(instruction);
2957     uint64 rs_value = extract_rs_20_19_18_17_16(instruction);
2958     int64 s_value = extract_s__se14_0_13_to_1_s1(instruction);
2959 
2960     const char *rs = GPR(rs_value, info);
2961     const char *rt = GPR(rt_value, info);
2962     g_autofree char *s = ADDRESS(s_value, 4, info);
2963 
2964     return img_format("BGEUC %s, %s, %s", rs, rt, s);
2965 }
2966 
2967 
2968 /*
2969  *
2970  *
2971  *   3         2         1
2972  *  10987654321098765432109876543210
2973  *  001000               x1110000101
2974  *     rt -----
2975  *          rs -----
2976  *               rd -----
2977  */
2978 static char *BLTC(uint64 instruction, Dis_info *info)
2979 {
2980     uint64 rt_value = extract_rt_25_24_23_22_21(instruction);
2981     uint64 rs_value = extract_rs_20_19_18_17_16(instruction);
2982     int64 s_value = extract_s__se14_0_13_to_1_s1(instruction);
2983 
2984     const char *rs = GPR(rs_value, info);
2985     const char *rt = GPR(rt_value, info);
2986     g_autofree char *s = ADDRESS(s_value, 4, info);
2987 
2988     return img_format("BLTC %s, %s, %s", rs, rt, s);
2989 }
2990 
2991 
2992 /*
2993  *
2994  *
2995  *   3         2         1
2996  *  10987654321098765432109876543210
2997  *  001000               x1110000101
2998  *     rt -----
2999  *          rs -----
3000  *               rd -----
3001  */
3002 static char *BLTIC(uint64 instruction, Dis_info *info)
3003 {
3004     uint64 rt_value = extract_rt_25_24_23_22_21(instruction);
3005     uint64 u_value = extract_u_17_16_15_14_13_12_11(instruction);
3006     int64 s_value = extract_s__se11_0_10_9_8_7_6_5_4_3_2_1_0_s1(instruction);
3007 
3008     const char *rt = GPR(rt_value, info);
3009     g_autofree char *s = ADDRESS(s_value, 4, info);
3010 
3011     return img_format("BLTIC %s, 0x%" PRIx64 ", %s", rt, u_value, s);
3012 }
3013 
3014 
3015 /*
3016  *
3017  *
3018  *   3         2         1
3019  *  10987654321098765432109876543210
3020  *  001000               x1110000101
3021  *     rt -----
3022  *          rs -----
3023  *               rd -----
3024  */
3025 static char *BLTIUC(uint64 instruction, Dis_info *info)
3026 {
3027     uint64 rt_value = extract_rt_25_24_23_22_21(instruction);
3028     uint64 u_value = extract_u_17_16_15_14_13_12_11(instruction);
3029     int64 s_value = extract_s__se11_0_10_9_8_7_6_5_4_3_2_1_0_s1(instruction);
3030 
3031     const char *rt = GPR(rt_value, info);
3032     g_autofree char *s = ADDRESS(s_value, 4, info);
3033 
3034     return img_format("BLTIUC %s, 0x%" PRIx64 ", %s", rt, u_value, s);
3035 }
3036 
3037 
3038 /*
3039  *
3040  *
3041  *   3         2         1
3042  *  10987654321098765432109876543210
3043  *  001000               x1110000101
3044  *     rt -----
3045  *          rs -----
3046  *               rd -----
3047  */
3048 static char *BLTUC(uint64 instruction, Dis_info *info)
3049 {
3050     uint64 rt_value = extract_rt_25_24_23_22_21(instruction);
3051     uint64 rs_value = extract_rs_20_19_18_17_16(instruction);
3052     int64 s_value = extract_s__se14_0_13_to_1_s1(instruction);
3053 
3054     const char *rs = GPR(rs_value, info);
3055     const char *rt = GPR(rt_value, info);
3056     g_autofree char *s = ADDRESS(s_value, 4, info);
3057 
3058     return img_format("BLTUC %s, %s, %s", rs, rt, s);
3059 }
3060 
3061 
3062 /*
3063  *
3064  *
3065  *   3         2         1
3066  *  10987654321098765432109876543210
3067  *  001000               x1110000101
3068  *     rt -----
3069  *          rs -----
3070  *               rd -----
3071  */
3072 static char *BNEC_16_(uint64 instruction, Dis_info *info)
3073 {
3074     uint64 rt3_value = extract_rt3_9_8_7(instruction);
3075     uint64 rs3_value = extract_rs3_6_5_4(instruction);
3076     uint64 u_value = extract_u_3_2_1_0__s1(instruction);
3077 
3078     const char *rs3 = GPR(decode_gpr_gpr3(rs3_value, info), info);
3079     const char *rt3 = GPR(decode_gpr_gpr3(rt3_value, info), info);
3080     g_autofree char *u = ADDRESS(u_value, 2, info);
3081 
3082     return img_format("BNEC %s, %s, %s", rs3, rt3, u);
3083 }
3084 
3085 
3086 /*
3087  *
3088  *
3089  *   3         2         1
3090  *  10987654321098765432109876543210
3091  *  001000               x1110000101
3092  *     rt -----
3093  *          rs -----
3094  *               rd -----
3095  */
3096 static char *BNEC_32_(uint64 instruction, Dis_info *info)
3097 {
3098     uint64 rt_value = extract_rt_25_24_23_22_21(instruction);
3099     uint64 rs_value = extract_rs_20_19_18_17_16(instruction);
3100     int64 s_value = extract_s__se14_0_13_to_1_s1(instruction);
3101 
3102     const char *rs = GPR(rs_value, info);
3103     const char *rt = GPR(rt_value, info);
3104     g_autofree char *s = ADDRESS(s_value, 4, info);
3105 
3106     return img_format("BNEC %s, %s, %s", rs, rt, s);
3107 }
3108 
3109 
3110 /*
3111  *
3112  *
3113  *   3         2         1
3114  *  10987654321098765432109876543210
3115  *  001000               x1110000101
3116  *     rt -----
3117  *          rs -----
3118  *               rd -----
3119  */
3120 static char *BNEIC(uint64 instruction, Dis_info *info)
3121 {
3122     uint64 rt_value = extract_rt_25_24_23_22_21(instruction);
3123     uint64 u_value = extract_u_17_16_15_14_13_12_11(instruction);
3124     int64 s_value = extract_s__se11_0_10_9_8_7_6_5_4_3_2_1_0_s1(instruction);
3125 
3126     const char *rt = GPR(rt_value, info);
3127     g_autofree char *s = ADDRESS(s_value, 4, info);
3128 
3129     return img_format("BNEIC %s, 0x%" PRIx64 ", %s", rt, u_value, s);
3130 }
3131 
3132 
3133 /*
3134  *
3135  *
3136  *   3         2         1
3137  *  10987654321098765432109876543210
3138  *  001000               x1110000101
3139  *     rt -----
3140  *          rs -----
3141  *               rd -----
3142  */
3143 static char *BNEZC_16_(uint64 instruction, Dis_info *info)
3144 {
3145     uint64 rt3_value = extract_rt3_9_8_7(instruction);
3146     int64 s_value = extract_s__se7_0_6_5_4_3_2_1_s1(instruction);
3147 
3148     const char *rt3 = GPR(decode_gpr_gpr3(rt3_value, info), info);
3149     g_autofree char *s = ADDRESS(s_value, 2, info);
3150 
3151     return img_format("BNEZC %s, %s", rt3, s);
3152 }
3153 
3154 
3155 /*
3156  * [DSP] BPOSGE32C offset - Branch on greater than or equal to value 32 in
3157  *   DSPControl Pos field
3158  *
3159  *   3         2         1
3160  *  10987654321098765432109876543210
3161  *  100010xxxxx0010001
3162  *            s[13:1] -------------
3163  *                           s[14] -
3164  */
3165 static char *BPOSGE32C(uint64 instruction, Dis_info *info)
3166 {
3167     int64 s_value = extract_s__se14_0_13_to_1_s1(instruction);
3168 
3169     g_autofree char *s = ADDRESS(s_value, 4, info);
3170 
3171     return img_format("BPOSGE32C %s", s);
3172 }
3173 
3174 
3175 /*
3176  *
3177  *
3178  *   3         2         1
3179  *  10987654321098765432109876543210
3180  *  001000               x1110000101
3181  *     rt -----
3182  *          rs -----
3183  *               rd -----
3184  */
3185 static char *BREAK_16_(uint64 instruction, Dis_info *info)
3186 {
3187     uint64 code_value = extract_code_2_1_0(instruction);
3188 
3189 
3190     return img_format("BREAK 0x%" PRIx64, code_value);
3191 }
3192 
3193 
3194 /*
3195  * BREAK code - Break. Cause a Breakpoint exception
3196  *
3197  *   3         2         1
3198  *  10987654321098765432109876543210
3199  *  001000               x1110000101
3200  *     rt -----
3201  *          rs -----
3202  *               rd -----
3203  */
3204 static char *BREAK_32_(uint64 instruction, Dis_info *info)
3205 {
3206     uint64 code_value = extract_code_18_to_0(instruction);
3207 
3208 
3209     return img_format("BREAK 0x%" PRIx64, code_value);
3210 }
3211 
3212 
3213 /*
3214  *
3215  *
3216  *   3         2         1
3217  *  10987654321098765432109876543210
3218  *  001000               x1110000101
3219  *     rt -----
3220  *          rs -----
3221  *               rd -----
3222  */
3223 static char *BRSC(uint64 instruction, Dis_info *info)
3224 {
3225     uint64 rs_value = extract_rs_20_19_18_17_16(instruction);
3226 
3227     const char *rs = GPR(rs_value, info);
3228 
3229     return img_format("BRSC %s", rs);
3230 }
3231 
3232 
3233 /*
3234  *
3235  *
3236  *   3         2         1
3237  *  10987654321098765432109876543210
3238  *  001000               x1110000101
3239  *     rt -----
3240  *          rs -----
3241  *               rd -----
3242  */
3243 static char *CACHE(uint64 instruction, Dis_info *info)
3244 {
3245     uint64 op_value = extract_op_25_24_23_22_21(instruction);
3246     uint64 rs_value = extract_rs_20_19_18_17_16(instruction);
3247     int64 s_value = extract_s__se8_15_7_6_5_4_3_2_1_0(instruction);
3248 
3249     const char *rs = GPR(rs_value, info);
3250 
3251     return img_format("CACHE 0x%" PRIx64 ", %" PRId64 "(%s)",
3252                       op_value, s_value, rs);
3253 }
3254 
3255 
3256 /*
3257  *
3258  *
3259  *   3         2         1
3260  *  10987654321098765432109876543210
3261  *  001000               x1110000101
3262  *     rt -----
3263  *          rs -----
3264  *               rd -----
3265  */
3266 static char *CACHEE(uint64 instruction, Dis_info *info)
3267 {
3268     uint64 op_value = extract_op_25_24_23_22_21(instruction);
3269     uint64 rs_value = extract_rs_20_19_18_17_16(instruction);
3270     int64 s_value = extract_s__se8_15_7_6_5_4_3_2_1_0(instruction);
3271 
3272     const char *rs = GPR(rs_value, info);
3273 
3274     return img_format("CACHEE 0x%" PRIx64 ", %" PRId64 "(%s)",
3275                       op_value, s_value, rs);
3276 }
3277 
3278 
3279 /*
3280  *
3281  *
3282  *   3         2         1
3283  *  10987654321098765432109876543210
3284  *  001000               x1110000101
3285  *     rt -----
3286  *          rs -----
3287  *               rd -----
3288  */
3289 static char *CEIL_L_D(uint64 instruction, Dis_info *info)
3290 {
3291     uint64 ft_value = extract_ft_25_24_23_22_21(instruction);
3292     uint64 fs_value = extract_fs_20_19_18_17_16(instruction);
3293 
3294     const char *ft = FPR(ft_value, info);
3295     const char *fs = FPR(fs_value, info);
3296 
3297     return img_format("CEIL.L.D %s, %s", ft, fs);
3298 }
3299 
3300 
3301 /*
3302  *
3303  *
3304  *   3         2         1
3305  *  10987654321098765432109876543210
3306  *  001000               x1110000101
3307  *     rt -----
3308  *          rs -----
3309  *               rd -----
3310  */
3311 static char *CEIL_L_S(uint64 instruction, Dis_info *info)
3312 {
3313     uint64 ft_value = extract_ft_25_24_23_22_21(instruction);
3314     uint64 fs_value = extract_fs_20_19_18_17_16(instruction);
3315 
3316     const char *ft = FPR(ft_value, info);
3317     const char *fs = FPR(fs_value, info);
3318 
3319     return img_format("CEIL.L.S %s, %s", ft, fs);
3320 }
3321 
3322 
3323 /*
3324  *
3325  *
3326  *   3         2         1
3327  *  10987654321098765432109876543210
3328  *  001000               x1110000101
3329  *     rt -----
3330  *          rs -----
3331  *               rd -----
3332  */
3333 static char *CEIL_W_D(uint64 instruction, Dis_info *info)
3334 {
3335     uint64 ft_value = extract_ft_25_24_23_22_21(instruction);
3336     uint64 fs_value = extract_fs_20_19_18_17_16(instruction);
3337 
3338     const char *ft = FPR(ft_value, info);
3339     const char *fs = FPR(fs_value, info);
3340 
3341     return img_format("CEIL.W.D %s, %s", ft, fs);
3342 }
3343 
3344 
3345 /*
3346  *
3347  *
3348  *   3         2         1
3349  *  10987654321098765432109876543210
3350  *  001000               x1110000101
3351  *     rt -----
3352  *          rs -----
3353  *               rd -----
3354  */
3355 static char *CEIL_W_S(uint64 instruction, Dis_info *info)
3356 {
3357     uint64 ft_value = extract_ft_25_24_23_22_21(instruction);
3358     uint64 fs_value = extract_fs_20_19_18_17_16(instruction);
3359 
3360     const char *ft = FPR(ft_value, info);
3361     const char *fs = FPR(fs_value, info);
3362 
3363     return img_format("CEIL.W.S %s, %s", ft, fs);
3364 }
3365 
3366 
3367 /*
3368  *
3369  *
3370  *   3         2         1
3371  *  10987654321098765432109876543210
3372  *  001000               x1110000101
3373  *     rt -----
3374  *          rs -----
3375  *               rd -----
3376  */
3377 static char *CFC1(uint64 instruction, Dis_info *info)
3378 {
3379     uint64 rt_value = extract_rt_25_24_23_22_21(instruction);
3380     uint64 cs_value = extract_cs_20_19_18_17_16(instruction);
3381 
3382     const char *rt = GPR(rt_value, info);
3383 
3384     return img_format("CFC1 %s, CP%" PRIu64, rt, cs_value);
3385 }
3386 
3387 
3388 /*
3389  *
3390  *
3391  *   3         2         1
3392  *  10987654321098765432109876543210
3393  *  001000               x1110000101
3394  *     rt -----
3395  *          rs -----
3396  *               rd -----
3397  */
3398 static char *CFC2(uint64 instruction, Dis_info *info)
3399 {
3400     uint64 rt_value = extract_rt_25_24_23_22_21(instruction);
3401     uint64 cs_value = extract_cs_20_19_18_17_16(instruction);
3402 
3403     const char *rt = GPR(rt_value, info);
3404 
3405     return img_format("CFC2 %s, CP%" PRIu64, rt, cs_value);
3406 }
3407 
3408 
3409 /*
3410  *
3411  *
3412  *   3         2         1
3413  *  10987654321098765432109876543210
3414  *  001000               x1110000101
3415  *     rt -----
3416  *          rs -----
3417  *               rd -----
3418  */
3419 static char *CLASS_D(uint64 instruction, Dis_info *info)
3420 {
3421     uint64 ft_value = extract_ft_25_24_23_22_21(instruction);
3422     uint64 fs_value = extract_fs_20_19_18_17_16(instruction);
3423 
3424     const char *ft = FPR(ft_value, info);
3425     const char *fs = FPR(fs_value, info);
3426 
3427     return img_format("CLASS.D %s, %s", ft, fs);
3428 }
3429 
3430 
3431 /*
3432  *
3433  *
3434  *   3         2         1
3435  *  10987654321098765432109876543210
3436  *  001000               x1110000101
3437  *     rt -----
3438  *          rs -----
3439  *               rd -----
3440  */
3441 static char *CLASS_S(uint64 instruction, Dis_info *info)
3442 {
3443     uint64 ft_value = extract_ft_25_24_23_22_21(instruction);
3444     uint64 fs_value = extract_fs_20_19_18_17_16(instruction);
3445 
3446     const char *ft = FPR(ft_value, info);
3447     const char *fs = FPR(fs_value, info);
3448 
3449     return img_format("CLASS.S %s, %s", ft, fs);
3450 }
3451 
3452 
3453 /*
3454  *
3455  *
3456  *   3         2         1
3457  *  10987654321098765432109876543210
3458  *  001000               x1110000101
3459  *     rt -----
3460  *          rs -----
3461  *               rd -----
3462  */
3463 static char *CLO(uint64 instruction, Dis_info *info)
3464 {
3465     uint64 rt_value = extract_rt_25_24_23_22_21(instruction);
3466     uint64 rs_value = extract_rs_20_19_18_17_16(instruction);
3467 
3468     const char *rt = GPR(rt_value, info);
3469     const char *rs = GPR(rs_value, info);
3470 
3471     return img_format("CLO %s, %s", rt, rs);
3472 }
3473 
3474 
3475 /*
3476  *
3477  *
3478  *   3         2         1
3479  *  10987654321098765432109876543210
3480  *  001000               x1110000101
3481  *     rt -----
3482  *          rs -----
3483  *               rd -----
3484  */
3485 static char *CLZ(uint64 instruction, Dis_info *info)
3486 {
3487     uint64 rt_value = extract_rt_25_24_23_22_21(instruction);
3488     uint64 rs_value = extract_rs_20_19_18_17_16(instruction);
3489 
3490     const char *rt = GPR(rt_value, info);
3491     const char *rs = GPR(rs_value, info);
3492 
3493     return img_format("CLZ %s, %s", rt, rs);
3494 }
3495 
3496 
3497 /*
3498  *
3499  *
3500  *   3         2         1
3501  *  10987654321098765432109876543210
3502  *  001000               x1110000101
3503  *     rt -----
3504  *          rs -----
3505  *               rd -----
3506  */
3507 static char *CMP_AF_D(uint64 instruction, Dis_info *info)
3508 {
3509     uint64 ft_value = extract_ft_25_24_23_22_21(instruction);
3510     uint64 fs_value = extract_fs_20_19_18_17_16(instruction);
3511     uint64 fd_value = extract_fd_15_14_13_12_11(instruction);
3512 
3513     const char *fd = FPR(fd_value, info);
3514     const char *fs = FPR(fs_value, info);
3515     const char *ft = FPR(ft_value, info);
3516 
3517     return img_format("CMP.AF.D %s, %s, %s", fd, fs, ft);
3518 }
3519 
3520 
3521 /*
3522  *
3523  *
3524  *   3         2         1
3525  *  10987654321098765432109876543210
3526  *  001000               x1110000101
3527  *     rt -----
3528  *          rs -----
3529  *               rd -----
3530  */
3531 static char *CMP_AF_S(uint64 instruction, Dis_info *info)
3532 {
3533     uint64 ft_value = extract_ft_25_24_23_22_21(instruction);
3534     uint64 fs_value = extract_fs_20_19_18_17_16(instruction);
3535     uint64 fd_value = extract_fd_15_14_13_12_11(instruction);
3536 
3537     const char *fd = FPR(fd_value, info);
3538     const char *fs = FPR(fs_value, info);
3539     const char *ft = FPR(ft_value, info);
3540 
3541     return img_format("CMP.AF.S %s, %s, %s", fd, fs, ft);
3542 }
3543 
3544 
3545 /*
3546  *
3547  *
3548  *   3         2         1
3549  *  10987654321098765432109876543210
3550  *  001000               x1110000101
3551  *     rt -----
3552  *          rs -----
3553  *               rd -----
3554  */
3555 static char *CMP_EQ_D(uint64 instruction, Dis_info *info)
3556 {
3557     uint64 ft_value = extract_ft_25_24_23_22_21(instruction);
3558     uint64 fs_value = extract_fs_20_19_18_17_16(instruction);
3559     uint64 fd_value = extract_fd_15_14_13_12_11(instruction);
3560 
3561     const char *fd = FPR(fd_value, info);
3562     const char *fs = FPR(fs_value, info);
3563     const char *ft = FPR(ft_value, info);
3564 
3565     return img_format("CMP.EQ.D %s, %s, %s", fd, fs, ft);
3566 }
3567 
3568 
3569 /*
3570  * [DSP] CMP.EQ.PH rs, rt - Compare vectors of signed integer halfword values
3571  *
3572  *   3         2         1
3573  *  10987654321098765432109876543210
3574  *  001000          xxxxxx0000000101
3575  *     rt -----
3576  *          rs -----
3577  */
3578 static char *CMP_EQ_PH(uint64 instruction, Dis_info *info)
3579 {
3580     uint64 rt_value = extract_rt_25_24_23_22_21(instruction);
3581     uint64 rs_value = extract_rs_20_19_18_17_16(instruction);
3582 
3583     const char *rs = GPR(rs_value, info);
3584     const char *rt = GPR(rt_value, info);
3585 
3586     return img_format("CMP.EQ.PH %s, %s", rs, rt);
3587 }
3588 
3589 
3590 /*
3591  *
3592  *
3593  *   3         2         1
3594  *  10987654321098765432109876543210
3595  *  001000               x1110000101
3596  *     rt -----
3597  *          rs -----
3598  *               rd -----
3599  */
3600 static char *CMP_EQ_S(uint64 instruction, Dis_info *info)
3601 {
3602     uint64 ft_value = extract_ft_25_24_23_22_21(instruction);
3603     uint64 fs_value = extract_fs_20_19_18_17_16(instruction);
3604     uint64 fd_value = extract_fd_15_14_13_12_11(instruction);
3605 
3606     const char *fd = FPR(fd_value, info);
3607     const char *fs = FPR(fs_value, info);
3608     const char *ft = FPR(ft_value, info);
3609 
3610     return img_format("CMP.EQ.S %s, %s, %s", fd, fs, ft);
3611 }
3612 
3613 
3614 /*
3615  *
3616  *
3617  *   3         2         1
3618  *  10987654321098765432109876543210
3619  *  001000               x1110000101
3620  *     rt -----
3621  *          rs -----
3622  *               rd -----
3623  */
3624 static char *CMP_LE_D(uint64 instruction, Dis_info *info)
3625 {
3626     uint64 ft_value = extract_ft_25_24_23_22_21(instruction);
3627     uint64 fs_value = extract_fs_20_19_18_17_16(instruction);
3628     uint64 fd_value = extract_fd_15_14_13_12_11(instruction);
3629 
3630     const char *fd = FPR(fd_value, info);
3631     const char *fs = FPR(fs_value, info);
3632     const char *ft = FPR(ft_value, info);
3633 
3634     return img_format("CMP.LE.D %s, %s, %s", fd, fs, ft);
3635 }
3636 
3637 
3638 /*
3639  * [DSP] CMP.LE.PH rs, rt - Compare vectors of signed integer halfword values
3640  *
3641  *   3         2         1
3642  *  10987654321098765432109876543210
3643  *  001000          xxxxxx0010000101
3644  *     rt -----
3645  *          rs -----
3646  */
3647 static char *CMP_LE_PH(uint64 instruction, Dis_info *info)
3648 {
3649     uint64 rt_value = extract_rt_25_24_23_22_21(instruction);
3650     uint64 rs_value = extract_rs_20_19_18_17_16(instruction);
3651 
3652     const char *rs = GPR(rs_value, info);
3653     const char *rt = GPR(rt_value, info);
3654 
3655     return img_format("CMP.LE.PH %s, %s", rs, rt);
3656 }
3657 
3658 
3659 /*
3660  *
3661  *
3662  *   3         2         1
3663  *  10987654321098765432109876543210
3664  *  001000               x1110000101
3665  *     rt -----
3666  *          rs -----
3667  *               rd -----
3668  */
3669 static char *CMP_LE_S(uint64 instruction, Dis_info *info)
3670 {
3671     uint64 ft_value = extract_ft_25_24_23_22_21(instruction);
3672     uint64 fs_value = extract_fs_20_19_18_17_16(instruction);
3673     uint64 fd_value = extract_fd_15_14_13_12_11(instruction);
3674 
3675     const char *fd = FPR(fd_value, info);
3676     const char *fs = FPR(fs_value, info);
3677     const char *ft = FPR(ft_value, info);
3678 
3679     return img_format("CMP.LE.S %s, %s, %s", fd, fs, ft);
3680 }
3681 
3682 
3683 /*
3684  *
3685  *
3686  *   3         2         1
3687  *  10987654321098765432109876543210
3688  *  001000               x1110000101
3689  *     rt -----
3690  *          rs -----
3691  *               rd -----
3692  */
3693 static char *CMP_LT_D(uint64 instruction, Dis_info *info)
3694 {
3695     uint64 ft_value = extract_ft_25_24_23_22_21(instruction);
3696     uint64 fs_value = extract_fs_20_19_18_17_16(instruction);
3697     uint64 fd_value = extract_fd_15_14_13_12_11(instruction);
3698 
3699     const char *fd = FPR(fd_value, info);
3700     const char *fs = FPR(fs_value, info);
3701     const char *ft = FPR(ft_value, info);
3702 
3703     return img_format("CMP.LT.D %s, %s, %s", fd, fs, ft);
3704 }
3705 
3706 
3707 /*
3708  * [DSP] CMP.LT.PH rs, rt - Compare vectors of signed integer halfword values
3709  *
3710  *   3         2         1
3711  *  10987654321098765432109876543210
3712  *  001000          xxxxxx0001000101
3713  *     rt -----
3714  *          rs -----
3715  */
3716 static char *CMP_LT_PH(uint64 instruction, Dis_info *info)
3717 {
3718     uint64 rt_value = extract_rt_25_24_23_22_21(instruction);
3719     uint64 rs_value = extract_rs_20_19_18_17_16(instruction);
3720 
3721     const char *rs = GPR(rs_value, info);
3722     const char *rt = GPR(rt_value, info);
3723 
3724     return img_format("CMP.LT.PH %s, %s", rs, rt);
3725 }
3726 
3727 
3728 /*
3729  *
3730  *
3731  *   3         2         1
3732  *  10987654321098765432109876543210
3733  *  001000               x1110000101
3734  *     rt -----
3735  *          rs -----
3736  *               rd -----
3737  */
3738 static char *CMP_LT_S(uint64 instruction, Dis_info *info)
3739 {
3740     uint64 ft_value = extract_ft_25_24_23_22_21(instruction);
3741     uint64 fs_value = extract_fs_20_19_18_17_16(instruction);
3742     uint64 fd_value = extract_fd_15_14_13_12_11(instruction);
3743 
3744     const char *fd = FPR(fd_value, info);
3745     const char *fs = FPR(fs_value, info);
3746     const char *ft = FPR(ft_value, info);
3747 
3748     return img_format("CMP.LT.S %s, %s, %s", fd, fs, ft);
3749 }
3750 
3751 
3752 /*
3753  *
3754  *
3755  *   3         2         1
3756  *  10987654321098765432109876543210
3757  *  001000               x1110000101
3758  *     rt -----
3759  *          rs -----
3760  *               rd -----
3761  */
3762 static char *CMP_NE_D(uint64 instruction, Dis_info *info)
3763 {
3764     uint64 ft_value = extract_ft_25_24_23_22_21(instruction);
3765     uint64 fs_value = extract_fs_20_19_18_17_16(instruction);
3766     uint64 fd_value = extract_fd_15_14_13_12_11(instruction);
3767 
3768     const char *fd = FPR(fd_value, info);
3769     const char *fs = FPR(fs_value, info);
3770     const char *ft = FPR(ft_value, info);
3771 
3772     return img_format("CMP.NE.D %s, %s, %s", fd, fs, ft);
3773 }
3774 
3775 
3776 /*
3777  *
3778  *
3779  *   3         2         1
3780  *  10987654321098765432109876543210
3781  *  001000               x1110000101
3782  *     rt -----
3783  *          rs -----
3784  *               rd -----
3785  */
3786 static char *CMP_NE_S(uint64 instruction, Dis_info *info)
3787 {
3788     uint64 ft_value = extract_ft_25_24_23_22_21(instruction);
3789     uint64 fs_value = extract_fs_20_19_18_17_16(instruction);
3790     uint64 fd_value = extract_fd_15_14_13_12_11(instruction);
3791 
3792     const char *fd = FPR(fd_value, info);
3793     const char *fs = FPR(fs_value, info);
3794     const char *ft = FPR(ft_value, info);
3795 
3796     return img_format("CMP.NE.S %s, %s, %s", fd, fs, ft);
3797 }
3798 
3799 
3800 /*
3801  *
3802  *
3803  *   3         2         1
3804  *  10987654321098765432109876543210
3805  *  001000               x1110000101
3806  *     rt -----
3807  *          rs -----
3808  *               rd -----
3809  */
3810 static char *CMP_OR_D(uint64 instruction, Dis_info *info)
3811 {
3812     uint64 ft_value = extract_ft_25_24_23_22_21(instruction);
3813     uint64 fs_value = extract_fs_20_19_18_17_16(instruction);
3814     uint64 fd_value = extract_fd_15_14_13_12_11(instruction);
3815 
3816     const char *fd = FPR(fd_value, info);
3817     const char *fs = FPR(fs_value, info);
3818     const char *ft = FPR(ft_value, info);
3819 
3820     return img_format("CMP.OR.D %s, %s, %s", fd, fs, ft);
3821 }
3822 
3823 
3824 /*
3825  *
3826  *
3827  *   3         2         1
3828  *  10987654321098765432109876543210
3829  *  001000               x1110000101
3830  *     rt -----
3831  *          rs -----
3832  *               rd -----
3833  */
3834 static char *CMP_OR_S(uint64 instruction, Dis_info *info)
3835 {
3836     uint64 ft_value = extract_ft_25_24_23_22_21(instruction);
3837     uint64 fs_value = extract_fs_20_19_18_17_16(instruction);
3838     uint64 fd_value = extract_fd_15_14_13_12_11(instruction);
3839 
3840     const char *fd = FPR(fd_value, info);
3841     const char *fs = FPR(fs_value, info);
3842     const char *ft = FPR(ft_value, info);
3843 
3844     return img_format("CMP.OR.S %s, %s, %s", fd, fs, ft);
3845 }
3846 
3847 
3848 /*
3849  *
3850  *
3851  *   3         2         1
3852  *  10987654321098765432109876543210
3853  *  001000               x1110000101
3854  *     rt -----
3855  *          rs -----
3856  *               rd -----
3857  */
3858 static char *CMP_SAF_D(uint64 instruction, Dis_info *info)
3859 {
3860     uint64 ft_value = extract_ft_25_24_23_22_21(instruction);
3861     uint64 fs_value = extract_fs_20_19_18_17_16(instruction);
3862     uint64 fd_value = extract_fd_15_14_13_12_11(instruction);
3863 
3864     const char *fd = FPR(fd_value, info);
3865     const char *fs = FPR(fs_value, info);
3866     const char *ft = FPR(ft_value, info);
3867 
3868     return img_format("CMP.SAF.D %s, %s, %s", fd, fs, ft);
3869 }
3870 
3871 
3872 /*
3873  *
3874  *
3875  *   3         2         1
3876  *  10987654321098765432109876543210
3877  *  001000               x1110000101
3878  *     rt -----
3879  *          rs -----
3880  *               rd -----
3881  */
3882 static char *CMP_SAF_S(uint64 instruction, Dis_info *info)
3883 {
3884     uint64 ft_value = extract_ft_25_24_23_22_21(instruction);
3885     uint64 fs_value = extract_fs_20_19_18_17_16(instruction);
3886     uint64 fd_value = extract_fd_15_14_13_12_11(instruction);
3887 
3888     const char *fd = FPR(fd_value, info);
3889     const char *fs = FPR(fs_value, info);
3890     const char *ft = FPR(ft_value, info);
3891 
3892     return img_format("CMP.SAF.S %s, %s, %s", fd, fs, ft);
3893 }
3894 
3895 
3896 /*
3897  *
3898  *
3899  *   3         2         1
3900  *  10987654321098765432109876543210
3901  *  001000               x1110000101
3902  *     rt -----
3903  *          rs -----
3904  *               rd -----
3905  */
3906 static char *CMP_SEQ_D(uint64 instruction, Dis_info *info)
3907 {
3908     uint64 ft_value = extract_ft_25_24_23_22_21(instruction);
3909     uint64 fs_value = extract_fs_20_19_18_17_16(instruction);
3910     uint64 fd_value = extract_fd_15_14_13_12_11(instruction);
3911 
3912     const char *fd = FPR(fd_value, info);
3913     const char *fs = FPR(fs_value, info);
3914     const char *ft = FPR(ft_value, info);
3915 
3916     return img_format("CMP.SEQ.D %s, %s, %s", fd, fs, ft);
3917 }
3918 
3919 
3920 /*
3921  *
3922  *
3923  *   3         2         1
3924  *  10987654321098765432109876543210
3925  *  001000               x1110000101
3926  *     rt -----
3927  *          rs -----
3928  *               rd -----
3929  */
3930 static char *CMP_SEQ_S(uint64 instruction, Dis_info *info)
3931 {
3932     uint64 ft_value = extract_ft_25_24_23_22_21(instruction);
3933     uint64 fs_value = extract_fs_20_19_18_17_16(instruction);
3934     uint64 fd_value = extract_fd_15_14_13_12_11(instruction);
3935 
3936     const char *fd = FPR(fd_value, info);
3937     const char *fs = FPR(fs_value, info);
3938     const char *ft = FPR(ft_value, info);
3939 
3940     return img_format("CMP.SEQ.S %s, %s, %s", fd, fs, ft);
3941 }
3942 
3943 
3944 /*
3945  *
3946  *
3947  *   3         2         1
3948  *  10987654321098765432109876543210
3949  *  001000               x1110000101
3950  *     rt -----
3951  *          rs -----
3952  *               rd -----
3953  */
3954 static char *CMP_SLE_D(uint64 instruction, Dis_info *info)
3955 {
3956     uint64 ft_value = extract_ft_25_24_23_22_21(instruction);
3957     uint64 fs_value = extract_fs_20_19_18_17_16(instruction);
3958     uint64 fd_value = extract_fd_15_14_13_12_11(instruction);
3959 
3960     const char *fd = FPR(fd_value, info);
3961     const char *fs = FPR(fs_value, info);
3962     const char *ft = FPR(ft_value, info);
3963 
3964     return img_format("CMP.SLE.D %s, %s, %s", fd, fs, ft);
3965 }
3966 
3967 
3968 /*
3969  *
3970  *
3971  *   3         2         1
3972  *  10987654321098765432109876543210
3973  *  001000               x1110000101
3974  *     rt -----
3975  *          rs -----
3976  *               rd -----
3977  */
3978 static char *CMP_SLE_S(uint64 instruction, Dis_info *info)
3979 {
3980     uint64 ft_value = extract_ft_25_24_23_22_21(instruction);
3981     uint64 fs_value = extract_fs_20_19_18_17_16(instruction);
3982     uint64 fd_value = extract_fd_15_14_13_12_11(instruction);
3983 
3984     const char *fd = FPR(fd_value, info);
3985     const char *fs = FPR(fs_value, info);
3986     const char *ft = FPR(ft_value, info);
3987 
3988     return img_format("CMP.SLE.S %s, %s, %s", fd, fs, ft);
3989 }
3990 
3991 
3992 /*
3993  *
3994  *
3995  *   3         2         1
3996  *  10987654321098765432109876543210
3997  *  001000               x1110000101
3998  *     rt -----
3999  *          rs -----
4000  *               rd -----
4001  */
4002 static char *CMP_SLT_D(uint64 instruction, Dis_info *info)
4003 {
4004     uint64 ft_value = extract_ft_25_24_23_22_21(instruction);
4005     uint64 fs_value = extract_fs_20_19_18_17_16(instruction);
4006     uint64 fd_value = extract_fd_15_14_13_12_11(instruction);
4007 
4008     const char *fd = FPR(fd_value, info);
4009     const char *fs = FPR(fs_value, info);
4010     const char *ft = FPR(ft_value, info);
4011 
4012     return img_format("CMP.SLT.D %s, %s, %s", fd, fs, ft);
4013 }
4014 
4015 
4016 /*
4017  *
4018  *
4019  *   3         2         1
4020  *  10987654321098765432109876543210
4021  *  001000               x1110000101
4022  *     rt -----
4023  *          rs -----
4024  *               rd -----
4025  */
4026 static char *CMP_SLT_S(uint64 instruction, Dis_info *info)
4027 {
4028     uint64 ft_value = extract_ft_25_24_23_22_21(instruction);
4029     uint64 fs_value = extract_fs_20_19_18_17_16(instruction);
4030     uint64 fd_value = extract_fd_15_14_13_12_11(instruction);
4031 
4032     const char *fd = FPR(fd_value, info);
4033     const char *fs = FPR(fs_value, info);
4034     const char *ft = FPR(ft_value, info);
4035 
4036     return img_format("CMP.SLT.S %s, %s, %s", fd, fs, ft);
4037 }
4038 
4039 
4040 /*
4041  *
4042  *
4043  *   3         2         1
4044  *  10987654321098765432109876543210
4045  *  001000               x1110000101
4046  *     rt -----
4047  *          rs -----
4048  *               rd -----
4049  */
4050 static char *CMP_SNE_D(uint64 instruction, Dis_info *info)
4051 {
4052     uint64 ft_value = extract_ft_25_24_23_22_21(instruction);
4053     uint64 fs_value = extract_fs_20_19_18_17_16(instruction);
4054     uint64 fd_value = extract_fd_15_14_13_12_11(instruction);
4055 
4056     const char *fd = FPR(fd_value, info);
4057     const char *fs = FPR(fs_value, info);
4058     const char *ft = FPR(ft_value, info);
4059 
4060     return img_format("CMP.SNE.D %s, %s, %s", fd, fs, ft);
4061 }
4062 
4063 
4064 /*
4065  *
4066  *
4067  *   3         2         1
4068  *  10987654321098765432109876543210
4069  *  001000               x1110000101
4070  *     rt -----
4071  *          rs -----
4072  *               rd -----
4073  */
4074 static char *CMP_SNE_S(uint64 instruction, Dis_info *info)
4075 {
4076     uint64 ft_value = extract_ft_25_24_23_22_21(instruction);
4077     uint64 fs_value = extract_fs_20_19_18_17_16(instruction);
4078     uint64 fd_value = extract_fd_15_14_13_12_11(instruction);
4079 
4080     const char *fd = FPR(fd_value, info);
4081     const char *fs = FPR(fs_value, info);
4082     const char *ft = FPR(ft_value, info);
4083 
4084     return img_format("CMP.SNE.S %s, %s, %s", fd, fs, ft);
4085 }
4086 
4087 
4088 /*
4089  *
4090  *
4091  *   3         2         1
4092  *  10987654321098765432109876543210
4093  *  001000               x1110000101
4094  *     rt -----
4095  *          rs -----
4096  *               rd -----
4097  */
4098 static char *CMP_SOR_D(uint64 instruction, Dis_info *info)
4099 {
4100     uint64 ft_value = extract_ft_25_24_23_22_21(instruction);
4101     uint64 fs_value = extract_fs_20_19_18_17_16(instruction);
4102     uint64 fd_value = extract_fd_15_14_13_12_11(instruction);
4103 
4104     const char *fd = FPR(fd_value, info);
4105     const char *fs = FPR(fs_value, info);
4106     const char *ft = FPR(ft_value, info);
4107 
4108     return img_format("CMP.SOR.D %s, %s, %s", fd, fs, ft);
4109 }
4110 
4111 
4112 /*
4113  *
4114  *
4115  *   3         2         1
4116  *  10987654321098765432109876543210
4117  *  001000               x1110000101
4118  *     rt -----
4119  *          rs -----
4120  *               rd -----
4121  */
4122 static char *CMP_SOR_S(uint64 instruction, Dis_info *info)
4123 {
4124     uint64 ft_value = extract_ft_25_24_23_22_21(instruction);
4125     uint64 fs_value = extract_fs_20_19_18_17_16(instruction);
4126     uint64 fd_value = extract_fd_15_14_13_12_11(instruction);
4127 
4128     const char *fd = FPR(fd_value, info);
4129     const char *fs = FPR(fs_value, info);
4130     const char *ft = FPR(ft_value, info);
4131 
4132     return img_format("CMP.SOR.S %s, %s, %s", fd, fs, ft);
4133 }
4134 
4135 
4136 /*
4137  *
4138  *
4139  *   3         2         1
4140  *  10987654321098765432109876543210
4141  *  001000               x1110000101
4142  *     rt -----
4143  *          rs -----
4144  *               rd -----
4145  */
4146 static char *CMP_SUEQ_D(uint64 instruction, Dis_info *info)
4147 {
4148     uint64 ft_value = extract_ft_25_24_23_22_21(instruction);
4149     uint64 fs_value = extract_fs_20_19_18_17_16(instruction);
4150     uint64 fd_value = extract_fd_15_14_13_12_11(instruction);
4151 
4152     const char *fd = FPR(fd_value, info);
4153     const char *fs = FPR(fs_value, info);
4154     const char *ft = FPR(ft_value, info);
4155 
4156     return img_format("CMP.SUEQ.D %s, %s, %s", fd, fs, ft);
4157 }
4158 
4159 
4160 /*
4161  *
4162  *
4163  *   3         2         1
4164  *  10987654321098765432109876543210
4165  *  001000               x1110000101
4166  *     rt -----
4167  *          rs -----
4168  *               rd -----
4169  */
4170 static char *CMP_SUEQ_S(uint64 instruction, Dis_info *info)
4171 {
4172     uint64 ft_value = extract_ft_25_24_23_22_21(instruction);
4173     uint64 fs_value = extract_fs_20_19_18_17_16(instruction);
4174     uint64 fd_value = extract_fd_15_14_13_12_11(instruction);
4175 
4176     const char *fd = FPR(fd_value, info);
4177     const char *fs = FPR(fs_value, info);
4178     const char *ft = FPR(ft_value, info);
4179 
4180     return img_format("CMP.SUEQ.S %s, %s, %s", fd, fs, ft);
4181 }
4182 
4183 
4184 /*
4185  *
4186  *
4187  *   3         2         1
4188  *  10987654321098765432109876543210
4189  *  001000               x1110000101
4190  *     rt -----
4191  *          rs -----
4192  *               rd -----
4193  */
4194 static char *CMP_SULE_D(uint64 instruction, Dis_info *info)
4195 {
4196     uint64 ft_value = extract_ft_25_24_23_22_21(instruction);
4197     uint64 fs_value = extract_fs_20_19_18_17_16(instruction);
4198     uint64 fd_value = extract_fd_15_14_13_12_11(instruction);
4199 
4200     const char *fd = FPR(fd_value, info);
4201     const char *fs = FPR(fs_value, info);
4202     const char *ft = FPR(ft_value, info);
4203 
4204     return img_format("CMP.SULE.D %s, %s, %s", fd, fs, ft);
4205 }
4206 
4207 
4208 /*
4209  *
4210  *
4211  *   3         2         1
4212  *  10987654321098765432109876543210
4213  *  001000               x1110000101
4214  *     rt -----
4215  *          rs -----
4216  *               rd -----
4217  */
4218 static char *CMP_SULE_S(uint64 instruction, Dis_info *info)
4219 {
4220     uint64 ft_value = extract_ft_25_24_23_22_21(instruction);
4221     uint64 fs_value = extract_fs_20_19_18_17_16(instruction);
4222     uint64 fd_value = extract_fd_15_14_13_12_11(instruction);
4223 
4224     const char *fd = FPR(fd_value, info);
4225     const char *fs = FPR(fs_value, info);
4226     const char *ft = FPR(ft_value, info);
4227 
4228     return img_format("CMP.SULE.S %s, %s, %s", fd, fs, ft);
4229 }
4230 
4231 
4232 /*
4233  *
4234  *
4235  *   3         2         1
4236  *  10987654321098765432109876543210
4237  *  001000               x1110000101
4238  *     rt -----
4239  *          rs -----
4240  *               rd -----
4241  */
4242 static char *CMP_SULT_D(uint64 instruction, Dis_info *info)
4243 {
4244     uint64 ft_value = extract_ft_25_24_23_22_21(instruction);
4245     uint64 fs_value = extract_fs_20_19_18_17_16(instruction);
4246     uint64 fd_value = extract_fd_15_14_13_12_11(instruction);
4247 
4248     const char *fd = FPR(fd_value, info);
4249     const char *fs = FPR(fs_value, info);
4250     const char *ft = FPR(ft_value, info);
4251 
4252     return img_format("CMP.SULT.D %s, %s, %s", fd, fs, ft);
4253 }
4254 
4255 
4256 /*
4257  *
4258  *
4259  *   3         2         1
4260  *  10987654321098765432109876543210
4261  *  001000               x1110000101
4262  *     rt -----
4263  *          rs -----
4264  *               rd -----
4265  */
4266 static char *CMP_SULT_S(uint64 instruction, Dis_info *info)
4267 {
4268     uint64 ft_value = extract_ft_25_24_23_22_21(instruction);
4269     uint64 fs_value = extract_fs_20_19_18_17_16(instruction);
4270     uint64 fd_value = extract_fd_15_14_13_12_11(instruction);
4271 
4272     const char *fd = FPR(fd_value, info);
4273     const char *fs = FPR(fs_value, info);
4274     const char *ft = FPR(ft_value, info);
4275 
4276     return img_format("CMP.SULT.S %s, %s, %s", fd, fs, ft);
4277 }
4278 
4279 
4280 /*
4281  *
4282  *
4283  *   3         2         1
4284  *  10987654321098765432109876543210
4285  *  001000               x1110000101
4286  *     rt -----
4287  *          rs -----
4288  *               rd -----
4289  */
4290 static char *CMP_SUN_D(uint64 instruction, Dis_info *info)
4291 {
4292     uint64 ft_value = extract_ft_25_24_23_22_21(instruction);
4293     uint64 fs_value = extract_fs_20_19_18_17_16(instruction);
4294     uint64 fd_value = extract_fd_15_14_13_12_11(instruction);
4295 
4296     const char *fd = FPR(fd_value, info);
4297     const char *fs = FPR(fs_value, info);
4298     const char *ft = FPR(ft_value, info);
4299 
4300     return img_format("CMP.SUN.D %s, %s, %s", fd, fs, ft);
4301 }
4302 
4303 
4304 /*
4305  *
4306  *
4307  *   3         2         1
4308  *  10987654321098765432109876543210
4309  *  001000               x1110000101
4310  *     rt -----
4311  *          rs -----
4312  *               rd -----
4313  */
4314 static char *CMP_SUNE_D(uint64 instruction, Dis_info *info)
4315 {
4316     uint64 ft_value = extract_ft_25_24_23_22_21(instruction);
4317     uint64 fs_value = extract_fs_20_19_18_17_16(instruction);
4318     uint64 fd_value = extract_fd_15_14_13_12_11(instruction);
4319 
4320     const char *fd = FPR(fd_value, info);
4321     const char *fs = FPR(fs_value, info);
4322     const char *ft = FPR(ft_value, info);
4323 
4324     return img_format("CMP.SUNE.D %s, %s, %s", fd, fs, ft);
4325 }
4326 
4327 
4328 /*
4329  *
4330  *
4331  *   3         2         1
4332  *  10987654321098765432109876543210
4333  *  001000               x1110000101
4334  *     rt -----
4335  *          rs -----
4336  *               rd -----
4337  */
4338 static char *CMP_SUNE_S(uint64 instruction, Dis_info *info)
4339 {
4340     uint64 ft_value = extract_ft_25_24_23_22_21(instruction);
4341     uint64 fs_value = extract_fs_20_19_18_17_16(instruction);
4342     uint64 fd_value = extract_fd_15_14_13_12_11(instruction);
4343 
4344     const char *fd = FPR(fd_value, info);
4345     const char *fs = FPR(fs_value, info);
4346     const char *ft = FPR(ft_value, info);
4347 
4348     return img_format("CMP.SUNE.S %s, %s, %s", fd, fs, ft);
4349 }
4350 
4351 
4352 /*
4353  *
4354  *
4355  *   3         2         1
4356  *  10987654321098765432109876543210
4357  *  001000               x1110000101
4358  *     rt -----
4359  *          rs -----
4360  *               rd -----
4361  */
4362 static char *CMP_SUN_S(uint64 instruction, Dis_info *info)
4363 {
4364     uint64 ft_value = extract_ft_25_24_23_22_21(instruction);
4365     uint64 fs_value = extract_fs_20_19_18_17_16(instruction);
4366     uint64 fd_value = extract_fd_15_14_13_12_11(instruction);
4367 
4368     const char *fd = FPR(fd_value, info);
4369     const char *fs = FPR(fs_value, info);
4370     const char *ft = FPR(ft_value, info);
4371 
4372     return img_format("CMP.SUN.S %s, %s, %s", fd, fs, ft);
4373 }
4374 
4375 
4376 /*
4377  *
4378  *
4379  *   3         2         1
4380  *  10987654321098765432109876543210
4381  *  001000               x1110000101
4382  *     rt -----
4383  *          rs -----
4384  *               rd -----
4385  */
4386 static char *CMP_UEQ_D(uint64 instruction, Dis_info *info)
4387 {
4388     uint64 ft_value = extract_ft_25_24_23_22_21(instruction);
4389     uint64 fs_value = extract_fs_20_19_18_17_16(instruction);
4390     uint64 fd_value = extract_fd_15_14_13_12_11(instruction);
4391 
4392     const char *fd = FPR(fd_value, info);
4393     const char *fs = FPR(fs_value, info);
4394     const char *ft = FPR(ft_value, info);
4395 
4396     return img_format("CMP.UEQ.D %s, %s, %s", fd, fs, ft);
4397 }
4398 
4399 
4400 /*
4401  *
4402  *
4403  *   3         2         1
4404  *  10987654321098765432109876543210
4405  *  001000               x1110000101
4406  *     rt -----
4407  *          rs -----
4408  *               rd -----
4409  */
4410 static char *CMP_UEQ_S(uint64 instruction, Dis_info *info)
4411 {
4412     uint64 ft_value = extract_ft_25_24_23_22_21(instruction);
4413     uint64 fs_value = extract_fs_20_19_18_17_16(instruction);
4414     uint64 fd_value = extract_fd_15_14_13_12_11(instruction);
4415 
4416     const char *fd = FPR(fd_value, info);
4417     const char *fs = FPR(fs_value, info);
4418     const char *ft = FPR(ft_value, info);
4419 
4420     return img_format("CMP.UEQ.S %s, %s, %s", fd, fs, ft);
4421 }
4422 
4423 
4424 /*
4425  *
4426  *
4427  *   3         2         1
4428  *  10987654321098765432109876543210
4429  *  001000               x1110000101
4430  *     rt -----
4431  *          rs -----
4432  *               rd -----
4433  */
4434 static char *CMP_ULE_D(uint64 instruction, Dis_info *info)
4435 {
4436     uint64 ft_value = extract_ft_25_24_23_22_21(instruction);
4437     uint64 fs_value = extract_fs_20_19_18_17_16(instruction);
4438     uint64 fd_value = extract_fd_15_14_13_12_11(instruction);
4439 
4440     const char *fd = FPR(fd_value, info);
4441     const char *fs = FPR(fs_value, info);
4442     const char *ft = FPR(ft_value, info);
4443 
4444     return img_format("CMP.ULE.D %s, %s, %s", fd, fs, ft);
4445 }
4446 
4447 
4448 /*
4449  *
4450  *
4451  *   3         2         1
4452  *  10987654321098765432109876543210
4453  *  001000               x1110000101
4454  *     rt -----
4455  *          rs -----
4456  *               rd -----
4457  */
4458 static char *CMP_ULE_S(uint64 instruction, Dis_info *info)
4459 {
4460     uint64 ft_value = extract_ft_25_24_23_22_21(instruction);
4461     uint64 fs_value = extract_fs_20_19_18_17_16(instruction);
4462     uint64 fd_value = extract_fd_15_14_13_12_11(instruction);
4463 
4464     const char *fd = FPR(fd_value, info);
4465     const char *fs = FPR(fs_value, info);
4466     const char *ft = FPR(ft_value, info);
4467 
4468     return img_format("CMP.ULE.S %s, %s, %s", fd, fs, ft);
4469 }
4470 
4471 
4472 /*
4473  *
4474  *
4475  *   3         2         1
4476  *  10987654321098765432109876543210
4477  *  001000               x1110000101
4478  *     rt -----
4479  *          rs -----
4480  *               rd -----
4481  */
4482 static char *CMP_ULT_D(uint64 instruction, Dis_info *info)
4483 {
4484     uint64 ft_value = extract_ft_25_24_23_22_21(instruction);
4485     uint64 fs_value = extract_fs_20_19_18_17_16(instruction);
4486     uint64 fd_value = extract_fd_15_14_13_12_11(instruction);
4487 
4488     const char *fd = FPR(fd_value, info);
4489     const char *fs = FPR(fs_value, info);
4490     const char *ft = FPR(ft_value, info);
4491 
4492     return img_format("CMP.ULT.D %s, %s, %s", fd, fs, ft);
4493 }
4494 
4495 
4496 /*
4497  *
4498  *
4499  *   3         2         1
4500  *  10987654321098765432109876543210
4501  *  001000               x1110000101
4502  *     rt -----
4503  *          rs -----
4504  *               rd -----
4505  */
4506 static char *CMP_ULT_S(uint64 instruction, Dis_info *info)
4507 {
4508     uint64 ft_value = extract_ft_25_24_23_22_21(instruction);
4509     uint64 fs_value = extract_fs_20_19_18_17_16(instruction);
4510     uint64 fd_value = extract_fd_15_14_13_12_11(instruction);
4511 
4512     const char *fd = FPR(fd_value, info);
4513     const char *fs = FPR(fs_value, info);
4514     const char *ft = FPR(ft_value, info);
4515 
4516     return img_format("CMP.ULT.S %s, %s, %s", fd, fs, ft);
4517 }
4518 
4519 
4520 /*
4521  *
4522  *
4523  *   3         2         1
4524  *  10987654321098765432109876543210
4525  *  001000               x1110000101
4526  *     rt -----
4527  *          rs -----
4528  *               rd -----
4529  */
4530 static char *CMP_UN_D(uint64 instruction, Dis_info *info)
4531 {
4532     uint64 ft_value = extract_ft_25_24_23_22_21(instruction);
4533     uint64 fs_value = extract_fs_20_19_18_17_16(instruction);
4534     uint64 fd_value = extract_fd_15_14_13_12_11(instruction);
4535 
4536     const char *fd = FPR(fd_value, info);
4537     const char *fs = FPR(fs_value, info);
4538     const char *ft = FPR(ft_value, info);
4539 
4540     return img_format("CMP.UN.D %s, %s, %s", fd, fs, ft);
4541 }
4542 
4543 
4544 /*
4545  *
4546  *
4547  *   3         2         1
4548  *  10987654321098765432109876543210
4549  *  001000               x1110000101
4550  *     rt -----
4551  *          rs -----
4552  *               rd -----
4553  */
4554 static char *CMP_UNE_D(uint64 instruction, Dis_info *info)
4555 {
4556     uint64 ft_value = extract_ft_25_24_23_22_21(instruction);
4557     uint64 fs_value = extract_fs_20_19_18_17_16(instruction);
4558     uint64 fd_value = extract_fd_15_14_13_12_11(instruction);
4559 
4560     const char *fd = FPR(fd_value, info);
4561     const char *fs = FPR(fs_value, info);
4562     const char *ft = FPR(ft_value, info);
4563 
4564     return img_format("CMP.UNE.D %s, %s, %s", fd, fs, ft);
4565 }
4566 
4567 
4568 /*
4569  *
4570  *
4571  *   3         2         1
4572  *  10987654321098765432109876543210
4573  *  001000               x1110000101
4574  *     rt -----
4575  *          rs -----
4576  *               rd -----
4577  */
4578 static char *CMP_UNE_S(uint64 instruction, Dis_info *info)
4579 {
4580     uint64 ft_value = extract_ft_25_24_23_22_21(instruction);
4581     uint64 fs_value = extract_fs_20_19_18_17_16(instruction);
4582     uint64 fd_value = extract_fd_15_14_13_12_11(instruction);
4583 
4584     const char *fd = FPR(fd_value, info);
4585     const char *fs = FPR(fs_value, info);
4586     const char *ft = FPR(ft_value, info);
4587 
4588     return img_format("CMP.UNE.S %s, %s, %s", fd, fs, ft);
4589 }
4590 
4591 
4592 /*
4593  *
4594  *
4595  *   3         2         1
4596  *  10987654321098765432109876543210
4597  *  001000               x1110000101
4598  *     rt -----
4599  *          rs -----
4600  *               rd -----
4601  */
4602 static char *CMP_UN_S(uint64 instruction, Dis_info *info)
4603 {
4604     uint64 ft_value = extract_ft_25_24_23_22_21(instruction);
4605     uint64 fs_value = extract_fs_20_19_18_17_16(instruction);
4606     uint64 fd_value = extract_fd_15_14_13_12_11(instruction);
4607 
4608     const char *fd = FPR(fd_value, info);
4609     const char *fs = FPR(fs_value, info);
4610     const char *ft = FPR(ft_value, info);
4611 
4612     return img_format("CMP.UN.S %s, %s, %s", fd, fs, ft);
4613 }
4614 
4615 
4616 /*
4617  * [DSP] CMPGDU.EQ.QB rd, rs, rt - Compare unsigned vector of
4618  *   four bytes and write result to GPR and DSPControl
4619  *
4620  *   3         2         1
4621  *  10987654321098765432109876543210
4622  *  001000               x0110000101
4623  *     rt -----
4624  *          rs -----
4625  *               rd -----
4626  */
4627 static char *CMPGDU_EQ_QB(uint64 instruction, Dis_info *info)
4628 {
4629     uint64 rt_value = extract_rt_25_24_23_22_21(instruction);
4630     uint64 rs_value = extract_rs_20_19_18_17_16(instruction);
4631     uint64 rd_value = extract_rd_15_14_13_12_11(instruction);
4632 
4633     const char *rd = GPR(rd_value, info);
4634     const char *rs = GPR(rs_value, info);
4635     const char *rt = GPR(rt_value, info);
4636 
4637     return img_format("CMPGDU.EQ.QB %s, %s, %s", rd, rs, rt);
4638 }
4639 
4640 
4641 /*
4642  * [DSP] CMPGDU.LE.QB rd, rs, rt - Compare unsigned vector of
4643  *   four bytes and write result to GPR and DSPControl
4644  *
4645  *   3         2         1
4646  *  10987654321098765432109876543210
4647  *  001000               x1000000101
4648  *     rt -----
4649  *          rs -----
4650  *               rd -----
4651  */
4652 static char *CMPGDU_LE_QB(uint64 instruction, Dis_info *info)
4653 {
4654     uint64 rt_value = extract_rt_25_24_23_22_21(instruction);
4655     uint64 rs_value = extract_rs_20_19_18_17_16(instruction);
4656     uint64 rd_value = extract_rd_15_14_13_12_11(instruction);
4657 
4658     const char *rd = GPR(rd_value, info);
4659     const char *rs = GPR(rs_value, info);
4660     const char *rt = GPR(rt_value, info);
4661 
4662     return img_format("CMPGDU.LE.QB %s, %s, %s", rd, rs, rt);
4663 }
4664 
4665 
4666 /*
4667  * [DSP] CMPGDU.EQ.QB rd, rs, rt - Compare unsigned vector of
4668  *   four bytes and write result to GPR and DSPControl
4669  *
4670  *   3         2         1
4671  *  10987654321098765432109876543210
4672  *  001000               x0111000101
4673  *     rt -----
4674  *          rs -----
4675  *               rd -----
4676  */
4677 static char *CMPGDU_LT_QB(uint64 instruction, Dis_info *info)
4678 {
4679     uint64 rt_value = extract_rt_25_24_23_22_21(instruction);
4680     uint64 rs_value = extract_rs_20_19_18_17_16(instruction);
4681     uint64 rd_value = extract_rd_15_14_13_12_11(instruction);
4682 
4683     const char *rd = GPR(rd_value, info);
4684     const char *rs = GPR(rs_value, info);
4685     const char *rt = GPR(rt_value, info);
4686 
4687     return img_format("CMPGDU.LT.QB %s, %s, %s", rd, rs, rt);
4688 }
4689 
4690 
4691 /*
4692  * [DSP] CMPGU.EQ.QB rd, rs, rt - Compare vectors of unsigned
4693  *   byte values and write result to a GPR
4694  *
4695  *   3         2         1
4696  *  10987654321098765432109876543210
4697  *  001000               x0011000101
4698  *     rt -----
4699  *          rs -----
4700  *               rd -----
4701  */
4702 static char *CMPGU_EQ_QB(uint64 instruction, Dis_info *info)
4703 {
4704     uint64 rt_value = extract_rt_25_24_23_22_21(instruction);
4705     uint64 rs_value = extract_rs_20_19_18_17_16(instruction);
4706     uint64 rd_value = extract_rd_15_14_13_12_11(instruction);
4707 
4708     const char *rd = GPR(rd_value, info);
4709     const char *rs = GPR(rs_value, info);
4710     const char *rt = GPR(rt_value, info);
4711 
4712     return img_format("CMPGU.EQ.QB %s, %s, %s", rd, rs, rt);
4713 }
4714 
4715 
4716 /*
4717  * [DSP] CMPGU.LE.QB rd, rs, rt - Compare vectors of unsigned
4718  *   byte values and write result to a GPR
4719  *
4720  *   3         2         1
4721  *  10987654321098765432109876543210
4722  *  001000               x0101000101
4723  *     rt -----
4724  *          rs -----
4725  *               rd -----
4726  */
4727 static char *CMPGU_LE_QB(uint64 instruction, Dis_info *info)
4728 {
4729     uint64 rt_value = extract_rt_25_24_23_22_21(instruction);
4730     uint64 rs_value = extract_rs_20_19_18_17_16(instruction);
4731     uint64 rd_value = extract_rd_15_14_13_12_11(instruction);
4732 
4733     const char *rd = GPR(rd_value, info);
4734     const char *rs = GPR(rs_value, info);
4735     const char *rt = GPR(rt_value, info);
4736 
4737     return img_format("CMPGU.LE.QB %s, %s, %s", rd, rs, rt);
4738 }
4739 
4740 
4741 /*
4742  * [DSP] CMPGU.LT.QB rd, rs, rt - Compare vectors of unsigned
4743  *   byte values and write result to a GPR
4744  *
4745  *   3         2         1
4746  *  10987654321098765432109876543210
4747  *  001000               x0100000101
4748  *     rt -----
4749  *          rs -----
4750  *               rd -----
4751  */
4752 static char *CMPGU_LT_QB(uint64 instruction, Dis_info *info)
4753 {
4754     uint64 rt_value = extract_rt_25_24_23_22_21(instruction);
4755     uint64 rs_value = extract_rs_20_19_18_17_16(instruction);
4756     uint64 rd_value = extract_rd_15_14_13_12_11(instruction);
4757 
4758     const char *rd = GPR(rd_value, info);
4759     const char *rs = GPR(rs_value, info);
4760     const char *rt = GPR(rt_value, info);
4761 
4762     return img_format("CMPGU.LT.QB %s, %s, %s", rd, rs, rt);
4763 }
4764 
4765 
4766 /*
4767  * [DSP] CMPU.EQ.QB rd, rs, rt - Compare vectors of unsigned
4768  *   byte values
4769  *
4770  *   3         2         1
4771  *  10987654321098765432109876543210
4772  *  001000          xxxxxx1001000101
4773  *     rt -----
4774  *          rs -----
4775  */
4776 static char *CMPU_EQ_QB(uint64 instruction, Dis_info *info)
4777 {
4778     uint64 rt_value = extract_rt_25_24_23_22_21(instruction);
4779     uint64 rs_value = extract_rs_20_19_18_17_16(instruction);
4780 
4781     const char *rs = GPR(rs_value, info);
4782     const char *rt = GPR(rt_value, info);
4783 
4784     return img_format("CMPU.EQ.QB %s, %s", rs, rt);
4785 }
4786 
4787 
4788 /*
4789  * [DSP] CMPU.LE.QB rd, rs, rt - Compare vectors of unsigned
4790  *   byte values
4791  *
4792  *   3         2         1
4793  *  10987654321098765432109876543210
4794  *  001000          xxxxxx1011000101
4795  *     rt -----
4796  *          rs -----
4797  */
4798 static char *CMPU_LE_QB(uint64 instruction, Dis_info *info)
4799 {
4800     uint64 rt_value = extract_rt_25_24_23_22_21(instruction);
4801     uint64 rs_value = extract_rs_20_19_18_17_16(instruction);
4802 
4803     const char *rs = GPR(rs_value, info);
4804     const char *rt = GPR(rt_value, info);
4805 
4806     return img_format("CMPU.LE.QB %s, %s", rs, rt);
4807 }
4808 
4809 
4810 /*
4811  * [DSP] CMPU.LT.QB rd, rs, rt - Compare vectors of unsigned
4812  *   byte values
4813  *
4814  *   3         2         1
4815  *  10987654321098765432109876543210
4816  *  001000          xxxxxx1010000101
4817  *     rt -----
4818  *          rs -----
4819  */
4820 static char *CMPU_LT_QB(uint64 instruction, Dis_info *info)
4821 {
4822     uint64 rt_value = extract_rt_25_24_23_22_21(instruction);
4823     uint64 rs_value = extract_rs_20_19_18_17_16(instruction);
4824 
4825     const char *rs = GPR(rs_value, info);
4826     const char *rt = GPR(rt_value, info);
4827 
4828     return img_format("CMPU.LT.QB %s, %s", rs, rt);
4829 }
4830 
4831 
4832 /*
4833  *
4834  *
4835  *   3         2         1
4836  *  10987654321098765432109876543210
4837  *  001000               x1110000101
4838  *     rt -----
4839  *          rs -----
4840  *               rd -----
4841  */
4842 static char *COP2_1(uint64 instruction, Dis_info *info)
4843 {
4844     uint64 cofun_value = extract_cofun_25_24_23(instruction);
4845 
4846 
4847     return img_format("COP2_1 0x%" PRIx64, cofun_value);
4848 }
4849 
4850 
4851 /*
4852  *
4853  *
4854  *   3         2         1
4855  *  10987654321098765432109876543210
4856  *  001000               x1110000101
4857  *     rt -----
4858  *          rs -----
4859  *               rd -----
4860  */
4861 static char *CTC1(uint64 instruction, Dis_info *info)
4862 {
4863     uint64 rt_value = extract_rt_25_24_23_22_21(instruction);
4864     uint64 cs_value = extract_cs_20_19_18_17_16(instruction);
4865 
4866     const char *rt = GPR(rt_value, info);
4867 
4868     return img_format("CTC1 %s, CP%" PRIu64, rt, cs_value);
4869 }
4870 
4871 
4872 /*
4873  *
4874  *
4875  *   3         2         1
4876  *  10987654321098765432109876543210
4877  *  001000               x1110000101
4878  *     rt -----
4879  *          rs -----
4880  *               rd -----
4881  */
4882 static char *CTC2(uint64 instruction, Dis_info *info)
4883 {
4884     uint64 rt_value = extract_rt_25_24_23_22_21(instruction);
4885     uint64 cs_value = extract_cs_20_19_18_17_16(instruction);
4886 
4887     const char *rt = GPR(rt_value, info);
4888 
4889     return img_format("CTC2 %s, CP%" PRIu64, rt, cs_value);
4890 }
4891 
4892 
4893 /*
4894  *
4895  *
4896  *   3         2         1
4897  *  10987654321098765432109876543210
4898  *  001000               x1110000101
4899  *     rt -----
4900  *          rs -----
4901  *               rd -----
4902  */
4903 static char *CVT_D_L(uint64 instruction, Dis_info *info)
4904 {
4905     uint64 ft_value = extract_ft_25_24_23_22_21(instruction);
4906     uint64 fs_value = extract_fs_20_19_18_17_16(instruction);
4907 
4908     const char *ft = FPR(ft_value, info);
4909     const char *fs = FPR(fs_value, info);
4910 
4911     return img_format("CVT.D.L %s, %s", ft, fs);
4912 }
4913 
4914 
4915 /*
4916  *
4917  *
4918  *   3         2         1
4919  *  10987654321098765432109876543210
4920  *  001000               x1110000101
4921  *     rt -----
4922  *          rs -----
4923  *               rd -----
4924  */
4925 static char *CVT_D_S(uint64 instruction, Dis_info *info)
4926 {
4927     uint64 ft_value = extract_ft_25_24_23_22_21(instruction);
4928     uint64 fs_value = extract_fs_20_19_18_17_16(instruction);
4929 
4930     const char *ft = FPR(ft_value, info);
4931     const char *fs = FPR(fs_value, info);
4932 
4933     return img_format("CVT.D.S %s, %s", ft, fs);
4934 }
4935 
4936 
4937 /*
4938  *
4939  *
4940  *   3         2         1
4941  *  10987654321098765432109876543210
4942  *  001000               x1110000101
4943  *     rt -----
4944  *          rs -----
4945  *               rd -----
4946  */
4947 static char *CVT_D_W(uint64 instruction, Dis_info *info)
4948 {
4949     uint64 ft_value = extract_ft_25_24_23_22_21(instruction);
4950     uint64 fs_value = extract_fs_20_19_18_17_16(instruction);
4951 
4952     const char *ft = FPR(ft_value, info);
4953     const char *fs = FPR(fs_value, info);
4954 
4955     return img_format("CVT.D.W %s, %s", ft, fs);
4956 }
4957 
4958 
4959 /*
4960  *
4961  *
4962  *   3         2         1
4963  *  10987654321098765432109876543210
4964  *  001000               x1110000101
4965  *     rt -----
4966  *          rs -----
4967  *               rd -----
4968  */
4969 static char *CVT_L_D(uint64 instruction, Dis_info *info)
4970 {
4971     uint64 ft_value = extract_ft_25_24_23_22_21(instruction);
4972     uint64 fs_value = extract_fs_20_19_18_17_16(instruction);
4973 
4974     const char *ft = FPR(ft_value, info);
4975     const char *fs = FPR(fs_value, info);
4976 
4977     return img_format("CVT.L.D %s, %s", ft, fs);
4978 }
4979 
4980 
4981 /*
4982  *
4983  *
4984  *   3         2         1
4985  *  10987654321098765432109876543210
4986  *  001000               x1110000101
4987  *     rt -----
4988  *          rs -----
4989  *               rd -----
4990  */
4991 static char *CVT_L_S(uint64 instruction, Dis_info *info)
4992 {
4993     uint64 ft_value = extract_ft_25_24_23_22_21(instruction);
4994     uint64 fs_value = extract_fs_20_19_18_17_16(instruction);
4995 
4996     const char *ft = FPR(ft_value, info);
4997     const char *fs = FPR(fs_value, info);
4998 
4999     return img_format("CVT.L.S %s, %s", ft, fs);
5000 }
5001 
5002 
5003 /*
5004  *
5005  *
5006  *   3         2         1
5007  *  10987654321098765432109876543210
5008  *  001000               x1110000101
5009  *     rt -----
5010  *          rs -----
5011  *               rd -----
5012  */
5013 static char *CVT_S_D(uint64 instruction, Dis_info *info)
5014 {
5015     uint64 ft_value = extract_ft_25_24_23_22_21(instruction);
5016     uint64 fs_value = extract_fs_20_19_18_17_16(instruction);
5017 
5018     const char *ft = FPR(ft_value, info);
5019     const char *fs = FPR(fs_value, info);
5020 
5021     return img_format("CVT.S.D %s, %s", ft, fs);
5022 }
5023 
5024 
5025 /*
5026  *
5027  *
5028  *   3         2         1
5029  *  10987654321098765432109876543210
5030  *  001000               x1110000101
5031  *     rt -----
5032  *          rs -----
5033  *               rd -----
5034  */
5035 static char *CVT_S_L(uint64 instruction, Dis_info *info)
5036 {
5037     uint64 ft_value = extract_ft_25_24_23_22_21(instruction);
5038     uint64 fs_value = extract_fs_20_19_18_17_16(instruction);
5039 
5040     const char *ft = FPR(ft_value, info);
5041     const char *fs = FPR(fs_value, info);
5042 
5043     return img_format("CVT.S.L %s, %s", ft, fs);
5044 }
5045 
5046 
5047 /*
5048  *
5049  *
5050  *   3         2         1
5051  *  10987654321098765432109876543210
5052  *  001000               x1110000101
5053  *     rt -----
5054  *          rs -----
5055  *               rd -----
5056  */
5057 static char *CVT_S_PL(uint64 instruction, Dis_info *info)
5058 {
5059     uint64 ft_value = extract_ft_25_24_23_22_21(instruction);
5060     uint64 fs_value = extract_fs_20_19_18_17_16(instruction);
5061 
5062     const char *ft = FPR(ft_value, info);
5063     const char *fs = FPR(fs_value, info);
5064 
5065     return img_format("CVT.S.PL %s, %s", ft, fs);
5066 }
5067 
5068 
5069 /*
5070  *
5071  *
5072  *   3         2         1
5073  *  10987654321098765432109876543210
5074  *  001000               x1110000101
5075  *     rt -----
5076  *          rs -----
5077  *               rd -----
5078  */
5079 static char *CVT_S_PU(uint64 instruction, Dis_info *info)
5080 {
5081     uint64 ft_value = extract_ft_25_24_23_22_21(instruction);
5082     uint64 fs_value = extract_fs_20_19_18_17_16(instruction);
5083 
5084     const char *ft = FPR(ft_value, info);
5085     const char *fs = FPR(fs_value, info);
5086 
5087     return img_format("CVT.S.PU %s, %s", ft, fs);
5088 }
5089 
5090 
5091 /*
5092  *
5093  *
5094  *   3         2         1
5095  *  10987654321098765432109876543210
5096  *  001000               x1110000101
5097  *     rt -----
5098  *          rs -----
5099  *               rd -----
5100  */
5101 static char *CVT_S_W(uint64 instruction, Dis_info *info)
5102 {
5103     uint64 ft_value = extract_ft_25_24_23_22_21(instruction);
5104     uint64 fs_value = extract_fs_20_19_18_17_16(instruction);
5105 
5106     const char *ft = FPR(ft_value, info);
5107     const char *fs = FPR(fs_value, info);
5108 
5109     return img_format("CVT.S.W %s, %s", ft, fs);
5110 }
5111 
5112 
5113 /*
5114  *
5115  *
5116  *   3         2         1
5117  *  10987654321098765432109876543210
5118  *  001000               x1110000101
5119  *     rt -----
5120  *          rs -----
5121  *               rd -----
5122  */
5123 static char *CVT_W_D(uint64 instruction, Dis_info *info)
5124 {
5125     uint64 ft_value = extract_ft_25_24_23_22_21(instruction);
5126     uint64 fs_value = extract_fs_20_19_18_17_16(instruction);
5127 
5128     const char *ft = FPR(ft_value, info);
5129     const char *fs = FPR(fs_value, info);
5130 
5131     return img_format("CVT.W.D %s, %s", ft, fs);
5132 }
5133 
5134 
5135 /*
5136  *
5137  *
5138  *   3         2         1
5139  *  10987654321098765432109876543210
5140  *  001000               x1110000101
5141  *     rt -----
5142  *          rs -----
5143  *               rd -----
5144  */
5145 static char *CVT_W_S(uint64 instruction, Dis_info *info)
5146 {
5147     uint64 ft_value = extract_ft_25_24_23_22_21(instruction);
5148     uint64 fs_value = extract_fs_20_19_18_17_16(instruction);
5149 
5150     const char *ft = FPR(ft_value, info);
5151     const char *fs = FPR(fs_value, info);
5152 
5153     return img_format("CVT.W.S %s, %s", ft, fs);
5154 }
5155 
5156 
5157 /*
5158  *
5159  *
5160  *   3         2         1
5161  *  10987654321098765432109876543210
5162  *  001000               x1110000101
5163  *     rt -----
5164  *          rs -----
5165  *               rd -----
5166  */
5167 static char *DADDIU_48_(uint64 instruction, Dis_info *info)
5168 {
5169     uint64 rt_value = extract_rt_41_40_39_38_37(instruction);
5170     int64 s_value = extract_s__se31_15_to_0_31_to_16(instruction);
5171 
5172     const char *rt = GPR(rt_value, info);
5173 
5174     return img_format("DADDIU %s, %" PRId64, rt, s_value);
5175 }
5176 
5177 
5178 /*
5179  *
5180  *
5181  *   3         2         1
5182  *  10987654321098765432109876543210
5183  *  001000               x1110000101
5184  *     rt -----
5185  *          rs -----
5186  *               rd -----
5187  */
5188 static char *DADDIU_NEG_(uint64 instruction, Dis_info *info)
5189 {
5190     uint64 rt_value = extract_rt_25_24_23_22_21(instruction);
5191     uint64 rs_value = extract_rs_20_19_18_17_16(instruction);
5192     uint64 u_value = extract_u_11_10_9_8_7_6_5_4_3_2_1_0(instruction);
5193 
5194     const char *rt = GPR(rt_value, info);
5195     const char *rs = GPR(rs_value, info);
5196     int64 u = neg_copy(u_value);
5197 
5198     return img_format("DADDIU %s, %s, %" PRId64, rt, rs, u);
5199 }
5200 
5201 
5202 /*
5203  *
5204  *
5205  *   3         2         1
5206  *  10987654321098765432109876543210
5207  *  001000               x1110000101
5208  *     rt -----
5209  *          rs -----
5210  *               rd -----
5211  */
5212 static char *DADDIU_U12_(uint64 instruction, Dis_info *info)
5213 {
5214     uint64 rt_value = extract_rt_25_24_23_22_21(instruction);
5215     uint64 rs_value = extract_rs_20_19_18_17_16(instruction);
5216     uint64 u_value = extract_u_11_10_9_8_7_6_5_4_3_2_1_0(instruction);
5217 
5218     const char *rt = GPR(rt_value, info);
5219     const char *rs = GPR(rs_value, info);
5220 
5221     return img_format("DADDIU %s, %s, 0x%" PRIx64, rt, rs, u_value);
5222 }
5223 
5224 
5225 /*
5226  *
5227  *
5228  *   3         2         1
5229  *  10987654321098765432109876543210
5230  *  001000               x1110000101
5231  *     rt -----
5232  *          rs -----
5233  *               rd -----
5234  */
5235 static char *DADD(uint64 instruction, Dis_info *info)
5236 {
5237     uint64 rt_value = extract_rt_25_24_23_22_21(instruction);
5238     uint64 rs_value = extract_rs_20_19_18_17_16(instruction);
5239     uint64 rd_value = extract_rd_15_14_13_12_11(instruction);
5240 
5241     const char *rd = GPR(rd_value, info);
5242     const char *rs = GPR(rs_value, info);
5243     const char *rt = GPR(rt_value, info);
5244 
5245     return img_format("DADD %s, %s, %s", rd, rs, rt);
5246 }
5247 
5248 
5249 /*
5250  *
5251  *
5252  *   3         2         1
5253  *  10987654321098765432109876543210
5254  *  001000               x1110000101
5255  *     rt -----
5256  *          rs -----
5257  *               rd -----
5258  */
5259 static char *DADDU(uint64 instruction, Dis_info *info)
5260 {
5261     uint64 rt_value = extract_rt_25_24_23_22_21(instruction);
5262     uint64 rs_value = extract_rs_20_19_18_17_16(instruction);
5263     uint64 rd_value = extract_rd_15_14_13_12_11(instruction);
5264 
5265     const char *rd = GPR(rd_value, info);
5266     const char *rs = GPR(rs_value, info);
5267     const char *rt = GPR(rt_value, info);
5268 
5269     return img_format("DADDU %s, %s, %s", rd, rs, rt);
5270 }
5271 
5272 
5273 /*
5274  *
5275  *
5276  *   3         2         1
5277  *  10987654321098765432109876543210
5278  *  001000               x1110000101
5279  *     rt -----
5280  *          rs -----
5281  *               rd -----
5282  */
5283 static char *DCLO(uint64 instruction, Dis_info *info)
5284 {
5285     uint64 rt_value = extract_rt_25_24_23_22_21(instruction);
5286     uint64 rs_value = extract_rs_20_19_18_17_16(instruction);
5287 
5288     const char *rt = GPR(rt_value, info);
5289     const char *rs = GPR(rs_value, info);
5290 
5291     return img_format("DCLO %s, %s", rt, rs);
5292 }
5293 
5294 
5295 /*
5296  *
5297  *
5298  *   3         2         1
5299  *  10987654321098765432109876543210
5300  *  001000               x1110000101
5301  *     rt -----
5302  *          rs -----
5303  *               rd -----
5304  */
5305 static char *DCLZ(uint64 instruction, Dis_info *info)
5306 {
5307     uint64 rt_value = extract_rt_25_24_23_22_21(instruction);
5308     uint64 rs_value = extract_rs_20_19_18_17_16(instruction);
5309 
5310     const char *rt = GPR(rt_value, info);
5311     const char *rs = GPR(rs_value, info);
5312 
5313     return img_format("DCLZ %s, %s", rt, rs);
5314 }
5315 
5316 
5317 /*
5318  *
5319  *
5320  *   3         2         1
5321  *  10987654321098765432109876543210
5322  *  001000               x1110000101
5323  *     rt -----
5324  *          rs -----
5325  *               rd -----
5326  */
5327 static char *DDIV(uint64 instruction, Dis_info *info)
5328 {
5329     uint64 rt_value = extract_rt_25_24_23_22_21(instruction);
5330     uint64 rs_value = extract_rs_20_19_18_17_16(instruction);
5331     uint64 rd_value = extract_rd_15_14_13_12_11(instruction);
5332 
5333     const char *rd = GPR(rd_value, info);
5334     const char *rs = GPR(rs_value, info);
5335     const char *rt = GPR(rt_value, info);
5336 
5337     return img_format("DDIV %s, %s, %s", rd, rs, rt);
5338 }
5339 
5340 
5341 /*
5342  *
5343  *
5344  *   3         2         1
5345  *  10987654321098765432109876543210
5346  *  001000               x1110000101
5347  *     rt -----
5348  *          rs -----
5349  *               rd -----
5350  */
5351 static char *DDIVU(uint64 instruction, Dis_info *info)
5352 {
5353     uint64 rt_value = extract_rt_25_24_23_22_21(instruction);
5354     uint64 rs_value = extract_rs_20_19_18_17_16(instruction);
5355     uint64 rd_value = extract_rd_15_14_13_12_11(instruction);
5356 
5357     const char *rd = GPR(rd_value, info);
5358     const char *rs = GPR(rs_value, info);
5359     const char *rt = GPR(rt_value, info);
5360 
5361     return img_format("DDIVU %s, %s, %s", rd, rs, rt);
5362 }
5363 
5364 
5365 /*
5366  *
5367  *
5368  *   3         2         1
5369  *  10987654321098765432109876543210
5370  *  001000               x1110000101
5371  *     rt -----
5372  *          rs -----
5373  *               rd -----
5374  */
5375 static char *DERET(uint64 instruction, Dis_info *info)
5376 {
5377     (void)instruction;
5378 
5379     return g_strdup("DERET ");
5380 }
5381 
5382 
5383 /*
5384  *
5385  *
5386  *   3         2         1
5387  *  10987654321098765432109876543210
5388  *  001000               x1110000101
5389  *     rt -----
5390  *          rs -----
5391  *               rd -----
5392  */
5393 static char *DEXTM(uint64 instruction, Dis_info *info)
5394 {
5395     uint64 rt_value = extract_rt_25_24_23_22_21(instruction);
5396     uint64 rs_value = extract_rs_20_19_18_17_16(instruction);
5397     uint64 msbd_value = extract_msbt_10_9_8_7_6(instruction);
5398     uint64 lsb_value = extract_lsb_4_3_2_1_0(instruction);
5399 
5400     const char *rt = GPR(rt_value, info);
5401     const char *rs = GPR(rs_value, info);
5402     uint64 msbd = encode_msbd_from_size(msbd_value);
5403 
5404     return img_format("DEXTM %s, %s, 0x%" PRIx64 ", 0x%" PRIx64,
5405                       rt, rs, lsb_value, msbd);
5406 }
5407 
5408 
5409 /*
5410  *
5411  *
5412  *   3         2         1
5413  *  10987654321098765432109876543210
5414  *  001000               x1110000101
5415  *     rt -----
5416  *          rs -----
5417  *               rd -----
5418  */
5419 static char *DEXT(uint64 instruction, Dis_info *info)
5420 {
5421     uint64 rt_value = extract_rt_25_24_23_22_21(instruction);
5422     uint64 rs_value = extract_rs_20_19_18_17_16(instruction);
5423     uint64 msbd_value = extract_msbt_10_9_8_7_6(instruction);
5424     uint64 lsb_value = extract_lsb_4_3_2_1_0(instruction);
5425 
5426     const char *rt = GPR(rt_value, info);
5427     const char *rs = GPR(rs_value, info);
5428     uint64 msbd = encode_msbd_from_size(msbd_value);
5429 
5430     return img_format("DEXT %s, %s, 0x%" PRIx64 ", 0x%" PRIx64,
5431                       rt, rs, lsb_value, msbd);
5432 }
5433 
5434 
5435 /*
5436  *
5437  *
5438  *   3         2         1
5439  *  10987654321098765432109876543210
5440  *  001000               x1110000101
5441  *     rt -----
5442  *          rs -----
5443  *               rd -----
5444  */
5445 static char *DEXTU(uint64 instruction, Dis_info *info)
5446 {
5447     uint64 rt_value = extract_rt_25_24_23_22_21(instruction);
5448     uint64 rs_value = extract_rs_20_19_18_17_16(instruction);
5449     uint64 msbd_value = extract_msbt_10_9_8_7_6(instruction);
5450     uint64 lsb_value = extract_lsb_4_3_2_1_0(instruction);
5451 
5452     const char *rt = GPR(rt_value, info);
5453     const char *rs = GPR(rs_value, info);
5454     uint64 msbd = encode_msbd_from_size(msbd_value);
5455 
5456     return img_format("DEXTU %s, %s, 0x%" PRIx64 ", 0x%" PRIx64,
5457                       rt, rs, lsb_value, msbd);
5458 }
5459 
5460 
5461 /*
5462  *
5463  *
5464  *   3         2         1
5465  *  10987654321098765432109876543210
5466  *  001000               x1110000101
5467  *     rt -----
5468  *          rs -----
5469  *               rd -----
5470  */
5471 static char *DINSM(uint64 instruction, Dis_info *info)
5472 {
5473     uint64 rt_value = extract_rt_25_24_23_22_21(instruction);
5474     uint64 rs_value = extract_rs_20_19_18_17_16(instruction);
5475     uint64 msbd_value = extract_msbt_10_9_8_7_6(instruction);
5476     uint64 lsb_value = extract_lsb_4_3_2_1_0(instruction);
5477 
5478     const char *rt = GPR(rt_value, info);
5479     const char *rs = GPR(rs_value, info);
5480     /* !!!!!!!!!! - no conversion function */
5481 
5482     return img_format("DINSM %s, %s, 0x%" PRIx64 ", 0x%" PRIx64,
5483                       rt, rs, lsb_value, msbd_value);
5484     /* hand edited */
5485 }
5486 
5487 
5488 /*
5489  *
5490  *
5491  *   3         2         1
5492  *  10987654321098765432109876543210
5493  *  001000               x1110000101
5494  *     rt -----
5495  *          rs -----
5496  *               rd -----
5497  */
5498 static char *DINS(uint64 instruction, Dis_info *info)
5499 {
5500     uint64 rt_value = extract_rt_25_24_23_22_21(instruction);
5501     uint64 rs_value = extract_rs_20_19_18_17_16(instruction);
5502     uint64 msbd_value = extract_msbt_10_9_8_7_6(instruction);
5503     uint64 lsb_value = extract_lsb_4_3_2_1_0(instruction);
5504 
5505     const char *rt = GPR(rt_value, info);
5506     const char *rs = GPR(rs_value, info);
5507     /* !!!!!!!!!! - no conversion function */
5508 
5509     return img_format("DINS %s, %s, 0x%" PRIx64 ", 0x%" PRIx64,
5510                       rt, rs, lsb_value, msbd_value);
5511     /* hand edited */
5512 }
5513 
5514 
5515 /*
5516  *
5517  *
5518  *   3         2         1
5519  *  10987654321098765432109876543210
5520  *  001000               x1110000101
5521  *     rt -----
5522  *          rs -----
5523  *               rd -----
5524  */
5525 static char *DINSU(uint64 instruction, Dis_info *info)
5526 {
5527     uint64 rt_value = extract_rt_25_24_23_22_21(instruction);
5528     uint64 rs_value = extract_rs_20_19_18_17_16(instruction);
5529     uint64 msbd_value = extract_msbt_10_9_8_7_6(instruction);
5530     uint64 lsb_value = extract_lsb_4_3_2_1_0(instruction);
5531 
5532     const char *rt = GPR(rt_value, info);
5533     const char *rs = GPR(rs_value, info);
5534     /* !!!!!!!!!! - no conversion function */
5535 
5536     return img_format("DINSU %s, %s, 0x%" PRIx64 ", 0x%" PRIx64,
5537                       rt, rs, lsb_value, msbd_value);
5538     /* hand edited */
5539 }
5540 
5541 
5542 /*
5543  *
5544  *
5545  *   3         2         1
5546  *  10987654321098765432109876543210
5547  *  001000               x1110000101
5548  *     rt -----
5549  *          rs -----
5550  *               rd -----
5551  */
5552 static char *DI(uint64 instruction, Dis_info *info)
5553 {
5554     uint64 rt_value = extract_rt_25_24_23_22_21(instruction);
5555 
5556     const char *rt = GPR(rt_value, info);
5557 
5558     return img_format("DI %s", rt);
5559 }
5560 
5561 
5562 /*
5563  *
5564  *
5565  *   3         2         1
5566  *  10987654321098765432109876543210
5567  *  001000               x1110000101
5568  *     rt -----
5569  *          rs -----
5570  *               rd -----
5571  */
5572 static char *DIV(uint64 instruction, Dis_info *info)
5573 {
5574     uint64 rt_value = extract_rt_25_24_23_22_21(instruction);
5575     uint64 rs_value = extract_rs_20_19_18_17_16(instruction);
5576     uint64 rd_value = extract_rd_15_14_13_12_11(instruction);
5577 
5578     const char *rd = GPR(rd_value, info);
5579     const char *rs = GPR(rs_value, info);
5580     const char *rt = GPR(rt_value, info);
5581 
5582     return img_format("DIV %s, %s, %s", rd, rs, rt);
5583 }
5584 
5585 
5586 /*
5587  *
5588  *
5589  *   3         2         1
5590  *  10987654321098765432109876543210
5591  *  001000               x1110000101
5592  *     rt -----
5593  *          rs -----
5594  *               rd -----
5595  */
5596 static char *DIV_D(uint64 instruction, Dis_info *info)
5597 {
5598     uint64 ft_value = extract_ft_25_24_23_22_21(instruction);
5599     uint64 fs_value = extract_fs_20_19_18_17_16(instruction);
5600     uint64 fd_value = extract_fd_15_14_13_12_11(instruction);
5601 
5602     const char *fd = FPR(fd_value, info);
5603     const char *fs = FPR(fs_value, info);
5604     const char *ft = FPR(ft_value, info);
5605 
5606     return img_format("DIV.D %s, %s, %s", fd, fs, ft);
5607 }
5608 
5609 
5610 /*
5611  *
5612  *
5613  *   3         2         1
5614  *  10987654321098765432109876543210
5615  *  001000               x1110000101
5616  *     rt -----
5617  *          rs -----
5618  *               rd -----
5619  */
5620 static char *DIV_S(uint64 instruction, Dis_info *info)
5621 {
5622     uint64 ft_value = extract_ft_25_24_23_22_21(instruction);
5623     uint64 fs_value = extract_fs_20_19_18_17_16(instruction);
5624     uint64 fd_value = extract_fd_15_14_13_12_11(instruction);
5625 
5626     const char *fd = FPR(fd_value, info);
5627     const char *fs = FPR(fs_value, info);
5628     const char *ft = FPR(ft_value, info);
5629 
5630     return img_format("DIV.S %s, %s, %s", fd, fs, ft);
5631 }
5632 
5633 
5634 /*
5635  *
5636  *
5637  *   3         2         1
5638  *  10987654321098765432109876543210
5639  *  001000               x1110000101
5640  *     rt -----
5641  *          rs -----
5642  *               rd -----
5643  */
5644 static char *DIVU(uint64 instruction, Dis_info *info)
5645 {
5646     uint64 rt_value = extract_rt_25_24_23_22_21(instruction);
5647     uint64 rs_value = extract_rs_20_19_18_17_16(instruction);
5648     uint64 rd_value = extract_rd_15_14_13_12_11(instruction);
5649 
5650     const char *rd = GPR(rd_value, info);
5651     const char *rs = GPR(rs_value, info);
5652     const char *rt = GPR(rt_value, info);
5653 
5654     return img_format("DIVU %s, %s, %s", rd, rs, rt);
5655 }
5656 
5657 
5658 /*
5659  *
5660  *
5661  *   3         2         1
5662  *  10987654321098765432109876543210
5663  *  001000               x1110000101
5664  *     rt -----
5665  *          rs -----
5666  *               rd -----
5667  */
5668 static char *DLSA(uint64 instruction, Dis_info *info)
5669 {
5670     uint64 rt_value = extract_rt_25_24_23_22_21(instruction);
5671     uint64 rs_value = extract_rs_20_19_18_17_16(instruction);
5672     uint64 rd_value = extract_rd_15_14_13_12_11(instruction);
5673     uint64 u2_value = extract_u2_10_9(instruction);
5674 
5675     const char *rd = GPR(rd_value, info);
5676     const char *rs = GPR(rs_value, info);
5677     const char *rt = GPR(rt_value, info);
5678 
5679     return img_format("DLSA %s, %s, %s, 0x%" PRIx64, rd, rs, rt, u2_value);
5680 }
5681 
5682 
5683 /*
5684  *
5685  *
5686  *   3         2         1
5687  *  10987654321098765432109876543210
5688  *  001000               x1110000101
5689  *     rt -----
5690  *          rs -----
5691  *               rd -----
5692  */
5693 static char *DLUI_48_(uint64 instruction, Dis_info *info)
5694 {
5695     uint64 rt_value = extract_rt_41_40_39_38_37(instruction);
5696     uint64 u_value = extract_u_31_to_0__s32(instruction);
5697 
5698     const char *rt = GPR(rt_value, info);
5699 
5700     return img_format("DLUI %s, 0x%" PRIx64, rt, u_value);
5701 }
5702 
5703 
5704 /*
5705  *
5706  *
5707  *   3         2         1
5708  *  10987654321098765432109876543210
5709  *  001000               x1110000101
5710  *     rt -----
5711  *          rs -----
5712  *               rd -----
5713  */
5714 static char *DMFC0(uint64 instruction, Dis_info *info)
5715 {
5716     uint64 rt_value = extract_rt_25_24_23_22_21(instruction);
5717     uint64 c0s_value = extract_c0s_20_19_18_17_16(instruction);
5718     uint64 sel_value = extract_sel_15_14_13_12_11(instruction);
5719 
5720     const char *rt = GPR(rt_value, info);
5721 
5722     return img_format("DMFC0 %s, CP%" PRIu64 ", 0x%" PRIx64,
5723                       rt, c0s_value, sel_value);
5724 }
5725 
5726 
5727 /*
5728  *
5729  *
5730  *   3         2         1
5731  *  10987654321098765432109876543210
5732  *  001000               x1110000101
5733  *     rt -----
5734  *          rs -----
5735  *               rd -----
5736  */
5737 static char *DMFC1(uint64 instruction, Dis_info *info)
5738 {
5739     uint64 rt_value = extract_rt_25_24_23_22_21(instruction);
5740     uint64 fs_value = extract_fs_20_19_18_17_16(instruction);
5741 
5742     const char *rt = GPR(rt_value, info);
5743     const char *fs = FPR(fs_value, info);
5744 
5745     return img_format("DMFC1 %s, %s", rt, fs);
5746 }
5747 
5748 
5749 /*
5750  *
5751  *
5752  *   3         2         1
5753  *  10987654321098765432109876543210
5754  *  001000               x1110000101
5755  *     rt -----
5756  *          rs -----
5757  *               rd -----
5758  */
5759 static char *DMFC2(uint64 instruction, Dis_info *info)
5760 {
5761     uint64 rt_value = extract_rt_25_24_23_22_21(instruction);
5762     uint64 cs_value = extract_cs_20_19_18_17_16(instruction);
5763 
5764     const char *rt = GPR(rt_value, info);
5765 
5766     return img_format("DMFC2 %s, CP%" PRIu64, rt, cs_value);
5767 }
5768 
5769 
5770 /*
5771  *
5772  *
5773  *   3         2         1
5774  *  10987654321098765432109876543210
5775  *  001000               x1110000101
5776  *     rt -----
5777  *          rs -----
5778  *               rd -----
5779  */
5780 static char *DMFGC0(uint64 instruction, Dis_info *info)
5781 {
5782     uint64 rt_value = extract_rt_25_24_23_22_21(instruction);
5783     uint64 c0s_value = extract_c0s_20_19_18_17_16(instruction);
5784     uint64 sel_value = extract_sel_15_14_13_12_11(instruction);
5785 
5786     const char *rt = GPR(rt_value, info);
5787 
5788     return img_format("DMFGC0 %s, CP%" PRIu64 ", 0x%" PRIx64,
5789                       rt, c0s_value, sel_value);
5790 }
5791 
5792 
5793 /*
5794  *
5795  *
5796  *   3         2         1
5797  *  10987654321098765432109876543210
5798  *  001000               x1110000101
5799  *     rt -----
5800  *          rs -----
5801  *               rd -----
5802  */
5803 static char *DMOD(uint64 instruction, Dis_info *info)
5804 {
5805     uint64 rt_value = extract_rt_25_24_23_22_21(instruction);
5806     uint64 rs_value = extract_rs_20_19_18_17_16(instruction);
5807     uint64 rd_value = extract_rd_15_14_13_12_11(instruction);
5808 
5809     const char *rd = GPR(rd_value, info);
5810     const char *rs = GPR(rs_value, info);
5811     const char *rt = GPR(rt_value, info);
5812 
5813     return img_format("DMOD %s, %s, %s", rd, rs, rt);
5814 }
5815 
5816 
5817 /*
5818  *
5819  *
5820  *   3         2         1
5821  *  10987654321098765432109876543210
5822  *  001000               x1110000101
5823  *     rt -----
5824  *          rs -----
5825  *               rd -----
5826  */
5827 static char *DMODU(uint64 instruction, Dis_info *info)
5828 {
5829     uint64 rt_value = extract_rt_25_24_23_22_21(instruction);
5830     uint64 rs_value = extract_rs_20_19_18_17_16(instruction);
5831     uint64 rd_value = extract_rd_15_14_13_12_11(instruction);
5832 
5833     const char *rd = GPR(rd_value, info);
5834     const char *rs = GPR(rs_value, info);
5835     const char *rt = GPR(rt_value, info);
5836 
5837     return img_format("DMODU %s, %s, %s", rd, rs, rt);
5838 }
5839 
5840 
5841 /*
5842  *
5843  *
5844  *   3         2         1
5845  *  10987654321098765432109876543210
5846  *  001000               x1110000101
5847  *     rt -----
5848  *          rs -----
5849  *               rd -----
5850  */
5851 static char *DMTC0(uint64 instruction, Dis_info *info)
5852 {
5853     uint64 rt_value = extract_rt_25_24_23_22_21(instruction);
5854     uint64 c0s_value = extract_c0s_20_19_18_17_16(instruction);
5855     uint64 sel_value = extract_sel_15_14_13_12_11(instruction);
5856 
5857     const char *rt = GPR(rt_value, info);
5858 
5859     return img_format("DMTC0 %s, CP%" PRIu64 ", 0x%" PRIx64,
5860                       rt, c0s_value, sel_value);
5861 }
5862 
5863 
5864 /*
5865  *
5866  *
5867  *   3         2         1
5868  *  10987654321098765432109876543210
5869  *  001000               x1110000101
5870  *     rt -----
5871  *          rs -----
5872  *               rd -----
5873  */
5874 static char *DMTC1(uint64 instruction, Dis_info *info)
5875 {
5876     uint64 rt_value = extract_rt_25_24_23_22_21(instruction);
5877     uint64 fs_value = extract_fs_20_19_18_17_16(instruction);
5878 
5879     const char *rt = GPR(rt_value, info);
5880     const char *fs = FPR(fs_value, info);
5881 
5882     return img_format("DMTC1 %s, %s", rt, fs);
5883 }
5884 
5885 
5886 /*
5887  *
5888  *
5889  *   3         2         1
5890  *  10987654321098765432109876543210
5891  *  001000               x1110000101
5892  *     rt -----
5893  *          rs -----
5894  *               rd -----
5895  */
5896 static char *DMTC2(uint64 instruction, Dis_info *info)
5897 {
5898     uint64 rt_value = extract_rt_25_24_23_22_21(instruction);
5899     uint64 cs_value = extract_cs_20_19_18_17_16(instruction);
5900 
5901     const char *rt = GPR(rt_value, info);
5902 
5903     return img_format("DMTC2 %s, CP%" PRIu64, rt, cs_value);
5904 }
5905 
5906 
5907 /*
5908  *
5909  *
5910  *   3         2         1
5911  *  10987654321098765432109876543210
5912  *  001000               x1110000101
5913  *     rt -----
5914  *          rs -----
5915  *               rd -----
5916  */
5917 static char *DMTGC0(uint64 instruction, Dis_info *info)
5918 {
5919     uint64 rt_value = extract_rt_25_24_23_22_21(instruction);
5920     uint64 c0s_value = extract_c0s_20_19_18_17_16(instruction);
5921     uint64 sel_value = extract_sel_15_14_13_12_11(instruction);
5922 
5923     const char *rt = GPR(rt_value, info);
5924 
5925     return img_format("DMTGC0 %s, CP%" PRIu64 ", 0x%" PRIx64,
5926                       rt, c0s_value, sel_value);
5927 }
5928 
5929 
5930 /*
5931  *
5932  *
5933  *   3         2         1
5934  *  10987654321098765432109876543210
5935  *  001000               x1110000101
5936  *     rt -----
5937  *          rs -----
5938  *               rd -----
5939  */
5940 static char *DMT(uint64 instruction, Dis_info *info)
5941 {
5942     uint64 rt_value = extract_rt_25_24_23_22_21(instruction);
5943 
5944     const char *rt = GPR(rt_value, info);
5945 
5946     return img_format("DMT %s", rt);
5947 }
5948 
5949 
5950 /*
5951  *
5952  *
5953  *   3         2         1
5954  *  10987654321098765432109876543210
5955  *  001000               x1110000101
5956  *     rt -----
5957  *          rs -----
5958  *               rd -----
5959  */
5960 static char *DMUH(uint64 instruction, Dis_info *info)
5961 {
5962     uint64 rt_value = extract_rt_25_24_23_22_21(instruction);
5963     uint64 rs_value = extract_rs_20_19_18_17_16(instruction);
5964     uint64 rd_value = extract_rd_15_14_13_12_11(instruction);
5965 
5966     const char *rd = GPR(rd_value, info);
5967     const char *rs = GPR(rs_value, info);
5968     const char *rt = GPR(rt_value, info);
5969 
5970     return img_format("DMUH %s, %s, %s", rd, rs, rt);
5971 }
5972 
5973 
5974 /*
5975  *
5976  *
5977  *   3         2         1
5978  *  10987654321098765432109876543210
5979  *  001000               x1110000101
5980  *     rt -----
5981  *          rs -----
5982  *               rd -----
5983  */
5984 static char *DMUHU(uint64 instruction, Dis_info *info)
5985 {
5986     uint64 rt_value = extract_rt_25_24_23_22_21(instruction);
5987     uint64 rs_value = extract_rs_20_19_18_17_16(instruction);
5988     uint64 rd_value = extract_rd_15_14_13_12_11(instruction);
5989 
5990     const char *rd = GPR(rd_value, info);
5991     const char *rs = GPR(rs_value, info);
5992     const char *rt = GPR(rt_value, info);
5993 
5994     return img_format("DMUHU %s, %s, %s", rd, rs, rt);
5995 }
5996 
5997 
5998 /*
5999  *
6000  *
6001  *   3         2         1
6002  *  10987654321098765432109876543210
6003  *  001000               x1110000101
6004  *     rt -----
6005  *          rs -----
6006  *               rd -----
6007  */
6008 static char *DMUL(uint64 instruction, Dis_info *info)
6009 {
6010     uint64 rt_value = extract_rt_25_24_23_22_21(instruction);
6011     uint64 rs_value = extract_rs_20_19_18_17_16(instruction);
6012     uint64 rd_value = extract_rd_15_14_13_12_11(instruction);
6013 
6014     const char *rd = GPR(rd_value, info);
6015     const char *rs = GPR(rs_value, info);
6016     const char *rt = GPR(rt_value, info);
6017 
6018     return img_format("DMUL %s, %s, %s", rd, rs, rt);
6019 }
6020 
6021 
6022 /*
6023  *
6024  *
6025  *   3         2         1
6026  *  10987654321098765432109876543210
6027  *  001000               x1110000101
6028  *     rt -----
6029  *          rs -----
6030  *               rd -----
6031  */
6032 static char *DMULU(uint64 instruction, Dis_info *info)
6033 {
6034     uint64 rt_value = extract_rt_25_24_23_22_21(instruction);
6035     uint64 rs_value = extract_rs_20_19_18_17_16(instruction);
6036     uint64 rd_value = extract_rd_15_14_13_12_11(instruction);
6037 
6038     const char *rd = GPR(rd_value, info);
6039     const char *rs = GPR(rs_value, info);
6040     const char *rt = GPR(rt_value, info);
6041 
6042     return img_format("DMULU %s, %s, %s", rd, rs, rt);
6043 }
6044 
6045 
6046 /*
6047  * [DSP] DPA.W.PH ac, rs, rt - Dot product with accumulate on
6048  *   vector integer halfword elements
6049  *
6050  *   3         2         1
6051  *  10987654321098765432109876543210
6052  *  001000            00000010111111
6053  *     rt -----
6054  *          rs -----
6055  *               ac --
6056  */
6057 static char *DPA_W_PH(uint64 instruction, Dis_info *info)
6058 {
6059     uint64 rt_value = extract_rt_25_24_23_22_21(instruction);
6060     uint64 rs_value = extract_rs_20_19_18_17_16(instruction);
6061     uint64 ac_value = extract_ac_15_14(instruction);
6062 
6063     const char *ac = AC(ac_value, info);
6064     const char *rs = GPR(rs_value, info);
6065     const char *rt = GPR(rt_value, info);
6066 
6067     return img_format("DPA.W.PH %s, %s, %s", ac, rs, rt);
6068 }
6069 
6070 
6071 /*
6072  *
6073  *
6074  *   3         2         1
6075  *  10987654321098765432109876543210
6076  *  001000               x1110000101
6077  *     rt -----
6078  *          rs -----
6079  *               rd -----
6080  */
6081 static char *DPAQ_SA_L_W(uint64 instruction, Dis_info *info)
6082 {
6083     uint64 rt_value = extract_rt_25_24_23_22_21(instruction);
6084     uint64 rs_value = extract_rs_20_19_18_17_16(instruction);
6085     uint64 ac_value = extract_ac_15_14(instruction);
6086 
6087     const char *ac = AC(ac_value, info);
6088     const char *rs = GPR(rs_value, info);
6089     const char *rt = GPR(rt_value, info);
6090 
6091     return img_format("DPAQ_SA.L.W %s, %s, %s", ac, rs, rt);
6092 }
6093 
6094 
6095 /*
6096  *
6097  *
6098  *   3         2         1
6099  *  10987654321098765432109876543210
6100  *  001000               x1110000101
6101  *     rt -----
6102  *          rs -----
6103  *               rd -----
6104  */
6105 static char *DPAQ_S_W_PH(uint64 instruction, Dis_info *info)
6106 {
6107     uint64 rt_value = extract_rt_25_24_23_22_21(instruction);
6108     uint64 rs_value = extract_rs_20_19_18_17_16(instruction);
6109     uint64 ac_value = extract_ac_15_14(instruction);
6110 
6111     const char *ac = AC(ac_value, info);
6112     const char *rs = GPR(rs_value, info);
6113     const char *rt = GPR(rt_value, info);
6114 
6115     return img_format("DPAQ_S.W.PH %s, %s, %s", ac, rs, rt);
6116 }
6117 
6118 
6119 /*
6120  *
6121  *
6122  *   3         2         1
6123  *  10987654321098765432109876543210
6124  *  001000               x1110000101
6125  *     rt -----
6126  *          rs -----
6127  *               rd -----
6128  */
6129 static char *DPAQX_SA_W_PH(uint64 instruction, Dis_info *info)
6130 {
6131     uint64 rt_value = extract_rt_25_24_23_22_21(instruction);
6132     uint64 rs_value = extract_rs_20_19_18_17_16(instruction);
6133     uint64 ac_value = extract_ac_15_14(instruction);
6134 
6135     const char *ac = AC(ac_value, info);
6136     const char *rs = GPR(rs_value, info);
6137     const char *rt = GPR(rt_value, info);
6138 
6139     return img_format("DPAQX_SA.W.PH %s, %s, %s", ac, rs, rt);
6140 }
6141 
6142 
6143 /*
6144  *
6145  *
6146  *   3         2         1
6147  *  10987654321098765432109876543210
6148  *  001000               x1110000101
6149  *     rt -----
6150  *          rs -----
6151  *               rd -----
6152  */
6153 static char *DPAQX_S_W_PH(uint64 instruction, Dis_info *info)
6154 {
6155     uint64 rt_value = extract_rt_25_24_23_22_21(instruction);
6156     uint64 rs_value = extract_rs_20_19_18_17_16(instruction);
6157     uint64 ac_value = extract_ac_15_14(instruction);
6158 
6159     const char *ac = AC(ac_value, info);
6160     const char *rs = GPR(rs_value, info);
6161     const char *rt = GPR(rt_value, info);
6162 
6163     return img_format("DPAQX_S.W.PH %s, %s, %s", ac, rs, rt);
6164 }
6165 
6166 
6167 /*
6168  *
6169  *
6170  *   3         2         1
6171  *  10987654321098765432109876543210
6172  *  001000               x1110000101
6173  *     rt -----
6174  *          rs -----
6175  *               rd -----
6176  */
6177 static char *DPAU_H_QBL(uint64 instruction, Dis_info *info)
6178 {
6179     uint64 rt_value = extract_rt_25_24_23_22_21(instruction);
6180     uint64 rs_value = extract_rs_20_19_18_17_16(instruction);
6181     uint64 ac_value = extract_ac_15_14(instruction);
6182 
6183     const char *ac = AC(ac_value, info);
6184     const char *rs = GPR(rs_value, info);
6185     const char *rt = GPR(rt_value, info);
6186 
6187     return img_format("DPAU.H.QBL %s, %s, %s", ac, rs, rt);
6188 }
6189 
6190 
6191 /*
6192  *
6193  *
6194  *   3         2         1
6195  *  10987654321098765432109876543210
6196  *  001000               x1110000101
6197  *     rt -----
6198  *          rs -----
6199  *               rd -----
6200  */
6201 static char *DPAU_H_QBR(uint64 instruction, Dis_info *info)
6202 {
6203     uint64 rt_value = extract_rt_25_24_23_22_21(instruction);
6204     uint64 rs_value = extract_rs_20_19_18_17_16(instruction);
6205     uint64 ac_value = extract_ac_15_14(instruction);
6206 
6207     const char *ac = AC(ac_value, info);
6208     const char *rs = GPR(rs_value, info);
6209     const char *rt = GPR(rt_value, info);
6210 
6211     return img_format("DPAU.H.QBR %s, %s, %s", ac, rs, rt);
6212 }
6213 
6214 
6215 /*
6216  *
6217  *
6218  *   3         2         1
6219  *  10987654321098765432109876543210
6220  *  001000               x1110000101
6221  *     rt -----
6222  *          rs -----
6223  *               rd -----
6224  */
6225 static char *DPAX_W_PH(uint64 instruction, Dis_info *info)
6226 {
6227     uint64 rt_value = extract_rt_25_24_23_22_21(instruction);
6228     uint64 rs_value = extract_rs_20_19_18_17_16(instruction);
6229     uint64 ac_value = extract_ac_15_14(instruction);
6230 
6231     const char *ac = AC(ac_value, info);
6232     const char *rs = GPR(rs_value, info);
6233     const char *rt = GPR(rt_value, info);
6234 
6235     return img_format("DPAX.W.PH %s, %s, %s", ac, rs, rt);
6236 }
6237 
6238 
6239 /*
6240  *
6241  *
6242  *   3         2         1
6243  *  10987654321098765432109876543210
6244  *  001000               x1110000101
6245  *     rt -----
6246  *          rs -----
6247  *               rd -----
6248  */
6249 static char *DPS_W_PH(uint64 instruction, Dis_info *info)
6250 {
6251     uint64 rt_value = extract_rt_25_24_23_22_21(instruction);
6252     uint64 rs_value = extract_rs_20_19_18_17_16(instruction);
6253     uint64 ac_value = extract_ac_15_14(instruction);
6254 
6255     const char *ac = AC(ac_value, info);
6256     const char *rs = GPR(rs_value, info);
6257     const char *rt = GPR(rt_value, info);
6258 
6259     return img_format("DPS.W.PH %s, %s, %s", ac, rs, rt);
6260 }
6261 
6262 
6263 /*
6264  *
6265  *
6266  *   3         2         1
6267  *  10987654321098765432109876543210
6268  *  001000               x1110000101
6269  *     rt -----
6270  *          rs -----
6271  *               rd -----
6272  */
6273 static char *DPSQ_SA_L_W(uint64 instruction, Dis_info *info)
6274 {
6275     uint64 rt_value = extract_rt_25_24_23_22_21(instruction);
6276     uint64 rs_value = extract_rs_20_19_18_17_16(instruction);
6277     uint64 ac_value = extract_ac_15_14(instruction);
6278 
6279     const char *ac = AC(ac_value, info);
6280     const char *rs = GPR(rs_value, info);
6281     const char *rt = GPR(rt_value, info);
6282 
6283     return img_format("DPSQ_SA.L.W %s, %s, %s", ac, rs, rt);
6284 }
6285 
6286 
6287 /*
6288  *
6289  *
6290  *   3         2         1
6291  *  10987654321098765432109876543210
6292  *  001000               x1110000101
6293  *     rt -----
6294  *          rs -----
6295  *               rd -----
6296  */
6297 static char *DPSQ_S_W_PH(uint64 instruction, Dis_info *info)
6298 {
6299     uint64 rt_value = extract_rt_25_24_23_22_21(instruction);
6300     uint64 rs_value = extract_rs_20_19_18_17_16(instruction);
6301     uint64 ac_value = extract_ac_15_14(instruction);
6302 
6303     const char *ac = AC(ac_value, info);
6304     const char *rs = GPR(rs_value, info);
6305     const char *rt = GPR(rt_value, info);
6306 
6307     return img_format("DPSQ_S.W.PH %s, %s, %s", ac, rs, rt);
6308 }
6309 
6310 
6311 /*
6312  *
6313  *
6314  *   3         2         1
6315  *  10987654321098765432109876543210
6316  *  001000               x1110000101
6317  *     rt -----
6318  *          rs -----
6319  *               rd -----
6320  */
6321 static char *DPSQX_SA_W_PH(uint64 instruction, Dis_info *info)
6322 {
6323     uint64 rt_value = extract_rt_25_24_23_22_21(instruction);
6324     uint64 rs_value = extract_rs_20_19_18_17_16(instruction);
6325     uint64 ac_value = extract_ac_15_14(instruction);
6326 
6327     const char *ac = AC(ac_value, info);
6328     const char *rs = GPR(rs_value, info);
6329     const char *rt = GPR(rt_value, info);
6330 
6331     return img_format("DPSQX_SA.W.PH %s, %s, %s", ac, rs, rt);
6332 }
6333 
6334 
6335 /*
6336  *
6337  *
6338  *   3         2         1
6339  *  10987654321098765432109876543210
6340  *  001000               x1110000101
6341  *     rt -----
6342  *          rs -----
6343  *               rd -----
6344  */
6345 static char *DPSQX_S_W_PH(uint64 instruction, Dis_info *info)
6346 {
6347     uint64 rt_value = extract_rt_25_24_23_22_21(instruction);
6348     uint64 rs_value = extract_rs_20_19_18_17_16(instruction);
6349     uint64 ac_value = extract_ac_15_14(instruction);
6350 
6351     const char *ac = AC(ac_value, info);
6352     const char *rs = GPR(rs_value, info);
6353     const char *rt = GPR(rt_value, info);
6354 
6355     return img_format("DPSQX_S.W.PH %s, %s, %s", ac, rs, rt);
6356 }
6357 
6358 
6359 /*
6360  *
6361  *
6362  *   3         2         1
6363  *  10987654321098765432109876543210
6364  *  001000               x1110000101
6365  *     rt -----
6366  *          rs -----
6367  *               rd -----
6368  */
6369 static char *DPSU_H_QBL(uint64 instruction, Dis_info *info)
6370 {
6371     uint64 rt_value = extract_rt_25_24_23_22_21(instruction);
6372     uint64 rs_value = extract_rs_20_19_18_17_16(instruction);
6373     uint64 ac_value = extract_ac_15_14(instruction);
6374 
6375     const char *ac = AC(ac_value, info);
6376     const char *rs = GPR(rs_value, info);
6377     const char *rt = GPR(rt_value, info);
6378 
6379     return img_format("DPSU.H.QBL %s, %s, %s", ac, rs, rt);
6380 }
6381 
6382 
6383 /*
6384  *
6385  *
6386  *   3         2         1
6387  *  10987654321098765432109876543210
6388  *  001000               x1110000101
6389  *     rt -----
6390  *          rs -----
6391  *               rd -----
6392  */
6393 static char *DPSU_H_QBR(uint64 instruction, Dis_info *info)
6394 {
6395     uint64 rt_value = extract_rt_25_24_23_22_21(instruction);
6396     uint64 rs_value = extract_rs_20_19_18_17_16(instruction);
6397     uint64 ac_value = extract_ac_15_14(instruction);
6398 
6399     const char *ac = AC(ac_value, info);
6400     const char *rs = GPR(rs_value, info);
6401     const char *rt = GPR(rt_value, info);
6402 
6403     return img_format("DPSU.H.QBR %s, %s, %s", ac, rs, rt);
6404 }
6405 
6406 
6407 /*
6408  *
6409  *
6410  *   3         2         1
6411  *  10987654321098765432109876543210
6412  *  001000               x1110000101
6413  *     rt -----
6414  *          rs -----
6415  *               rd -----
6416  */
6417 static char *DPSX_W_PH(uint64 instruction, Dis_info *info)
6418 {
6419     uint64 rt_value = extract_rt_25_24_23_22_21(instruction);
6420     uint64 rs_value = extract_rs_20_19_18_17_16(instruction);
6421     uint64 ac_value = extract_ac_15_14(instruction);
6422 
6423     const char *ac = AC(ac_value, info);
6424     const char *rs = GPR(rs_value, info);
6425     const char *rt = GPR(rt_value, info);
6426 
6427     return img_format("DPSX.W.PH %s, %s, %s", ac, rs, rt);
6428 }
6429 
6430 
6431 /*
6432  * DROTR -
6433  *
6434  *   3         2         1
6435  *  10987654321098765432109876543210
6436  *  001000               x1110000101
6437  *     rt -----
6438  *          rs -----
6439  *               rd -----
6440  */
6441 static char *DROTR(uint64 instruction, Dis_info *info)
6442 {
6443     uint64 rt_value = extract_rt_25_24_23_22_21(instruction);
6444     uint64 rs_value = extract_rs_20_19_18_17_16(instruction);
6445     uint64 shift_value = extract_shift_4_3_2_1_0(instruction);
6446 
6447     const char *rt = GPR(rt_value, info);
6448     const char *rs = GPR(rs_value, info);
6449 
6450     return img_format("DROTR %s, %s, 0x%" PRIx64, rt, rs, shift_value);
6451 }
6452 
6453 
6454 /*
6455  * DROTR[32] -
6456  *
6457  *   3         2         1
6458  *  10987654321098765432109876543210
6459  *  10o000          1100xxx0110
6460  *     rt -----
6461  *          rs -----
6462  *                       shift -----
6463  */
6464 static char *DROTR32(uint64 instruction, Dis_info *info)
6465 {
6466     uint64 rt_value = extract_rt_25_24_23_22_21(instruction);
6467     uint64 rs_value = extract_rs_20_19_18_17_16(instruction);
6468     uint64 shift_value = extract_shift_4_3_2_1_0(instruction);
6469 
6470     const char *rt = GPR(rt_value, info);
6471     const char *rs = GPR(rs_value, info);
6472 
6473     return img_format("DROTR32 %s, %s, 0x%" PRIx64, rt, rs, shift_value);
6474 }
6475 
6476 
6477 /*
6478  *
6479  *
6480  *   3         2         1
6481  *  10987654321098765432109876543210
6482  *  001000               x1110000101
6483  *     rt -----
6484  *          rs -----
6485  *               rd -----
6486  */
6487 static char *DROTRV(uint64 instruction, Dis_info *info)
6488 {
6489     uint64 rt_value = extract_rt_25_24_23_22_21(instruction);
6490     uint64 rs_value = extract_rs_20_19_18_17_16(instruction);
6491     uint64 rd_value = extract_rd_15_14_13_12_11(instruction);
6492 
6493     const char *rd = GPR(rd_value, info);
6494     const char *rs = GPR(rs_value, info);
6495     const char *rt = GPR(rt_value, info);
6496 
6497     return img_format("DROTRV %s, %s, %s", rd, rs, rt);
6498 }
6499 
6500 
6501 /*
6502  *
6503  *
6504  *   3         2         1
6505  *  10987654321098765432109876543210
6506  *  001000               x1110000101
6507  *     rt -----
6508  *          rs -----
6509  *               rd -----
6510  */
6511 static char *DROTX(uint64 instruction, Dis_info *info)
6512 {
6513     uint64 rt_value = extract_rt_25_24_23_22_21(instruction);
6514     uint64 rs_value = extract_rs_20_19_18_17_16(instruction);
6515     uint64 shiftx_value = extract_shiftx_11_10_9_8_7_6(instruction);
6516     uint64 shift_value = extract_shift_5_4_3_2_1_0(instruction);
6517 
6518     const char *rt = GPR(rt_value, info);
6519     const char *rs = GPR(rs_value, info);
6520 
6521     return img_format("DROTX %s, %s, 0x%" PRIx64 ", 0x%" PRIx64,
6522                       rt, rs, shift_value, shiftx_value);
6523 }
6524 
6525 
6526 /*
6527  * DSLL -
6528  *
6529  *   3         2         1
6530  *  10987654321098765432109876543210
6531  *  10o000          1100xxx0000
6532  *     rt -----
6533  *          rs -----
6534  *                       shift -----
6535  */
6536 static char *DSLL(uint64 instruction, Dis_info *info)
6537 {
6538     uint64 rt_value = extract_rt_25_24_23_22_21(instruction);
6539     uint64 rs_value = extract_rs_20_19_18_17_16(instruction);
6540     uint64 shift_value = extract_shift_4_3_2_1_0(instruction);
6541 
6542     const char *rt = GPR(rt_value, info);
6543     const char *rs = GPR(rs_value, info);
6544 
6545     return img_format("DSLL %s, %s, 0x%" PRIx64, rt, rs, shift_value);
6546 }
6547 
6548 
6549 /*
6550  * DSLL[32] -
6551  *
6552  *   3         2         1
6553  *  10987654321098765432109876543210
6554  *  10o000          1100xxx0000
6555  *     rt -----
6556  *          rs -----
6557  *                       shift -----
6558  */
6559 static char *DSLL32(uint64 instruction, Dis_info *info)
6560 {
6561     uint64 rt_value = extract_rt_25_24_23_22_21(instruction);
6562     uint64 rs_value = extract_rs_20_19_18_17_16(instruction);
6563     uint64 shift_value = extract_shift_4_3_2_1_0(instruction);
6564 
6565     const char *rt = GPR(rt_value, info);
6566     const char *rs = GPR(rs_value, info);
6567 
6568     return img_format("DSLL32 %s, %s, 0x%" PRIx64, rt, rs, shift_value);
6569 }
6570 
6571 
6572 /*
6573  *
6574  *
6575  *   3         2         1
6576  *  10987654321098765432109876543210
6577  *  001000               x1110000101
6578  *     rt -----
6579  *          rs -----
6580  *               rd -----
6581  */
6582 static char *DSLLV(uint64 instruction, Dis_info *info)
6583 {
6584     uint64 rt_value = extract_rt_25_24_23_22_21(instruction);
6585     uint64 rs_value = extract_rs_20_19_18_17_16(instruction);
6586     uint64 rd_value = extract_rd_15_14_13_12_11(instruction);
6587 
6588     const char *rd = GPR(rd_value, info);
6589     const char *rs = GPR(rs_value, info);
6590     const char *rt = GPR(rt_value, info);
6591 
6592     return img_format("DSLLV %s, %s, %s", rd, rs, rt);
6593 }
6594 
6595 
6596 /*
6597  * DSRA -
6598  *
6599  *   3         2         1
6600  *  10987654321098765432109876543210
6601  *  10o000          1100xxx0100
6602  *     rt -----
6603  *          rs -----
6604  *                       shift -----
6605  */
6606 static char *DSRA(uint64 instruction, Dis_info *info)
6607 {
6608     uint64 rt_value = extract_rt_25_24_23_22_21(instruction);
6609     uint64 rs_value = extract_rs_20_19_18_17_16(instruction);
6610     uint64 shift_value = extract_shift_4_3_2_1_0(instruction);
6611 
6612     const char *rt = GPR(rt_value, info);
6613     const char *rs = GPR(rs_value, info);
6614 
6615     return img_format("DSRA %s, %s, 0x%" PRIx64, rt, rs, shift_value);
6616 }
6617 
6618 
6619 /*
6620  * DSRA[32] -
6621  *
6622  *   3         2         1
6623  *  10987654321098765432109876543210
6624  *  10o000          1100xxx0100
6625  *     rt -----
6626  *          rs -----
6627  *                       shift -----
6628  */
6629 static char *DSRA32(uint64 instruction, Dis_info *info)
6630 {
6631     uint64 rt_value = extract_rt_25_24_23_22_21(instruction);
6632     uint64 rs_value = extract_rs_20_19_18_17_16(instruction);
6633     uint64 shift_value = extract_shift_4_3_2_1_0(instruction);
6634 
6635     const char *rt = GPR(rt_value, info);
6636     const char *rs = GPR(rs_value, info);
6637 
6638     return img_format("DSRA32 %s, %s, 0x%" PRIx64, rt, rs, shift_value);
6639 }
6640 
6641 
6642 /*
6643  *
6644  *
6645  *   3         2         1
6646  *  10987654321098765432109876543210
6647  *  001000               x1110000101
6648  *     rt -----
6649  *          rs -----
6650  *               rd -----
6651  */
6652 static char *DSRAV(uint64 instruction, Dis_info *info)
6653 {
6654     uint64 rt_value = extract_rt_25_24_23_22_21(instruction);
6655     uint64 rs_value = extract_rs_20_19_18_17_16(instruction);
6656     uint64 rd_value = extract_rd_15_14_13_12_11(instruction);
6657 
6658     const char *rd = GPR(rd_value, info);
6659     const char *rs = GPR(rs_value, info);
6660     const char *rt = GPR(rt_value, info);
6661 
6662     return img_format("DSRAV %s, %s, %s", rd, rs, rt);
6663 }
6664 
6665 
6666 /*
6667  * DSRL -
6668  *
6669  *   3         2         1
6670  *  10987654321098765432109876543210
6671  *  10o000          1100xxx0100
6672  *     rt -----
6673  *          rs -----
6674  *                       shift -----
6675  */
6676 static char *DSRL(uint64 instruction, Dis_info *info)
6677 {
6678     uint64 rt_value = extract_rt_25_24_23_22_21(instruction);
6679     uint64 rs_value = extract_rs_20_19_18_17_16(instruction);
6680     uint64 shift_value = extract_shift_4_3_2_1_0(instruction);
6681 
6682     const char *rt = GPR(rt_value, info);
6683     const char *rs = GPR(rs_value, info);
6684 
6685     return img_format("DSRL %s, %s, 0x%" PRIx64, rt, rs, shift_value);
6686 }
6687 
6688 
6689 /*
6690  * DSRL[32] -
6691  *
6692  *   3         2         1
6693  *  10987654321098765432109876543210
6694  *  10o000          1100xxx0010
6695  *     rt -----
6696  *          rs -----
6697  *                       shift -----
6698  */
6699 static char *DSRL32(uint64 instruction, Dis_info *info)
6700 {
6701     uint64 rt_value = extract_rt_25_24_23_22_21(instruction);
6702     uint64 rs_value = extract_rs_20_19_18_17_16(instruction);
6703     uint64 shift_value = extract_shift_4_3_2_1_0(instruction);
6704 
6705     const char *rt = GPR(rt_value, info);
6706     const char *rs = GPR(rs_value, info);
6707 
6708     return img_format("DSRL32 %s, %s, 0x%" PRIx64, rt, rs, shift_value);
6709 }
6710 
6711 
6712 /*
6713  *
6714  *
6715  *   3         2         1
6716  *  10987654321098765432109876543210
6717  *  001000               x1110000101
6718  *     rt -----
6719  *          rs -----
6720  *               rd -----
6721  */
6722 static char *DSRLV(uint64 instruction, Dis_info *info)
6723 {
6724     uint64 rt_value = extract_rt_25_24_23_22_21(instruction);
6725     uint64 rs_value = extract_rs_20_19_18_17_16(instruction);
6726     uint64 rd_value = extract_rd_15_14_13_12_11(instruction);
6727 
6728     const char *rd = GPR(rd_value, info);
6729     const char *rs = GPR(rs_value, info);
6730     const char *rt = GPR(rt_value, info);
6731 
6732     return img_format("DSRLV %s, %s, %s", rd, rs, rt);
6733 }
6734 
6735 
6736 /*
6737  *
6738  *
6739  *   3         2         1
6740  *  10987654321098765432109876543210
6741  *  001000               x1110000101
6742  *     rt -----
6743  *          rs -----
6744  *               rd -----
6745  */
6746 static char *DSUB(uint64 instruction, Dis_info *info)
6747 {
6748     uint64 rt_value = extract_rt_25_24_23_22_21(instruction);
6749     uint64 rs_value = extract_rs_20_19_18_17_16(instruction);
6750     uint64 rd_value = extract_rd_15_14_13_12_11(instruction);
6751 
6752     const char *rd = GPR(rd_value, info);
6753     const char *rs = GPR(rs_value, info);
6754     const char *rt = GPR(rt_value, info);
6755 
6756     return img_format("DSUB %s, %s, %s", rd, rs, rt);
6757 }
6758 
6759 
6760 /*
6761  *
6762  *
6763  *   3         2         1
6764  *  10987654321098765432109876543210
6765  *  001000               x1110000101
6766  *     rt -----
6767  *          rs -----
6768  *               rd -----
6769  */
6770 static char *DSUBU(uint64 instruction, Dis_info *info)
6771 {
6772     uint64 rt_value = extract_rt_25_24_23_22_21(instruction);
6773     uint64 rs_value = extract_rs_20_19_18_17_16(instruction);
6774     uint64 rd_value = extract_rd_15_14_13_12_11(instruction);
6775 
6776     const char *rd = GPR(rd_value, info);
6777     const char *rs = GPR(rs_value, info);
6778     const char *rt = GPR(rt_value, info);
6779 
6780     return img_format("DSUBU %s, %s, %s", rd, rs, rt);
6781 }
6782 
6783 
6784 /*
6785  *
6786  *
6787  *   3         2         1
6788  *  10987654321098765432109876543210
6789  *  001000               x1110000101
6790  *     rt -----
6791  *          rs -----
6792  *               rd -----
6793  */
6794 static char *DVPE(uint64 instruction, Dis_info *info)
6795 {
6796     uint64 rt_value = extract_rt_25_24_23_22_21(instruction);
6797 
6798     const char *rt = GPR(rt_value, info);
6799 
6800     return img_format("DVPE %s", rt);
6801 }
6802 
6803 
6804 /*
6805  *
6806  *
6807  *   3         2         1
6808  *  10987654321098765432109876543210
6809  *  001000               x1110000101
6810  *     rt -----
6811  *          rs -----
6812  *               rd -----
6813  */
6814 static char *DVP(uint64 instruction, Dis_info *info)
6815 {
6816     uint64 rt_value = extract_rt_25_24_23_22_21(instruction);
6817 
6818     const char *rt = GPR(rt_value, info);
6819 
6820     return img_format("DVP %s", rt);
6821 }
6822 
6823 
6824 /*
6825  *
6826  *
6827  *   3         2         1
6828  *  10987654321098765432109876543210
6829  *  001000               x1110000101
6830  *     rt -----
6831  *          rs -----
6832  *               rd -----
6833  */
6834 static char *EHB(uint64 instruction, Dis_info *info)
6835 {
6836     (void)instruction;
6837 
6838     return g_strdup("EHB ");
6839 }
6840 
6841 
6842 /*
6843  *
6844  *
6845  *   3         2         1
6846  *  10987654321098765432109876543210
6847  *  001000               x1110000101
6848  *     rt -----
6849  *          rs -----
6850  *               rd -----
6851  */
6852 static char *EI(uint64 instruction, Dis_info *info)
6853 {
6854     uint64 rt_value = extract_rt_25_24_23_22_21(instruction);
6855 
6856     const char *rt = GPR(rt_value, info);
6857 
6858     return img_format("EI %s", rt);
6859 }
6860 
6861 
6862 /*
6863  *
6864  *
6865  *   3         2         1
6866  *  10987654321098765432109876543210
6867  *  001000               x1110000101
6868  *     rt -----
6869  *          rs -----
6870  *               rd -----
6871  */
6872 static char *EMT(uint64 instruction, Dis_info *info)
6873 {
6874     uint64 rt_value = extract_rt_25_24_23_22_21(instruction);
6875 
6876     const char *rt = GPR(rt_value, info);
6877 
6878     return img_format("EMT %s", rt);
6879 }
6880 
6881 
6882 /*
6883  *
6884  *
6885  *   3         2         1
6886  *  10987654321098765432109876543210
6887  *  001000               x1110000101
6888  *     rt -----
6889  *          rs -----
6890  *               rd -----
6891  */
6892 static char *ERET(uint64 instruction, Dis_info *info)
6893 {
6894     (void)instruction;
6895 
6896     return g_strdup("ERET ");
6897 }
6898 
6899 
6900 /*
6901  *
6902  *
6903  *   3         2         1
6904  *  10987654321098765432109876543210
6905  *  001000               x1110000101
6906  *     rt -----
6907  *          rs -----
6908  *               rd -----
6909  */
6910 static char *ERETNC(uint64 instruction, Dis_info *info)
6911 {
6912     (void)instruction;
6913 
6914     return g_strdup("ERETNC ");
6915 }
6916 
6917 
6918 /*
6919  *
6920  *
6921  *   3         2         1
6922  *  10987654321098765432109876543210
6923  *  001000               x1110000101
6924  *     rt -----
6925  *          rs -----
6926  *               rd -----
6927  */
6928 static char *EVP(uint64 instruction, Dis_info *info)
6929 {
6930     uint64 rt_value = extract_rt_25_24_23_22_21(instruction);
6931 
6932     const char *rt = GPR(rt_value, info);
6933 
6934     return img_format("EVP %s", rt);
6935 }
6936 
6937 
6938 /*
6939  *
6940  *
6941  *   3         2         1
6942  *  10987654321098765432109876543210
6943  *  001000               x1110000101
6944  *     rt -----
6945  *          rs -----
6946  *               rd -----
6947  */
6948 static char *EVPE(uint64 instruction, Dis_info *info)
6949 {
6950     uint64 rt_value = extract_rt_25_24_23_22_21(instruction);
6951 
6952     const char *rt = GPR(rt_value, info);
6953 
6954     return img_format("EVPE %s", rt);
6955 }
6956 
6957 
6958 /*
6959  *
6960  *
6961  *   3         2         1
6962  *  10987654321098765432109876543210
6963  *  001000               x1110000101
6964  *     rt -----
6965  *          rs -----
6966  *               rd -----
6967  */
6968 static char *EXT(uint64 instruction, Dis_info *info)
6969 {
6970     uint64 rt_value = extract_rt_25_24_23_22_21(instruction);
6971     uint64 rs_value = extract_rs_20_19_18_17_16(instruction);
6972     uint64 msbd_value = extract_msbt_10_9_8_7_6(instruction);
6973     uint64 lsb_value = extract_lsb_4_3_2_1_0(instruction);
6974 
6975     const char *rt = GPR(rt_value, info);
6976     const char *rs = GPR(rs_value, info);
6977     uint64 msbd = encode_msbd_from_size(msbd_value);
6978 
6979     return img_format("EXT %s, %s, 0x%" PRIx64 ", 0x%" PRIx64,
6980                       rt, rs, lsb_value, msbd);
6981 }
6982 
6983 
6984 /*
6985  *
6986  *
6987  *   3         2         1
6988  *  10987654321098765432109876543210
6989  *  001000               x1110000101
6990  *     rt -----
6991  *          rs -----
6992  *               rd -----
6993  */
6994 static char *EXTD(uint64 instruction, Dis_info *info)
6995 {
6996     uint64 rt_value = extract_rt_25_24_23_22_21(instruction);
6997     uint64 rs_value = extract_rs_20_19_18_17_16(instruction);
6998     uint64 rd_value = extract_rd_15_14_13_12_11(instruction);
6999     uint64 shift_value = extract_shift_10_9_8_7_6(instruction);
7000 
7001     const char *rd = GPR(rd_value, info);
7002     const char *rs = GPR(rs_value, info);
7003     const char *rt = GPR(rt_value, info);
7004 
7005     return img_format("EXTD %s, %s, %s, 0x%" PRIx64, rd, rs, rt, shift_value);
7006 }
7007 
7008 
7009 /*
7010  *
7011  *
7012  *   3         2         1
7013  *  10987654321098765432109876543210
7014  *  001000               x1110000101
7015  *     rt -----
7016  *          rs -----
7017  *               rd -----
7018  */
7019 static char *EXTD32(uint64 instruction, Dis_info *info)
7020 {
7021     uint64 rt_value = extract_rt_25_24_23_22_21(instruction);
7022     uint64 rs_value = extract_rs_20_19_18_17_16(instruction);
7023     uint64 rd_value = extract_rd_15_14_13_12_11(instruction);
7024     uint64 shift_value = extract_shift_10_9_8_7_6(instruction);
7025 
7026     const char *rd = GPR(rd_value, info);
7027     const char *rs = GPR(rs_value, info);
7028     const char *rt = GPR(rt_value, info);
7029 
7030     return img_format("EXTD32 %s, %s, %s, 0x%" PRIx64, rd, rs, rt, shift_value);
7031 }
7032 
7033 
7034 /*
7035  *
7036  *
7037  *   3         2         1
7038  *  10987654321098765432109876543210
7039  *  001000               x1110000101
7040  *     rt -----
7041  *          rs -----
7042  *               rd -----
7043  */
7044 static char *EXTPDP(uint64 instruction, Dis_info *info)
7045 {
7046     uint64 rt_value = extract_rt_25_24_23_22_21(instruction);
7047     uint64 size_value = extract_size_20_19_18_17_16(instruction);
7048     uint64 ac_value = extract_ac_15_14(instruction);
7049 
7050     const char *rt = GPR(rt_value, info);
7051     const char *ac = AC(ac_value, info);
7052 
7053     return img_format("EXTPDP %s, %s, 0x%" PRIx64, rt, ac, size_value);
7054 }
7055 
7056 
7057 /*
7058  *
7059  *
7060  *   3         2         1
7061  *  10987654321098765432109876543210
7062  *  001000               x1110000101
7063  *     rt -----
7064  *          rs -----
7065  *               rd -----
7066  */
7067 static char *EXTPDPV(uint64 instruction, Dis_info *info)
7068 {
7069     uint64 rt_value = extract_rt_25_24_23_22_21(instruction);
7070     uint64 rs_value = extract_rs_20_19_18_17_16(instruction);
7071     uint64 ac_value = extract_ac_15_14(instruction);
7072 
7073     const char *rt = GPR(rt_value, info);
7074     const char *ac = AC(ac_value, info);
7075     const char *rs = GPR(rs_value, info);
7076 
7077     return img_format("EXTPDPV %s, %s, %s", rt, ac, rs);
7078 }
7079 
7080 
7081 /*
7082  *
7083  *
7084  *   3         2         1
7085  *  10987654321098765432109876543210
7086  *  001000               x1110000101
7087  *     rt -----
7088  *          rs -----
7089  *               rd -----
7090  */
7091 static char *EXTP(uint64 instruction, Dis_info *info)
7092 {
7093     uint64 rt_value = extract_rt_25_24_23_22_21(instruction);
7094     uint64 size_value = extract_size_20_19_18_17_16(instruction);
7095     uint64 ac_value = extract_ac_15_14(instruction);
7096 
7097     const char *rt = GPR(rt_value, info);
7098     const char *ac = AC(ac_value, info);
7099 
7100     return img_format("EXTP %s, %s, 0x%" PRIx64, rt, ac, size_value);
7101 }
7102 
7103 
7104 /*
7105  *
7106  *
7107  *   3         2         1
7108  *  10987654321098765432109876543210
7109  *  001000               x1110000101
7110  *     rt -----
7111  *          rs -----
7112  *               rd -----
7113  */
7114 static char *EXTPV(uint64 instruction, Dis_info *info)
7115 {
7116     uint64 rt_value = extract_rt_25_24_23_22_21(instruction);
7117     uint64 rs_value = extract_rs_20_19_18_17_16(instruction);
7118     uint64 ac_value = extract_ac_15_14(instruction);
7119 
7120     const char *rt = GPR(rt_value, info);
7121     const char *ac = AC(ac_value, info);
7122     const char *rs = GPR(rs_value, info);
7123 
7124     return img_format("EXTPV %s, %s, %s", rt, ac, rs);
7125 }
7126 
7127 
7128 /*
7129  * [DSP] EXTR_RS.W rt, ac, shift - Extract word value from accumulator to GPR
7130  *   with right shift
7131  *
7132  *   3         2         1
7133  *  10987654321098765432109876543210
7134  *  001000            10111001111111
7135  *     rt -----
7136  *       shift -----
7137  *               ac --
7138  */
7139 static char *EXTR_RS_W(uint64 instruction, Dis_info *info)
7140 {
7141     uint64 rt_value = extract_rt_25_24_23_22_21(instruction);
7142     uint64 shift_value = extract_shift_20_19_18_17_16(instruction);
7143     uint64 ac_value = extract_ac_15_14(instruction);
7144 
7145     const char *rt = GPR(rt_value, info);
7146     const char *ac = AC(ac_value, info);
7147 
7148     return img_format("EXTR_RS.W %s, %s, 0x%" PRIx64, rt, ac, shift_value);
7149 }
7150 
7151 
7152 /*
7153  * [DSP] EXTR_R.W rt, ac, shift - Extract word value from accumulator to GPR
7154  *   with right shift
7155  *
7156  *   3         2         1
7157  *  10987654321098765432109876543210
7158  *  001000            01111001111111
7159  *     rt -----
7160  *       shift -----
7161  *               ac --
7162  */
7163 static char *EXTR_R_W(uint64 instruction, Dis_info *info)
7164 {
7165     uint64 rt_value = extract_rt_25_24_23_22_21(instruction);
7166     uint64 shift_value = extract_shift_20_19_18_17_16(instruction);
7167     uint64 ac_value = extract_ac_15_14(instruction);
7168 
7169     const char *rt = GPR(rt_value, info);
7170     const char *ac = AC(ac_value, info);
7171 
7172     return img_format("EXTR_R.W %s, %s, 0x%" PRIx64, rt, ac, shift_value);
7173 }
7174 
7175 
7176 /*
7177  * [DSP] EXTR_S.H rt, ac, shift - Extract halfword value from accumulator
7178  *   to GPR with right shift and saturate
7179  *
7180  *   3         2         1
7181  *  10987654321098765432109876543210
7182  *  001000            11111001111111
7183  *     rt -----
7184  *       shift -----
7185  *               ac --
7186  */
7187 static char *EXTR_S_H(uint64 instruction, Dis_info *info)
7188 {
7189     uint64 rt_value = extract_rt_25_24_23_22_21(instruction);
7190     uint64 shift_value = extract_shift_20_19_18_17_16(instruction);
7191     uint64 ac_value = extract_ac_15_14(instruction);
7192 
7193     const char *rt = GPR(rt_value, info);
7194     const char *ac = AC(ac_value, info);
7195 
7196     return img_format("EXTR_S.H %s, %s, 0x%" PRIx64, rt, ac, shift_value);
7197 }
7198 
7199 
7200 /*
7201  * [DSP] EXTR.W rt, ac, shift - Extract word value from accumulator to GPR
7202  *   with right shift
7203  *
7204  *   3         2         1
7205  *  10987654321098765432109876543210
7206  *  001000            00111001111111
7207  *     rt -----
7208  *       shift -----
7209  *               ac --
7210  */
7211 static char *EXTR_W(uint64 instruction, Dis_info *info)
7212 {
7213     uint64 rt_value = extract_rt_25_24_23_22_21(instruction);
7214     uint64 shift_value = extract_shift_20_19_18_17_16(instruction);
7215     uint64 ac_value = extract_ac_15_14(instruction);
7216 
7217     const char *rt = GPR(rt_value, info);
7218     const char *ac = AC(ac_value, info);
7219 
7220     return img_format("EXTR.W %s, %s, 0x%" PRIx64, rt, ac, shift_value);
7221 }
7222 
7223 
7224 /*
7225  * [DSP] EXTRV_RS.W rt, ac, rs - Extract word value with variable
7226  *   right shift from accumulator to GPR
7227  *
7228  *   3         2         1
7229  *  10987654321098765432109876543210
7230  *  001000            10111010111111
7231  *     rt -----
7232  *          rs -----
7233  *               ac --
7234  */
7235 static char *EXTRV_RS_W(uint64 instruction, Dis_info *info)
7236 {
7237     uint64 rt_value = extract_rt_25_24_23_22_21(instruction);
7238     uint64 rs_value = extract_rs_20_19_18_17_16(instruction);
7239     uint64 ac_value = extract_ac_15_14(instruction);
7240 
7241     const char *rt = GPR(rt_value, info);
7242     const char *ac = AC(ac_value, info);
7243     const char *rs = GPR(rs_value, info);
7244 
7245     return img_format("EXTRV_RS.W %s, %s, %s", rt, ac, rs);
7246 }
7247 
7248 
7249 /*
7250  * [DSP] EXTRV_R.W rt, ac, rs - Extract word value with variable
7251  *   right shift from accumulator to GPR
7252  *
7253  *   3         2         1
7254  *  10987654321098765432109876543210
7255  *  001000            01111010111111
7256  *     rt -----
7257  *          rs -----
7258  *               ac --
7259  */
7260 static char *EXTRV_R_W(uint64 instruction, Dis_info *info)
7261 {
7262     uint64 rt_value = extract_rt_25_24_23_22_21(instruction);
7263     uint64 rs_value = extract_rs_20_19_18_17_16(instruction);
7264     uint64 ac_value = extract_ac_15_14(instruction);
7265 
7266     const char *rt = GPR(rt_value, info);
7267     const char *ac = AC(ac_value, info);
7268     const char *rs = GPR(rs_value, info);
7269 
7270     return img_format("EXTRV_R.W %s, %s, %s", rt, ac, rs);
7271 }
7272 
7273 
7274 /*
7275  * [DSP] EXTRV_S.H rt, ac, rs - Extract halfword value variable from
7276  *   accumulator to GPR with right shift and saturate
7277  *
7278  *   3         2         1
7279  *  10987654321098765432109876543210
7280  *  001000            11111010111111
7281  *     rt -----
7282  *          rs -----
7283  *               ac --
7284  */
7285 static char *EXTRV_S_H(uint64 instruction, Dis_info *info)
7286 {
7287     uint64 rt_value = extract_rt_25_24_23_22_21(instruction);
7288     uint64 rs_value = extract_rs_20_19_18_17_16(instruction);
7289     uint64 ac_value = extract_ac_15_14(instruction);
7290 
7291     const char *rt = GPR(rt_value, info);
7292     const char *ac = AC(ac_value, info);
7293     const char *rs = GPR(rs_value, info);
7294 
7295     return img_format("EXTRV_S.H %s, %s, %s", rt, ac, rs);
7296 }
7297 
7298 
7299 /*
7300  * [DSP] EXTRV.W rt, ac, rs - Extract word value with variable
7301  *   right shift from accumulator to GPR
7302  *
7303  *   3         2         1
7304  *  10987654321098765432109876543210
7305  *  001000            00111010111111
7306  *     rt -----
7307  *          rs -----
7308  *               ac --
7309  */
7310 static char *EXTRV_W(uint64 instruction, Dis_info *info)
7311 {
7312     uint64 rt_value = extract_rt_25_24_23_22_21(instruction);
7313     uint64 rs_value = extract_rs_20_19_18_17_16(instruction);
7314     uint64 ac_value = extract_ac_15_14(instruction);
7315 
7316     const char *rt = GPR(rt_value, info);
7317     const char *ac = AC(ac_value, info);
7318     const char *rs = GPR(rs_value, info);
7319 
7320     return img_format("EXTRV.W %s, %s, %s", rt, ac, rs);
7321 }
7322 
7323 
7324 /*
7325  * EXTW - Extract Word
7326  *
7327  *   3         2         1
7328  *  10987654321098765432109876543210
7329  *  001000                    011111
7330  *     rt -----
7331  *          rs -----
7332  *               rd -----
7333  *                 shift -----
7334  */
7335 static char *EXTW(uint64 instruction, Dis_info *info)
7336 {
7337     uint64 rt_value = extract_rt_25_24_23_22_21(instruction);
7338     uint64 rs_value = extract_rs_20_19_18_17_16(instruction);
7339     uint64 rd_value = extract_rd_15_14_13_12_11(instruction);
7340     uint64 shift_value = extract_shift_10_9_8_7_6(instruction);
7341 
7342     const char *rd = GPR(rd_value, info);
7343     const char *rs = GPR(rs_value, info);
7344     const char *rt = GPR(rt_value, info);
7345 
7346     return img_format("EXTW %s, %s, %s, 0x%" PRIx64, rd, rs, rt, shift_value);
7347 }
7348 
7349 
7350 /*
7351  *
7352  *
7353  *   3         2         1
7354  *  10987654321098765432109876543210
7355  *  001000               x1110000101
7356  *     rt -----
7357  *          rs -----
7358  *               rd -----
7359  */
7360 static char *FLOOR_L_D(uint64 instruction, Dis_info *info)
7361 {
7362     uint64 ft_value = extract_ft_25_24_23_22_21(instruction);
7363     uint64 fs_value = extract_fs_20_19_18_17_16(instruction);
7364 
7365     const char *ft = FPR(ft_value, info);
7366     const char *fs = FPR(fs_value, info);
7367 
7368     return img_format("FLOOR.L.D %s, %s", ft, fs);
7369 }
7370 
7371 
7372 /*
7373  *
7374  *
7375  *   3         2         1
7376  *  10987654321098765432109876543210
7377  *  001000               x1110000101
7378  *     rt -----
7379  *          rs -----
7380  *               rd -----
7381  */
7382 static char *FLOOR_L_S(uint64 instruction, Dis_info *info)
7383 {
7384     uint64 ft_value = extract_ft_25_24_23_22_21(instruction);
7385     uint64 fs_value = extract_fs_20_19_18_17_16(instruction);
7386 
7387     const char *ft = FPR(ft_value, info);
7388     const char *fs = FPR(fs_value, info);
7389 
7390     return img_format("FLOOR.L.S %s, %s", ft, fs);
7391 }
7392 
7393 
7394 /*
7395  *
7396  *
7397  *   3         2         1
7398  *  10987654321098765432109876543210
7399  *  001000               x1110000101
7400  *     rt -----
7401  *          rs -----
7402  *               rd -----
7403  */
7404 static char *FLOOR_W_D(uint64 instruction, Dis_info *info)
7405 {
7406     uint64 ft_value = extract_ft_25_24_23_22_21(instruction);
7407     uint64 fs_value = extract_fs_20_19_18_17_16(instruction);
7408 
7409     const char *ft = FPR(ft_value, info);
7410     const char *fs = FPR(fs_value, info);
7411 
7412     return img_format("FLOOR.W.D %s, %s", ft, fs);
7413 }
7414 
7415 
7416 /*
7417  *
7418  *
7419  *   3         2         1
7420  *  10987654321098765432109876543210
7421  *  001000               x1110000101
7422  *     rt -----
7423  *          rs -----
7424  *               rd -----
7425  */
7426 static char *FLOOR_W_S(uint64 instruction, Dis_info *info)
7427 {
7428     uint64 ft_value = extract_ft_25_24_23_22_21(instruction);
7429     uint64 fs_value = extract_fs_20_19_18_17_16(instruction);
7430 
7431     const char *ft = FPR(ft_value, info);
7432     const char *fs = FPR(fs_value, info);
7433 
7434     return img_format("FLOOR.W.S %s, %s", ft, fs);
7435 }
7436 
7437 
7438 /*
7439  *
7440  *
7441  *   3         2         1
7442  *  10987654321098765432109876543210
7443  *  001000               x1110000101
7444  *     rt -----
7445  *          rs -----
7446  *               rd -----
7447  */
7448 static char *FORK(uint64 instruction, Dis_info *info)
7449 {
7450     uint64 rt_value = extract_rt_25_24_23_22_21(instruction);
7451     uint64 rs_value = extract_rs_20_19_18_17_16(instruction);
7452     uint64 rd_value = extract_rd_15_14_13_12_11(instruction);
7453 
7454     const char *rd = GPR(rd_value, info);
7455     const char *rs = GPR(rs_value, info);
7456     const char *rt = GPR(rt_value, info);
7457 
7458     return img_format("FORK %s, %s, %s", rd, rs, rt);
7459 }
7460 
7461 
7462 /*
7463  *
7464  *
7465  *   3         2         1
7466  *  10987654321098765432109876543210
7467  *  001000               x1110000101
7468  *     rt -----
7469  *          rs -----
7470  *               rd -----
7471  */
7472 static char *HYPCALL(uint64 instruction, Dis_info *info)
7473 {
7474     uint64 code_value = extract_code_17_to_0(instruction);
7475 
7476 
7477     return img_format("HYPCALL 0x%" PRIx64, code_value);
7478 }
7479 
7480 
7481 /*
7482  *
7483  *
7484  *   3         2         1
7485  *  10987654321098765432109876543210
7486  *  001000               x1110000101
7487  *     rt -----
7488  *          rs -----
7489  *               rd -----
7490  */
7491 static char *HYPCALL_16_(uint64 instruction, Dis_info *info)
7492 {
7493     uint64 code_value = extract_code_1_0(instruction);
7494 
7495 
7496     return img_format("HYPCALL 0x%" PRIx64, code_value);
7497 }
7498 
7499 
7500 /*
7501  *
7502  *
7503  *   3         2         1
7504  *  10987654321098765432109876543210
7505  *  001000               x1110000101
7506  *     rt -----
7507  *          rs -----
7508  *               rd -----
7509  */
7510 static char *INS(uint64 instruction, Dis_info *info)
7511 {
7512     uint64 rt_value = extract_rt_25_24_23_22_21(instruction);
7513     uint64 rs_value = extract_rs_20_19_18_17_16(instruction);
7514     uint64 msbd_value = extract_msbt_10_9_8_7_6(instruction);
7515     uint64 lsb_value = extract_lsb_4_3_2_1_0(instruction);
7516 
7517     const char *rt = GPR(rt_value, info);
7518     const char *rs = GPR(rs_value, info);
7519     /* !!!!!!!!!! - no conversion function */
7520 
7521     return img_format("INS %s, %s, 0x%" PRIx64 ", 0x%" PRIx64,
7522                       rt, rs, lsb_value, msbd_value);
7523     /* hand edited */
7524 }
7525 
7526 
7527 /*
7528  * [DSP] INSV rt, rs - Insert bit field variable
7529  *
7530  *   3         2         1
7531  *  10987654321098765432109876543210
7532  *  001000          0100000100111111
7533  *     rt -----
7534  *          rs -----
7535  */
7536 static char *INSV(uint64 instruction, Dis_info *info)
7537 {
7538     uint64 rt_value = extract_rt_25_24_23_22_21(instruction);
7539     uint64 rs_value = extract_rs_20_19_18_17_16(instruction);
7540 
7541     const char *rt = GPR(rt_value, info);
7542     const char *rs = GPR(rs_value, info);
7543 
7544     return img_format("INSV %s, %s", rt, rs);
7545 }
7546 
7547 
7548 /*
7549  *
7550  *
7551  *   3         2         1
7552  *  10987654321098765432109876543210
7553  *  001000               x1110000101
7554  *     rt -----
7555  *          rs -----
7556  *               rd -----
7557  */
7558 static char *IRET(uint64 instruction, Dis_info *info)
7559 {
7560     (void)instruction;
7561 
7562     return g_strdup("IRET ");
7563 }
7564 
7565 
7566 /*
7567  *
7568  *
7569  *   3         2         1
7570  *  10987654321098765432109876543210
7571  *  001000               x1110000101
7572  *     rt -----
7573  *          rs -----
7574  *               rd -----
7575  */
7576 static char *JALRC_16_(uint64 instruction, Dis_info *info)
7577 {
7578     uint64 rt_value = extract_rt_9_8_7_6_5(instruction);
7579 
7580     const char *rt = GPR(rt_value, info);
7581 
7582     return img_format("JALRC $%d, %s", 31, rt);
7583 }
7584 
7585 
7586 /*
7587  *
7588  *
7589  *   3         2         1
7590  *  10987654321098765432109876543210
7591  *  001000               x1110000101
7592  *     rt -----
7593  *          rs -----
7594  *               rd -----
7595  */
7596 static char *JALRC_32_(uint64 instruction, Dis_info *info)
7597 {
7598     uint64 rt_value = extract_rt_25_24_23_22_21(instruction);
7599     uint64 rs_value = extract_rs_20_19_18_17_16(instruction);
7600 
7601     const char *rt = GPR(rt_value, info);
7602     const char *rs = GPR(rs_value, info);
7603 
7604     return img_format("JALRC %s, %s", rt, rs);
7605 }
7606 
7607 
7608 /*
7609  *
7610  *
7611  *   3         2         1
7612  *  10987654321098765432109876543210
7613  *  001000               x1110000101
7614  *     rt -----
7615  *          rs -----
7616  *               rd -----
7617  */
7618 static char *JALRC_HB(uint64 instruction, Dis_info *info)
7619 {
7620     uint64 rt_value = extract_rt_25_24_23_22_21(instruction);
7621     uint64 rs_value = extract_rs_20_19_18_17_16(instruction);
7622 
7623     const char *rt = GPR(rt_value, info);
7624     const char *rs = GPR(rs_value, info);
7625 
7626     return img_format("JALRC.HB %s, %s", rt, rs);
7627 }
7628 
7629 
7630 /*
7631  *
7632  *
7633  *   3         2         1
7634  *  10987654321098765432109876543210
7635  *  001000               x1110000101
7636  *     rt -----
7637  *          rs -----
7638  *               rd -----
7639  */
7640 static char *JRC(uint64 instruction, Dis_info *info)
7641 {
7642     uint64 rt_value = extract_rt_9_8_7_6_5(instruction);
7643 
7644     const char *rt = GPR(rt_value, info);
7645 
7646     return img_format("JRC %s", rt);
7647 }
7648 
7649 
7650 /*
7651  *
7652  *
7653  *   3         2         1
7654  *  10987654321098765432109876543210
7655  *  001000               x1110000101
7656  *     rt -----
7657  *          rs -----
7658  *               rd -----
7659  */
7660 static char *LB_16_(uint64 instruction, Dis_info *info)
7661 {
7662     uint64 rt3_value = extract_rt3_9_8_7(instruction);
7663     uint64 rs3_value = extract_rs3_6_5_4(instruction);
7664     uint64 u_value = extract_u_1_0(instruction);
7665 
7666     const char *rt3 = GPR(decode_gpr_gpr3(rt3_value, info), info);
7667     const char *rs3 = GPR(decode_gpr_gpr3(rs3_value, info), info);
7668 
7669     return img_format("LB %s, 0x%" PRIx64 "(%s)", rt3, u_value, rs3);
7670 }
7671 
7672 
7673 /*
7674  *
7675  *
7676  *   3         2         1
7677  *  10987654321098765432109876543210
7678  *  001000               x1110000101
7679  *     rt -----
7680  *          rs -----
7681  *               rd -----
7682  */
7683 static char *LB_GP_(uint64 instruction, Dis_info *info)
7684 {
7685     uint64 rt_value = extract_rt_25_24_23_22_21(instruction);
7686     uint64 u_value = extract_u_17_to_0(instruction);
7687 
7688     const char *rt = GPR(rt_value, info);
7689 
7690     return img_format("LB %s, 0x%" PRIx64 "($%d)", rt, u_value, 28);
7691 }
7692 
7693 
7694 /*
7695  *
7696  *
7697  *   3         2         1
7698  *  10987654321098765432109876543210
7699  *  001000               x1110000101
7700  *     rt -----
7701  *          rs -----
7702  *               rd -----
7703  */
7704 static char *LB_S9_(uint64 instruction, Dis_info *info)
7705 {
7706     uint64 rt_value = extract_rt_25_24_23_22_21(instruction);
7707     uint64 rs_value = extract_rs_20_19_18_17_16(instruction);
7708     int64 s_value = extract_s__se8_15_7_6_5_4_3_2_1_0(instruction);
7709 
7710     const char *rt = GPR(rt_value, info);
7711     const char *rs = GPR(rs_value, info);
7712 
7713     return img_format("LB %s, %" PRId64 "(%s)", rt, s_value, rs);
7714 }
7715 
7716 
7717 /*
7718  *
7719  *
7720  *   3         2         1
7721  *  10987654321098765432109876543210
7722  *  001000               x1110000101
7723  *     rt -----
7724  *          rs -----
7725  *               rd -----
7726  */
7727 static char *LB_U12_(uint64 instruction, Dis_info *info)
7728 {
7729     uint64 rt_value = extract_rt_25_24_23_22_21(instruction);
7730     uint64 rs_value = extract_rs_20_19_18_17_16(instruction);
7731     uint64 u_value = extract_u_11_10_9_8_7_6_5_4_3_2_1_0(instruction);
7732 
7733     const char *rt = GPR(rt_value, info);
7734     const char *rs = GPR(rs_value, info);
7735 
7736     return img_format("LB %s, 0x%" PRIx64 "(%s)", rt, u_value, rs);
7737 }
7738 
7739 
7740 /*
7741  *
7742  *
7743  *   3         2         1
7744  *  10987654321098765432109876543210
7745  *  001000               x1110000101
7746  *     rt -----
7747  *          rs -----
7748  *               rd -----
7749  */
7750 static char *LBE(uint64 instruction, Dis_info *info)
7751 {
7752     uint64 rt_value = extract_rt_25_24_23_22_21(instruction);
7753     uint64 rs_value = extract_rs_20_19_18_17_16(instruction);
7754     int64 s_value = extract_s__se8_15_7_6_5_4_3_2_1_0(instruction);
7755 
7756     const char *rt = GPR(rt_value, info);
7757     const char *rs = GPR(rs_value, info);
7758 
7759     return img_format("LBE %s, %" PRId64 "(%s)", rt, s_value, rs);
7760 }
7761 
7762 
7763 /*
7764  *
7765  *
7766  *   3         2         1
7767  *  10987654321098765432109876543210
7768  *  001000               x1110000101
7769  *     rt -----
7770  *          rs -----
7771  *               rd -----
7772  */
7773 static char *LBU_16_(uint64 instruction, Dis_info *info)
7774 {
7775     uint64 rt3_value = extract_rt3_9_8_7(instruction);
7776     uint64 rs3_value = extract_rs3_6_5_4(instruction);
7777     uint64 u_value = extract_u_1_0(instruction);
7778 
7779     const char *rt3 = GPR(decode_gpr_gpr3(rt3_value, info), info);
7780     const char *rs3 = GPR(decode_gpr_gpr3(rs3_value, info), info);
7781 
7782     return img_format("LBU %s, 0x%" PRIx64 "(%s)", rt3, u_value, rs3);
7783 }
7784 
7785 
7786 /*
7787  *
7788  *
7789  *   3         2         1
7790  *  10987654321098765432109876543210
7791  *  001000               x1110000101
7792  *     rt -----
7793  *          rs -----
7794  *               rd -----
7795  */
7796 static char *LBU_GP_(uint64 instruction, Dis_info *info)
7797 {
7798     uint64 rt_value = extract_rt_25_24_23_22_21(instruction);
7799     uint64 u_value = extract_u_17_to_0(instruction);
7800 
7801     const char *rt = GPR(rt_value, info);
7802 
7803     return img_format("LBU %s, 0x%" PRIx64 "($%d)", rt, u_value, 28);
7804 }
7805 
7806 
7807 /*
7808  *
7809  *
7810  *   3         2         1
7811  *  10987654321098765432109876543210
7812  *  001000               x1110000101
7813  *     rt -----
7814  *          rs -----
7815  *               rd -----
7816  */
7817 static char *LBU_S9_(uint64 instruction, Dis_info *info)
7818 {
7819     uint64 rt_value = extract_rt_25_24_23_22_21(instruction);
7820     uint64 rs_value = extract_rs_20_19_18_17_16(instruction);
7821     int64 s_value = extract_s__se8_15_7_6_5_4_3_2_1_0(instruction);
7822 
7823     const char *rt = GPR(rt_value, info);
7824     const char *rs = GPR(rs_value, info);
7825 
7826     return img_format("LBU %s, %" PRId64 "(%s)", rt, s_value, rs);
7827 }
7828 
7829 
7830 /*
7831  *
7832  *
7833  *   3         2         1
7834  *  10987654321098765432109876543210
7835  *  001000               x1110000101
7836  *     rt -----
7837  *          rs -----
7838  *               rd -----
7839  */
7840 static char *LBU_U12_(uint64 instruction, Dis_info *info)
7841 {
7842     uint64 rt_value = extract_rt_25_24_23_22_21(instruction);
7843     uint64 rs_value = extract_rs_20_19_18_17_16(instruction);
7844     uint64 u_value = extract_u_11_10_9_8_7_6_5_4_3_2_1_0(instruction);
7845 
7846     const char *rt = GPR(rt_value, info);
7847     const char *rs = GPR(rs_value, info);
7848 
7849     return img_format("LBU %s, 0x%" PRIx64 "(%s)", rt, u_value, rs);
7850 }
7851 
7852 
7853 /*
7854  *
7855  *
7856  *   3         2         1
7857  *  10987654321098765432109876543210
7858  *  001000               x1110000101
7859  *     rt -----
7860  *          rs -----
7861  *               rd -----
7862  */
7863 static char *LBUE(uint64 instruction, Dis_info *info)
7864 {
7865     uint64 rt_value = extract_rt_25_24_23_22_21(instruction);
7866     uint64 rs_value = extract_rs_20_19_18_17_16(instruction);
7867     int64 s_value = extract_s__se8_15_7_6_5_4_3_2_1_0(instruction);
7868 
7869     const char *rt = GPR(rt_value, info);
7870     const char *rs = GPR(rs_value, info);
7871 
7872     return img_format("LBUE %s, %" PRId64 "(%s)", rt, s_value, rs);
7873 }
7874 
7875 
7876 /*
7877  *
7878  *
7879  *   3         2         1
7880  *  10987654321098765432109876543210
7881  *  001000               x1110000101
7882  *     rt -----
7883  *          rs -----
7884  *               rd -----
7885  */
7886 static char *LBUX(uint64 instruction, Dis_info *info)
7887 {
7888     uint64 rt_value = extract_rt_25_24_23_22_21(instruction);
7889     uint64 rs_value = extract_rs_20_19_18_17_16(instruction);
7890     uint64 rd_value = extract_rd_15_14_13_12_11(instruction);
7891 
7892     const char *rd = GPR(rd_value, info);
7893     const char *rs = GPR(rs_value, info);
7894     const char *rt = GPR(rt_value, info);
7895 
7896     return img_format("LBUX %s, %s(%s)", rd, rs, rt);
7897 }
7898 
7899 
7900 /*
7901  *
7902  *
7903  *   3         2         1
7904  *  10987654321098765432109876543210
7905  *  001000               x1110000101
7906  *     rt -----
7907  *          rs -----
7908  *               rd -----
7909  */
7910 static char *LBX(uint64 instruction, Dis_info *info)
7911 {
7912     uint64 rt_value = extract_rt_25_24_23_22_21(instruction);
7913     uint64 rs_value = extract_rs_20_19_18_17_16(instruction);
7914     uint64 rd_value = extract_rd_15_14_13_12_11(instruction);
7915 
7916     const char *rd = GPR(rd_value, info);
7917     const char *rs = GPR(rs_value, info);
7918     const char *rt = GPR(rt_value, info);
7919 
7920     return img_format("LBX %s, %s(%s)", rd, rs, rt);
7921 }
7922 
7923 
7924 /*
7925  *
7926  *
7927  *   3         2         1
7928  *  10987654321098765432109876543210
7929  *  001000               x1110000101
7930  *     rt -----
7931  *          rs -----
7932  *               rd -----
7933  */
7934 static char *LD_GP_(uint64 instruction, Dis_info *info)
7935 {
7936     uint64 rt_value = extract_rt_25_24_23_22_21(instruction);
7937     uint64 u_value = extract_u_20_to_3__s3(instruction);
7938 
7939     const char *rt = GPR(rt_value, info);
7940 
7941     return img_format("LD %s, 0x%" PRIx64 "($%d)", rt, u_value, 28);
7942 }
7943 
7944 
7945 /*
7946  *
7947  *
7948  *   3         2         1
7949  *  10987654321098765432109876543210
7950  *  001000               x1110000101
7951  *     rt -----
7952  *          rs -----
7953  *               rd -----
7954  */
7955 static char *LD_S9_(uint64 instruction, Dis_info *info)
7956 {
7957     uint64 rt_value = extract_rt_25_24_23_22_21(instruction);
7958     uint64 rs_value = extract_rs_20_19_18_17_16(instruction);
7959     int64 s_value = extract_s__se8_15_7_6_5_4_3_2_1_0(instruction);
7960 
7961     const char *rt = GPR(rt_value, info);
7962     const char *rs = GPR(rs_value, info);
7963 
7964     return img_format("LD %s, %" PRId64 "(%s)", rt, s_value, rs);
7965 }
7966 
7967 
7968 /*
7969  *
7970  *
7971  *   3         2         1
7972  *  10987654321098765432109876543210
7973  *  001000               x1110000101
7974  *     rt -----
7975  *          rs -----
7976  *               rd -----
7977  */
7978 static char *LD_U12_(uint64 instruction, Dis_info *info)
7979 {
7980     uint64 rt_value = extract_rt_25_24_23_22_21(instruction);
7981     uint64 rs_value = extract_rs_20_19_18_17_16(instruction);
7982     uint64 u_value = extract_u_11_10_9_8_7_6_5_4_3_2_1_0(instruction);
7983 
7984     const char *rt = GPR(rt_value, info);
7985     const char *rs = GPR(rs_value, info);
7986 
7987     return img_format("LD %s, 0x%" PRIx64 "(%s)", rt, u_value, rs);
7988 }
7989 
7990 
7991 /*
7992  *
7993  *
7994  *   3         2         1
7995  *  10987654321098765432109876543210
7996  *  001000               x1110000101
7997  *     rt -----
7998  *          rs -----
7999  *               rd -----
8000  */
8001 static char *LDC1_GP_(uint64 instruction, Dis_info *info)
8002 {
8003     uint64 ft_value = extract_ft_25_24_23_22_21(instruction);
8004     uint64 u_value = extract_u_17_to_2__s2(instruction);
8005 
8006     const char *ft = FPR(ft_value, info);
8007 
8008     return img_format("LDC1 %s, 0x%" PRIx64 "($%d)", ft, u_value, 28);
8009 }
8010 
8011 
8012 /*
8013  *
8014  *
8015  *   3         2         1
8016  *  10987654321098765432109876543210
8017  *  001000               x1110000101
8018  *     rt -----
8019  *          rs -----
8020  *               rd -----
8021  */
8022 static char *LDC1_S9_(uint64 instruction, Dis_info *info)
8023 {
8024     uint64 ft_value = extract_ft_25_24_23_22_21(instruction);
8025     uint64 rs_value = extract_rs_20_19_18_17_16(instruction);
8026     int64 s_value = extract_s__se8_15_7_6_5_4_3_2_1_0(instruction);
8027 
8028     const char *ft = FPR(ft_value, info);
8029     const char *rs = GPR(rs_value, info);
8030 
8031     return img_format("LDC1 %s, %" PRId64 "(%s)", ft, s_value, rs);
8032 }
8033 
8034 
8035 /*
8036  *
8037  *
8038  *   3         2         1
8039  *  10987654321098765432109876543210
8040  *  001000               x1110000101
8041  *     rt -----
8042  *          rs -----
8043  *               rd -----
8044  */
8045 static char *LDC1_U12_(uint64 instruction, Dis_info *info)
8046 {
8047     uint64 ft_value = extract_ft_25_24_23_22_21(instruction);
8048     uint64 rs_value = extract_rs_20_19_18_17_16(instruction);
8049     uint64 u_value = extract_u_11_10_9_8_7_6_5_4_3_2_1_0(instruction);
8050 
8051     const char *ft = FPR(ft_value, info);
8052     const char *rs = GPR(rs_value, info);
8053 
8054     return img_format("LDC1 %s, 0x%" PRIx64 "(%s)", ft, u_value, rs);
8055 }
8056 
8057 
8058 /*
8059  *
8060  *
8061  *   3         2         1
8062  *  10987654321098765432109876543210
8063  *  001000               x1110000101
8064  *     rt -----
8065  *          rs -----
8066  *               rd -----
8067  */
8068 static char *LDC1XS(uint64 instruction, Dis_info *info)
8069 {
8070     uint64 rt_value = extract_rt_25_24_23_22_21(instruction);
8071     uint64 rs_value = extract_rs_20_19_18_17_16(instruction);
8072     uint64 ft_value = extract_ft_15_14_13_12_11(instruction);
8073 
8074     const char *ft = FPR(ft_value, info);
8075     const char *rs = GPR(rs_value, info);
8076     const char *rt = GPR(rt_value, info);
8077 
8078     return img_format("LDC1XS %s, %s(%s)", ft, rs, rt);
8079 }
8080 
8081 
8082 /*
8083  *
8084  *
8085  *   3         2         1
8086  *  10987654321098765432109876543210
8087  *  001000               x1110000101
8088  *     rt -----
8089  *          rs -----
8090  *               rd -----
8091  */
8092 static char *LDC1X(uint64 instruction, Dis_info *info)
8093 {
8094     uint64 rt_value = extract_rt_25_24_23_22_21(instruction);
8095     uint64 rs_value = extract_rs_20_19_18_17_16(instruction);
8096     uint64 ft_value = extract_ft_15_14_13_12_11(instruction);
8097 
8098     const char *ft = FPR(ft_value, info);
8099     const char *rs = GPR(rs_value, info);
8100     const char *rt = GPR(rt_value, info);
8101 
8102     return img_format("LDC1X %s, %s(%s)", ft, rs, rt);
8103 }
8104 
8105 
8106 /*
8107  *
8108  *
8109  *   3         2         1
8110  *  10987654321098765432109876543210
8111  *  001000               x1110000101
8112  *     rt -----
8113  *          rs -----
8114  *               rd -----
8115  */
8116 static char *LDC2(uint64 instruction, Dis_info *info)
8117 {
8118     uint64 ct_value = extract_ct_25_24_23_22_21(instruction);
8119     uint64 rs_value = extract_rs_20_19_18_17_16(instruction);
8120     int64 s_value = extract_s__se8_15_7_6_5_4_3_2_1_0(instruction);
8121 
8122     const char *rs = GPR(rs_value, info);
8123 
8124     return img_format("LDC2 CP%" PRIu64 ", %" PRId64 "(%s)",
8125                       ct_value, s_value, rs);
8126 }
8127 
8128 
8129 /*
8130  *
8131  *
8132  *   3         2         1
8133  *  10987654321098765432109876543210
8134  *  001000               x1110000101
8135  *     rt -----
8136  *          rs -----
8137  *               rd -----
8138  */
8139 static char *LDM(uint64 instruction, Dis_info *info)
8140 {
8141     uint64 rt_value = extract_rt_25_24_23_22_21(instruction);
8142     uint64 rs_value = extract_rs_20_19_18_17_16(instruction);
8143     int64 s_value = extract_s__se8_15_7_6_5_4_3_2_1_0(instruction);
8144     uint64 count3_value = extract_count3_14_13_12(instruction);
8145 
8146     const char *rt = GPR(rt_value, info);
8147     const char *rs = GPR(rs_value, info);
8148     uint64 count3 = encode_count3_from_count(count3_value);
8149 
8150     return img_format("LDM %s, %" PRId64 "(%s), 0x%" PRIx64,
8151                       rt, s_value, rs, count3);
8152 }
8153 
8154 
8155 /*
8156  *
8157  *
8158  *   3         2         1
8159  *  10987654321098765432109876543210
8160  *  001000               x1110000101
8161  *     rt -----
8162  *          rs -----
8163  *               rd -----
8164  */
8165 static char *LDPC_48_(uint64 instruction, Dis_info *info)
8166 {
8167     uint64 rt_value = extract_rt_41_40_39_38_37(instruction);
8168     int64 s_value = extract_s__se31_15_to_0_31_to_16(instruction);
8169 
8170     const char *rt = GPR(rt_value, info);
8171     g_autofree char *s = ADDRESS(s_value, 6, info);
8172 
8173     return img_format("LDPC %s, %s", rt, s);
8174 }
8175 
8176 
8177 /*
8178  *
8179  *
8180  *   3         2         1
8181  *  10987654321098765432109876543210
8182  *  001000               x1110000101
8183  *     rt -----
8184  *          rs -----
8185  *               rd -----
8186  */
8187 static char *LDX(uint64 instruction, Dis_info *info)
8188 {
8189     uint64 rt_value = extract_rt_25_24_23_22_21(instruction);
8190     uint64 rs_value = extract_rs_20_19_18_17_16(instruction);
8191     uint64 rd_value = extract_rd_15_14_13_12_11(instruction);
8192 
8193     const char *rd = GPR(rd_value, info);
8194     const char *rs = GPR(rs_value, info);
8195     const char *rt = GPR(rt_value, info);
8196 
8197     return img_format("LDX %s, %s(%s)", rd, rs, rt);
8198 }
8199 
8200 
8201 /*
8202  *
8203  *
8204  *   3         2         1
8205  *  10987654321098765432109876543210
8206  *  001000               x1110000101
8207  *     rt -----
8208  *          rs -----
8209  *               rd -----
8210  */
8211 static char *LDXS(uint64 instruction, Dis_info *info)
8212 {
8213     uint64 rt_value = extract_rt_25_24_23_22_21(instruction);
8214     uint64 rs_value = extract_rs_20_19_18_17_16(instruction);
8215     uint64 rd_value = extract_rd_15_14_13_12_11(instruction);
8216 
8217     const char *rd = GPR(rd_value, info);
8218     const char *rs = GPR(rs_value, info);
8219     const char *rt = GPR(rt_value, info);
8220 
8221     return img_format("LDXS %s, %s(%s)", rd, rs, rt);
8222 }
8223 
8224 
8225 /*
8226  *
8227  *
8228  *   3         2         1
8229  *  10987654321098765432109876543210
8230  *  001000               x1110000101
8231  *     rt -----
8232  *          rs -----
8233  *               rd -----
8234  */
8235 static char *LH_16_(uint64 instruction, Dis_info *info)
8236 {
8237     uint64 rt3_value = extract_rt3_9_8_7(instruction);
8238     uint64 rs3_value = extract_rs3_6_5_4(instruction);
8239     uint64 u_value = extract_u_2_1__s1(instruction);
8240 
8241     const char *rt3 = GPR(decode_gpr_gpr3(rt3_value, info), info);
8242     const char *rs3 = GPR(decode_gpr_gpr3(rs3_value, info), info);
8243 
8244     return img_format("LH %s, 0x%" PRIx64 "(%s)", rt3, u_value, rs3);
8245 }
8246 
8247 
8248 /*
8249  *
8250  *
8251  *   3         2         1
8252  *  10987654321098765432109876543210
8253  *  001000               x1110000101
8254  *     rt -----
8255  *          rs -----
8256  *               rd -----
8257  */
8258 static char *LH_GP_(uint64 instruction, Dis_info *info)
8259 {
8260     uint64 rt_value = extract_rt_25_24_23_22_21(instruction);
8261     uint64 u_value = extract_u_17_to_1__s1(instruction);
8262 
8263     const char *rt = GPR(rt_value, info);
8264 
8265     return img_format("LH %s, 0x%" PRIx64 "($%d)", rt, u_value, 28);
8266 }
8267 
8268 
8269 /*
8270  *
8271  *
8272  *   3         2         1
8273  *  10987654321098765432109876543210
8274  *  001000               x1110000101
8275  *     rt -----
8276  *          rs -----
8277  *               rd -----
8278  */
8279 static char *LH_S9_(uint64 instruction, Dis_info *info)
8280 {
8281     uint64 rt_value = extract_rt_25_24_23_22_21(instruction);
8282     uint64 rs_value = extract_rs_20_19_18_17_16(instruction);
8283     int64 s_value = extract_s__se8_15_7_6_5_4_3_2_1_0(instruction);
8284 
8285     const char *rt = GPR(rt_value, info);
8286     const char *rs = GPR(rs_value, info);
8287 
8288     return img_format("LH %s, %" PRId64 "(%s)", rt, s_value, rs);
8289 }
8290 
8291 
8292 /*
8293  *
8294  *
8295  *   3         2         1
8296  *  10987654321098765432109876543210
8297  *  001000               x1110000101
8298  *     rt -----
8299  *          rs -----
8300  *               rd -----
8301  */
8302 static char *LH_U12_(uint64 instruction, Dis_info *info)
8303 {
8304     uint64 rt_value = extract_rt_25_24_23_22_21(instruction);
8305     uint64 rs_value = extract_rs_20_19_18_17_16(instruction);
8306     uint64 u_value = extract_u_11_10_9_8_7_6_5_4_3_2_1_0(instruction);
8307 
8308     const char *rt = GPR(rt_value, info);
8309     const char *rs = GPR(rs_value, info);
8310 
8311     return img_format("LH %s, 0x%" PRIx64 "(%s)", rt, u_value, rs);
8312 }
8313 
8314 
8315 /*
8316  *
8317  *
8318  *   3         2         1
8319  *  10987654321098765432109876543210
8320  *  001000               x1110000101
8321  *     rt -----
8322  *          rs -----
8323  *               rd -----
8324  */
8325 static char *LHE(uint64 instruction, Dis_info *info)
8326 {
8327     uint64 rt_value = extract_rt_25_24_23_22_21(instruction);
8328     uint64 rs_value = extract_rs_20_19_18_17_16(instruction);
8329     int64 s_value = extract_s__se8_15_7_6_5_4_3_2_1_0(instruction);
8330 
8331     const char *rt = GPR(rt_value, info);
8332     const char *rs = GPR(rs_value, info);
8333 
8334     return img_format("LHE %s, %" PRId64 "(%s)", rt, s_value, rs);
8335 }
8336 
8337 
8338 /*
8339  *
8340  *
8341  *   3         2         1
8342  *  10987654321098765432109876543210
8343  *  001000               x1110000101
8344  *     rt -----
8345  *          rs -----
8346  *               rd -----
8347  */
8348 static char *LHU_16_(uint64 instruction, Dis_info *info)
8349 {
8350     uint64 rt3_value = extract_rt3_9_8_7(instruction);
8351     uint64 rs3_value = extract_rs3_6_5_4(instruction);
8352     uint64 u_value = extract_u_2_1__s1(instruction);
8353 
8354     const char *rt3 = GPR(decode_gpr_gpr3(rt3_value, info), info);
8355     const char *rs3 = GPR(decode_gpr_gpr3(rs3_value, info), info);
8356 
8357     return img_format("LHU %s, 0x%" PRIx64 "(%s)", rt3, u_value, rs3);
8358 }
8359 
8360 
8361 /*
8362  *
8363  *
8364  *   3         2         1
8365  *  10987654321098765432109876543210
8366  *  001000               x1110000101
8367  *     rt -----
8368  *          rs -----
8369  *               rd -----
8370  */
8371 static char *LHU_GP_(uint64 instruction, Dis_info *info)
8372 {
8373     uint64 rt_value = extract_rt_25_24_23_22_21(instruction);
8374     uint64 u_value = extract_u_17_to_1__s1(instruction);
8375 
8376     const char *rt = GPR(rt_value, info);
8377 
8378     return img_format("LHU %s, 0x%" PRIx64 "($%d)", rt, u_value, 28);
8379 }
8380 
8381 
8382 /*
8383  *
8384  *
8385  *   3         2         1
8386  *  10987654321098765432109876543210
8387  *  001000               x1110000101
8388  *     rt -----
8389  *          rs -----
8390  *               rd -----
8391  */
8392 static char *LHU_S9_(uint64 instruction, Dis_info *info)
8393 {
8394     uint64 rt_value = extract_rt_25_24_23_22_21(instruction);
8395     uint64 rs_value = extract_rs_20_19_18_17_16(instruction);
8396     int64 s_value = extract_s__se8_15_7_6_5_4_3_2_1_0(instruction);
8397 
8398     const char *rt = GPR(rt_value, info);
8399     const char *rs = GPR(rs_value, info);
8400 
8401     return img_format("LHU %s, %" PRId64 "(%s)", rt, s_value, rs);
8402 }
8403 
8404 
8405 /*
8406  *
8407  *
8408  *   3         2         1
8409  *  10987654321098765432109876543210
8410  *  001000               x1110000101
8411  *     rt -----
8412  *          rs -----
8413  *               rd -----
8414  */
8415 static char *LHU_U12_(uint64 instruction, Dis_info *info)
8416 {
8417     uint64 rt_value = extract_rt_25_24_23_22_21(instruction);
8418     uint64 rs_value = extract_rs_20_19_18_17_16(instruction);
8419     uint64 u_value = extract_u_11_10_9_8_7_6_5_4_3_2_1_0(instruction);
8420 
8421     const char *rt = GPR(rt_value, info);
8422     const char *rs = GPR(rs_value, info);
8423 
8424     return img_format("LHU %s, 0x%" PRIx64 "(%s)", rt, u_value, rs);
8425 }
8426 
8427 
8428 /*
8429  *
8430  *
8431  *   3         2         1
8432  *  10987654321098765432109876543210
8433  *  001000               x1110000101
8434  *     rt -----
8435  *          rs -----
8436  *               rd -----
8437  */
8438 static char *LHUE(uint64 instruction, Dis_info *info)
8439 {
8440     uint64 rt_value = extract_rt_25_24_23_22_21(instruction);
8441     uint64 rs_value = extract_rs_20_19_18_17_16(instruction);
8442     int64 s_value = extract_s__se8_15_7_6_5_4_3_2_1_0(instruction);
8443 
8444     const char *rt = GPR(rt_value, info);
8445     const char *rs = GPR(rs_value, info);
8446 
8447     return img_format("LHUE %s, %" PRId64 "(%s)", rt, s_value, rs);
8448 }
8449 
8450 
8451 /*
8452  *
8453  *
8454  *   3         2         1
8455  *  10987654321098765432109876543210
8456  *  001000               x1110000101
8457  *     rt -----
8458  *          rs -----
8459  *               rd -----
8460  */
8461 static char *LHUX(uint64 instruction, Dis_info *info)
8462 {
8463     uint64 rt_value = extract_rt_25_24_23_22_21(instruction);
8464     uint64 rs_value = extract_rs_20_19_18_17_16(instruction);
8465     uint64 rd_value = extract_rd_15_14_13_12_11(instruction);
8466 
8467     const char *rd = GPR(rd_value, info);
8468     const char *rs = GPR(rs_value, info);
8469     const char *rt = GPR(rt_value, info);
8470 
8471     return img_format("LHUX %s, %s(%s)", rd, rs, rt);
8472 }
8473 
8474 
8475 /*
8476  *
8477  *
8478  *   3         2         1
8479  *  10987654321098765432109876543210
8480  *  001000               x1110000101
8481  *     rt -----
8482  *          rs -----
8483  *               rd -----
8484  */
8485 static char *LHUXS(uint64 instruction, Dis_info *info)
8486 {
8487     uint64 rt_value = extract_rt_25_24_23_22_21(instruction);
8488     uint64 rs_value = extract_rs_20_19_18_17_16(instruction);
8489     uint64 rd_value = extract_rd_15_14_13_12_11(instruction);
8490 
8491     const char *rd = GPR(rd_value, info);
8492     const char *rs = GPR(rs_value, info);
8493     const char *rt = GPR(rt_value, info);
8494 
8495     return img_format("LHUXS %s, %s(%s)", rd, rs, rt);
8496 }
8497 
8498 
8499 /*
8500  *
8501  *
8502  *   3         2         1
8503  *  10987654321098765432109876543210
8504  *  001000               x1110000101
8505  *     rt -----
8506  *          rs -----
8507  *               rd -----
8508  */
8509 static char *LHXS(uint64 instruction, Dis_info *info)
8510 {
8511     uint64 rt_value = extract_rt_25_24_23_22_21(instruction);
8512     uint64 rs_value = extract_rs_20_19_18_17_16(instruction);
8513     uint64 rd_value = extract_rd_15_14_13_12_11(instruction);
8514 
8515     const char *rd = GPR(rd_value, info);
8516     const char *rs = GPR(rs_value, info);
8517     const char *rt = GPR(rt_value, info);
8518 
8519     return img_format("LHXS %s, %s(%s)", rd, rs, rt);
8520 }
8521 
8522 
8523 /*
8524  *
8525  *
8526  *   3         2         1
8527  *  10987654321098765432109876543210
8528  *  001000               x1110000101
8529  *     rt -----
8530  *          rs -----
8531  *               rd -----
8532  */
8533 static char *LHX(uint64 instruction, Dis_info *info)
8534 {
8535     uint64 rt_value = extract_rt_25_24_23_22_21(instruction);
8536     uint64 rs_value = extract_rs_20_19_18_17_16(instruction);
8537     uint64 rd_value = extract_rd_15_14_13_12_11(instruction);
8538 
8539     const char *rd = GPR(rd_value, info);
8540     const char *rs = GPR(rs_value, info);
8541     const char *rt = GPR(rt_value, info);
8542 
8543     return img_format("LHX %s, %s(%s)", rd, rs, rt);
8544 }
8545 
8546 
8547 /*
8548  *
8549  *
8550  *   3         2         1
8551  *  10987654321098765432109876543210
8552  *  001000               x1110000101
8553  *     rt -----
8554  *          rs -----
8555  *               rd -----
8556  */
8557 static char *LI_16_(uint64 instruction, Dis_info *info)
8558 {
8559     uint64 rt3_value = extract_rt3_9_8_7(instruction);
8560     uint64 eu_value = extract_eu_6_5_4_3_2_1_0(instruction);
8561 
8562     const char *rt3 = GPR(decode_gpr_gpr3(rt3_value, info), info);
8563     int64 eu = encode_eu_from_s_li16(eu_value);
8564 
8565     return img_format("LI %s, %" PRId64, rt3, eu);
8566 }
8567 
8568 
8569 /*
8570  *
8571  *
8572  *   3         2         1
8573  *  10987654321098765432109876543210
8574  *  001000               x1110000101
8575  *     rt -----
8576  *          rs -----
8577  *               rd -----
8578  */
8579 static char *LI_48_(uint64 instruction, Dis_info *info)
8580 {
8581     uint64 rt_value = extract_rt_41_40_39_38_37(instruction);
8582     int64 s_value = extract_s__se31_15_to_0_31_to_16(instruction);
8583 
8584     const char *rt = GPR(rt_value, info);
8585 
8586     return img_format("LI %s, %" PRId64, rt, s_value);
8587 }
8588 
8589 
8590 /*
8591  *
8592  *
8593  *   3         2         1
8594  *  10987654321098765432109876543210
8595  *  001000               x1110000101
8596  *     rt -----
8597  *          rs -----
8598  *               rd -----
8599  */
8600 static char *LL(uint64 instruction, Dis_info *info)
8601 {
8602     uint64 rt_value = extract_rt_25_24_23_22_21(instruction);
8603     uint64 rs_value = extract_rs_20_19_18_17_16(instruction);
8604     int64 s_value = extract_s__se8_15_7_6_5_4_3_2_s2(instruction);
8605 
8606     const char *rt = GPR(rt_value, info);
8607     const char *rs = GPR(rs_value, info);
8608 
8609     return img_format("LL %s, %" PRId64 "(%s)", rt, s_value, rs);
8610 }
8611 
8612 
8613 /*
8614  *
8615  *
8616  *   3         2         1
8617  *  10987654321098765432109876543210
8618  *  001000               x1110000101
8619  *     rt -----
8620  *          rs -----
8621  *               rd -----
8622  */
8623 static char *LLD(uint64 instruction, Dis_info *info)
8624 {
8625     uint64 rt_value = extract_rt_25_24_23_22_21(instruction);
8626     uint64 rs_value = extract_rs_20_19_18_17_16(instruction);
8627     int64 s_value = extract_s__se8_15_7_6_5_4_3_s3(instruction);
8628 
8629     const char *rt = GPR(rt_value, info);
8630     const char *rs = GPR(rs_value, info);
8631 
8632     return img_format("LLD %s, %" PRId64 "(%s)", rt, s_value, rs);
8633 }
8634 
8635 
8636 /*
8637  *
8638  *
8639  *   3         2         1
8640  *  10987654321098765432109876543210
8641  *  001000               x1110000101
8642  *     rt -----
8643  *          rs -----
8644  *               rd -----
8645  */
8646 static char *LLDP(uint64 instruction, Dis_info *info)
8647 {
8648     uint64 rt_value = extract_rt_25_24_23_22_21(instruction);
8649     uint64 rs_value = extract_rs_20_19_18_17_16(instruction);
8650     uint64 ru_value = extract_ru_7_6_5_4_3(instruction);
8651 
8652     const char *rt = GPR(rt_value, info);
8653     const char *ru = GPR(ru_value, info);
8654     const char *rs = GPR(rs_value, info);
8655 
8656     return img_format("LLDP %s, %s, (%s)", rt, ru, rs);
8657 }
8658 
8659 
8660 /*
8661  *
8662  *
8663  *   3         2         1
8664  *  10987654321098765432109876543210
8665  *  001000               x1110000101
8666  *     rt -----
8667  *          rs -----
8668  *               rd -----
8669  */
8670 static char *LLE(uint64 instruction, Dis_info *info)
8671 {
8672     uint64 rt_value = extract_rt_25_24_23_22_21(instruction);
8673     uint64 rs_value = extract_rs_20_19_18_17_16(instruction);
8674     int64 s_value = extract_s__se8_15_7_6_5_4_3_2_s2(instruction);
8675 
8676     const char *rt = GPR(rt_value, info);
8677     const char *rs = GPR(rs_value, info);
8678 
8679     return img_format("LLE %s, %" PRId64 "(%s)", rt, s_value, rs);
8680 }
8681 
8682 
8683 /*
8684  *
8685  *
8686  *   3         2         1
8687  *  10987654321098765432109876543210
8688  *  001000               x1110000101
8689  *     rt -----
8690  *          rs -----
8691  *               rd -----
8692  */
8693 static char *LLWP(uint64 instruction, Dis_info *info)
8694 {
8695     uint64 rt_value = extract_rt_25_24_23_22_21(instruction);
8696     uint64 rs_value = extract_rs_20_19_18_17_16(instruction);
8697     uint64 ru_value = extract_ru_7_6_5_4_3(instruction);
8698 
8699     const char *rt = GPR(rt_value, info);
8700     const char *ru = GPR(ru_value, info);
8701     const char *rs = GPR(rs_value, info);
8702 
8703     return img_format("LLWP %s, %s, (%s)", rt, ru, rs);
8704 }
8705 
8706 
8707 /*
8708  *
8709  *
8710  *   3         2         1
8711  *  10987654321098765432109876543210
8712  *  001000               x1110000101
8713  *     rt -----
8714  *          rs -----
8715  *               rd -----
8716  */
8717 static char *LLWPE(uint64 instruction, Dis_info *info)
8718 {
8719     uint64 rt_value = extract_rt_25_24_23_22_21(instruction);
8720     uint64 rs_value = extract_rs_20_19_18_17_16(instruction);
8721     uint64 ru_value = extract_ru_7_6_5_4_3(instruction);
8722 
8723     const char *rt = GPR(rt_value, info);
8724     const char *ru = GPR(ru_value, info);
8725     const char *rs = GPR(rs_value, info);
8726 
8727     return img_format("LLWPE %s, %s, (%s)", rt, ru, rs);
8728 }
8729 
8730 
8731 /*
8732  *
8733  *
8734  *   3         2         1
8735  *  10987654321098765432109876543210
8736  *  001000               x1110000101
8737  *     rt -----
8738  *          rs -----
8739  *               rd -----
8740  */
8741 static char *LSA(uint64 instruction, Dis_info *info)
8742 {
8743     uint64 rt_value = extract_rt_25_24_23_22_21(instruction);
8744     uint64 rs_value = extract_rs_20_19_18_17_16(instruction);
8745     uint64 rd_value = extract_rd_15_14_13_12_11(instruction);
8746     uint64 u2_value = extract_u2_10_9(instruction);
8747 
8748     const char *rd = GPR(rd_value, info);
8749     const char *rs = GPR(rs_value, info);
8750     const char *rt = GPR(rt_value, info);
8751 
8752     return img_format("LSA %s, %s, %s, 0x%" PRIx64, rd, rs, rt, u2_value);
8753 }
8754 
8755 
8756 /*
8757  *
8758  *
8759  *   3         2         1
8760  *  10987654321098765432109876543210
8761  *  001000               x1110000101
8762  *     rt -----
8763  *          rs -----
8764  *               rd -----
8765  */
8766 static char *LUI(uint64 instruction, Dis_info *info)
8767 {
8768     uint64 rt_value = extract_rt_25_24_23_22_21(instruction);
8769     int64 s_value = extract_s__se31_0_11_to_2_20_to_12_s12(instruction);
8770 
8771     const char *rt = GPR(rt_value, info);
8772 
8773     return img_format("LUI %s, %%hi(%" PRId64 ")", rt, s_value);
8774 }
8775 
8776 
8777 /*
8778  *
8779  *
8780  *   3         2         1
8781  *  10987654321098765432109876543210
8782  *  001000               x1110000101
8783  *     rt -----
8784  *          rs -----
8785  *               rd -----
8786  */
8787 static char *LW_16_(uint64 instruction, Dis_info *info)
8788 {
8789     uint64 rt3_value = extract_rt3_9_8_7(instruction);
8790     uint64 rs3_value = extract_rs3_6_5_4(instruction);
8791     uint64 u_value = extract_u_3_2_1_0__s2(instruction);
8792 
8793     const char *rt3 = GPR(decode_gpr_gpr3(rt3_value, info), info);
8794     const char *rs3 = GPR(decode_gpr_gpr3(rs3_value, info), info);
8795 
8796     return img_format("LW %s, 0x%" PRIx64 "(%s)", rt3, u_value, rs3);
8797 }
8798 
8799 
8800 /*
8801  *
8802  *
8803  *   3         2         1
8804  *  10987654321098765432109876543210
8805  *  001000               x1110000101
8806  *     rt -----
8807  *          rs -----
8808  *               rd -----
8809  */
8810 static char *LW_4X4_(uint64 instruction, Dis_info *info)
8811 {
8812     uint64 rt4_value = extract_rt4_9_7_6_5(instruction);
8813     uint64 rs4_value = extract_rs4_4_2_1_0(instruction);
8814     uint64 u_value = extract_u_3_8__s2(instruction);
8815 
8816     const char *rt4 = GPR(decode_gpr_gpr4(rt4_value, info), info);
8817     const char *rs4 = GPR(decode_gpr_gpr4(rs4_value, info), info);
8818 
8819     return img_format("LW %s, 0x%" PRIx64 "(%s)", rt4, u_value, rs4);
8820 }
8821 
8822 
8823 /*
8824  *
8825  *
8826  *   3         2         1
8827  *  10987654321098765432109876543210
8828  *  001000               x1110000101
8829  *     rt -----
8830  *          rs -----
8831  *               rd -----
8832  */
8833 static char *LW_GP_(uint64 instruction, Dis_info *info)
8834 {
8835     uint64 rt_value = extract_rt_25_24_23_22_21(instruction);
8836     uint64 u_value = extract_u_20_to_2__s2(instruction);
8837 
8838     const char *rt = GPR(rt_value, info);
8839 
8840     return img_format("LW %s, 0x%" PRIx64 "($%d)", rt, u_value, 28);
8841 }
8842 
8843 
8844 /*
8845  *
8846  *
8847  *   3         2         1
8848  *  10987654321098765432109876543210
8849  *  001000               x1110000101
8850  *     rt -----
8851  *          rs -----
8852  *               rd -----
8853  */
8854 static char *LW_GP16_(uint64 instruction, Dis_info *info)
8855 {
8856     uint64 rt3_value = extract_rt3_9_8_7(instruction);
8857     uint64 u_value = extract_u_6_5_4_3_2_1_0__s2(instruction);
8858 
8859     const char *rt3 = GPR(decode_gpr_gpr3(rt3_value, info), info);
8860 
8861     return img_format("LW %s, 0x%" PRIx64 "($%d)", rt3, u_value, 28);
8862 }
8863 
8864 
8865 /*
8866  *
8867  *
8868  *   3         2         1
8869  *  10987654321098765432109876543210
8870  *  001000               x1110000101
8871  *     rt -----
8872  *          rs -----
8873  *               rd -----
8874  */
8875 static char *LW_S9_(uint64 instruction, Dis_info *info)
8876 {
8877     uint64 rt_value = extract_rt_25_24_23_22_21(instruction);
8878     uint64 rs_value = extract_rs_20_19_18_17_16(instruction);
8879     int64 s_value = extract_s__se8_15_7_6_5_4_3_2_1_0(instruction);
8880 
8881     const char *rt = GPR(rt_value, info);
8882     const char *rs = GPR(rs_value, info);
8883 
8884     return img_format("LW %s, %" PRId64 "(%s)", rt, s_value, rs);
8885 }
8886 
8887 
8888 /*
8889  *
8890  *
8891  *   3         2         1
8892  *  10987654321098765432109876543210
8893  *  001000               x1110000101
8894  *     rt -----
8895  *          rs -----
8896  *               rd -----
8897  */
8898 static char *LW_SP_(uint64 instruction, Dis_info *info)
8899 {
8900     uint64 rt_value = extract_rt_9_8_7_6_5(instruction);
8901     uint64 u_value = extract_u_4_3_2_1_0__s2(instruction);
8902 
8903     const char *rt = GPR(rt_value, info);
8904 
8905     return img_format("LW %s, 0x%" PRIx64 "($%d)", rt, u_value, 29);
8906 }
8907 
8908 
8909 /*
8910  *
8911  *
8912  *   3         2         1
8913  *  10987654321098765432109876543210
8914  *  001000               x1110000101
8915  *     rt -----
8916  *          rs -----
8917  *               rd -----
8918  */
8919 static char *LW_U12_(uint64 instruction, Dis_info *info)
8920 {
8921     uint64 rt_value = extract_rt_25_24_23_22_21(instruction);
8922     uint64 rs_value = extract_rs_20_19_18_17_16(instruction);
8923     uint64 u_value = extract_u_11_10_9_8_7_6_5_4_3_2_1_0(instruction);
8924 
8925     const char *rt = GPR(rt_value, info);
8926     const char *rs = GPR(rs_value, info);
8927 
8928     return img_format("LW %s, 0x%" PRIx64 "(%s)", rt, u_value, rs);
8929 }
8930 
8931 
8932 /*
8933  *
8934  *
8935  *   3         2         1
8936  *  10987654321098765432109876543210
8937  *  001000               x1110000101
8938  *     rt -----
8939  *          rs -----
8940  *               rd -----
8941  */
8942 static char *LWC1_GP_(uint64 instruction, Dis_info *info)
8943 {
8944     uint64 ft_value = extract_ft_25_24_23_22_21(instruction);
8945     uint64 u_value = extract_u_17_to_2__s2(instruction);
8946 
8947     const char *ft = FPR(ft_value, info);
8948 
8949     return img_format("LWC1 %s, 0x%" PRIx64 "($%d)", ft, u_value, 28);
8950 }
8951 
8952 
8953 /*
8954  *
8955  *
8956  *   3         2         1
8957  *  10987654321098765432109876543210
8958  *  001000               x1110000101
8959  *     rt -----
8960  *          rs -----
8961  *               rd -----
8962  */
8963 static char *LWC1_S9_(uint64 instruction, Dis_info *info)
8964 {
8965     uint64 ft_value = extract_ft_25_24_23_22_21(instruction);
8966     uint64 rs_value = extract_rs_20_19_18_17_16(instruction);
8967     int64 s_value = extract_s__se8_15_7_6_5_4_3_2_1_0(instruction);
8968 
8969     const char *ft = FPR(ft_value, info);
8970     const char *rs = GPR(rs_value, info);
8971 
8972     return img_format("LWC1 %s, %" PRId64 "(%s)", ft, s_value, rs);
8973 }
8974 
8975 
8976 /*
8977  *
8978  *
8979  *   3         2         1
8980  *  10987654321098765432109876543210
8981  *  001000               x1110000101
8982  *     rt -----
8983  *          rs -----
8984  *               rd -----
8985  */
8986 static char *LWC1_U12_(uint64 instruction, Dis_info *info)
8987 {
8988     uint64 ft_value = extract_ft_25_24_23_22_21(instruction);
8989     uint64 rs_value = extract_rs_20_19_18_17_16(instruction);
8990     uint64 u_value = extract_u_11_10_9_8_7_6_5_4_3_2_1_0(instruction);
8991 
8992     const char *ft = FPR(ft_value, info);
8993     const char *rs = GPR(rs_value, info);
8994 
8995     return img_format("LWC1 %s, 0x%" PRIx64 "(%s)", ft, u_value, rs);
8996 }
8997 
8998 
8999 /*
9000  *
9001  *
9002  *   3         2         1
9003  *  10987654321098765432109876543210
9004  *  001000               x1110000101
9005  *     rt -----
9006  *          rs -----
9007  *               rd -----
9008  */
9009 static char *LWC1X(uint64 instruction, Dis_info *info)
9010 {
9011     uint64 rt_value = extract_rt_25_24_23_22_21(instruction);
9012     uint64 rs_value = extract_rs_20_19_18_17_16(instruction);
9013     uint64 ft_value = extract_ft_15_14_13_12_11(instruction);
9014 
9015     const char *ft = FPR(ft_value, info);
9016     const char *rs = GPR(rs_value, info);
9017     const char *rt = GPR(rt_value, info);
9018 
9019     return img_format("LWC1X %s, %s(%s)", ft, rs, rt);
9020 }
9021 
9022 
9023 /*
9024  *
9025  *
9026  *   3         2         1
9027  *  10987654321098765432109876543210
9028  *  001000               x1110000101
9029  *     rt -----
9030  *          rs -----
9031  *               rd -----
9032  */
9033 static char *LWC1XS(uint64 instruction, Dis_info *info)
9034 {
9035     uint64 rt_value = extract_rt_25_24_23_22_21(instruction);
9036     uint64 rs_value = extract_rs_20_19_18_17_16(instruction);
9037     uint64 ft_value = extract_ft_15_14_13_12_11(instruction);
9038 
9039     const char *ft = FPR(ft_value, info);
9040     const char *rs = GPR(rs_value, info);
9041     const char *rt = GPR(rt_value, info);
9042 
9043     return img_format("LWC1XS %s, %s(%s)", ft, rs, rt);
9044 }
9045 
9046 
9047 /*
9048  *
9049  *
9050  *   3         2         1
9051  *  10987654321098765432109876543210
9052  *  001000               x1110000101
9053  *     rt -----
9054  *          rs -----
9055  *               rd -----
9056  */
9057 static char *LWC2(uint64 instruction, Dis_info *info)
9058 {
9059     uint64 ct_value = extract_ct_25_24_23_22_21(instruction);
9060     uint64 rs_value = extract_rs_20_19_18_17_16(instruction);
9061     int64 s_value = extract_s__se8_15_7_6_5_4_3_2_1_0(instruction);
9062 
9063     const char *rs = GPR(rs_value, info);
9064 
9065     return img_format("LWC2 CP%" PRIu64 ", %" PRId64 "(%s)",
9066                       ct_value, s_value, rs);
9067 }
9068 
9069 
9070 /*
9071  *
9072  *
9073  *   3         2         1
9074  *  10987654321098765432109876543210
9075  *  001000               x1110000101
9076  *     rt -----
9077  *          rs -----
9078  *               rd -----
9079  */
9080 static char *LWE(uint64 instruction, Dis_info *info)
9081 {
9082     uint64 rt_value = extract_rt_25_24_23_22_21(instruction);
9083     uint64 rs_value = extract_rs_20_19_18_17_16(instruction);
9084     int64 s_value = extract_s__se8_15_7_6_5_4_3_2_1_0(instruction);
9085 
9086     const char *rt = GPR(rt_value, info);
9087     const char *rs = GPR(rs_value, info);
9088 
9089     return img_format("LWE %s, %" PRId64 "(%s)", rt, s_value, rs);
9090 }
9091 
9092 
9093 /*
9094  *
9095  *
9096  *   3         2         1
9097  *  10987654321098765432109876543210
9098  *  001000               x1110000101
9099  *     rt -----
9100  *          rs -----
9101  *               rd -----
9102  */
9103 static char *LWM(uint64 instruction, Dis_info *info)
9104 {
9105     uint64 rt_value = extract_rt_25_24_23_22_21(instruction);
9106     uint64 rs_value = extract_rs_20_19_18_17_16(instruction);
9107     int64 s_value = extract_s__se8_15_7_6_5_4_3_2_1_0(instruction);
9108     uint64 count3_value = extract_count3_14_13_12(instruction);
9109 
9110     const char *rt = GPR(rt_value, info);
9111     const char *rs = GPR(rs_value, info);
9112     uint64 count3 = encode_count3_from_count(count3_value);
9113 
9114     return img_format("LWM %s, %" PRId64 "(%s), 0x%" PRIx64,
9115                       rt, s_value, rs, count3);
9116 }
9117 
9118 
9119 /*
9120  *
9121  *
9122  *   3         2         1
9123  *  10987654321098765432109876543210
9124  *  001000               x1110000101
9125  *     rt -----
9126  *          rs -----
9127  *               rd -----
9128  */
9129 static char *LWPC_48_(uint64 instruction, Dis_info *info)
9130 {
9131     uint64 rt_value = extract_rt_41_40_39_38_37(instruction);
9132     int64 s_value = extract_s__se31_15_to_0_31_to_16(instruction);
9133 
9134     const char *rt = GPR(rt_value, info);
9135     g_autofree char *s = ADDRESS(s_value, 6, info);
9136 
9137     return img_format("LWPC %s, %s", rt, s);
9138 }
9139 
9140 
9141 /*
9142  *
9143  *
9144  *   3         2         1
9145  *  10987654321098765432109876543210
9146  *  001000               x1110000101
9147  *     rt -----
9148  *          rs -----
9149  *               rd -----
9150  */
9151 static char *LWU_GP_(uint64 instruction, Dis_info *info)
9152 {
9153     uint64 rt_value = extract_rt_25_24_23_22_21(instruction);
9154     uint64 u_value = extract_u_17_to_2__s2(instruction);
9155 
9156     const char *rt = GPR(rt_value, info);
9157 
9158     return img_format("LWU %s, 0x%" PRIx64 "($%d)", rt, u_value, 28);
9159 }
9160 
9161 
9162 /*
9163  *
9164  *
9165  *   3         2         1
9166  *  10987654321098765432109876543210
9167  *  001000               x1110000101
9168  *     rt -----
9169  *          rs -----
9170  *               rd -----
9171  */
9172 static char *LWU_S9_(uint64 instruction, Dis_info *info)
9173 {
9174     uint64 rt_value = extract_rt_25_24_23_22_21(instruction);
9175     uint64 rs_value = extract_rs_20_19_18_17_16(instruction);
9176     int64 s_value = extract_s__se8_15_7_6_5_4_3_2_1_0(instruction);
9177 
9178     const char *rt = GPR(rt_value, info);
9179     const char *rs = GPR(rs_value, info);
9180 
9181     return img_format("LWU %s, %" PRId64 "(%s)", rt, s_value, rs);
9182 }
9183 
9184 
9185 /*
9186  *
9187  *
9188  *   3         2         1
9189  *  10987654321098765432109876543210
9190  *  001000               x1110000101
9191  *     rt -----
9192  *          rs -----
9193  *               rd -----
9194  */
9195 static char *LWU_U12_(uint64 instruction, Dis_info *info)
9196 {
9197     uint64 rt_value = extract_rt_25_24_23_22_21(instruction);
9198     uint64 rs_value = extract_rs_20_19_18_17_16(instruction);
9199     uint64 u_value = extract_u_11_10_9_8_7_6_5_4_3_2_1_0(instruction);
9200 
9201     const char *rt = GPR(rt_value, info);
9202     const char *rs = GPR(rs_value, info);
9203 
9204     return img_format("LWU %s, 0x%" PRIx64 "(%s)", rt, u_value, rs);
9205 }
9206 
9207 
9208 /*
9209  *
9210  *
9211  *   3         2         1
9212  *  10987654321098765432109876543210
9213  *  001000               x1110000101
9214  *     rt -----
9215  *          rs -----
9216  *               rd -----
9217  */
9218 static char *LWUX(uint64 instruction, Dis_info *info)
9219 {
9220     uint64 rt_value = extract_rt_25_24_23_22_21(instruction);
9221     uint64 rs_value = extract_rs_20_19_18_17_16(instruction);
9222     uint64 rd_value = extract_rd_15_14_13_12_11(instruction);
9223 
9224     const char *rd = GPR(rd_value, info);
9225     const char *rs = GPR(rs_value, info);
9226     const char *rt = GPR(rt_value, info);
9227 
9228     return img_format("LWUX %s, %s(%s)", rd, rs, rt);
9229 }
9230 
9231 
9232 /*
9233  *
9234  *
9235  *   3         2         1
9236  *  10987654321098765432109876543210
9237  *  001000               x1110000101
9238  *     rt -----
9239  *          rs -----
9240  *               rd -----
9241  */
9242 static char *LWUXS(uint64 instruction, Dis_info *info)
9243 {
9244     uint64 rt_value = extract_rt_25_24_23_22_21(instruction);
9245     uint64 rs_value = extract_rs_20_19_18_17_16(instruction);
9246     uint64 rd_value = extract_rd_15_14_13_12_11(instruction);
9247 
9248     const char *rd = GPR(rd_value, info);
9249     const char *rs = GPR(rs_value, info);
9250     const char *rt = GPR(rt_value, info);
9251 
9252     return img_format("LWUXS %s, %s(%s)", rd, rs, rt);
9253 }
9254 
9255 
9256 /*
9257  *
9258  *
9259  *   3         2         1
9260  *  10987654321098765432109876543210
9261  *  001000               x1110000101
9262  *     rt -----
9263  *          rs -----
9264  *               rd -----
9265  */
9266 static char *LWX(uint64 instruction, Dis_info *info)
9267 {
9268     uint64 rt_value = extract_rt_25_24_23_22_21(instruction);
9269     uint64 rs_value = extract_rs_20_19_18_17_16(instruction);
9270     uint64 rd_value = extract_rd_15_14_13_12_11(instruction);
9271 
9272     const char *rd = GPR(rd_value, info);
9273     const char *rs = GPR(rs_value, info);
9274     const char *rt = GPR(rt_value, info);
9275 
9276     return img_format("LWX %s, %s(%s)", rd, rs, rt);
9277 }
9278 
9279 
9280 /*
9281  *
9282  *
9283  *   3         2         1
9284  *  10987654321098765432109876543210
9285  *  001000               x1110000101
9286  *     rt -----
9287  *          rs -----
9288  *               rd -----
9289  */
9290 static char *LWXS_16_(uint64 instruction, Dis_info *info)
9291 {
9292     uint64 rt3_value = extract_rt3_9_8_7(instruction);
9293     uint64 rs3_value = extract_rs3_6_5_4(instruction);
9294     uint64 rd3_value = extract_rd3_3_2_1(instruction);
9295 
9296     const char *rd3 = GPR(decode_gpr_gpr3(rd3_value, info), info);
9297     const char *rs3 = GPR(decode_gpr_gpr3(rs3_value, info), info);
9298     uint64 rt3 = decode_gpr_gpr3(rt3_value, info);
9299 
9300     return img_format("LWXS %s, %s(0x%" PRIx64 ")", rd3, rs3, rt3);
9301 }
9302 
9303 
9304 /*
9305  *
9306  *
9307  *   3         2         1
9308  *  10987654321098765432109876543210
9309  *  001000               x1110000101
9310  *     rt -----
9311  *          rs -----
9312  *               rd -----
9313  */
9314 static char *LWXS_32_(uint64 instruction, Dis_info *info)
9315 {
9316     uint64 rt_value = extract_rt_25_24_23_22_21(instruction);
9317     uint64 rs_value = extract_rs_20_19_18_17_16(instruction);
9318     uint64 rd_value = extract_rd_15_14_13_12_11(instruction);
9319 
9320     const char *rd = GPR(rd_value, info);
9321     const char *rs = GPR(rs_value, info);
9322     const char *rt = GPR(rt_value, info);
9323 
9324     return img_format("LWXS %s, %s(%s)", rd, rs, rt);
9325 }
9326 
9327 
9328 /*
9329  * [DSP] MADD ac, rs, rt - Multiply two words and add to the specified
9330  *         accumulator
9331  *
9332  *   3         2         1
9333  *  10987654321098765432109876543210
9334  *  001000               x1110000101
9335  *     rt -----
9336  *          rs -----
9337  *               rd -----
9338  */
9339 static char *MADD_DSP_(uint64 instruction, Dis_info *info)
9340 {
9341     uint64 rt_value = extract_rt_25_24_23_22_21(instruction);
9342     uint64 rs_value = extract_rs_20_19_18_17_16(instruction);
9343     uint64 ac_value = extract_ac_15_14(instruction);
9344 
9345     const char *ac = AC(ac_value, info);
9346     const char *rs = GPR(rs_value, info);
9347     const char *rt = GPR(rt_value, info);
9348 
9349     return img_format("MADD %s, %s, %s", ac, rs, rt);
9350 }
9351 
9352 
9353 /*
9354  *
9355  *
9356  *   3         2         1
9357  *  10987654321098765432109876543210
9358  *  001000               x1110000101
9359  *     rt -----
9360  *          rs -----
9361  *               rd -----
9362  */
9363 static char *MADDF_D(uint64 instruction, Dis_info *info)
9364 {
9365     uint64 ft_value = extract_ft_25_24_23_22_21(instruction);
9366     uint64 fs_value = extract_fs_20_19_18_17_16(instruction);
9367     uint64 fd_value = extract_fd_15_14_13_12_11(instruction);
9368 
9369     const char *fd = FPR(fd_value, info);
9370     const char *fs = FPR(fs_value, info);
9371     const char *ft = FPR(ft_value, info);
9372 
9373     return img_format("MADDF.D %s, %s, %s", fd, fs, ft);
9374 }
9375 
9376 
9377 /*
9378  *
9379  *
9380  *   3         2         1
9381  *  10987654321098765432109876543210
9382  *  001000               x1110000101
9383  *     rt -----
9384  *          rs -----
9385  *               rd -----
9386  */
9387 static char *MADDF_S(uint64 instruction, Dis_info *info)
9388 {
9389     uint64 ft_value = extract_ft_25_24_23_22_21(instruction);
9390     uint64 fs_value = extract_fs_20_19_18_17_16(instruction);
9391     uint64 fd_value = extract_fd_15_14_13_12_11(instruction);
9392 
9393     const char *fd = FPR(fd_value, info);
9394     const char *fs = FPR(fs_value, info);
9395     const char *ft = FPR(ft_value, info);
9396 
9397     return img_format("MADDF.S %s, %s, %s", fd, fs, ft);
9398 }
9399 
9400 
9401 /*
9402  * [DSP] MADDU ac, rs, rt - Multiply two unsigned words and add to the
9403  *         specified accumulator
9404  *
9405  *   3         2         1
9406  *  10987654321098765432109876543210
9407  *  001000               x1110000101
9408  *     rt -----
9409  *          rs -----
9410  *               rd -----
9411  */
9412 static char *MADDU_DSP_(uint64 instruction, Dis_info *info)
9413 {
9414     uint64 rt_value = extract_rt_25_24_23_22_21(instruction);
9415     uint64 rs_value = extract_rs_20_19_18_17_16(instruction);
9416     uint64 ac_value = extract_ac_15_14(instruction);
9417 
9418     const char *ac = AC(ac_value, info);
9419     const char *rs = GPR(rs_value, info);
9420     const char *rt = GPR(rt_value, info);
9421 
9422     return img_format("MADDU %s, %s, %s", ac, rs, rt);
9423 }
9424 
9425 
9426 /*
9427  * [DSP] MAQ_S.W.PHL ac, rs, rt - Multiply the left-most single vector
9428  *         fractional halfword elements with accumulation
9429  *
9430  *   3         2         1
9431  *  10987654321098765432109876543210
9432  *  001000               x1110000101
9433  *     rt -----
9434  *          rs -----
9435  *               rd -----
9436  */
9437 static char *MAQ_S_W_PHL(uint64 instruction, Dis_info *info)
9438 {
9439     uint64 rt_value = extract_rt_25_24_23_22_21(instruction);
9440     uint64 rs_value = extract_rs_20_19_18_17_16(instruction);
9441     uint64 ac_value = extract_ac_15_14(instruction);
9442 
9443     const char *ac = AC(ac_value, info);
9444     const char *rs = GPR(rs_value, info);
9445     const char *rt = GPR(rt_value, info);
9446 
9447     return img_format("MAQ_S.W.PHL %s, %s, %s", ac, rs, rt);
9448 }
9449 
9450 
9451 /*
9452  * [DSP] MAQ_S.W.PHR ac, rs, rt - Multiply the right-most single vector
9453  *         fractional halfword elements with accumulation
9454  *
9455  *   3         2         1
9456  *  10987654321098765432109876543210
9457  *  001000               x1110000101
9458  *     rt -----
9459  *          rs -----
9460  *               rd -----
9461  */
9462 static char *MAQ_S_W_PHR(uint64 instruction, Dis_info *info)
9463 {
9464     uint64 rt_value = extract_rt_25_24_23_22_21(instruction);
9465     uint64 rs_value = extract_rs_20_19_18_17_16(instruction);
9466     uint64 ac_value = extract_ac_15_14(instruction);
9467 
9468     const char *ac = AC(ac_value, info);
9469     const char *rs = GPR(rs_value, info);
9470     const char *rt = GPR(rt_value, info);
9471 
9472     return img_format("MAQ_S.W.PHR %s, %s, %s", ac, rs, rt);
9473 }
9474 
9475 
9476 /*
9477  * [DSP] MAQ_SA.W.PHL ac, rs, rt - Multiply the left-most single vector
9478  *         fractional halfword elements with saturating accumulation
9479  *
9480  *   3         2         1
9481  *  10987654321098765432109876543210
9482  *  001000               x1110000101
9483  *     rt -----
9484  *          rs -----
9485  *               rd -----
9486  */
9487 static char *MAQ_SA_W_PHL(uint64 instruction, Dis_info *info)
9488 {
9489     uint64 rt_value = extract_rt_25_24_23_22_21(instruction);
9490     uint64 rs_value = extract_rs_20_19_18_17_16(instruction);
9491     uint64 ac_value = extract_ac_15_14(instruction);
9492 
9493     const char *ac = AC(ac_value, info);
9494     const char *rs = GPR(rs_value, info);
9495     const char *rt = GPR(rt_value, info);
9496 
9497     return img_format("MAQ_SA.W.PHL %s, %s, %s", ac, rs, rt);
9498 }
9499 
9500 
9501 /*
9502  * [DSP] MAQ_SA.W.PHR ac, rs, rt - Multiply the right-most single vector
9503  *         fractional halfword elements with saturating accumulation
9504  *
9505  *   3         2         1
9506  *  10987654321098765432109876543210
9507  *  001000               x1110000101
9508  *     rt -----
9509  *          rs -----
9510  *               rd -----
9511  */
9512 static char *MAQ_SA_W_PHR(uint64 instruction, Dis_info *info)
9513 {
9514     uint64 rt_value = extract_rt_25_24_23_22_21(instruction);
9515     uint64 rs_value = extract_rs_20_19_18_17_16(instruction);
9516     uint64 ac_value = extract_ac_15_14(instruction);
9517 
9518     const char *ac = AC(ac_value, info);
9519     const char *rs = GPR(rs_value, info);
9520     const char *rt = GPR(rt_value, info);
9521 
9522     return img_format("MAQ_SA.W.PHR %s, %s, %s", ac, rs, rt);
9523 }
9524 
9525 
9526 /*
9527  *
9528  *
9529  *   3         2         1
9530  *  10987654321098765432109876543210
9531  *  001000               x1110000101
9532  *     rt -----
9533  *          rs -----
9534  *               rd -----
9535  */
9536 static char *MAX_D(uint64 instruction, Dis_info *info)
9537 {
9538     uint64 ft_value = extract_ft_25_24_23_22_21(instruction);
9539     uint64 fs_value = extract_fs_20_19_18_17_16(instruction);
9540     uint64 fd_value = extract_fd_15_14_13_12_11(instruction);
9541 
9542     const char *fd = FPR(fd_value, info);
9543     const char *fs = FPR(fs_value, info);
9544     const char *ft = FPR(ft_value, info);
9545 
9546     return img_format("MAX.D %s, %s, %s", fd, fs, ft);
9547 }
9548 
9549 
9550 /*
9551  *
9552  *
9553  *   3         2         1
9554  *  10987654321098765432109876543210
9555  *  001000               x1110000101
9556  *     rt -----
9557  *          rs -----
9558  *               rd -----
9559  */
9560 static char *MAX_S(uint64 instruction, Dis_info *info)
9561 {
9562     uint64 ft_value = extract_ft_25_24_23_22_21(instruction);
9563     uint64 fs_value = extract_fs_20_19_18_17_16(instruction);
9564     uint64 fd_value = extract_fd_15_14_13_12_11(instruction);
9565 
9566     const char *fd = FPR(fd_value, info);
9567     const char *fs = FPR(fs_value, info);
9568     const char *ft = FPR(ft_value, info);
9569 
9570     return img_format("MAX.S %s, %s, %s", fd, fs, ft);
9571 }
9572 
9573 
9574 /*
9575  *
9576  *
9577  *   3         2         1
9578  *  10987654321098765432109876543210
9579  *  001000               x1110000101
9580  *     rt -----
9581  *          rs -----
9582  *               rd -----
9583  */
9584 static char *MAXA_D(uint64 instruction, Dis_info *info)
9585 {
9586     uint64 ft_value = extract_ft_25_24_23_22_21(instruction);
9587     uint64 fs_value = extract_fs_20_19_18_17_16(instruction);
9588     uint64 fd_value = extract_fd_15_14_13_12_11(instruction);
9589 
9590     const char *fd = FPR(fd_value, info);
9591     const char *fs = FPR(fs_value, info);
9592     const char *ft = FPR(ft_value, info);
9593 
9594     return img_format("MAXA.D %s, %s, %s", fd, fs, ft);
9595 }
9596 
9597 
9598 /*
9599  *
9600  *
9601  *   3         2         1
9602  *  10987654321098765432109876543210
9603  *  001000               x1110000101
9604  *     rt -----
9605  *          rs -----
9606  *               rd -----
9607  */
9608 static char *MAXA_S(uint64 instruction, Dis_info *info)
9609 {
9610     uint64 ft_value = extract_ft_25_24_23_22_21(instruction);
9611     uint64 fs_value = extract_fs_20_19_18_17_16(instruction);
9612     uint64 fd_value = extract_fd_15_14_13_12_11(instruction);
9613 
9614     const char *fd = FPR(fd_value, info);
9615     const char *fs = FPR(fs_value, info);
9616     const char *ft = FPR(ft_value, info);
9617 
9618     return img_format("MAXA.S %s, %s, %s", fd, fs, ft);
9619 }
9620 
9621 
9622 /*
9623  *
9624  *
9625  *   3         2         1
9626  *  10987654321098765432109876543210
9627  *  001000               x1110000101
9628  *     rt -----
9629  *          rs -----
9630  *               rd -----
9631  */
9632 static char *MFC0(uint64 instruction, Dis_info *info)
9633 {
9634     uint64 rt_value = extract_rt_25_24_23_22_21(instruction);
9635     uint64 c0s_value = extract_c0s_20_19_18_17_16(instruction);
9636     uint64 sel_value = extract_sel_15_14_13_12_11(instruction);
9637 
9638     const char *rt = GPR(rt_value, info);
9639 
9640     return img_format("MFC0 %s, CP%" PRIu64 ", 0x%" PRIx64,
9641                       rt, c0s_value, sel_value);
9642 }
9643 
9644 
9645 /*
9646  *
9647  *
9648  *   3         2         1
9649  *  10987654321098765432109876543210
9650  *  001000               x1110000101
9651  *     rt -----
9652  *          rs -----
9653  *               rd -----
9654  */
9655 static char *MFC1(uint64 instruction, Dis_info *info)
9656 {
9657     uint64 rt_value = extract_rt_25_24_23_22_21(instruction);
9658     uint64 fs_value = extract_fs_20_19_18_17_16(instruction);
9659 
9660     const char *rt = GPR(rt_value, info);
9661     const char *fs = FPR(fs_value, info);
9662 
9663     return img_format("MFC1 %s, %s", rt, fs);
9664 }
9665 
9666 
9667 /*
9668  *
9669  *
9670  *   3         2         1
9671  *  10987654321098765432109876543210
9672  *  001000               x1110000101
9673  *     rt -----
9674  *          rs -----
9675  *               rd -----
9676  */
9677 static char *MFC2(uint64 instruction, Dis_info *info)
9678 {
9679     uint64 rt_value = extract_rt_25_24_23_22_21(instruction);
9680     uint64 cs_value = extract_cs_20_19_18_17_16(instruction);
9681 
9682     const char *rt = GPR(rt_value, info);
9683 
9684     return img_format("MFC2 %s, CP%" PRIu64, rt, cs_value);
9685 }
9686 
9687 
9688 /*
9689  *
9690  *
9691  *   3         2         1
9692  *  10987654321098765432109876543210
9693  *  001000               x1110000101
9694  *     rt -----
9695  *          rs -----
9696  *               rd -----
9697  */
9698 static char *MFGC0(uint64 instruction, Dis_info *info)
9699 {
9700     uint64 rt_value = extract_rt_25_24_23_22_21(instruction);
9701     uint64 c0s_value = extract_c0s_20_19_18_17_16(instruction);
9702     uint64 sel_value = extract_sel_15_14_13_12_11(instruction);
9703 
9704     const char *rt = GPR(rt_value, info);
9705 
9706     return img_format("MFGC0 %s, CP%" PRIu64 ", 0x%" PRIx64,
9707                       rt, c0s_value, sel_value);
9708 }
9709 
9710 
9711 /*
9712  *
9713  *
9714  *   3         2         1
9715  *  10987654321098765432109876543210
9716  *  001000               x1110000101
9717  *     rt -----
9718  *          rs -----
9719  *               rd -----
9720  */
9721 static char *MFHC0(uint64 instruction, Dis_info *info)
9722 {
9723     uint64 rt_value = extract_rt_25_24_23_22_21(instruction);
9724     uint64 c0s_value = extract_c0s_20_19_18_17_16(instruction);
9725     uint64 sel_value = extract_sel_15_14_13_12_11(instruction);
9726 
9727     const char *rt = GPR(rt_value, info);
9728 
9729     return img_format("MFHC0 %s, CP%" PRIu64 ", 0x%" PRIx64,
9730                       rt, c0s_value, sel_value);
9731 }
9732 
9733 
9734 /*
9735  *
9736  *
9737  *   3         2         1
9738  *  10987654321098765432109876543210
9739  *  001000               x1110000101
9740  *     rt -----
9741  *          rs -----
9742  *               rd -----
9743  */
9744 static char *MFHC1(uint64 instruction, Dis_info *info)
9745 {
9746     uint64 rt_value = extract_rt_25_24_23_22_21(instruction);
9747     uint64 fs_value = extract_fs_20_19_18_17_16(instruction);
9748 
9749     const char *rt = GPR(rt_value, info);
9750     const char *fs = FPR(fs_value, info);
9751 
9752     return img_format("MFHC1 %s, %s", rt, fs);
9753 }
9754 
9755 
9756 /*
9757  *
9758  *
9759  *   3         2         1
9760  *  10987654321098765432109876543210
9761  *  001000               x1110000101
9762  *     rt -----
9763  *          rs -----
9764  *               rd -----
9765  */
9766 static char *MFHC2(uint64 instruction, Dis_info *info)
9767 {
9768     uint64 rt_value = extract_rt_25_24_23_22_21(instruction);
9769     uint64 cs_value = extract_cs_20_19_18_17_16(instruction);
9770 
9771     const char *rt = GPR(rt_value, info);
9772 
9773     return img_format("MFHC2 %s, CP%" PRIu64, rt, cs_value);
9774 }
9775 
9776 
9777 /*
9778  *
9779  *
9780  *   3         2         1
9781  *  10987654321098765432109876543210
9782  *  001000               x1110000101
9783  *     rt -----
9784  *          rs -----
9785  *               rd -----
9786  */
9787 static char *MFHGC0(uint64 instruction, Dis_info *info)
9788 {
9789     uint64 rt_value = extract_rt_25_24_23_22_21(instruction);
9790     uint64 c0s_value = extract_c0s_20_19_18_17_16(instruction);
9791     uint64 sel_value = extract_sel_15_14_13_12_11(instruction);
9792 
9793     const char *rt = GPR(rt_value, info);
9794 
9795     return img_format("MFHGC0 %s, CP%" PRIu64 ", 0x%" PRIx64,
9796                       rt, c0s_value, sel_value);
9797 }
9798 
9799 
9800 /*
9801  * [DSP] MFHI rs, ac - Move from HI register
9802  *
9803  *   3         2         1
9804  *  10987654321098765432109876543210
9805  *  001000     xxxxx  00000001111111
9806  *     rt -----
9807  *               ac --
9808  */
9809 static char *MFHI_DSP_(uint64 instruction, Dis_info *info)
9810 {
9811     uint64 rt_value = extract_rt_25_24_23_22_21(instruction);
9812     uint64 ac_value = extract_ac_15_14(instruction);
9813 
9814     const char *rt = GPR(rt_value, info);
9815     const char *ac = AC(ac_value, info);
9816 
9817     return img_format("MFHI %s, %s", rt, ac);
9818 }
9819 
9820 
9821 /*
9822  *
9823  *
9824  *   3         2         1
9825  *  10987654321098765432109876543210
9826  *  001000               x1110000101
9827  *     rt -----
9828  *          rs -----
9829  *               rd -----
9830  */
9831 static char *MFHTR(uint64 instruction, Dis_info *info)
9832 {
9833     uint64 rt_value = extract_rt_25_24_23_22_21(instruction);
9834     uint64 c0s_value = extract_c0s_20_19_18_17_16(instruction);
9835     uint64 sel_value = extract_sel_15_14_13_12_11(instruction);
9836     uint64 u_value = extract_u_10(instruction);
9837 
9838     const char *rt = GPR(rt_value, info);
9839 
9840     return img_format("MFHTR %s, 0x%" PRIx64 ", 0x%" PRIx64 ", 0x%" PRIx64,
9841                       rt, c0s_value, u_value, sel_value);
9842 }
9843 
9844 
9845 /*
9846  * [DSP] MFLO rs, ac - Move from HI register
9847  *
9848  *   3         2         1
9849  *  10987654321098765432109876543210
9850  *  001000     xxxxx  01000001111111
9851  *     rt -----
9852  *               ac --
9853  */
9854 static char *MFLO_DSP_(uint64 instruction, Dis_info *info)
9855 {
9856     uint64 rt_value = extract_rt_25_24_23_22_21(instruction);
9857     uint64 ac_value = extract_ac_15_14(instruction);
9858 
9859     const char *rt = GPR(rt_value, info);
9860     const char *ac = AC(ac_value, info);
9861 
9862     return img_format("MFLO %s, %s", rt, ac);
9863 }
9864 
9865 
9866 /*
9867  *
9868  *
9869  *   3         2         1
9870  *  10987654321098765432109876543210
9871  *  001000               x1110000101
9872  *     rt -----
9873  *          rs -----
9874  *               rd -----
9875  */
9876 static char *MFTR(uint64 instruction, Dis_info *info)
9877 {
9878     uint64 rt_value = extract_rt_25_24_23_22_21(instruction);
9879     uint64 c0s_value = extract_c0s_20_19_18_17_16(instruction);
9880     uint64 sel_value = extract_sel_15_14_13_12_11(instruction);
9881     uint64 u_value = extract_u_10(instruction);
9882 
9883     const char *rt = GPR(rt_value, info);
9884 
9885     return img_format("MFTR %s, 0x%" PRIx64 ", 0x%" PRIx64 ", 0x%" PRIx64,
9886                       rt, c0s_value, u_value, sel_value);
9887 }
9888 
9889 
9890 /*
9891  *
9892  *
9893  *   3         2         1
9894  *  10987654321098765432109876543210
9895  *  001000               x1110000101
9896  *     rt -----
9897  *          rs -----
9898  *               rd -----
9899  */
9900 static char *MIN_D(uint64 instruction, Dis_info *info)
9901 {
9902     uint64 ft_value = extract_ft_25_24_23_22_21(instruction);
9903     uint64 fs_value = extract_fs_20_19_18_17_16(instruction);
9904     uint64 fd_value = extract_fd_15_14_13_12_11(instruction);
9905 
9906     const char *fd = FPR(fd_value, info);
9907     const char *fs = FPR(fs_value, info);
9908     const char *ft = FPR(ft_value, info);
9909 
9910     return img_format("MIN.D %s, %s, %s", fd, fs, ft);
9911 }
9912 
9913 
9914 /*
9915  *
9916  *
9917  *   3         2         1
9918  *  10987654321098765432109876543210
9919  *  001000               x1110000101
9920  *     rt -----
9921  *          rs -----
9922  *               rd -----
9923  */
9924 static char *MIN_S(uint64 instruction, Dis_info *info)
9925 {
9926     uint64 ft_value = extract_ft_25_24_23_22_21(instruction);
9927     uint64 fs_value = extract_fs_20_19_18_17_16(instruction);
9928     uint64 fd_value = extract_fd_15_14_13_12_11(instruction);
9929 
9930     const char *fd = FPR(fd_value, info);
9931     const char *fs = FPR(fs_value, info);
9932     const char *ft = FPR(ft_value, info);
9933 
9934     return img_format("MIN.S %s, %s, %s", fd, fs, ft);
9935 }
9936 
9937 
9938 /*
9939  *
9940  *
9941  *   3         2         1
9942  *  10987654321098765432109876543210
9943  *  001000               x1110000101
9944  *     rt -----
9945  *          rs -----
9946  *               rd -----
9947  */
9948 static char *MINA_D(uint64 instruction, Dis_info *info)
9949 {
9950     uint64 ft_value = extract_ft_25_24_23_22_21(instruction);
9951     uint64 fs_value = extract_fs_20_19_18_17_16(instruction);
9952     uint64 fd_value = extract_fd_15_14_13_12_11(instruction);
9953 
9954     const char *fd = FPR(fd_value, info);
9955     const char *fs = FPR(fs_value, info);
9956     const char *ft = FPR(ft_value, info);
9957 
9958     return img_format("MINA.D %s, %s, %s", fd, fs, ft);
9959 }
9960 
9961 
9962 /*
9963  *
9964  *
9965  *   3         2         1
9966  *  10987654321098765432109876543210
9967  *  001000               x1110000101
9968  *     rt -----
9969  *          rs -----
9970  *               rd -----
9971  */
9972 static char *MINA_S(uint64 instruction, Dis_info *info)
9973 {
9974     uint64 ft_value = extract_ft_25_24_23_22_21(instruction);
9975     uint64 fs_value = extract_fs_20_19_18_17_16(instruction);
9976     uint64 fd_value = extract_fd_15_14_13_12_11(instruction);
9977 
9978     const char *fd = FPR(fd_value, info);
9979     const char *fs = FPR(fs_value, info);
9980     const char *ft = FPR(ft_value, info);
9981 
9982     return img_format("MINA.S %s, %s, %s", fd, fs, ft);
9983 }
9984 
9985 
9986 /*
9987  *
9988  *
9989  *   3         2         1
9990  *  10987654321098765432109876543210
9991  *  001000               x1110000101
9992  *     rt -----
9993  *          rs -----
9994  *               rd -----
9995  */
9996 static char *MOD(uint64 instruction, Dis_info *info)
9997 {
9998     uint64 rt_value = extract_rt_25_24_23_22_21(instruction);
9999     uint64 rs_value = extract_rs_20_19_18_17_16(instruction);
10000     uint64 rd_value = extract_rd_15_14_13_12_11(instruction);
10001 
10002     const char *rd = GPR(rd_value, info);
10003     const char *rs = GPR(rs_value, info);
10004     const char *rt = GPR(rt_value, info);
10005 
10006     return img_format("MOD %s, %s, %s", rd, rs, rt);
10007 }
10008 
10009 
10010 /*
10011  * [DSP] MODSUB rd, rs, rt - Modular subtraction on an index value
10012  *
10013  *   3         2         1
10014  *  10987654321098765432109876543210
10015  *  001000               x1110000101
10016  *     rt -----
10017  *          rs -----
10018  *               rd -----
10019  */
10020 static char *MODSUB(uint64 instruction, Dis_info *info)
10021 {
10022     uint64 rt_value = extract_rt_25_24_23_22_21(instruction);
10023     uint64 rs_value = extract_rs_20_19_18_17_16(instruction);
10024     uint64 rd_value = extract_rd_15_14_13_12_11(instruction);
10025 
10026     const char *rd = GPR(rd_value, info);
10027     const char *rs = GPR(rs_value, info);
10028     const char *rt = GPR(rt_value, info);
10029 
10030     return img_format("MODSUB %s, %s, %s", rd, rs, rt);
10031 }
10032 
10033 
10034 /*
10035  *
10036  *
10037  *   3         2         1
10038  *  10987654321098765432109876543210
10039  *  001000               x1010010101
10040  *     rt -----
10041  *          rs -----
10042  *               rd -----
10043  */
10044 static char *MODU(uint64 instruction, Dis_info *info)
10045 {
10046     uint64 rt_value = extract_rt_25_24_23_22_21(instruction);
10047     uint64 rs_value = extract_rs_20_19_18_17_16(instruction);
10048     uint64 rd_value = extract_rd_15_14_13_12_11(instruction);
10049 
10050     const char *rd = GPR(rd_value, info);
10051     const char *rs = GPR(rs_value, info);
10052     const char *rt = GPR(rt_value, info);
10053 
10054     return img_format("MODU %s, %s, %s", rd, rs, rt);
10055 }
10056 
10057 
10058 /*
10059  *
10060  *
10061  *   3         2         1
10062  *  10987654321098765432109876543210
10063  *  001000               x1110000101
10064  *     rt -----
10065  *          rs -----
10066  *               rd -----
10067  */
10068 static char *MOV_D(uint64 instruction, Dis_info *info)
10069 {
10070     uint64 ft_value = extract_ft_25_24_23_22_21(instruction);
10071     uint64 fs_value = extract_fs_20_19_18_17_16(instruction);
10072 
10073     const char *ft = FPR(ft_value, info);
10074     const char *fs = FPR(fs_value, info);
10075 
10076     return img_format("MOV.D %s, %s", ft, fs);
10077 }
10078 
10079 
10080 /*
10081  *
10082  *
10083  *   3         2         1
10084  *  10987654321098765432109876543210
10085  *  001000               x1110000101
10086  *     rt -----
10087  *          rs -----
10088  *               rd -----
10089  */
10090 static char *MOV_S(uint64 instruction, Dis_info *info)
10091 {
10092     uint64 ft_value = extract_ft_25_24_23_22_21(instruction);
10093     uint64 fs_value = extract_fs_20_19_18_17_16(instruction);
10094 
10095     const char *ft = FPR(ft_value, info);
10096     const char *fs = FPR(fs_value, info);
10097 
10098     return img_format("MOV.S %s, %s", ft, fs);
10099 }
10100 
10101 
10102 /*
10103  *
10104  *
10105  *   3         2         1
10106  *  10987654321098765432109876543210
10107  *  001000               x1110000101
10108  *     rt -----
10109  *          rs -----
10110  *               rd -----
10111  */
10112 static char *MOVE_BALC(uint64 instruction, Dis_info *info)
10113 {
10114     uint64 rtz4_value = extract_rtz4_27_26_25_23_22_21(instruction);
10115     uint64 rd1_value = extract_rdl_25_24(instruction);
10116     int64 s_value = extract_s__se21_0_20_to_1_s1(instruction);
10117 
10118     const char *rd1 = GPR(decode_gpr_gpr1(rd1_value, info), info);
10119     const char *rtz4 = GPR(decode_gpr_gpr4_zero(rtz4_value, info), info);
10120     g_autofree char *s = ADDRESS(s_value, 4, info);
10121 
10122     return img_format("MOVE.BALC %s, %s, %s", rd1, rtz4, s);
10123 }
10124 
10125 
10126 /*
10127  *
10128  *
10129  *   3         2         1
10130  *  10987654321098765432109876543210
10131  *  001000               x1110000101
10132  *     rt -----
10133  *          rs -----
10134  *               rd -----
10135  */
10136 static char *MOVEP(uint64 instruction, Dis_info *info)
10137 {
10138     uint64 rtz4_value = extract_rtz4_9_7_6_5(instruction);
10139     uint64 rd2_value = extract_rd2_3_8(instruction);
10140     uint64 rsz4_value = extract_rsz4_4_2_1_0(instruction);
10141 
10142     const char *rd2 = GPR(decode_gpr_gpr2_reg1(rd2_value, info), info);
10143     const char *re2 = GPR(decode_gpr_gpr2_reg2(rd2_value, info), info);
10144     /* !!!!!!!!!! - no conversion function */
10145     const char *rsz4 = GPR(decode_gpr_gpr4_zero(rsz4_value, info), info);
10146     const char *rtz4 = GPR(decode_gpr_gpr4_zero(rtz4_value, info), info);
10147 
10148     return img_format("MOVEP %s, %s, %s, %s", rd2, re2, rsz4, rtz4);
10149     /* hand edited */
10150 }
10151 
10152 
10153 /*
10154  *
10155  *
10156  *   3         2         1
10157  *  10987654321098765432109876543210
10158  *  001000               x1110000101
10159  *     rt -----
10160  *          rs -----
10161  *               rd -----
10162  */
10163 static char *MOVEP_REV_(uint64 instruction, Dis_info *info)
10164 {
10165     uint64 rt4_value = extract_rt4_9_7_6_5(instruction);
10166     uint64 rd2_value = extract_rd2_3_8(instruction);
10167     uint64 rs4_value = extract_rs4_4_2_1_0(instruction);
10168 
10169     const char *rs4 = GPR(decode_gpr_gpr4(rs4_value, info), info);
10170     const char *rt4 = GPR(decode_gpr_gpr4(rt4_value, info), info);
10171     const char *rd2 = GPR(decode_gpr_gpr2_reg1(rd2_value, info), info);
10172     const char *rs2 = GPR(decode_gpr_gpr2_reg2(rd2_value, info), info);
10173     /* !!!!!!!!!! - no conversion function */
10174 
10175     return img_format("MOVEP %s, %s, %s, %s", rs4, rt4, rd2, rs2);
10176     /* hand edited */
10177 }
10178 
10179 
10180 /*
10181  * ADDQH_R.W rd, rt, rs - Add Fractional Words And Shift Right to Halve Results
10182  *
10183  *   3         2         1
10184  *  10987654321098765432109876543210
10185  *  001000               00010001101
10186  *     rt -----
10187  *          rs -----
10188  *               rd -----
10189  */
10190 static char *MOVE(uint64 instruction, Dis_info *info)
10191 {
10192     uint64 rt_value = extract_rt_9_8_7_6_5(instruction);
10193     uint64 rs_value = extract_rs_4_3_2_1_0(instruction);
10194 
10195     const char *rt = GPR(rt_value, info);
10196     const char *rs = GPR(rs_value, info);
10197 
10198     return img_format("MOVE %s, %s", rt, rs);
10199 }
10200 
10201 
10202 /*
10203  * ADDQH_R.W rd, rt, rs - Add Fractional Words And Shift Right to Halve Results
10204  *
10205  *   3         2         1
10206  *  10987654321098765432109876543210
10207  *  001000               00010001101
10208  *     rt -----
10209  *          rs -----
10210  *               rd -----
10211  */
10212 static char *MOVN(uint64 instruction, Dis_info *info)
10213 {
10214     uint64 rt_value = extract_rt_25_24_23_22_21(instruction);
10215     uint64 rs_value = extract_rs_20_19_18_17_16(instruction);
10216     uint64 rd_value = extract_rd_15_14_13_12_11(instruction);
10217 
10218     const char *rd = GPR(rd_value, info);
10219     const char *rs = GPR(rs_value, info);
10220     const char *rt = GPR(rt_value, info);
10221 
10222     return img_format("MOVN %s, %s, %s", rd, rs, rt);
10223 }
10224 
10225 
10226 /*
10227  * ADDQH_R.W rd, rt, rs - Add Fractional Words And Shift Right to Halve Results
10228  *
10229  *   3         2         1
10230  *  10987654321098765432109876543210
10231  *  001000               00010001101
10232  *     rt -----
10233  *          rs -----
10234  *               rd -----
10235  */
10236 static char *MOVZ(uint64 instruction, Dis_info *info)
10237 {
10238     uint64 rt_value = extract_rt_25_24_23_22_21(instruction);
10239     uint64 rs_value = extract_rs_20_19_18_17_16(instruction);
10240     uint64 rd_value = extract_rd_15_14_13_12_11(instruction);
10241 
10242     const char *rd = GPR(rd_value, info);
10243     const char *rs = GPR(rs_value, info);
10244     const char *rt = GPR(rt_value, info);
10245 
10246     return img_format("MOVZ %s, %s, %s", rd, rs, rt);
10247 }
10248 
10249 
10250 /*
10251  * [DSP] MSUB ac, rs, rt - Multiply word and subtract from accumulator
10252  *
10253  *   3         2         1
10254  *  10987654321098765432109876543210
10255  *  001000            10101010111111
10256  *     rt -----
10257  *          rs -----
10258  *               ac --
10259  */
10260 static char *MSUB_DSP_(uint64 instruction, Dis_info *info)
10261 {
10262     uint64 rt_value = extract_rt_25_24_23_22_21(instruction);
10263     uint64 rs_value = extract_rs_20_19_18_17_16(instruction);
10264     uint64 ac_value = extract_ac_15_14(instruction);
10265 
10266     const char *ac = AC(ac_value, info);
10267     const char *rs = GPR(rs_value, info);
10268     const char *rt = GPR(rt_value, info);
10269 
10270     return img_format("MSUB %s, %s, %s", ac, rs, rt);
10271 }
10272 
10273 
10274 /*
10275  * ADDQH_R.W rd, rt, rs - Add Fractional Words And Shift Right to Halve Results
10276  *
10277  *   3         2         1
10278  *  10987654321098765432109876543210
10279  *  001000               00010001101
10280  *     rt -----
10281  *          rs -----
10282  *               rd -----
10283  */
10284 static char *MSUBF_D(uint64 instruction, Dis_info *info)
10285 {
10286     uint64 ft_value = extract_ft_25_24_23_22_21(instruction);
10287     uint64 fs_value = extract_fs_20_19_18_17_16(instruction);
10288     uint64 fd_value = extract_fd_15_14_13_12_11(instruction);
10289 
10290     const char *fd = FPR(fd_value, info);
10291     const char *fs = FPR(fs_value, info);
10292     const char *ft = FPR(ft_value, info);
10293 
10294     return img_format("MSUBF.D %s, %s, %s", fd, fs, ft);
10295 }
10296 
10297 
10298 /*
10299  * ADDQH_R.W rd, rt, rs - Add Fractional Words And Shift Right to Halve Results
10300  *
10301  *   3         2         1
10302  *  10987654321098765432109876543210
10303  *  001000               00010001101
10304  *     rt -----
10305  *          rs -----
10306  *               rd -----
10307  */
10308 static char *MSUBF_S(uint64 instruction, Dis_info *info)
10309 {
10310     uint64 ft_value = extract_ft_25_24_23_22_21(instruction);
10311     uint64 fs_value = extract_fs_20_19_18_17_16(instruction);
10312     uint64 fd_value = extract_fd_15_14_13_12_11(instruction);
10313 
10314     const char *fd = FPR(fd_value, info);
10315     const char *fs = FPR(fs_value, info);
10316     const char *ft = FPR(ft_value, info);
10317 
10318     return img_format("MSUBF.S %s, %s, %s", fd, fs, ft);
10319 }
10320 
10321 
10322 /*
10323  * [DSP] MSUBU ac, rs, rt - Multiply word and add to accumulator
10324  *
10325  *   3         2         1
10326  *  10987654321098765432109876543210
10327  *  001000            11101010111111
10328  *     rt -----
10329  *          rs -----
10330  *               ac --
10331  */
10332 static char *MSUBU_DSP_(uint64 instruction, Dis_info *info)
10333 {
10334     uint64 rt_value = extract_rt_25_24_23_22_21(instruction);
10335     uint64 rs_value = extract_rs_20_19_18_17_16(instruction);
10336     uint64 ac_value = extract_ac_15_14(instruction);
10337 
10338     const char *ac = AC(ac_value, info);
10339     const char *rs = GPR(rs_value, info);
10340     const char *rt = GPR(rt_value, info);
10341 
10342     return img_format("MSUBU %s, %s, %s", ac, rs, rt);
10343 }
10344 
10345 
10346 /*
10347  * ADDQH_R.W rd, rt, rs - Add Fractional Words And Shift Right to Halve Results
10348  *
10349  *   3         2         1
10350  *  10987654321098765432109876543210
10351  *  001000               00010001101
10352  *     rt -----
10353  *          rs -----
10354  *               rd -----
10355  */
10356 static char *MTC0(uint64 instruction, Dis_info *info)
10357 {
10358     uint64 rt_value = extract_rt_25_24_23_22_21(instruction);
10359     uint64 c0s_value = extract_c0s_20_19_18_17_16(instruction);
10360     uint64 sel_value = extract_sel_15_14_13_12_11(instruction);
10361 
10362     const char *rt = GPR(rt_value, info);
10363 
10364     return img_format("MTC0 %s, CP%" PRIu64 ", 0x%" PRIx64,
10365                       rt, c0s_value, sel_value);
10366 }
10367 
10368 
10369 /*
10370  * ADDQH_R.W rd, rt, rs - Add Fractional Words And Shift Right to Halve Results
10371  *
10372  *   3         2         1
10373  *  10987654321098765432109876543210
10374  *  001000               00010001101
10375  *     rt -----
10376  *          rs -----
10377  *               rd -----
10378  */
10379 static char *MTC1(uint64 instruction, Dis_info *info)
10380 {
10381     uint64 rt_value = extract_rt_25_24_23_22_21(instruction);
10382     uint64 fs_value = extract_fs_20_19_18_17_16(instruction);
10383 
10384     const char *rt = GPR(rt_value, info);
10385     const char *fs = FPR(fs_value, info);
10386 
10387     return img_format("MTC1 %s, %s", rt, fs);
10388 }
10389 
10390 
10391 /*
10392  * ADDQH_R.W rd, rt, rs - Add Fractional Words And Shift Right to Halve Results
10393  *
10394  *   3         2         1
10395  *  10987654321098765432109876543210
10396  *  001000               00010001101
10397  *     rt -----
10398  *          rs -----
10399  *               rd -----
10400  */
10401 static char *MTC2(uint64 instruction, Dis_info *info)
10402 {
10403     uint64 rt_value = extract_rt_25_24_23_22_21(instruction);
10404     uint64 cs_value = extract_cs_20_19_18_17_16(instruction);
10405 
10406     const char *rt = GPR(rt_value, info);
10407 
10408     return img_format("MTC2 %s, CP%" PRIu64, rt, cs_value);
10409 }
10410 
10411 
10412 /*
10413  * ADDQH_R.W rd, rt, rs - Add Fractional Words And Shift Right to Halve Results
10414  *
10415  *   3         2         1
10416  *  10987654321098765432109876543210
10417  *  001000               00010001101
10418  *     rt -----
10419  *          rs -----
10420  *               rd -----
10421  */
10422 static char *MTGC0(uint64 instruction, Dis_info *info)
10423 {
10424     uint64 rt_value = extract_rt_25_24_23_22_21(instruction);
10425     uint64 c0s_value = extract_c0s_20_19_18_17_16(instruction);
10426     uint64 sel_value = extract_sel_15_14_13_12_11(instruction);
10427 
10428     const char *rt = GPR(rt_value, info);
10429 
10430     return img_format("MTGC0 %s, CP%" PRIu64 ", 0x%" PRIx64,
10431                       rt, c0s_value, sel_value);
10432 }
10433 
10434 
10435 /*
10436  * ADDQH_R.W rd, rt, rs - Add Fractional Words And Shift Right to Halve Results
10437  *
10438  *   3         2         1
10439  *  10987654321098765432109876543210
10440  *  001000               00010001101
10441  *     rt -----
10442  *          rs -----
10443  *               rd -----
10444  */
10445 static char *MTHC0(uint64 instruction, Dis_info *info)
10446 {
10447     uint64 rt_value = extract_rt_25_24_23_22_21(instruction);
10448     uint64 c0s_value = extract_c0s_20_19_18_17_16(instruction);
10449     uint64 sel_value = extract_sel_15_14_13_12_11(instruction);
10450 
10451     const char *rt = GPR(rt_value, info);
10452 
10453     return img_format("MTHC0 %s, CP%" PRIu64 ", 0x%" PRIx64,
10454                       rt, c0s_value, sel_value);
10455 }
10456 
10457 
10458 /*
10459  * ADDQH_R.W rd, rt, rs - Add Fractional Words And Shift Right to Halve Results
10460  *
10461  *   3         2         1
10462  *  10987654321098765432109876543210
10463  *  001000               00010001101
10464  *     rt -----
10465  *          rs -----
10466  *               rd -----
10467  */
10468 static char *MTHC1(uint64 instruction, Dis_info *info)
10469 {
10470     uint64 rt_value = extract_rt_25_24_23_22_21(instruction);
10471     uint64 fs_value = extract_fs_20_19_18_17_16(instruction);
10472 
10473     const char *rt = GPR(rt_value, info);
10474     const char *fs = FPR(fs_value, info);
10475 
10476     return img_format("MTHC1 %s, %s", rt, fs);
10477 }
10478 
10479 
10480 /*
10481  * ADDQH_R.W rd, rt, rs - Add Fractional Words And Shift Right to Halve Results
10482  *
10483  *   3         2         1
10484  *  10987654321098765432109876543210
10485  *  001000               00010001101
10486  *     rt -----
10487  *          rs -----
10488  *               rd -----
10489  */
10490 static char *MTHC2(uint64 instruction, Dis_info *info)
10491 {
10492     uint64 rt_value = extract_rt_25_24_23_22_21(instruction);
10493     uint64 cs_value = extract_cs_20_19_18_17_16(instruction);
10494 
10495     const char *rt = GPR(rt_value, info);
10496 
10497     return img_format("MTHC2 %s, CP%" PRIu64, rt, cs_value);
10498 }
10499 
10500 
10501 /*
10502  * ADDQH_R.W rd, rt, rs - Add Fractional Words And Shift Right to Halve Results
10503  *
10504  *   3         2         1
10505  *  10987654321098765432109876543210
10506  *  001000               00010001101
10507  *     rt -----
10508  *          rs -----
10509  *               rd -----
10510  */
10511 static char *MTHGC0(uint64 instruction, Dis_info *info)
10512 {
10513     uint64 rt_value = extract_rt_25_24_23_22_21(instruction);
10514     uint64 c0s_value = extract_c0s_20_19_18_17_16(instruction);
10515     uint64 sel_value = extract_sel_15_14_13_12_11(instruction);
10516 
10517     const char *rt = GPR(rt_value, info);
10518 
10519     return img_format("MTHGC0 %s, CP%" PRIu64 ", 0x%" PRIx64,
10520                       rt, c0s_value, sel_value);
10521 }
10522 
10523 
10524 /*
10525  * [DSP] MTHI rs, ac - Move to HI register
10526  *
10527  *   3         2         1
10528  *  10987654321098765432109876543210
10529  *  001000xxxxx       10000001111111
10530  *          rs -----
10531  *               ac --
10532  */
10533 static char *MTHI_DSP_(uint64 instruction, Dis_info *info)
10534 {
10535     uint64 rs_value = extract_rs_20_19_18_17_16(instruction);
10536     uint64 ac_value = extract_ac_15_14(instruction);
10537 
10538     const char *rs = GPR(rs_value, info);
10539     const char *ac = AC(ac_value, info);
10540 
10541     return img_format("MTHI %s, %s", rs, ac);
10542 }
10543 
10544 
10545 /*
10546  * [DSP] MTHLIP rs, ac - Copy LO to HI and a GPR to LO and increment pos by 32
10547  *
10548  *   3         2         1
10549  *  10987654321098765432109876543210
10550  *  001000xxxxx       00001001111111
10551  *          rs -----
10552  *               ac --
10553  */
10554 static char *MTHLIP(uint64 instruction, Dis_info *info)
10555 {
10556     uint64 rs_value = extract_rs_20_19_18_17_16(instruction);
10557     uint64 ac_value = extract_ac_15_14(instruction);
10558 
10559     const char *rs = GPR(rs_value, info);
10560     const char *ac = AC(ac_value, info);
10561 
10562     return img_format("MTHLIP %s, %s", rs, ac);
10563 }
10564 
10565 
10566 /*
10567  * ADDQH_R.W rd, rt, rs - Add Fractional Words And Shift Right to Halve Results
10568  *
10569  *   3         2         1
10570  *  10987654321098765432109876543210
10571  *  001000               00010001101
10572  *     rt -----
10573  *          rs -----
10574  *               rd -----
10575  */
10576 static char *MTHTR(uint64 instruction, Dis_info *info)
10577 {
10578     uint64 rt_value = extract_rt_25_24_23_22_21(instruction);
10579     uint64 c0s_value = extract_c0s_20_19_18_17_16(instruction);
10580     uint64 sel_value = extract_sel_15_14_13_12_11(instruction);
10581     uint64 u_value = extract_u_10(instruction);
10582 
10583     const char *rt = GPR(rt_value, info);
10584 
10585     return img_format("MTHTR %s, 0x%" PRIx64 ", 0x%" PRIx64 ", 0x%" PRIx64,
10586                       rt, c0s_value, u_value, sel_value);
10587 }
10588 
10589 
10590 /*
10591  * [DSP] MTLO rs, ac - Move to LO register
10592  *
10593  *   3         2         1
10594  *  10987654321098765432109876543210
10595  *  001000xxxxx       11000001111111
10596  *          rs -----
10597  *               ac --
10598  */
10599 static char *MTLO_DSP_(uint64 instruction, Dis_info *info)
10600 {
10601     uint64 rs_value = extract_rs_20_19_18_17_16(instruction);
10602     uint64 ac_value = extract_ac_15_14(instruction);
10603 
10604     const char *rs = GPR(rs_value, info);
10605     const char *ac = AC(ac_value, info);
10606 
10607     return img_format("MTLO %s, %s", rs, ac);
10608 }
10609 
10610 
10611 /*
10612  * ADDQH_R.W rd, rt, rs - Add Fractional Words And Shift Right to Halve Results
10613  *
10614  *   3         2         1
10615  *  10987654321098765432109876543210
10616  *  001000               00010001101
10617  *     rt -----
10618  *          rs -----
10619  *               rd -----
10620  */
10621 static char *MTTR(uint64 instruction, Dis_info *info)
10622 {
10623     uint64 rt_value = extract_rt_25_24_23_22_21(instruction);
10624     uint64 c0s_value = extract_c0s_20_19_18_17_16(instruction);
10625     uint64 sel_value = extract_sel_15_14_13_12_11(instruction);
10626     uint64 u_value = extract_u_10(instruction);
10627 
10628     const char *rt = GPR(rt_value, info);
10629 
10630     return img_format("MTTR %s, 0x%" PRIx64 ", 0x%" PRIx64 ", 0x%" PRIx64,
10631                       rt, c0s_value, u_value, sel_value);
10632 }
10633 
10634 
10635 /*
10636  * ADDQH_R.W rd, rt, rs - Add Fractional Words And Shift Right to Halve Results
10637  *
10638  *   3         2         1
10639  *  10987654321098765432109876543210
10640  *  001000               00010001101
10641  *     rt -----
10642  *          rs -----
10643  *               rd -----
10644  */
10645 static char *MUH(uint64 instruction, Dis_info *info)
10646 {
10647     uint64 rt_value = extract_rt_25_24_23_22_21(instruction);
10648     uint64 rs_value = extract_rs_20_19_18_17_16(instruction);
10649     uint64 rd_value = extract_rd_15_14_13_12_11(instruction);
10650 
10651     const char *rd = GPR(rd_value, info);
10652     const char *rs = GPR(rs_value, info);
10653     const char *rt = GPR(rt_value, info);
10654 
10655     return img_format("MUH %s, %s, %s", rd, rs, rt);
10656 }
10657 
10658 
10659 /*
10660  * ADDQH_R.W rd, rt, rs - Add Fractional Words And Shift Right to Halve Results
10661  *
10662  *   3         2         1
10663  *  10987654321098765432109876543210
10664  *  001000               00010001101
10665  *     rt -----
10666  *          rs -----
10667  *               rd -----
10668  */
10669 static char *MUHU(uint64 instruction, Dis_info *info)
10670 {
10671     uint64 rt_value = extract_rt_25_24_23_22_21(instruction);
10672     uint64 rs_value = extract_rs_20_19_18_17_16(instruction);
10673     uint64 rd_value = extract_rd_15_14_13_12_11(instruction);
10674 
10675     const char *rd = GPR(rd_value, info);
10676     const char *rs = GPR(rs_value, info);
10677     const char *rt = GPR(rt_value, info);
10678 
10679     return img_format("MUHU %s, %s, %s", rd, rs, rt);
10680 }
10681 
10682 
10683 /*
10684  * ADDQH_R.W rd, rt, rs - Add Fractional Words And Shift Right to Halve Results
10685  *
10686  *   3         2         1
10687  *  10987654321098765432109876543210
10688  *  001000               00010001101
10689  *     rt -----
10690  *          rs -----
10691  *               rd -----
10692  */
10693 static char *MUL_32_(uint64 instruction, Dis_info *info)
10694 {
10695     uint64 rt_value = extract_rt_25_24_23_22_21(instruction);
10696     uint64 rs_value = extract_rs_20_19_18_17_16(instruction);
10697     uint64 rd_value = extract_rd_15_14_13_12_11(instruction);
10698 
10699     const char *rd = GPR(rd_value, info);
10700     const char *rs = GPR(rs_value, info);
10701     const char *rt = GPR(rt_value, info);
10702 
10703     return img_format("MUL %s, %s, %s", rd, rs, rt);
10704 }
10705 
10706 
10707 /*
10708  * ADDQH_R.W rd, rt, rs - Add Fractional Words And Shift Right to Halve Results
10709  *
10710  *   3         2         1
10711  *  10987654321098765432109876543210
10712  *  001000               00010001101
10713  *     rt -----
10714  *          rs -----
10715  *               rd -----
10716  */
10717 static char *MUL_4X4_(uint64 instruction, Dis_info *info)
10718 {
10719     uint64 rt4_value = extract_rt4_9_7_6_5(instruction);
10720     uint64 rs4_value = extract_rs4_4_2_1_0(instruction);
10721 
10722     const char *rs4 = GPR(decode_gpr_gpr4(rs4_value, info), info);
10723     const char *rt4 = GPR(decode_gpr_gpr4(rt4_value, info), info);
10724 
10725     return img_format("MUL %s, %s", rs4, rt4);
10726 }
10727 
10728 
10729 /*
10730  * ADDQH_R.W rd, rt, rs - Add Fractional Words And Shift Right to Halve Results
10731  *
10732  *   3         2         1
10733  *  10987654321098765432109876543210
10734  *  001000               00010001101
10735  *     rt -----
10736  *          rs -----
10737  *               rd -----
10738  */
10739 static char *MUL_D(uint64 instruction, Dis_info *info)
10740 {
10741     uint64 ft_value = extract_ft_25_24_23_22_21(instruction);
10742     uint64 fs_value = extract_fs_20_19_18_17_16(instruction);
10743     uint64 fd_value = extract_fd_15_14_13_12_11(instruction);
10744 
10745     const char *fd = FPR(fd_value, info);
10746     const char *fs = FPR(fs_value, info);
10747     const char *ft = FPR(ft_value, info);
10748 
10749     return img_format("MUL.D %s, %s, %s", fd, fs, ft);
10750 }
10751 
10752 
10753 /*
10754  * [DSP] MUL.PH rd, rs, rt - Multiply vector integer half words to same size
10755  *   products
10756  *
10757  *   3         2         1
10758  *  10987654321098765432109876543210
10759  *  001000               00000101101
10760  *     rt -----
10761  *          rs -----
10762  *               rd -----
10763  */
10764 static char *MUL_PH(uint64 instruction, Dis_info *info)
10765 {
10766     uint64 rt_value = extract_rt_25_24_23_22_21(instruction);
10767     uint64 rs_value = extract_rs_20_19_18_17_16(instruction);
10768     uint64 rd_value = extract_rd_15_14_13_12_11(instruction);
10769 
10770     const char *rd = GPR(rd_value, info);
10771     const char *rs = GPR(rs_value, info);
10772     const char *rt = GPR(rt_value, info);
10773 
10774     return img_format("MUL.PH %s, %s, %s", rd, rs, rt);
10775 }
10776 
10777 
10778 /*
10779  * [DSP] MUL_S.PH rd, rs, rt - Multiply vector integer half words to same size
10780  *   products (saturated)
10781  *
10782  *   3         2         1
10783  *  10987654321098765432109876543210
10784  *  001000               10000101101
10785  *     rt -----
10786  *          rs -----
10787  *               rd -----
10788  */
10789 static char *MUL_S_PH(uint64 instruction, Dis_info *info)
10790 {
10791     uint64 rt_value = extract_rt_25_24_23_22_21(instruction);
10792     uint64 rs_value = extract_rs_20_19_18_17_16(instruction);
10793     uint64 rd_value = extract_rd_15_14_13_12_11(instruction);
10794 
10795     const char *rd = GPR(rd_value, info);
10796     const char *rs = GPR(rs_value, info);
10797     const char *rt = GPR(rt_value, info);
10798 
10799     return img_format("MUL_S.PH %s, %s, %s", rd, rs, rt);
10800 }
10801 
10802 
10803 /*
10804  * ADDQH_R.W rd, rt, rs - Add Fractional Words And Shift Right to Halve Results
10805  *
10806  *   3         2         1
10807  *  10987654321098765432109876543210
10808  *  001000               00010001101
10809  *     rt -----
10810  *          rs -----
10811  *               rd -----
10812  */
10813 static char *MUL_S(uint64 instruction, Dis_info *info)
10814 {
10815     uint64 ft_value = extract_ft_25_24_23_22_21(instruction);
10816     uint64 fs_value = extract_fs_20_19_18_17_16(instruction);
10817     uint64 fd_value = extract_fd_15_14_13_12_11(instruction);
10818 
10819     const char *fd = FPR(fd_value, info);
10820     const char *fs = FPR(fs_value, info);
10821     const char *ft = FPR(ft_value, info);
10822 
10823     return img_format("MUL.S %s, %s, %s", fd, fs, ft);
10824 }
10825 
10826 
10827 /*
10828  * [DSP] MULEQ_S.W.PHL rd, rs, rt - Multiply vector fractional left halfwords
10829  *   to expanded width products
10830  *
10831  *   3         2         1
10832  *  10987654321098765432109876543210
10833  *  001000               x0000100101
10834  *     rt -----
10835  *          rs -----
10836  *               rd -----
10837  */
10838 static char *MULEQ_S_W_PHL(uint64 instruction, Dis_info *info)
10839 {
10840     uint64 rt_value = extract_rt_25_24_23_22_21(instruction);
10841     uint64 rs_value = extract_rs_20_19_18_17_16(instruction);
10842     uint64 rd_value = extract_rd_15_14_13_12_11(instruction);
10843 
10844     const char *rd = GPR(rd_value, info);
10845     const char *rs = GPR(rs_value, info);
10846     const char *rt = GPR(rt_value, info);
10847 
10848     return img_format("MULEQ_S.W.PHL %s, %s, %s", rd, rs, rt);
10849 }
10850 
10851 
10852 /*
10853  * [DSP] MULEQ_S.W.PHR rd, rs, rt - Multiply vector fractional right halfwords
10854  *   to expanded width products
10855  *
10856  *   3         2         1
10857  *  10987654321098765432109876543210
10858  *  001000               x0001100101
10859  *     rt -----
10860  *          rs -----
10861  *               rd -----
10862  */
10863 static char *MULEQ_S_W_PHR(uint64 instruction, Dis_info *info)
10864 {
10865     uint64 rt_value = extract_rt_25_24_23_22_21(instruction);
10866     uint64 rs_value = extract_rs_20_19_18_17_16(instruction);
10867     uint64 rd_value = extract_rd_15_14_13_12_11(instruction);
10868 
10869     const char *rd = GPR(rd_value, info);
10870     const char *rs = GPR(rs_value, info);
10871     const char *rt = GPR(rt_value, info);
10872 
10873     return img_format("MULEQ_S.W.PHR %s, %s, %s", rd, rs, rt);
10874 }
10875 
10876 
10877 /*
10878  * [DSP] MULEU_S.PH.QBL rd, rs, rt - Multiply vector fractional left bytes
10879  *   by halfwords to halfword products
10880  *
10881  *   3         2         1
10882  *  10987654321098765432109876543210
10883  *  001000               x0010010101
10884  *     rt -----
10885  *          rs -----
10886  *               rd -----
10887  */
10888 static char *MULEU_S_PH_QBL(uint64 instruction, Dis_info *info)
10889 {
10890     uint64 rt_value = extract_rt_25_24_23_22_21(instruction);
10891     uint64 rs_value = extract_rs_20_19_18_17_16(instruction);
10892     uint64 rd_value = extract_rd_15_14_13_12_11(instruction);
10893 
10894     const char *rd = GPR(rd_value, info);
10895     const char *rs = GPR(rs_value, info);
10896     const char *rt = GPR(rt_value, info);
10897 
10898     return img_format("MULEU_S.PH.QBL %s, %s, %s", rd, rs, rt);
10899 }
10900 
10901 
10902 /*
10903  * [DSP] MULEU_S.PH.QBR rd, rs, rt - Multiply vector fractional right bytes
10904  *   by halfwords to halfword products
10905  *
10906  *   3         2         1
10907  *  10987654321098765432109876543210
10908  *  001000               x0011010101
10909  *     rt -----
10910  *          rs -----
10911  *               rd -----
10912  */
10913 static char *MULEU_S_PH_QBR(uint64 instruction, Dis_info *info)
10914 {
10915     uint64 rt_value = extract_rt_25_24_23_22_21(instruction);
10916     uint64 rs_value = extract_rs_20_19_18_17_16(instruction);
10917     uint64 rd_value = extract_rd_15_14_13_12_11(instruction);
10918 
10919     const char *rd = GPR(rd_value, info);
10920     const char *rs = GPR(rs_value, info);
10921     const char *rt = GPR(rt_value, info);
10922 
10923     return img_format("MULEU_S.PH.QBR %s, %s, %s", rd, rs, rt);
10924 }
10925 
10926 
10927 /*
10928  * [DSP] MULQ_RS.PH rd, rs, rt - Multiply vector fractional halfwords
10929  *   to fractional halfword products
10930  *
10931  *   3         2         1
10932  *  10987654321098765432109876543210
10933  *  001000               x0100010101
10934  *     rt -----
10935  *          rs -----
10936  *               rd -----
10937  */
10938 static char *MULQ_RS_PH(uint64 instruction, Dis_info *info)
10939 {
10940     uint64 rt_value = extract_rt_25_24_23_22_21(instruction);
10941     uint64 rs_value = extract_rs_20_19_18_17_16(instruction);
10942     uint64 rd_value = extract_rd_15_14_13_12_11(instruction);
10943 
10944     const char *rd = GPR(rd_value, info);
10945     const char *rs = GPR(rs_value, info);
10946     const char *rt = GPR(rt_value, info);
10947 
10948     return img_format("MULQ_RS.PH %s, %s, %s", rd, rs, rt);
10949 }
10950 
10951 
10952 /*
10953  * [DSP] MULQ_RS.W rd, rs, rt - Multiply fractional words to same size
10954  *   product with saturation and rounding
10955  *
10956  *   3         2         1
10957  *  10987654321098765432109876543210
10958  *  001000               x0110010101
10959  *     rt -----
10960  *          rs -----
10961  *               rd -----
10962  */
10963 static char *MULQ_RS_W(uint64 instruction, Dis_info *info)
10964 {
10965     uint64 rt_value = extract_rt_25_24_23_22_21(instruction);
10966     uint64 rs_value = extract_rs_20_19_18_17_16(instruction);
10967     uint64 rd_value = extract_rd_15_14_13_12_11(instruction);
10968 
10969     const char *rd = GPR(rd_value, info);
10970     const char *rs = GPR(rs_value, info);
10971     const char *rt = GPR(rt_value, info);
10972 
10973     return img_format("MULQ_RS.W %s, %s, %s", rd, rs, rt);
10974 }
10975 
10976 
10977 /*
10978  * [DSP] MULQ_S.PH rd, rs, rt - Multiply fractional halfwords to same size
10979  *   products
10980  *
10981  *   3         2         1
10982  *  10987654321098765432109876543210
10983  *  001000               x0101010101
10984  *     rt -----
10985  *          rs -----
10986  *               rd -----
10987  */
10988 static char *MULQ_S_PH(uint64 instruction, Dis_info *info)
10989 {
10990     uint64 rt_value = extract_rt_25_24_23_22_21(instruction);
10991     uint64 rs_value = extract_rs_20_19_18_17_16(instruction);
10992     uint64 rd_value = extract_rd_15_14_13_12_11(instruction);
10993 
10994     const char *rd = GPR(rd_value, info);
10995     const char *rs = GPR(rs_value, info);
10996     const char *rt = GPR(rt_value, info);
10997 
10998     return img_format("MULQ_S.PH %s, %s, %s", rd, rs, rt);
10999 }
11000 
11001 
11002 /*
11003  * [DSP] MULQ_S.W rd, rs, rt - Multiply fractional words to same size product
11004  *   with saturation
11005  *
11006  *   3         2         1
11007  *  10987654321098765432109876543210
11008  *  001000               x0111010101
11009  *     rt -----
11010  *          rs -----
11011  *               rd -----
11012  */
11013 static char *MULQ_S_W(uint64 instruction, Dis_info *info)
11014 {
11015     uint64 rt_value = extract_rt_25_24_23_22_21(instruction);
11016     uint64 rs_value = extract_rs_20_19_18_17_16(instruction);
11017     uint64 rd_value = extract_rd_15_14_13_12_11(instruction);
11018 
11019     const char *rd = GPR(rd_value, info);
11020     const char *rs = GPR(rs_value, info);
11021     const char *rt = GPR(rt_value, info);
11022 
11023     return img_format("MULQ_S.W %s, %s, %s", rd, rs, rt);
11024 }
11025 
11026 
11027 /*
11028  * [DSP] MULSA.W.PH ac, rs, rt - Multiply and subtract vector integer halfword
11029  *   elements and accumulate
11030  *
11031  *   3         2         1
11032  *  10987654321098765432109876543210
11033  *  001000            10110010111111
11034  *     rt -----
11035  *          rs -----
11036  *               ac --
11037  */
11038 static char *MULSA_W_PH(uint64 instruction, Dis_info *info)
11039 {
11040     uint64 rt_value = extract_rt_25_24_23_22_21(instruction);
11041     uint64 rs_value = extract_rs_20_19_18_17_16(instruction);
11042     uint64 ac_value = extract_ac_15_14(instruction);
11043 
11044     const char *ac = AC(ac_value, info);
11045     const char *rs = GPR(rs_value, info);
11046     const char *rt = GPR(rt_value, info);
11047 
11048     return img_format("MULSA.W.PH %s, %s, %s", ac, rs, rt);
11049 }
11050 
11051 
11052 /*
11053  * [DSP] MULSAQ_S.W.PH ac, rs, rt - Multiply and subtract vector fractional
11054  *   halfwords and accumulate
11055  *
11056  *   3         2         1
11057  *  10987654321098765432109876543210
11058  *  001000            11110010111111
11059  *     rt -----
11060  *          rs -----
11061  *               ac --
11062  */
11063 static char *MULSAQ_S_W_PH(uint64 instruction, Dis_info *info)
11064 {
11065     uint64 rt_value = extract_rt_25_24_23_22_21(instruction);
11066     uint64 rs_value = extract_rs_20_19_18_17_16(instruction);
11067     uint64 ac_value = extract_ac_15_14(instruction);
11068 
11069     const char *ac = AC(ac_value, info);
11070     const char *rs = GPR(rs_value, info);
11071     const char *rt = GPR(rt_value, info);
11072 
11073     return img_format("MULSAQ_S.W.PH %s, %s, %s", ac, rs, rt);
11074 }
11075 
11076 
11077 /*
11078  * [DSP] MULT ac, rs, rt - Multiply word
11079  *
11080  *   3         2         1
11081  *  10987654321098765432109876543210
11082  *  001000            00110010111111
11083  *     rt -----
11084  *          rs -----
11085  *               ac --
11086  */
11087 static char *MULT_DSP_(uint64 instruction, Dis_info *info)
11088 {
11089     uint64 rt_value = extract_rt_25_24_23_22_21(instruction);
11090     uint64 rs_value = extract_rs_20_19_18_17_16(instruction);
11091     uint64 ac_value = extract_ac_15_14(instruction);
11092 
11093     const char *ac = AC(ac_value, info);
11094     const char *rs = GPR(rs_value, info);
11095     const char *rt = GPR(rt_value, info);
11096 
11097     return img_format("MULT %s, %s, %s", ac, rs, rt);
11098 }
11099 
11100 
11101 /*
11102  * [DSP] MULTU ac, rs, rt - Multiply unsigned word
11103  *
11104  *   3         2         1
11105  *  10987654321098765432109876543210
11106  *  001000            01110010111111
11107  *     rt -----
11108  *          rs -----
11109  *               ac --
11110  */
11111 static char *MULTU_DSP_(uint64 instruction, Dis_info *info)
11112 {
11113     uint64 rt_value = extract_rt_25_24_23_22_21(instruction);
11114     uint64 rs_value = extract_rs_20_19_18_17_16(instruction);
11115     uint64 ac_value = extract_ac_15_14(instruction);
11116 
11117     const char *ac = AC(ac_value, info);
11118     const char *rs = GPR(rs_value, info);
11119     const char *rt = GPR(rt_value, info);
11120 
11121     return img_format("MULTU %s, %s, %s", ac, rs, rt);
11122 }
11123 
11124 
11125 /*
11126  * ADDQH_R.W rd, rt, rs - Add Fractional Words And Shift Right to Halve Results
11127  *
11128  *   3         2         1
11129  *  10987654321098765432109876543210
11130  *  001000               00010001101
11131  *     rt -----
11132  *          rs -----
11133  *               rd -----
11134  */
11135 static char *MULU(uint64 instruction, Dis_info *info)
11136 {
11137     uint64 rt_value = extract_rt_25_24_23_22_21(instruction);
11138     uint64 rs_value = extract_rs_20_19_18_17_16(instruction);
11139     uint64 rd_value = extract_rd_15_14_13_12_11(instruction);
11140 
11141     const char *rd = GPR(rd_value, info);
11142     const char *rs = GPR(rs_value, info);
11143     const char *rt = GPR(rt_value, info);
11144 
11145     return img_format("MULU %s, %s, %s", rd, rs, rt);
11146 }
11147 
11148 
11149 /*
11150  * ADDQH_R.W rd, rt, rs - Add Fractional Words And Shift Right to Halve Results
11151  *
11152  *   3         2         1
11153  *  10987654321098765432109876543210
11154  *  001000               00010001101
11155  *     rt -----
11156  *          rs -----
11157  *               rd -----
11158  */
11159 static char *NEG_D(uint64 instruction, Dis_info *info)
11160 {
11161     uint64 ft_value = extract_ft_25_24_23_22_21(instruction);
11162     uint64 fs_value = extract_fs_20_19_18_17_16(instruction);
11163 
11164     const char *ft = FPR(ft_value, info);
11165     const char *fs = FPR(fs_value, info);
11166 
11167     return img_format("NEG.D %s, %s", ft, fs);
11168 }
11169 
11170 
11171 /*
11172  * ADDQH_R.W rd, rt, rs - Add Fractional Words And Shift Right to Halve Results
11173  *
11174  *   3         2         1
11175  *  10987654321098765432109876543210
11176  *  001000               00010001101
11177  *     rt -----
11178  *          rs -----
11179  *               rd -----
11180  */
11181 static char *NEG_S(uint64 instruction, Dis_info *info)
11182 {
11183     uint64 ft_value = extract_ft_25_24_23_22_21(instruction);
11184     uint64 fs_value = extract_fs_20_19_18_17_16(instruction);
11185 
11186     const char *ft = FPR(ft_value, info);
11187     const char *fs = FPR(fs_value, info);
11188 
11189     return img_format("NEG.S %s, %s", ft, fs);
11190 }
11191 
11192 
11193 /*
11194  * ADDQH_R.W rd, rt, rs - Add Fractional Words And Shift Right to Halve Results
11195  *
11196  *   3         2         1
11197  *  10987654321098765432109876543210
11198  *  001000               00010001101
11199  *     rt -----
11200  *          rs -----
11201  *               rd -----
11202  */
11203 static char *NOP_16_(uint64 instruction, Dis_info *info)
11204 {
11205     (void)instruction;
11206 
11207     return g_strdup("NOP ");
11208 }
11209 
11210 
11211 /*
11212  * ADDQH_R.W rd, rt, rs - Add Fractional Words And Shift Right to Halve Results
11213  *
11214  *   3         2         1
11215  *  10987654321098765432109876543210
11216  *  001000               00010001101
11217  *     rt -----
11218  *          rs -----
11219  *               rd -----
11220  */
11221 static char *NOP_32_(uint64 instruction, Dis_info *info)
11222 {
11223     (void)instruction;
11224 
11225     return g_strdup("NOP ");
11226 }
11227 
11228 
11229 /*
11230  * ADDQH_R.W rd, rt, rs - Add Fractional Words And Shift Right to Halve Results
11231  *
11232  *   3         2         1
11233  *  10987654321098765432109876543210
11234  *  001000               00010001101
11235  *     rt -----
11236  *          rs -----
11237  *               rd -----
11238  */
11239 static char *NOR(uint64 instruction, Dis_info *info)
11240 {
11241     uint64 rt_value = extract_rt_25_24_23_22_21(instruction);
11242     uint64 rs_value = extract_rs_20_19_18_17_16(instruction);
11243     uint64 rd_value = extract_rd_15_14_13_12_11(instruction);
11244 
11245     const char *rd = GPR(rd_value, info);
11246     const char *rs = GPR(rs_value, info);
11247     const char *rt = GPR(rt_value, info);
11248 
11249     return img_format("NOR %s, %s, %s", rd, rs, rt);
11250 }
11251 
11252 
11253 /*
11254  * ADDQH_R.W rd, rt, rs - Add Fractional Words And Shift Right to Halve Results
11255  *
11256  *   3         2         1
11257  *  10987654321098765432109876543210
11258  *  001000               00010001101
11259  *     rt -----
11260  *          rs -----
11261  *               rd -----
11262  */
11263 static char *NOT_16_(uint64 instruction, Dis_info *info)
11264 {
11265     uint64 rt3_value = extract_rt3_9_8_7(instruction);
11266     uint64 rs3_value = extract_rs3_6_5_4(instruction);
11267 
11268     const char *rt3 = GPR(decode_gpr_gpr3(rt3_value, info), info);
11269     const char *rs3 = GPR(decode_gpr_gpr3(rs3_value, info), info);
11270 
11271     return img_format("NOT %s, %s", rt3, rs3);
11272 }
11273 
11274 
11275 /*
11276  * ADDQH_R.W rd, rt, rs - Add Fractional Words And Shift Right to Halve Results
11277  *
11278  *   3         2         1
11279  *  10987654321098765432109876543210
11280  *  001000               00010001101
11281  *     rt -----
11282  *          rs -----
11283  *               rd -----
11284  */
11285 static char *OR_16_(uint64 instruction, Dis_info *info)
11286 {
11287     uint64 rt3_value = extract_rt3_9_8_7(instruction);
11288     uint64 rs3_value = extract_rs3_6_5_4(instruction);
11289 
11290     const char *rs3 = GPR(decode_gpr_gpr3(rs3_value, info), info);
11291     const char *rt3 = GPR(decode_gpr_gpr3(rt3_value, info), info);
11292 
11293     return img_format("OR %s, %s", rs3, rt3);
11294 }
11295 
11296 
11297 /*
11298  * ADDQH_R.W rd, rt, rs - Add Fractional Words And Shift Right to Halve Results
11299  *
11300  *   3         2         1
11301  *  10987654321098765432109876543210
11302  *  001000               00010001101
11303  *     rt -----
11304  *          rs -----
11305  *               rd -----
11306  */
11307 static char *OR_32_(uint64 instruction, Dis_info *info)
11308 {
11309     uint64 rt_value = extract_rt_25_24_23_22_21(instruction);
11310     uint64 rs_value = extract_rs_20_19_18_17_16(instruction);
11311     uint64 rd_value = extract_rd_15_14_13_12_11(instruction);
11312 
11313     const char *rd = GPR(rd_value, info);
11314     const char *rs = GPR(rs_value, info);
11315     const char *rt = GPR(rt_value, info);
11316 
11317     return img_format("OR %s, %s, %s", rd, rs, rt);
11318 }
11319 
11320 
11321 /*
11322  * ADDQH_R.W rd, rt, rs - Add Fractional Words And Shift Right to Halve Results
11323  *
11324  *   3         2         1
11325  *  10987654321098765432109876543210
11326  *  001000               00010001101
11327  *     rt -----
11328  *          rs -----
11329  *               rd -----
11330  */
11331 static char *ORI(uint64 instruction, Dis_info *info)
11332 {
11333     uint64 rt_value = extract_rt_25_24_23_22_21(instruction);
11334     uint64 rs_value = extract_rs_20_19_18_17_16(instruction);
11335     uint64 u_value = extract_u_11_10_9_8_7_6_5_4_3_2_1_0(instruction);
11336 
11337     const char *rt = GPR(rt_value, info);
11338     const char *rs = GPR(rs_value, info);
11339 
11340     return img_format("ORI %s, %s, 0x%" PRIx64, rt, rs, u_value);
11341 }
11342 
11343 
11344 /*
11345  * [DSP] PACKRL.PH rd, rs, rt - Pack a word using the right halfword from one
11346  *         source register and left halfword from another source register
11347  *
11348  *   3         2         1
11349  *  10987654321098765432109876543210
11350  *  001000               00010001101
11351  *     rt -----
11352  *          rs -----
11353  *               rd -----
11354  */
11355 static char *PACKRL_PH(uint64 instruction, Dis_info *info)
11356 {
11357     uint64 rt_value = extract_rt_25_24_23_22_21(instruction);
11358     uint64 rs_value = extract_rs_20_19_18_17_16(instruction);
11359     uint64 rd_value = extract_rd_15_14_13_12_11(instruction);
11360 
11361     const char *rd = GPR(rd_value, info);
11362     const char *rs = GPR(rs_value, info);
11363     const char *rt = GPR(rt_value, info);
11364 
11365     return img_format("PACKRL.PH %s, %s, %s", rd, rs, rt);
11366 }
11367 
11368 
11369 /*
11370  * ADDQH_R.W rd, rt, rs - Add Fractional Words And Shift Right to Halve Results
11371  *
11372  *   3         2         1
11373  *  10987654321098765432109876543210
11374  *  001000               00010001101
11375  *     rt -----
11376  *          rs -----
11377  *               rd -----
11378  */
11379 static char *PAUSE(uint64 instruction, Dis_info *info)
11380 {
11381     (void)instruction;
11382 
11383     return g_strdup("PAUSE ");
11384 }
11385 
11386 
11387 /*
11388  * [DSP] PICK.PH rd, rs, rt - Pick a vector of halfwords based on condition
11389  *         code bits
11390  *
11391  *   3         2         1
11392  *  10987654321098765432109876543210
11393  *  001000               00010001101
11394  *     rt -----
11395  *          rs -----
11396  *               rd -----
11397  */
11398 static char *PICK_PH(uint64 instruction, Dis_info *info)
11399 {
11400     uint64 rt_value = extract_rt_25_24_23_22_21(instruction);
11401     uint64 rs_value = extract_rs_20_19_18_17_16(instruction);
11402     uint64 rd_value = extract_rd_15_14_13_12_11(instruction);
11403 
11404     const char *rd = GPR(rd_value, info);
11405     const char *rs = GPR(rs_value, info);
11406     const char *rt = GPR(rt_value, info);
11407 
11408     return img_format("PICK.PH %s, %s, %s", rd, rs, rt);
11409 }
11410 
11411 
11412 /*
11413  * [DSP] PICK.QB rd, rs, rt - Pick a vector of byte values based on condition
11414  *         code bits
11415  *
11416  *   3         2         1
11417  *  10987654321098765432109876543210
11418  *  001000               00010001101
11419  *     rt -----
11420  *          rs -----
11421  *               rd -----
11422  */
11423 static char *PICK_QB(uint64 instruction, Dis_info *info)
11424 {
11425     uint64 rt_value = extract_rt_25_24_23_22_21(instruction);
11426     uint64 rs_value = extract_rs_20_19_18_17_16(instruction);
11427     uint64 rd_value = extract_rd_15_14_13_12_11(instruction);
11428 
11429     const char *rd = GPR(rd_value, info);
11430     const char *rs = GPR(rs_value, info);
11431     const char *rt = GPR(rt_value, info);
11432 
11433     return img_format("PICK.QB %s, %s, %s", rd, rs, rt);
11434 }
11435 
11436 
11437 /*
11438  * [DSP] PRECEQ.W.PHL rt, rs - Expand the precision of the left-most element
11439  *         of a paired halfword
11440  *
11441  *   3         2         1
11442  *  10987654321098765432109876543210
11443  *  001000               00010001101
11444  *     rt -----
11445  *          rs -----
11446  *               rd -----
11447  */
11448 static char *PRECEQ_W_PHL(uint64 instruction, Dis_info *info)
11449 {
11450     uint64 rt_value = extract_rt_25_24_23_22_21(instruction);
11451     uint64 rs_value = extract_rs_20_19_18_17_16(instruction);
11452 
11453     const char *rt = GPR(rt_value, info);
11454     const char *rs = GPR(rs_value, info);
11455 
11456     return img_format("PRECEQ.W.PHL %s, %s", rt, rs);
11457 }
11458 
11459 
11460 /*
11461  * [DSP] PRECEQ.W.PHR rt, rs - Expand the precision of the right-most element
11462  *         of a paired halfword
11463  *
11464  *   3         2         1
11465  *  10987654321098765432109876543210
11466  *  001000               00010001101
11467  *     rt -----
11468  *          rs -----
11469  *               rd -----
11470  */
11471 static char *PRECEQ_W_PHR(uint64 instruction, Dis_info *info)
11472 {
11473     uint64 rt_value = extract_rt_25_24_23_22_21(instruction);
11474     uint64 rs_value = extract_rs_20_19_18_17_16(instruction);
11475 
11476     const char *rt = GPR(rt_value, info);
11477     const char *rs = GPR(rs_value, info);
11478 
11479     return img_format("PRECEQ.W.PHR %s, %s", rt, rs);
11480 }
11481 
11482 
11483 /*
11484  * [DSP] PRECEQU.PH.QBLA rt, rs - Expand the precision of the two
11485  *         left-alternate elements of a quad byte vector
11486  *
11487  *   3         2         1
11488  *  10987654321098765432109876543210
11489  *  001000               00010001101
11490  *     rt -----
11491  *          rs -----
11492  *               rd -----
11493  */
11494 static char *PRECEQU_PH_QBLA(uint64 instruction, Dis_info *info)
11495 {
11496     uint64 rt_value = extract_rt_25_24_23_22_21(instruction);
11497     uint64 rs_value = extract_rs_20_19_18_17_16(instruction);
11498 
11499     const char *rt = GPR(rt_value, info);
11500     const char *rs = GPR(rs_value, info);
11501 
11502     return img_format("PRECEQU.PH.QBLA %s, %s", rt, rs);
11503 }
11504 
11505 
11506 /*
11507  * [DSP] PRECEQU.PH.QBL rt, rs - Expand the precision of the two left-most
11508  *         elements of a quad byte vector
11509  *
11510  *   3         2         1
11511  *  10987654321098765432109876543210
11512  *  001000               00010001101
11513  *     rt -----
11514  *          rs -----
11515  *               rd -----
11516  */
11517 static char *PRECEQU_PH_QBL(uint64 instruction, Dis_info *info)
11518 {
11519     uint64 rt_value = extract_rt_25_24_23_22_21(instruction);
11520     uint64 rs_value = extract_rs_20_19_18_17_16(instruction);
11521 
11522     const char *rt = GPR(rt_value, info);
11523     const char *rs = GPR(rs_value, info);
11524 
11525     return img_format("PRECEQU.PH.QBL %s, %s", rt, rs);
11526 }
11527 
11528 
11529 /*
11530  * [DSP] PRECEQU.PH.QBRA rt, rs - Expand the precision of the two
11531  *         right-alternate elements of a quad byte vector
11532  *
11533  *   3         2         1
11534  *  10987654321098765432109876543210
11535  *  001000               00010001101
11536  *     rt -----
11537  *          rs -----
11538  *               rd -----
11539  */
11540 static char *PRECEQU_PH_QBRA(uint64 instruction, Dis_info *info)
11541 {
11542     uint64 rt_value = extract_rt_25_24_23_22_21(instruction);
11543     uint64 rs_value = extract_rs_20_19_18_17_16(instruction);
11544 
11545     const char *rt = GPR(rt_value, info);
11546     const char *rs = GPR(rs_value, info);
11547 
11548     return img_format("PRECEQU.PH.QBRA %s, %s", rt, rs);
11549 }
11550 
11551 
11552 /*
11553  * [DSP] PRECEQU.PH.QBR rt, rs - Expand the precision of the two right-most
11554  *         elements of a quad byte vector
11555  *
11556  *   3         2         1
11557  *  10987654321098765432109876543210
11558  *  001000               00010001101
11559  *     rt -----
11560  *          rs -----
11561  *               rd -----
11562  */
11563 static char *PRECEQU_PH_QBR(uint64 instruction, Dis_info *info)
11564 {
11565     uint64 rt_value = extract_rt_25_24_23_22_21(instruction);
11566     uint64 rs_value = extract_rs_20_19_18_17_16(instruction);
11567 
11568     const char *rt = GPR(rt_value, info);
11569     const char *rs = GPR(rs_value, info);
11570 
11571     return img_format("PRECEQU.PH.QBR %s, %s", rt, rs);
11572 }
11573 
11574 
11575 /*
11576  * [DSP] PRECEU.PH.QBLA rt, rs - Expand the precision of the two
11577  *         left-alternate elements of a quad byte vector to four unsigned
11578  *         halfwords
11579  *
11580  *   3         2         1
11581  *  10987654321098765432109876543210
11582  *  001000               00010001101
11583  *     rt -----
11584  *          rs -----
11585  *               rd -----
11586  */
11587 static char *PRECEU_PH_QBLA(uint64 instruction, Dis_info *info)
11588 {
11589     uint64 rt_value = extract_rt_25_24_23_22_21(instruction);
11590     uint64 rs_value = extract_rs_20_19_18_17_16(instruction);
11591 
11592     const char *rt = GPR(rt_value, info);
11593     const char *rs = GPR(rs_value, info);
11594 
11595     return img_format("PRECEU.PH.QBLA %s, %s", rt, rs);
11596 }
11597 
11598 
11599 /*
11600  * [DSP] PRECEU.PH.QBL rt, rs - Expand the precision of the two left-most
11601  *         elements of a quad byte vector to form unsigned halfwords
11602  *
11603  *   3         2         1
11604  *  10987654321098765432109876543210
11605  *  001000               00010001101
11606  *     rt -----
11607  *          rs -----
11608  *               rd -----
11609  */
11610 static char *PRECEU_PH_QBL(uint64 instruction, Dis_info *info)
11611 {
11612     uint64 rt_value = extract_rt_25_24_23_22_21(instruction);
11613     uint64 rs_value = extract_rs_20_19_18_17_16(instruction);
11614 
11615     const char *rt = GPR(rt_value, info);
11616     const char *rs = GPR(rs_value, info);
11617 
11618     return img_format("PRECEU.PH.QBL %s, %s", rt, rs);
11619 }
11620 
11621 
11622 /*
11623  * [DSP] PRECEU.PH.QBRA rt, rs - Expand the precision of the two
11624  *         right-alternate elements of a quad byte vector to form four
11625  *         unsigned halfwords
11626  *
11627  *   3         2         1
11628  *  10987654321098765432109876543210
11629  *  001000               00010001101
11630  *     rt -----
11631  *          rs -----
11632  *               rd -----
11633  */
11634 static char *PRECEU_PH_QBRA(uint64 instruction, Dis_info *info)
11635 {
11636     uint64 rt_value = extract_rt_25_24_23_22_21(instruction);
11637     uint64 rs_value = extract_rs_20_19_18_17_16(instruction);
11638 
11639     const char *rt = GPR(rt_value, info);
11640     const char *rs = GPR(rs_value, info);
11641 
11642     return img_format("PRECEU.PH.QBRA %s, %s", rt, rs);
11643 }
11644 
11645 
11646 /*
11647  * [DSP] PRECEU.PH.QBR rt, rs - Expand the precision of the two right-most
11648  *         elements of a quad byte vector to form unsigned halfwords
11649  *
11650  *   3         2         1
11651  *  10987654321098765432109876543210
11652  *  001000               00010001101
11653  *     rt -----
11654  *          rs -----
11655  *               rd -----
11656  */
11657 static char *PRECEU_PH_QBR(uint64 instruction, Dis_info *info)
11658 {
11659     uint64 rt_value = extract_rt_25_24_23_22_21(instruction);
11660     uint64 rs_value = extract_rs_20_19_18_17_16(instruction);
11661 
11662     const char *rt = GPR(rt_value, info);
11663     const char *rs = GPR(rs_value, info);
11664 
11665     return img_format("PRECEU.PH.QBR %s, %s", rt, rs);
11666 }
11667 
11668 
11669 /*
11670  * [DSP] PRECR.QB.PH rd, rs, rt - Reduce the precision of four integer
11671  *   halfwords to four bytes
11672  *
11673  *   3         2         1
11674  *  10987654321098765432109876543210
11675  *  001000               x0001101101
11676  *     rt -----
11677  *          rs -----
11678  *               rd -----
11679  */
11680 static char *PRECR_QB_PH(uint64 instruction, Dis_info *info)
11681 {
11682     uint64 rt_value = extract_rt_25_24_23_22_21(instruction);
11683     uint64 rs_value = extract_rs_20_19_18_17_16(instruction);
11684     uint64 rd_value = extract_rd_15_14_13_12_11(instruction);
11685 
11686     const char *rd = GPR(rd_value, info);
11687     const char *rs = GPR(rs_value, info);
11688     const char *rt = GPR(rt_value, info);
11689 
11690     return img_format("PRECR.QB.PH %s, %s, %s", rd, rs, rt);
11691 }
11692 
11693 
11694 /*
11695  * [DSP] PRECR_SRA.PH.W rt, rs, sa - Reduce the precision of two integer
11696  *   words to halfwords after a right shift
11697  *
11698  *   3         2         1
11699  *  10987654321098765432109876543210
11700  *  001000               x1110000101
11701  *     rt -----
11702  *          rs -----
11703  *               rd -----
11704  */
11705 static char *PRECR_SRA_PH_W(uint64 instruction, Dis_info *info)
11706 {
11707     uint64 rt_value = extract_rt_25_24_23_22_21(instruction);
11708     uint64 rs_value = extract_rs_20_19_18_17_16(instruction);
11709     uint64 sa_value = extract_sa_15_14_13_12_11(instruction);
11710 
11711     const char *rt = GPR(rt_value, info);
11712     const char *rs = GPR(rs_value, info);
11713 
11714     return img_format("PRECR_SRA.PH.W %s, %s, 0x%" PRIx64, rt, rs, sa_value);
11715 }
11716 
11717 
11718 /*
11719  * [DSP] PRECR_SRA_R.PH.W rt, rs, sa - Reduce the precision of two integer
11720  *   words to halfwords after a right shift with rounding
11721  *
11722  *   3         2         1
11723  *  10987654321098765432109876543210
11724  *  001000               x1110000101
11725  *     rt -----
11726  *          rs -----
11727  *               rd -----
11728  */
11729 static char *PRECR_SRA_R_PH_W(uint64 instruction, Dis_info *info)
11730 {
11731     uint64 rt_value = extract_rt_25_24_23_22_21(instruction);
11732     uint64 rs_value = extract_rs_20_19_18_17_16(instruction);
11733     uint64 sa_value = extract_sa_15_14_13_12_11(instruction);
11734 
11735     const char *rt = GPR(rt_value, info);
11736     const char *rs = GPR(rs_value, info);
11737 
11738     return img_format("PRECR_SRA_R.PH.W %s, %s, 0x%" PRIx64, rt, rs, sa_value);
11739 }
11740 
11741 
11742 /*
11743  * [DSP] PRECRQ.PH.W rd, rs, rt - Reduce the precision of fractional
11744  *   words to fractional halfwords
11745  *
11746  *   3         2         1
11747  *  10987654321098765432109876543210
11748  *  001000               x1110000101
11749  *     rt -----
11750  *          rs -----
11751  *               rd -----
11752  */
11753 static char *PRECRQ_PH_W(uint64 instruction, Dis_info *info)
11754 {
11755     uint64 rt_value = extract_rt_25_24_23_22_21(instruction);
11756     uint64 rs_value = extract_rs_20_19_18_17_16(instruction);
11757     uint64 rd_value = extract_rd_15_14_13_12_11(instruction);
11758 
11759     const char *rd = GPR(rd_value, info);
11760     const char *rs = GPR(rs_value, info);
11761     const char *rt = GPR(rt_value, info);
11762 
11763     return img_format("PRECRQ.PH.W %s, %s, %s", rd, rs, rt);
11764 }
11765 
11766 
11767 /*
11768  * [DSP] PRECRQ.QB.PH rd, rs, rt - Reduce the precision of four fractional
11769  *   halfwords to four bytes
11770  *
11771  *   3         2         1
11772  *  10987654321098765432109876543210
11773  *  001000               x0010101101
11774  *     rt -----
11775  *          rs -----
11776  *               rd -----
11777  */
11778 static char *PRECRQ_QB_PH(uint64 instruction, Dis_info *info)
11779 {
11780     uint64 rt_value = extract_rt_25_24_23_22_21(instruction);
11781     uint64 rs_value = extract_rs_20_19_18_17_16(instruction);
11782     uint64 rd_value = extract_rd_15_14_13_12_11(instruction);
11783 
11784     const char *rd = GPR(rd_value, info);
11785     const char *rs = GPR(rs_value, info);
11786     const char *rt = GPR(rt_value, info);
11787 
11788     return img_format("PRECRQ.QB.PH %s, %s, %s", rd, rs, rt);
11789 }
11790 
11791 
11792 /*
11793  * [DSP] PRECRQ_RS.PH.W rd, rs, rt - Reduce the precision of fractional
11794  *   words to halfwords with rounding and saturation
11795  *
11796  *   3         2         1
11797  *  10987654321098765432109876543210
11798  *  001000               x1110000101
11799  *     rt -----
11800  *          rs -----
11801  *               rd -----
11802  */
11803 static char *PRECRQ_RS_PH_W(uint64 instruction, Dis_info *info)
11804 {
11805     uint64 rt_value = extract_rt_25_24_23_22_21(instruction);
11806     uint64 rs_value = extract_rs_20_19_18_17_16(instruction);
11807     uint64 rd_value = extract_rd_15_14_13_12_11(instruction);
11808 
11809     const char *rd = GPR(rd_value, info);
11810     const char *rs = GPR(rs_value, info);
11811     const char *rt = GPR(rt_value, info);
11812 
11813     return img_format("PRECRQ_RS.PH.W %s, %s, %s", rd, rs, rt);
11814 }
11815 
11816 
11817 /*
11818  * [DSP] PRECRQU_S.QB.PH rd, rs, rt - Reduce the precision of fractional
11819  *   halfwords to unsigned bytes with saturation
11820  *
11821  *   3         2         1
11822  *  10987654321098765432109876543210
11823  *  001000               x1110000101
11824  *     rt -----
11825  *          rs -----
11826  *               rd -----
11827  */
11828 static char *PRECRQU_S_QB_PH(uint64 instruction, Dis_info *info)
11829 {
11830     uint64 rt_value = extract_rt_25_24_23_22_21(instruction);
11831     uint64 rs_value = extract_rs_20_19_18_17_16(instruction);
11832     uint64 rd_value = extract_rd_15_14_13_12_11(instruction);
11833 
11834     const char *rd = GPR(rd_value, info);
11835     const char *rs = GPR(rs_value, info);
11836     const char *rt = GPR(rt_value, info);
11837 
11838     return img_format("PRECRQU_S.QB.PH %s, %s, %s", rd, rs, rt);
11839 }
11840 
11841 
11842 /*
11843  *
11844  *
11845  *   3         2         1
11846  *  10987654321098765432109876543210
11847  *  001000               x1110000101
11848  *     rt -----
11849  *          rs -----
11850  *               rd -----
11851  */
11852 static char *PREF_S9_(uint64 instruction, Dis_info *info)
11853 {
11854     uint64 hint_value = extract_hint_25_24_23_22_21(instruction);
11855     uint64 rs_value = extract_rs_20_19_18_17_16(instruction);
11856     int64 s_value = extract_s__se8_15_7_6_5_4_3_2_1_0(instruction);
11857 
11858     const char *rs = GPR(rs_value, info);
11859 
11860     return img_format("PREF 0x%" PRIx64 ", %" PRId64 "(%s)",
11861                       hint_value, s_value, rs);
11862 }
11863 
11864 
11865 /*
11866  *
11867  *
11868  *   3         2         1
11869  *  10987654321098765432109876543210
11870  *  001000               x1110000101
11871  *     rt -----
11872  *          rs -----
11873  *               rd -----
11874  */
11875 static char *PREF_U12_(uint64 instruction, Dis_info *info)
11876 {
11877     uint64 hint_value = extract_hint_25_24_23_22_21(instruction);
11878     uint64 rs_value = extract_rs_20_19_18_17_16(instruction);
11879     uint64 u_value = extract_u_11_10_9_8_7_6_5_4_3_2_1_0(instruction);
11880 
11881     const char *rs = GPR(rs_value, info);
11882 
11883     return img_format("PREF 0x%" PRIx64 ", 0x%" PRIx64 "(%s)",
11884                       hint_value, u_value, rs);
11885 }
11886 
11887 
11888 /*
11889  *
11890  *
11891  *   3         2         1
11892  *  10987654321098765432109876543210
11893  *  001000               x1110000101
11894  *     rt -----
11895  *          rs -----
11896  *               rd -----
11897  */
11898 static char *PREFE(uint64 instruction, Dis_info *info)
11899 {
11900     uint64 hint_value = extract_hint_25_24_23_22_21(instruction);
11901     uint64 rs_value = extract_rs_20_19_18_17_16(instruction);
11902     int64 s_value = extract_s__se8_15_7_6_5_4_3_2_1_0(instruction);
11903 
11904     const char *rs = GPR(rs_value, info);
11905 
11906     return img_format("PREFE 0x%" PRIx64 ", %" PRId64 "(%s)",
11907                       hint_value, s_value, rs);
11908 }
11909 
11910 
11911 /*
11912  * [DSP] PREPEND rt, rs, sa - Right shift and prepend bits to the MSB
11913  *
11914  *   3         2         1
11915  *  10987654321098765432109876543210
11916  *  001000               x1110000101
11917  *     rt -----
11918  *          rs -----
11919  *               rd -----
11920  */
11921 static char *PREPEND(uint64 instruction, Dis_info *info)
11922 {
11923     uint64 rt_value = extract_rt_25_24_23_22_21(instruction);
11924     uint64 rs_value = extract_rs_20_19_18_17_16(instruction);
11925     uint64 sa_value = extract_sa_15_14_13_12_11(instruction);
11926 
11927     const char *rt = GPR(rt_value, info);
11928     const char *rs = GPR(rs_value, info);
11929 
11930     return img_format("PREPEND %s, %s, 0x%" PRIx64, rt, rs, sa_value);
11931 }
11932 
11933 
11934 /*
11935  * [DSP] RADDU.W.QB rt, rs - Unsigned reduction add of vector quad bytes
11936  *
11937  *   3         2         1
11938  *  10987654321098765432109876543210
11939  *  001000          1111000100111111
11940  *     rt -----
11941  *          rs -----
11942  */
11943 static char *RADDU_W_QB(uint64 instruction, Dis_info *info)
11944 {
11945     uint64 rt_value = extract_rt_25_24_23_22_21(instruction);
11946     uint64 rs_value = extract_rs_20_19_18_17_16(instruction);
11947 
11948     const char *rt = GPR(rt_value, info);
11949     const char *rs = GPR(rs_value, info);
11950 
11951     return img_format("RADDU.W.QB %s, %s", rt, rs);
11952 }
11953 
11954 
11955 /*
11956  * [DSP] RDDSP rt, mask - Read DSPControl register fields to a GPR
11957  *
11958  *   3         2         1
11959  *  10987654321098765432109876543210
11960  *  001000            00011001111111
11961  *     rt -----
11962  *        mask -------
11963  */
11964 static char *RDDSP(uint64 instruction, Dis_info *info)
11965 {
11966     uint64 rt_value = extract_rt_25_24_23_22_21(instruction);
11967     uint64 mask_value = extract_mask_20_19_18_17_16_15_14(instruction);
11968 
11969     const char *rt = GPR(rt_value, info);
11970 
11971     return img_format("RDDSP %s, 0x%" PRIx64, rt, mask_value);
11972 }
11973 
11974 
11975 /*
11976  *
11977  *
11978  *   3         2         1
11979  *  10987654321098765432109876543210
11980  *  001000               x1110000101
11981  *     rt -----
11982  *          rs -----
11983  *               rd -----
11984  */
11985 static char *RDHWR(uint64 instruction, Dis_info *info)
11986 {
11987     uint64 rt_value = extract_rt_25_24_23_22_21(instruction);
11988     uint64 hs_value = extract_hs_20_19_18_17_16(instruction);
11989     uint64 sel_value = extract_sel_13_12_11(instruction);
11990 
11991     const char *rt = GPR(rt_value, info);
11992 
11993     return img_format("RDHWR %s, CP%" PRIu64 ", 0x%" PRIx64,
11994                       rt, hs_value, sel_value);
11995 }
11996 
11997 
11998 /*
11999  *
12000  *
12001  *   3         2         1
12002  *  10987654321098765432109876543210
12003  *  001000               x1110000101
12004  *     rt -----
12005  *          rs -----
12006  *               rd -----
12007  */
12008 static char *RDPGPR(uint64 instruction, Dis_info *info)
12009 {
12010     uint64 rt_value = extract_rt_25_24_23_22_21(instruction);
12011     uint64 rs_value = extract_rs_20_19_18_17_16(instruction);
12012 
12013     const char *rt = GPR(rt_value, info);
12014     const char *rs = GPR(rs_value, info);
12015 
12016     return img_format("RDPGPR %s, %s", rt, rs);
12017 }
12018 
12019 
12020 /*
12021  *
12022  *
12023  *   3         2         1
12024  *  10987654321098765432109876543210
12025  *  001000               x1110000101
12026  *     rt -----
12027  *          rs -----
12028  *               rd -----
12029  */
12030 static char *RECIP_D(uint64 instruction, Dis_info *info)
12031 {
12032     uint64 ft_value = extract_ft_25_24_23_22_21(instruction);
12033     uint64 fs_value = extract_fs_20_19_18_17_16(instruction);
12034 
12035     const char *ft = FPR(ft_value, info);
12036     const char *fs = FPR(fs_value, info);
12037 
12038     return img_format("RECIP.D %s, %s", ft, fs);
12039 }
12040 
12041 
12042 /*
12043  *
12044  *
12045  *   3         2         1
12046  *  10987654321098765432109876543210
12047  *  001000               x1110000101
12048  *     rt -----
12049  *          rs -----
12050  *               rd -----
12051  */
12052 static char *RECIP_S(uint64 instruction, Dis_info *info)
12053 {
12054     uint64 ft_value = extract_ft_25_24_23_22_21(instruction);
12055     uint64 fs_value = extract_fs_20_19_18_17_16(instruction);
12056 
12057     const char *ft = FPR(ft_value, info);
12058     const char *fs = FPR(fs_value, info);
12059 
12060     return img_format("RECIP.S %s, %s", ft, fs);
12061 }
12062 
12063 
12064 /*
12065  * [DSP] REPL.PH rd, s - Replicate immediate integer into all vector element
12066  *   positions
12067  *
12068  *   3         2         1
12069  *  10987654321098765432109876543210
12070  *  001000               x0000111101
12071  *     rt -----
12072  *           s ----------
12073  */
12074 static char *REPL_PH(uint64 instruction, Dis_info *info)
12075 {
12076     uint64 rt_value = extract_rt_25_24_23_22_21(instruction);
12077     int64 s_value = extract_s__se9_20_19_18_17_16_15_14_13_12_11(instruction);
12078 
12079     const char *rt = GPR(rt_value, info);
12080 
12081     return img_format("REPL.PH %s, %" PRId64, rt, s_value);
12082 }
12083 
12084 
12085 /*
12086  * [DSP] REPL.QB rd, u - Replicate immediate integer into all vector element
12087  *   positions
12088  *
12089  *   3         2         1
12090  *  10987654321098765432109876543210
12091  *  001000             x010111111111
12092  *     rt -----
12093  *           u --------
12094  */
12095 static char *REPL_QB(uint64 instruction, Dis_info *info)
12096 {
12097     uint64 rt_value = extract_rt_25_24_23_22_21(instruction);
12098     uint64 u_value = extract_u_20_19_18_17_16_15_14_13(instruction);
12099 
12100     const char *rt = GPR(rt_value, info);
12101 
12102     return img_format("REPL.QB %s, 0x%" PRIx64, rt, u_value);
12103 }
12104 
12105 
12106 /*
12107  * [DSP] REPLV.PH rt, rs - Replicate a halfword into all vector element
12108  *   positions
12109  *
12110  *   3         2         1
12111  *  10987654321098765432109876543210
12112  *  001000          0000001100111111
12113  *     rt -----
12114  *          rs -----
12115  */
12116 static char *REPLV_PH(uint64 instruction, Dis_info *info)
12117 {
12118     uint64 rt_value = extract_rt_25_24_23_22_21(instruction);
12119     uint64 rs_value = extract_rs_20_19_18_17_16(instruction);
12120 
12121     const char *rt = GPR(rt_value, info);
12122     const char *rs = GPR(rs_value, info);
12123 
12124     return img_format("REPLV.PH %s, %s", rt, rs);
12125 }
12126 
12127 
12128 /*
12129  * [DSP] REPLV.QB rt, rs - Replicate byte into all vector element positions
12130  *
12131  *   3         2         1
12132  *  10987654321098765432109876543210
12133  *  001000          0001001100111111
12134  *     rt -----
12135  *          rs -----
12136  */
12137 static char *REPLV_QB(uint64 instruction, Dis_info *info)
12138 {
12139     uint64 rt_value = extract_rt_25_24_23_22_21(instruction);
12140     uint64 rs_value = extract_rs_20_19_18_17_16(instruction);
12141 
12142     const char *rt = GPR(rt_value, info);
12143     const char *rs = GPR(rs_value, info);
12144 
12145     return img_format("REPLV.QB %s, %s", rt, rs);
12146 }
12147 
12148 
12149 /*
12150  *
12151  *
12152  *   3         2         1
12153  *  10987654321098765432109876543210
12154  *  001000               x1110000101
12155  *     rt -----
12156  *          rs -----
12157  *               rd -----
12158  */
12159 static char *RESTORE_32_(uint64 instruction, Dis_info *info)
12160 {
12161     uint64 rt_value = extract_rt_25_24_23_22_21(instruction);
12162     uint64 count_value = extract_count_19_18_17_16(instruction);
12163     uint64 u_value = extract_u_11_10_9_8_7_6_5_4_3__s3(instruction);
12164     uint64 gp_value = extract_gp_2(instruction);
12165 
12166     g_autofree char *save_restore_str = save_restore_list(
12167         rt_value, count_value, gp_value, info);
12168     return img_format("RESTORE 0x%" PRIx64 "%s", u_value, save_restore_str);
12169 }
12170 
12171 
12172 /*
12173  *
12174  *
12175  *   3         2         1
12176  *  10987654321098765432109876543210
12177  *  001000               x1110000101
12178  *     rt -----
12179  *          rs -----
12180  *               rd -----
12181  */
12182 static char *RESTORE_JRC_16_(uint64 instruction, Dis_info *info)
12183 {
12184     uint64 rt1_value = extract_rtl_11(instruction);
12185     uint64 u_value = extract_u_7_6_5_4__s4(instruction);
12186     uint64 count_value = extract_count_3_2_1_0(instruction);
12187 
12188     g_autofree char *save_restore_str = save_restore_list(
12189         encode_rt1_from_rt(rt1_value), count_value, 0, info);
12190     return img_format("RESTORE.JRC 0x%" PRIx64 "%s", u_value, save_restore_str);
12191 }
12192 
12193 
12194 /*
12195  *
12196  *
12197  *   3         2         1
12198  *  10987654321098765432109876543210
12199  *  001000               x1110000101
12200  *     rt -----
12201  *          rs -----
12202  *               rd -----
12203  */
12204 static char *RESTORE_JRC_32_(uint64 instruction, Dis_info *info)
12205 {
12206     uint64 rt_value = extract_rt_25_24_23_22_21(instruction);
12207     uint64 count_value = extract_count_19_18_17_16(instruction);
12208     uint64 u_value = extract_u_11_10_9_8_7_6_5_4_3__s3(instruction);
12209     uint64 gp_value = extract_gp_2(instruction);
12210 
12211     g_autofree char *save_restore_str = save_restore_list(
12212         rt_value, count_value, gp_value, info);
12213     return img_format("RESTORE.JRC 0x%" PRIx64 "%s", u_value,
12214                       save_restore_str);
12215 }
12216 
12217 
12218 /*
12219  *
12220  *
12221  *   3         2         1
12222  *  10987654321098765432109876543210
12223  *  001000               x1110000101
12224  *     rt -----
12225  *          rs -----
12226  *               rd -----
12227  */
12228 static char *RESTOREF(uint64 instruction, Dis_info *info)
12229 {
12230     uint64 count_value = extract_count_19_18_17_16(instruction);
12231     uint64 u_value = extract_u_11_10_9_8_7_6_5_4_3__s3(instruction);
12232 
12233 
12234     return img_format("RESTOREF 0x%" PRIx64 ", 0x%" PRIx64,
12235                       u_value, count_value);
12236 }
12237 
12238 
12239 /*
12240  *
12241  *
12242  *   3         2         1
12243  *  10987654321098765432109876543210
12244  *  001000               x1110000101
12245  *     rt -----
12246  *          rs -----
12247  *               rd -----
12248  */
12249 static char *RINT_D(uint64 instruction, Dis_info *info)
12250 {
12251     uint64 ft_value = extract_ft_25_24_23_22_21(instruction);
12252     uint64 fs_value = extract_fs_20_19_18_17_16(instruction);
12253 
12254     const char *ft = FPR(ft_value, info);
12255     const char *fs = FPR(fs_value, info);
12256 
12257     return img_format("RINT.D %s, %s", ft, fs);
12258 }
12259 
12260 
12261 /*
12262  *
12263  *
12264  *   3         2         1
12265  *  10987654321098765432109876543210
12266  *  001000               x1110000101
12267  *     rt -----
12268  *          rs -----
12269  *               rd -----
12270  */
12271 static char *RINT_S(uint64 instruction, Dis_info *info)
12272 {
12273     uint64 ft_value = extract_ft_25_24_23_22_21(instruction);
12274     uint64 fs_value = extract_fs_20_19_18_17_16(instruction);
12275 
12276     const char *ft = FPR(ft_value, info);
12277     const char *fs = FPR(fs_value, info);
12278 
12279     return img_format("RINT.S %s, %s", ft, fs);
12280 }
12281 
12282 
12283 /*
12284  *
12285  *
12286  *   3         2         1
12287  *  10987654321098765432109876543210
12288  *  001000               x1110000101
12289  *     rt -----
12290  *          rs -----
12291  *               rd -----
12292  */
12293 static char *ROTR(uint64 instruction, Dis_info *info)
12294 {
12295     uint64 rt_value = extract_rt_25_24_23_22_21(instruction);
12296     uint64 rs_value = extract_rs_20_19_18_17_16(instruction);
12297     uint64 shift_value = extract_shift_4_3_2_1_0(instruction);
12298 
12299     const char *rt = GPR(rt_value, info);
12300     const char *rs = GPR(rs_value, info);
12301 
12302     return img_format("ROTR %s, %s, 0x%" PRIx64, rt, rs, shift_value);
12303 }
12304 
12305 
12306 /*
12307  *
12308  *
12309  *   3         2         1
12310  *  10987654321098765432109876543210
12311  *  001000               x1110000101
12312  *     rt -----
12313  *          rs -----
12314  *               rd -----
12315  */
12316 static char *ROTRV(uint64 instruction, Dis_info *info)
12317 {
12318     uint64 rt_value = extract_rt_25_24_23_22_21(instruction);
12319     uint64 rs_value = extract_rs_20_19_18_17_16(instruction);
12320     uint64 rd_value = extract_rd_15_14_13_12_11(instruction);
12321 
12322     const char *rd = GPR(rd_value, info);
12323     const char *rs = GPR(rs_value, info);
12324     const char *rt = GPR(rt_value, info);
12325 
12326     return img_format("ROTRV %s, %s, %s", rd, rs, rt);
12327 }
12328 
12329 
12330 /*
12331  *
12332  *
12333  *   3         2         1
12334  *  10987654321098765432109876543210
12335  *  001000               x1110000101
12336  *     rt -----
12337  *          rs -----
12338  *               rd -----
12339  */
12340 static char *ROTX(uint64 instruction, Dis_info *info)
12341 {
12342     uint64 rt_value = extract_rt_25_24_23_22_21(instruction);
12343     uint64 rs_value = extract_rs_20_19_18_17_16(instruction);
12344     uint64 shiftx_value = extract_shiftx_10_9_8_7__s1(instruction);
12345     uint64 stripe_value = extract_stripe_6(instruction);
12346     uint64 shift_value = extract_shift_4_3_2_1_0(instruction);
12347 
12348     const char *rt = GPR(rt_value, info);
12349     const char *rs = GPR(rs_value, info);
12350 
12351     return img_format("ROTX %s, %s, 0x%" PRIx64 ", 0x%" PRIx64 ", 0x%" PRIx64,
12352                        rt, rs, shift_value, shiftx_value, stripe_value);
12353 }
12354 
12355 
12356 /*
12357  *
12358  *
12359  *   3         2         1
12360  *  10987654321098765432109876543210
12361  *  001000               x1110000101
12362  *     rt -----
12363  *          rs -----
12364  *               rd -----
12365  */
12366 static char *ROUND_L_D(uint64 instruction, Dis_info *info)
12367 {
12368     uint64 ft_value = extract_ft_25_24_23_22_21(instruction);
12369     uint64 fs_value = extract_fs_20_19_18_17_16(instruction);
12370 
12371     const char *ft = FPR(ft_value, info);
12372     const char *fs = FPR(fs_value, info);
12373 
12374     return img_format("ROUND.L.D %s, %s", ft, fs);
12375 }
12376 
12377 
12378 /*
12379  *
12380  *
12381  *   3         2         1
12382  *  10987654321098765432109876543210
12383  *  001000               x1110000101
12384  *     rt -----
12385  *          rs -----
12386  *               rd -----
12387  */
12388 static char *ROUND_L_S(uint64 instruction, Dis_info *info)
12389 {
12390     uint64 ft_value = extract_ft_25_24_23_22_21(instruction);
12391     uint64 fs_value = extract_fs_20_19_18_17_16(instruction);
12392 
12393     const char *ft = FPR(ft_value, info);
12394     const char *fs = FPR(fs_value, info);
12395 
12396     return img_format("ROUND.L.S %s, %s", ft, fs);
12397 }
12398 
12399 
12400 /*
12401  *
12402  *
12403  *   3         2         1
12404  *  10987654321098765432109876543210
12405  *  001000               x1110000101
12406  *     rt -----
12407  *          rs -----
12408  *               rd -----
12409  */
12410 static char *ROUND_W_D(uint64 instruction, Dis_info *info)
12411 {
12412     uint64 ft_value = extract_ft_25_24_23_22_21(instruction);
12413     uint64 fs_value = extract_fs_20_19_18_17_16(instruction);
12414 
12415     const char *ft = FPR(ft_value, info);
12416     const char *fs = FPR(fs_value, info);
12417 
12418     return img_format("ROUND.W.D %s, %s", ft, fs);
12419 }
12420 
12421 
12422 /*
12423  *
12424  *
12425  *   3         2         1
12426  *  10987654321098765432109876543210
12427  *  001000               x1110000101
12428  *     rt -----
12429  *          rs -----
12430  *               rd -----
12431  */
12432 static char *ROUND_W_S(uint64 instruction, Dis_info *info)
12433 {
12434     uint64 ft_value = extract_ft_25_24_23_22_21(instruction);
12435     uint64 fs_value = extract_fs_20_19_18_17_16(instruction);
12436 
12437     const char *ft = FPR(ft_value, info);
12438     const char *fs = FPR(fs_value, info);
12439 
12440     return img_format("ROUND.W.S %s, %s", ft, fs);
12441 }
12442 
12443 
12444 /*
12445  *
12446  *
12447  *   3         2         1
12448  *  10987654321098765432109876543210
12449  *  001000               x1110000101
12450  *     rt -----
12451  *          rs -----
12452  *               rd -----
12453  */
12454 static char *RSQRT_D(uint64 instruction, Dis_info *info)
12455 {
12456     uint64 ft_value = extract_ft_25_24_23_22_21(instruction);
12457     uint64 fs_value = extract_fs_20_19_18_17_16(instruction);
12458 
12459     const char *ft = FPR(ft_value, info);
12460     const char *fs = FPR(fs_value, info);
12461 
12462     return img_format("RSQRT.D %s, %s", ft, fs);
12463 }
12464 
12465 
12466 /*
12467  *
12468  *
12469  *   3         2         1
12470  *  10987654321098765432109876543210
12471  *  001000               x1110000101
12472  *     rt -----
12473  *          rs -----
12474  *               rd -----
12475  */
12476 static char *RSQRT_S(uint64 instruction, Dis_info *info)
12477 {
12478     uint64 ft_value = extract_ft_25_24_23_22_21(instruction);
12479     uint64 fs_value = extract_fs_20_19_18_17_16(instruction);
12480 
12481     const char *ft = FPR(ft_value, info);
12482     const char *fs = FPR(fs_value, info);
12483 
12484     return img_format("RSQRT.S %s, %s", ft, fs);
12485 }
12486 
12487 
12488 /*
12489  *
12490  *
12491  *   3         2         1
12492  *  10987654321098765432109876543210
12493  *  001000               01001001101
12494  *     rt -----
12495  *          rs -----
12496  *               rd -----
12497  */
12498 static char *SAVE_16_(uint64 instruction, Dis_info *info)
12499 {
12500     uint64 rt1_value = extract_rtl_11(instruction);
12501     uint64 u_value = extract_u_7_6_5_4__s4(instruction);
12502     uint64 count_value = extract_count_3_2_1_0(instruction);
12503 
12504     g_autofree char *save_restore_str = save_restore_list(
12505         encode_rt1_from_rt(rt1_value), count_value, 0, info);
12506     return img_format("SAVE 0x%" PRIx64 "%s", u_value, save_restore_str);
12507 }
12508 
12509 
12510 /*
12511  *
12512  *
12513  *   3         2         1
12514  *  10987654321098765432109876543210
12515  *  001000               01001001101
12516  *     rt -----
12517  *          rs -----
12518  *               rd -----
12519  */
12520 static char *SAVE_32_(uint64 instruction, Dis_info *info)
12521 {
12522     uint64 count_value = extract_count_19_18_17_16(instruction);
12523     uint64 rt_value = extract_rt_25_24_23_22_21(instruction);
12524     uint64 u_value = extract_u_11_10_9_8_7_6_5_4_3__s3(instruction);
12525     uint64 gp_value = extract_gp_2(instruction);
12526 
12527     g_autofree char *save_restore_str = save_restore_list(
12528         rt_value, count_value, gp_value, info);
12529     return img_format("SAVE 0x%" PRIx64 "%s", u_value, save_restore_str);
12530 }
12531 
12532 
12533 /*
12534  *
12535  *
12536  *   3         2         1
12537  *  10987654321098765432109876543210
12538  *  001000               01001001101
12539  *     rt -----
12540  *          rs -----
12541  *               rd -----
12542  */
12543 static char *SAVEF(uint64 instruction, Dis_info *info)
12544 {
12545     uint64 count_value = extract_count_19_18_17_16(instruction);
12546     uint64 u_value = extract_u_11_10_9_8_7_6_5_4_3__s3(instruction);
12547 
12548 
12549     return img_format("SAVEF 0x%" PRIx64 ", 0x%" PRIx64, u_value, count_value);
12550 }
12551 
12552 
12553 /*
12554  *
12555  *
12556  *   3         2         1
12557  *  10987654321098765432109876543210
12558  *  001000               01001001101
12559  *     rt -----
12560  *          rs -----
12561  *               rd -----
12562  */
12563 static char *SB_16_(uint64 instruction, Dis_info *info)
12564 {
12565     uint64 rtz3_value = extract_rtz3_9_8_7(instruction);
12566     uint64 rs3_value = extract_rs3_6_5_4(instruction);
12567     uint64 u_value = extract_u_1_0(instruction);
12568 
12569     const char *rtz3 = GPR(decode_gpr_gpr3_src_store(rtz3_value, info), info);
12570     const char *rs3 = GPR(decode_gpr_gpr3(rs3_value, info), info);
12571 
12572     return img_format("SB %s, 0x%" PRIx64 "(%s)", rtz3, u_value, rs3);
12573 }
12574 
12575 
12576 /*
12577  *
12578  *
12579  *   3         2         1
12580  *  10987654321098765432109876543210
12581  *  001000               01001001101
12582  *     rt -----
12583  *          rs -----
12584  *               rd -----
12585  */
12586 static char *SB_GP_(uint64 instruction, Dis_info *info)
12587 {
12588     uint64 rt_value = extract_rt_25_24_23_22_21(instruction);
12589     uint64 u_value = extract_u_17_to_0(instruction);
12590 
12591     const char *rt = GPR(rt_value, info);
12592 
12593     return img_format("SB %s, 0x%" PRIx64 "($%d)", rt, u_value, 28);
12594 }
12595 
12596 
12597 /*
12598  *
12599  *
12600  *   3         2         1
12601  *  10987654321098765432109876543210
12602  *  001000               01001001101
12603  *     rt -----
12604  *          rs -----
12605  *               rd -----
12606  */
12607 static char *SB_S9_(uint64 instruction, Dis_info *info)
12608 {
12609     uint64 rt_value = extract_rt_25_24_23_22_21(instruction);
12610     uint64 rs_value = extract_rs_20_19_18_17_16(instruction);
12611     int64 s_value = extract_s__se8_15_7_6_5_4_3_2_1_0(instruction);
12612 
12613     const char *rt = GPR(rt_value, info);
12614     const char *rs = GPR(rs_value, info);
12615 
12616     return img_format("SB %s, %" PRId64 "(%s)", rt, s_value, rs);
12617 }
12618 
12619 
12620 /*
12621  *
12622  *
12623  *   3         2         1
12624  *  10987654321098765432109876543210
12625  *  001000               01001001101
12626  *     rt -----
12627  *          rs -----
12628  *               rd -----
12629  */
12630 static char *SB_U12_(uint64 instruction, Dis_info *info)
12631 {
12632     uint64 rt_value = extract_rt_25_24_23_22_21(instruction);
12633     uint64 rs_value = extract_rs_20_19_18_17_16(instruction);
12634     uint64 u_value = extract_u_11_10_9_8_7_6_5_4_3_2_1_0(instruction);
12635 
12636     const char *rt = GPR(rt_value, info);
12637     const char *rs = GPR(rs_value, info);
12638 
12639     return img_format("SB %s, 0x%" PRIx64 "(%s)", rt, u_value, rs);
12640 }
12641 
12642 
12643 /*
12644  *
12645  *
12646  *   3         2         1
12647  *  10987654321098765432109876543210
12648  *  001000               01001001101
12649  *     rt -----
12650  *          rs -----
12651  *               rd -----
12652  */
12653 static char *SBE(uint64 instruction, Dis_info *info)
12654 {
12655     uint64 rt_value = extract_rt_25_24_23_22_21(instruction);
12656     uint64 rs_value = extract_rs_20_19_18_17_16(instruction);
12657     int64 s_value = extract_s__se8_15_7_6_5_4_3_2_1_0(instruction);
12658 
12659     const char *rt = GPR(rt_value, info);
12660     const char *rs = GPR(rs_value, info);
12661 
12662     return img_format("SBE %s, %" PRId64 "(%s)", rt, s_value, rs);
12663 }
12664 
12665 
12666 /*
12667  *
12668  *
12669  *   3         2         1
12670  *  10987654321098765432109876543210
12671  *  001000               01001001101
12672  *     rt -----
12673  *          rs -----
12674  *               rd -----
12675  */
12676 static char *SBX(uint64 instruction, Dis_info *info)
12677 {
12678     uint64 rt_value = extract_rt_25_24_23_22_21(instruction);
12679     uint64 rs_value = extract_rs_20_19_18_17_16(instruction);
12680     uint64 rd_value = extract_rd_15_14_13_12_11(instruction);
12681 
12682     const char *rd = GPR(rd_value, info);
12683     const char *rs = GPR(rs_value, info);
12684     const char *rt = GPR(rt_value, info);
12685 
12686     return img_format("SBX %s, %s(%s)", rd, rs, rt);
12687 }
12688 
12689 
12690 /*
12691  *
12692  *
12693  *   3         2         1
12694  *  10987654321098765432109876543210
12695  *  001000               01001001101
12696  *     rt -----
12697  *          rs -----
12698  *               rd -----
12699  */
12700 static char *SC(uint64 instruction, Dis_info *info)
12701 {
12702     uint64 rt_value = extract_rt_25_24_23_22_21(instruction);
12703     uint64 rs_value = extract_rs_20_19_18_17_16(instruction);
12704     int64 s_value = extract_s__se8_15_7_6_5_4_3_2_s2(instruction);
12705 
12706     const char *rt = GPR(rt_value, info);
12707     const char *rs = GPR(rs_value, info);
12708 
12709     return img_format("SC %s, %" PRId64 "(%s)", rt, s_value, rs);
12710 }
12711 
12712 
12713 /*
12714  *
12715  *
12716  *   3         2         1
12717  *  10987654321098765432109876543210
12718  *  001000               01001001101
12719  *     rt -----
12720  *          rs -----
12721  *               rd -----
12722  */
12723 static char *SCD(uint64 instruction, Dis_info *info)
12724 {
12725     uint64 rt_value = extract_rt_25_24_23_22_21(instruction);
12726     uint64 rs_value = extract_rs_20_19_18_17_16(instruction);
12727     int64 s_value = extract_s__se8_15_7_6_5_4_3_s3(instruction);
12728 
12729     const char *rt = GPR(rt_value, info);
12730     const char *rs = GPR(rs_value, info);
12731 
12732     return img_format("SCD %s, %" PRId64 "(%s)", rt, s_value, rs);
12733 }
12734 
12735 
12736 /*
12737  *
12738  *
12739  *   3         2         1
12740  *  10987654321098765432109876543210
12741  *  001000               01001001101
12742  *     rt -----
12743  *          rs -----
12744  *               rd -----
12745  */
12746 static char *SCDP(uint64 instruction, Dis_info *info)
12747 {
12748     uint64 rt_value = extract_rt_25_24_23_22_21(instruction);
12749     uint64 rs_value = extract_rs_20_19_18_17_16(instruction);
12750     uint64 ru_value = extract_ru_7_6_5_4_3(instruction);
12751 
12752     const char *rt = GPR(rt_value, info);
12753     const char *ru = GPR(ru_value, info);
12754     const char *rs = GPR(rs_value, info);
12755 
12756     return img_format("SCDP %s, %s, (%s)", rt, ru, rs);
12757 }
12758 
12759 
12760 /*
12761  *
12762  *
12763  *   3         2         1
12764  *  10987654321098765432109876543210
12765  *  001000               01001001101
12766  *     rt -----
12767  *          rs -----
12768  *               rd -----
12769  */
12770 static char *SCE(uint64 instruction, Dis_info *info)
12771 {
12772     uint64 rt_value = extract_rt_25_24_23_22_21(instruction);
12773     uint64 rs_value = extract_rs_20_19_18_17_16(instruction);
12774     int64 s_value = extract_s__se8_15_7_6_5_4_3_2_s2(instruction);
12775 
12776     const char *rt = GPR(rt_value, info);
12777     const char *rs = GPR(rs_value, info);
12778 
12779     return img_format("SCE %s, %" PRId64 "(%s)", rt, s_value, rs);
12780 }
12781 
12782 
12783 /*
12784  *
12785  *
12786  *   3         2         1
12787  *  10987654321098765432109876543210
12788  *  001000               01001001101
12789  *     rt -----
12790  *          rs -----
12791  *               rd -----
12792  */
12793 static char *SCWP(uint64 instruction, Dis_info *info)
12794 {
12795     uint64 rt_value = extract_rt_25_24_23_22_21(instruction);
12796     uint64 rs_value = extract_rs_20_19_18_17_16(instruction);
12797     uint64 ru_value = extract_ru_7_6_5_4_3(instruction);
12798 
12799     const char *rt = GPR(rt_value, info);
12800     const char *ru = GPR(ru_value, info);
12801     const char *rs = GPR(rs_value, info);
12802 
12803     return img_format("SCWP %s, %s, (%s)", rt, ru, rs);
12804 }
12805 
12806 
12807 /*
12808  *
12809  *
12810  *   3         2         1
12811  *  10987654321098765432109876543210
12812  *  001000               01001001101
12813  *     rt -----
12814  *          rs -----
12815  *               rd -----
12816  */
12817 static char *SCWPE(uint64 instruction, Dis_info *info)
12818 {
12819     uint64 rt_value = extract_rt_25_24_23_22_21(instruction);
12820     uint64 rs_value = extract_rs_20_19_18_17_16(instruction);
12821     uint64 ru_value = extract_ru_7_6_5_4_3(instruction);
12822 
12823     const char *rt = GPR(rt_value, info);
12824     const char *ru = GPR(ru_value, info);
12825     const char *rs = GPR(rs_value, info);
12826 
12827     return img_format("SCWPE %s, %s, (%s)", rt, ru, rs);
12828 }
12829 
12830 
12831 /*
12832  *
12833  *
12834  *   3         2         1
12835  *  10987654321098765432109876543210
12836  *  001000               01001001101
12837  *     rt -----
12838  *          rs -----
12839  *               rd -----
12840  */
12841 static char *SD_GP_(uint64 instruction, Dis_info *info)
12842 {
12843     uint64 rt_value = extract_rt_25_24_23_22_21(instruction);
12844     uint64 u_value = extract_u_20_to_3__s3(instruction);
12845 
12846     const char *rt = GPR(rt_value, info);
12847 
12848     return img_format("SD %s, 0x%" PRIx64 "($%d)", rt, u_value, 28);
12849 }
12850 
12851 
12852 /*
12853  *
12854  *
12855  *   3         2         1
12856  *  10987654321098765432109876543210
12857  *  001000               01001001101
12858  *     rt -----
12859  *          rs -----
12860  *               rd -----
12861  */
12862 static char *SD_S9_(uint64 instruction, Dis_info *info)
12863 {
12864     uint64 rt_value = extract_rt_25_24_23_22_21(instruction);
12865     uint64 rs_value = extract_rs_20_19_18_17_16(instruction);
12866     int64 s_value = extract_s__se8_15_7_6_5_4_3_2_1_0(instruction);
12867 
12868     const char *rt = GPR(rt_value, info);
12869     const char *rs = GPR(rs_value, info);
12870 
12871     return img_format("SD %s, %" PRId64 "(%s)", rt, s_value, rs);
12872 }
12873 
12874 
12875 /*
12876  *
12877  *
12878  *   3         2         1
12879  *  10987654321098765432109876543210
12880  *  001000               01001001101
12881  *     rt -----
12882  *          rs -----
12883  *               rd -----
12884  */
12885 static char *SD_U12_(uint64 instruction, Dis_info *info)
12886 {
12887     uint64 rt_value = extract_rt_25_24_23_22_21(instruction);
12888     uint64 rs_value = extract_rs_20_19_18_17_16(instruction);
12889     uint64 u_value = extract_u_11_10_9_8_7_6_5_4_3_2_1_0(instruction);
12890 
12891     const char *rt = GPR(rt_value, info);
12892     const char *rs = GPR(rs_value, info);
12893 
12894     return img_format("SD %s, 0x%" PRIx64 "(%s)", rt, u_value, rs);
12895 }
12896 
12897 
12898 /*
12899  *
12900  *
12901  *   3         2         1
12902  *  10987654321098765432109876543210
12903  *  001000               01001001101
12904  *     rt -----
12905  *          rs -----
12906  *               rd -----
12907  */
12908 static char *SDBBP_16_(uint64 instruction, Dis_info *info)
12909 {
12910     uint64 code_value = extract_code_2_1_0(instruction);
12911 
12912 
12913     return img_format("SDBBP 0x%" PRIx64, code_value);
12914 }
12915 
12916 
12917 /*
12918  *
12919  *
12920  *   3         2         1
12921  *  10987654321098765432109876543210
12922  *  001000               01001001101
12923  *     rt -----
12924  *          rs -----
12925  *               rd -----
12926  */
12927 static char *SDBBP_32_(uint64 instruction, Dis_info *info)
12928 {
12929     uint64 code_value = extract_code_18_to_0(instruction);
12930 
12931 
12932     return img_format("SDBBP 0x%" PRIx64, code_value);
12933 }
12934 
12935 
12936 /*
12937  *
12938  *
12939  *   3         2         1
12940  *  10987654321098765432109876543210
12941  *  001000               01001001101
12942  *     rt -----
12943  *          rs -----
12944  *               rd -----
12945  */
12946 static char *SDC1_GP_(uint64 instruction, Dis_info *info)
12947 {
12948     uint64 ft_value = extract_ft_25_24_23_22_21(instruction);
12949     uint64 u_value = extract_u_17_to_2__s2(instruction);
12950 
12951     const char *ft = FPR(ft_value, info);
12952 
12953     return img_format("SDC1 %s, 0x%" PRIx64 "($%d)", ft, u_value, 28);
12954 }
12955 
12956 
12957 /*
12958  *
12959  *
12960  *   3         2         1
12961  *  10987654321098765432109876543210
12962  *  001000               01001001101
12963  *     rt -----
12964  *          rs -----
12965  *               rd -----
12966  */
12967 static char *SDC1_S9_(uint64 instruction, Dis_info *info)
12968 {
12969     uint64 ft_value = extract_ft_25_24_23_22_21(instruction);
12970     uint64 rs_value = extract_rs_20_19_18_17_16(instruction);
12971     int64 s_value = extract_s__se8_15_7_6_5_4_3_2_1_0(instruction);
12972 
12973     const char *ft = FPR(ft_value, info);
12974     const char *rs = GPR(rs_value, info);
12975 
12976     return img_format("SDC1 %s, %" PRId64 "(%s)", ft, s_value, rs);
12977 }
12978 
12979 
12980 /*
12981  *
12982  *
12983  *   3         2         1
12984  *  10987654321098765432109876543210
12985  *  001000               01001001101
12986  *     rt -----
12987  *          rs -----
12988  *               rd -----
12989  */
12990 static char *SDC1_U12_(uint64 instruction, Dis_info *info)
12991 {
12992     uint64 ft_value = extract_ft_25_24_23_22_21(instruction);
12993     uint64 rs_value = extract_rs_20_19_18_17_16(instruction);
12994     uint64 u_value = extract_u_11_10_9_8_7_6_5_4_3_2_1_0(instruction);
12995 
12996     const char *ft = FPR(ft_value, info);
12997     const char *rs = GPR(rs_value, info);
12998 
12999     return img_format("SDC1 %s, 0x%" PRIx64 "(%s)", ft, u_value, rs);
13000 }
13001 
13002 
13003 /*
13004  *
13005  *
13006  *   3         2         1
13007  *  10987654321098765432109876543210
13008  *  001000               01001001101
13009  *     rt -----
13010  *          rs -----
13011  *               rd -----
13012  */
13013 static char *SDC1X(uint64 instruction, Dis_info *info)
13014 {
13015     uint64 rt_value = extract_rt_25_24_23_22_21(instruction);
13016     uint64 rs_value = extract_rs_20_19_18_17_16(instruction);
13017     uint64 ft_value = extract_ft_15_14_13_12_11(instruction);
13018 
13019     const char *ft = FPR(ft_value, info);
13020     const char *rs = GPR(rs_value, info);
13021     const char *rt = GPR(rt_value, info);
13022 
13023     return img_format("SDC1X %s, %s(%s)", ft, rs, rt);
13024 }
13025 
13026 
13027 /*
13028  *
13029  *
13030  *   3         2         1
13031  *  10987654321098765432109876543210
13032  *  001000               01001001101
13033  *     rt -----
13034  *          rs -----
13035  *               rd -----
13036  */
13037 static char *SDC1XS(uint64 instruction, Dis_info *info)
13038 {
13039     uint64 rt_value = extract_rt_25_24_23_22_21(instruction);
13040     uint64 rs_value = extract_rs_20_19_18_17_16(instruction);
13041     uint64 ft_value = extract_ft_15_14_13_12_11(instruction);
13042 
13043     const char *ft = FPR(ft_value, info);
13044     const char *rs = GPR(rs_value, info);
13045     const char *rt = GPR(rt_value, info);
13046 
13047     return img_format("SDC1XS %s, %s(%s)", ft, rs, rt);
13048 }
13049 
13050 
13051 /*
13052  *
13053  *
13054  *   3         2         1
13055  *  10987654321098765432109876543210
13056  *  001000               01001001101
13057  *     rt -----
13058  *          rs -----
13059  *               rd -----
13060  */
13061 static char *SDC2(uint64 instruction, Dis_info *info)
13062 {
13063     uint64 cs_value = extract_cs_25_24_23_22_21(instruction);
13064     uint64 rs_value = extract_rs_20_19_18_17_16(instruction);
13065     int64 s_value = extract_s__se8_15_7_6_5_4_3_2_1_0(instruction);
13066 
13067     const char *rs = GPR(rs_value, info);
13068 
13069     return img_format("SDC2 CP%" PRIu64 ", %" PRId64 "(%s)",
13070                       cs_value, s_value, rs);
13071 }
13072 
13073 
13074 /*
13075  *
13076  *
13077  *   3         2         1
13078  *  10987654321098765432109876543210
13079  *  001000               01001001101
13080  *     rt -----
13081  *          rs -----
13082  *               rd -----
13083  */
13084 static char *SDM(uint64 instruction, Dis_info *info)
13085 {
13086     uint64 rt_value = extract_rt_25_24_23_22_21(instruction);
13087     uint64 rs_value = extract_rs_20_19_18_17_16(instruction);
13088     int64 s_value = extract_s__se8_15_7_6_5_4_3_2_1_0(instruction);
13089     uint64 count3_value = extract_count3_14_13_12(instruction);
13090 
13091     const char *rt = GPR(rt_value, info);
13092     const char *rs = GPR(rs_value, info);
13093     uint64 count3 = encode_count3_from_count(count3_value);
13094 
13095     return img_format("SDM %s, %" PRId64 "(%s), 0x%" PRIx64,
13096                       rt, s_value, rs, count3);
13097 }
13098 
13099 
13100 /*
13101  *
13102  *
13103  *   3         2         1
13104  *  10987654321098765432109876543210
13105  *  001000               01001001101
13106  *     rt -----
13107  *          rs -----
13108  *               rd -----
13109  */
13110 static char *SDPC_48_(uint64 instruction, Dis_info *info)
13111 {
13112     uint64 rt_value = extract_rt_41_40_39_38_37(instruction);
13113     int64 s_value = extract_s__se31_15_to_0_31_to_16(instruction);
13114 
13115     const char *rt = GPR(rt_value, info);
13116     g_autofree char *s = ADDRESS(s_value, 6, info);
13117 
13118     return img_format("SDPC %s, %s", rt, s);
13119 }
13120 
13121 
13122 /*
13123  *
13124  *
13125  *   3         2         1
13126  *  10987654321098765432109876543210
13127  *  001000               01001001101
13128  *     rt -----
13129  *          rs -----
13130  *               rd -----
13131  */
13132 static char *SDXS(uint64 instruction, Dis_info *info)
13133 {
13134     uint64 rt_value = extract_rt_25_24_23_22_21(instruction);
13135     uint64 rs_value = extract_rs_20_19_18_17_16(instruction);
13136     uint64 rd_value = extract_rd_15_14_13_12_11(instruction);
13137 
13138     const char *rd = GPR(rd_value, info);
13139     const char *rs = GPR(rs_value, info);
13140     const char *rt = GPR(rt_value, info);
13141 
13142     return img_format("SDXS %s, %s(%s)", rd, rs, rt);
13143 }
13144 
13145 
13146 /*
13147  *
13148  *
13149  *   3         2         1
13150  *  10987654321098765432109876543210
13151  *  001000               01001001101
13152  *     rt -----
13153  *          rs -----
13154  *               rd -----
13155  */
13156 static char *SDX(uint64 instruction, Dis_info *info)
13157 {
13158     uint64 rt_value = extract_rt_25_24_23_22_21(instruction);
13159     uint64 rs_value = extract_rs_20_19_18_17_16(instruction);
13160     uint64 rd_value = extract_rd_15_14_13_12_11(instruction);
13161 
13162     const char *rd = GPR(rd_value, info);
13163     const char *rs = GPR(rs_value, info);
13164     const char *rt = GPR(rt_value, info);
13165 
13166     return img_format("SDX %s, %s(%s)", rd, rs, rt);
13167 }
13168 
13169 
13170 /*
13171  *
13172  *
13173  *   3         2         1
13174  *  10987654321098765432109876543210
13175  *  001000               01001001101
13176  *     rt -----
13177  *          rs -----
13178  *               rd -----
13179  */
13180 static char *SEB(uint64 instruction, Dis_info *info)
13181 {
13182     uint64 rt_value = extract_rt_25_24_23_22_21(instruction);
13183     uint64 rs_value = extract_rs_20_19_18_17_16(instruction);
13184 
13185     const char *rt = GPR(rt_value, info);
13186     const char *rs = GPR(rs_value, info);
13187 
13188     return img_format("SEB %s, %s", rt, rs);
13189 }
13190 
13191 
13192 /*
13193  *
13194  *
13195  *   3         2         1
13196  *  10987654321098765432109876543210
13197  *  001000               01001001101
13198  *     rt -----
13199  *          rs -----
13200  *               rd -----
13201  */
13202 static char *SEH(uint64 instruction, Dis_info *info)
13203 {
13204     uint64 rt_value = extract_rt_25_24_23_22_21(instruction);
13205     uint64 rs_value = extract_rs_20_19_18_17_16(instruction);
13206 
13207     const char *rt = GPR(rt_value, info);
13208     const char *rs = GPR(rs_value, info);
13209 
13210     return img_format("SEH %s, %s", rt, rs);
13211 }
13212 
13213 
13214 /*
13215  *
13216  *
13217  *   3         2         1
13218  *  10987654321098765432109876543210
13219  *  001000               01001001101
13220  *     rt -----
13221  *          rs -----
13222  *               rd -----
13223  */
13224 static char *SEL_D(uint64 instruction, Dis_info *info)
13225 {
13226     uint64 ft_value = extract_ft_25_24_23_22_21(instruction);
13227     uint64 fs_value = extract_fs_20_19_18_17_16(instruction);
13228     uint64 fd_value = extract_fd_15_14_13_12_11(instruction);
13229 
13230     const char *fd = FPR(fd_value, info);
13231     const char *fs = FPR(fs_value, info);
13232     const char *ft = FPR(ft_value, info);
13233 
13234     return img_format("SEL.D %s, %s, %s", fd, fs, ft);
13235 }
13236 
13237 
13238 /*
13239  *
13240  *
13241  *   3         2         1
13242  *  10987654321098765432109876543210
13243  *  001000               01001001101
13244  *     rt -----
13245  *          rs -----
13246  *               rd -----
13247  */
13248 static char *SEL_S(uint64 instruction, Dis_info *info)
13249 {
13250     uint64 ft_value = extract_ft_25_24_23_22_21(instruction);
13251     uint64 fs_value = extract_fs_20_19_18_17_16(instruction);
13252     uint64 fd_value = extract_fd_15_14_13_12_11(instruction);
13253 
13254     const char *fd = FPR(fd_value, info);
13255     const char *fs = FPR(fs_value, info);
13256     const char *ft = FPR(ft_value, info);
13257 
13258     return img_format("SEL.S %s, %s, %s", fd, fs, ft);
13259 }
13260 
13261 
13262 /*
13263  *
13264  *
13265  *   3         2         1
13266  *  10987654321098765432109876543210
13267  *  001000               01001001101
13268  *     rt -----
13269  *          rs -----
13270  *               rd -----
13271  */
13272 static char *SELEQZ_D(uint64 instruction, Dis_info *info)
13273 {
13274     uint64 ft_value = extract_ft_25_24_23_22_21(instruction);
13275     uint64 fs_value = extract_fs_20_19_18_17_16(instruction);
13276     uint64 fd_value = extract_fd_15_14_13_12_11(instruction);
13277 
13278     const char *fd = FPR(fd_value, info);
13279     const char *fs = FPR(fs_value, info);
13280     const char *ft = FPR(ft_value, info);
13281 
13282     return img_format("SELEQZ.D %s, %s, %s", fd, fs, ft);
13283 }
13284 
13285 
13286 /*
13287  *
13288  *
13289  *   3         2         1
13290  *  10987654321098765432109876543210
13291  *  001000               01001001101
13292  *     rt -----
13293  *          rs -----
13294  *               rd -----
13295  */
13296 static char *SELEQZ_S(uint64 instruction, Dis_info *info)
13297 {
13298     uint64 ft_value = extract_ft_25_24_23_22_21(instruction);
13299     uint64 fs_value = extract_fs_20_19_18_17_16(instruction);
13300     uint64 fd_value = extract_fd_15_14_13_12_11(instruction);
13301 
13302     const char *fd = FPR(fd_value, info);
13303     const char *fs = FPR(fs_value, info);
13304     const char *ft = FPR(ft_value, info);
13305 
13306     return img_format("SELEQZ.S %s, %s, %s", fd, fs, ft);
13307 }
13308 
13309 
13310 /*
13311  *
13312  *
13313  *   3         2         1
13314  *  10987654321098765432109876543210
13315  *  001000               01001001101
13316  *     rt -----
13317  *          rs -----
13318  *               rd -----
13319  */
13320 static char *SELNEZ_D(uint64 instruction, Dis_info *info)
13321 {
13322     uint64 ft_value = extract_ft_25_24_23_22_21(instruction);
13323     uint64 fs_value = extract_fs_20_19_18_17_16(instruction);
13324     uint64 fd_value = extract_fd_15_14_13_12_11(instruction);
13325 
13326     const char *fd = FPR(fd_value, info);
13327     const char *fs = FPR(fs_value, info);
13328     const char *ft = FPR(ft_value, info);
13329 
13330     return img_format("SELNEZ.D %s, %s, %s", fd, fs, ft);
13331 }
13332 
13333 
13334 /*
13335  *
13336  *
13337  *   3         2         1
13338  *  10987654321098765432109876543210
13339  *  001000               01001001101
13340  *     rt -----
13341  *          rs -----
13342  *               rd -----
13343  */
13344 static char *SELNEZ_S(uint64 instruction, Dis_info *info)
13345 {
13346     uint64 ft_value = extract_ft_25_24_23_22_21(instruction);
13347     uint64 fs_value = extract_fs_20_19_18_17_16(instruction);
13348     uint64 fd_value = extract_fd_15_14_13_12_11(instruction);
13349 
13350     const char *fd = FPR(fd_value, info);
13351     const char *fs = FPR(fs_value, info);
13352     const char *ft = FPR(ft_value, info);
13353 
13354     return img_format("SELNEZ.S %s, %s, %s", fd, fs, ft);
13355 }
13356 
13357 
13358 /*
13359  *
13360  *
13361  *   3         2         1
13362  *  10987654321098765432109876543210
13363  *  001000               01001001101
13364  *     rt -----
13365  *          rs -----
13366  *               rd -----
13367  */
13368 static char *SEQI(uint64 instruction, Dis_info *info)
13369 {
13370     uint64 rt_value = extract_rt_25_24_23_22_21(instruction);
13371     uint64 rs_value = extract_rs_20_19_18_17_16(instruction);
13372     uint64 u_value = extract_u_11_10_9_8_7_6_5_4_3_2_1_0(instruction);
13373 
13374     const char *rt = GPR(rt_value, info);
13375     const char *rs = GPR(rs_value, info);
13376 
13377     return img_format("SEQI %s, %s, 0x%" PRIx64, rt, rs, u_value);
13378 }
13379 
13380 
13381 /*
13382  *
13383  *
13384  *   3         2         1
13385  *  10987654321098765432109876543210
13386  *  001000               01001001101
13387  *     rt -----
13388  *          rs -----
13389  *               rd -----
13390  */
13391 static char *SH_16_(uint64 instruction, Dis_info *info)
13392 {
13393     uint64 rtz3_value = extract_rtz3_9_8_7(instruction);
13394     uint64 rs3_value = extract_rs3_6_5_4(instruction);
13395     uint64 u_value = extract_u_2_1__s1(instruction);
13396 
13397     const char *rtz3 = GPR(decode_gpr_gpr3_src_store(rtz3_value, info), info);
13398     const char *rs3 = GPR(decode_gpr_gpr3(rs3_value, info), info);
13399 
13400     return img_format("SH %s, 0x%" PRIx64 "(%s)", rtz3, u_value, rs3);
13401 }
13402 
13403 
13404 /*
13405  *
13406  *
13407  *   3         2         1
13408  *  10987654321098765432109876543210
13409  *  001000               01001001101
13410  *     rt -----
13411  *          rs -----
13412  *               rd -----
13413  */
13414 static char *SH_GP_(uint64 instruction, Dis_info *info)
13415 {
13416     uint64 rt_value = extract_rt_25_24_23_22_21(instruction);
13417     uint64 u_value = extract_u_17_to_1__s1(instruction);
13418 
13419     const char *rt = GPR(rt_value, info);
13420 
13421     return img_format("SH %s, 0x%" PRIx64 "($%d)", rt, u_value, 28);
13422 }
13423 
13424 
13425 /*
13426  *
13427  *
13428  *   3         2         1
13429  *  10987654321098765432109876543210
13430  *  001000               01001001101
13431  *     rt -----
13432  *          rs -----
13433  *               rd -----
13434  */
13435 static char *SH_S9_(uint64 instruction, Dis_info *info)
13436 {
13437     uint64 rt_value = extract_rt_25_24_23_22_21(instruction);
13438     uint64 rs_value = extract_rs_20_19_18_17_16(instruction);
13439     int64 s_value = extract_s__se8_15_7_6_5_4_3_2_1_0(instruction);
13440 
13441     const char *rt = GPR(rt_value, info);
13442     const char *rs = GPR(rs_value, info);
13443 
13444     return img_format("SH %s, %" PRId64 "(%s)", rt, s_value, rs);
13445 }
13446 
13447 
13448 /*
13449  *
13450  *
13451  *   3         2         1
13452  *  10987654321098765432109876543210
13453  *  001000               01001001101
13454  *     rt -----
13455  *          rs -----
13456  *               rd -----
13457  */
13458 static char *SH_U12_(uint64 instruction, Dis_info *info)
13459 {
13460     uint64 rt_value = extract_rt_25_24_23_22_21(instruction);
13461     uint64 rs_value = extract_rs_20_19_18_17_16(instruction);
13462     uint64 u_value = extract_u_11_10_9_8_7_6_5_4_3_2_1_0(instruction);
13463 
13464     const char *rt = GPR(rt_value, info);
13465     const char *rs = GPR(rs_value, info);
13466 
13467     return img_format("SH %s, 0x%" PRIx64 "(%s)", rt, u_value, rs);
13468 }
13469 
13470 
13471 /*
13472  *
13473  *
13474  *   3         2         1
13475  *  10987654321098765432109876543210
13476  *  001000               01001001101
13477  *     rt -----
13478  *          rs -----
13479  *               rd -----
13480  */
13481 static char *SHE(uint64 instruction, Dis_info *info)
13482 {
13483     uint64 rt_value = extract_rt_25_24_23_22_21(instruction);
13484     uint64 rs_value = extract_rs_20_19_18_17_16(instruction);
13485     int64 s_value = extract_s__se8_15_7_6_5_4_3_2_1_0(instruction);
13486 
13487     const char *rt = GPR(rt_value, info);
13488     const char *rs = GPR(rs_value, info);
13489 
13490     return img_format("SHE %s, %" PRId64 "(%s)", rt, s_value, rs);
13491 }
13492 
13493 
13494 /*
13495  * [DSP] SHILO ac, shift - Shift an accumulator value leaving the result in
13496  *   the same accumulator
13497  *
13498  *   3         2         1
13499  *  10987654321098765432109876543210
13500  *  001000xxxx        xxxx0000011101
13501  *      shift ------
13502  *               ac --
13503  */
13504 static char *SHILO(uint64 instruction, Dis_info *info)
13505 {
13506     int64 shift_value = extract_shift__se5_21_20_19_18_17_16(instruction);
13507     uint64 ac_value = extract_ac_15_14(instruction);
13508 
13509     const char *ac = AC(ac_value, info);
13510 
13511     return img_format("SHILO %s, 0x%" PRIx64, ac, shift_value);
13512 }
13513 
13514 
13515 /*
13516  * [DSP] SHILOV ac, rs - Variable shift of accumulator value leaving the result
13517  *   in the same accumulator
13518  *
13519  *   3         2         1
13520  *  10987654321098765432109876543210
13521  *  001000xxxxx       01001001111111
13522  *          rs -----
13523  *               ac --
13524  */
13525 static char *SHILOV(uint64 instruction, Dis_info *info)
13526 {
13527     uint64 rs_value = extract_rs_20_19_18_17_16(instruction);
13528     uint64 ac_value = extract_ac_15_14(instruction);
13529 
13530     const char *rs = GPR(rs_value, info);
13531     const char *ac = AC(ac_value, info);
13532 
13533     return img_format("SHILOV %s, %s", ac, rs);
13534 }
13535 
13536 
13537 /*
13538  * [DSP] SHLL.PH rt, rs, sa - Shift left logical vector pair halfwords
13539  *
13540  *   3         2         1
13541  *  10987654321098765432109876543210
13542  *  001000              001110110101
13543  *     rt -----
13544  *          rs -----
13545  *               sa ----
13546  */
13547 static char *SHLL_PH(uint64 instruction, Dis_info *info)
13548 {
13549     uint64 rt_value = extract_rt_25_24_23_22_21(instruction);
13550     uint64 rs_value = extract_rs_20_19_18_17_16(instruction);
13551     uint64 sa_value = extract_sa_15_14_13_12(instruction);
13552 
13553     const char *rt = GPR(rt_value, info);
13554     const char *rs = GPR(rs_value, info);
13555 
13556     return img_format("SHLL.PH %s, %s, 0x%" PRIx64, rt, rs, sa_value);
13557 }
13558 
13559 
13560 /*
13561  * [DSP] SHLL.QB rt, rs, sa - Shift left logical vector quad bytes
13562  *
13563  *   3         2         1
13564  *  10987654321098765432109876543210
13565  *  001000             0100001111111
13566  *     rt -----
13567  *          rs -----
13568  *               sa ---
13569  */
13570 static char *SHLL_QB(uint64 instruction, Dis_info *info)
13571 {
13572     uint64 rt_value = extract_rt_25_24_23_22_21(instruction);
13573     uint64 rs_value = extract_rs_20_19_18_17_16(instruction);
13574     uint64 sa_value = extract_sa_15_14_13(instruction);
13575 
13576     const char *rt = GPR(rt_value, info);
13577     const char *rs = GPR(rs_value, info);
13578 
13579     return img_format("SHLL.QB %s, %s, 0x%" PRIx64, rt, rs, sa_value);
13580 }
13581 
13582 
13583 /*
13584  * [DSP] SHLL_S.PH rt, rs, sa - Shift left logical vector pair halfwords
13585  *   with saturation
13586  *
13587  *   3         2         1
13588  *  10987654321098765432109876543210
13589  *  001000              001110110101
13590  *     rt -----
13591  *          rs -----
13592  *               sa ----
13593  */
13594 static char *SHLL_S_PH(uint64 instruction, Dis_info *info)
13595 {
13596     uint64 rt_value = extract_rt_25_24_23_22_21(instruction);
13597     uint64 rs_value = extract_rs_20_19_18_17_16(instruction);
13598     uint64 sa_value = extract_sa_15_14_13_12(instruction);
13599 
13600     const char *rt = GPR(rt_value, info);
13601     const char *rs = GPR(rs_value, info);
13602 
13603     return img_format("SHLL_S.PH %s, %s, 0x%" PRIx64, rt, rs, sa_value);
13604 }
13605 
13606 
13607 /*
13608  * [DSP] SHLL_S.PH rt, rs, sa - Shift left logical word with saturation
13609  *
13610  *   3         2         1
13611  *  10987654321098765432109876543210
13612  *  001000               x1111110101
13613  *     rt -----
13614  *          rs -----
13615  *               sa -----
13616  */
13617 static char *SHLL_S_W(uint64 instruction, Dis_info *info)
13618 {
13619     uint64 rt_value = extract_rt_25_24_23_22_21(instruction);
13620     uint64 rs_value = extract_rs_20_19_18_17_16(instruction);
13621     uint64 sa_value = extract_sa_15_14_13_12_11(instruction);
13622 
13623     const char *rt = GPR(rt_value, info);
13624     const char *rs = GPR(rs_value, info);
13625 
13626     return img_format("SHLL_S.W %s, %s, 0x%" PRIx64, rt, rs, sa_value);
13627 }
13628 
13629 
13630 /*
13631  * [DSP] SHLLV.PH rd, rt, rs - Shift left logical variable vector pair
13632  *   halfwords
13633  *
13634  *   3         2         1
13635  *  10987654321098765432109876543210
13636  *  001000               01110001101
13637  *     rt -----
13638  *          rs -----
13639  *               rd -----
13640  */
13641 static char *SHLLV_PH(uint64 instruction, Dis_info *info)
13642 {
13643     uint64 rt_value = extract_rt_25_24_23_22_21(instruction);
13644     uint64 rs_value = extract_rs_20_19_18_17_16(instruction);
13645     uint64 rd_value = extract_rd_15_14_13_12_11(instruction);
13646 
13647     const char *rd = GPR(rd_value, info);
13648     const char *rt = GPR(rt_value, info);
13649     const char *rs = GPR(rs_value, info);
13650 
13651     return img_format("SHLLV.PH %s, %s, %s", rd, rt, rs);
13652 }
13653 
13654 
13655 /*
13656  * [DSP] SHLLV_S.QB rd, rt, rs - Shift left logical variable vector quad bytes
13657  *
13658  *   3         2         1
13659  *  10987654321098765432109876543210
13660  *  001000               x1110010101
13661  *     rt -----
13662  *          rs -----
13663  *               rd -----
13664  */
13665 static char *SHLLV_QB(uint64 instruction, Dis_info *info)
13666 {
13667     uint64 rt_value = extract_rt_25_24_23_22_21(instruction);
13668     uint64 rs_value = extract_rs_20_19_18_17_16(instruction);
13669     uint64 rd_value = extract_rd_15_14_13_12_11(instruction);
13670 
13671     const char *rd = GPR(rd_value, info);
13672     const char *rt = GPR(rt_value, info);
13673     const char *rs = GPR(rs_value, info);
13674 
13675     return img_format("SHLLV.QB %s, %s, %s", rd, rt, rs);
13676 }
13677 
13678 
13679 /*
13680  * [DSP] SHLLV.PH rd, rt, rs - Shift left logical variable vector pair
13681  *   halfwords with saturation
13682  *
13683  *   3         2         1
13684  *  10987654321098765432109876543210
13685  *  001000               11110001101
13686  *     rt -----
13687  *          rs -----
13688  *               rd -----
13689  */
13690 static char *SHLLV_S_PH(uint64 instruction, Dis_info *info)
13691 {
13692     uint64 rt_value = extract_rt_25_24_23_22_21(instruction);
13693     uint64 rs_value = extract_rs_20_19_18_17_16(instruction);
13694     uint64 rd_value = extract_rd_15_14_13_12_11(instruction);
13695 
13696     const char *rd = GPR(rd_value, info);
13697     const char *rt = GPR(rt_value, info);
13698     const char *rs = GPR(rs_value, info);
13699 
13700     return img_format("SHLLV_S.PH %s, %s, %s", rd, rt, rs);
13701 }
13702 
13703 
13704 /*
13705  * [DSP] SHLLV_S.W rd, rt, rs - Shift left logical variable vector word
13706  *
13707  *   3         2         1
13708  *  10987654321098765432109876543210
13709  *  001000               x1111010101
13710  *     rt -----
13711  *          rs -----
13712  *               rd -----
13713  */
13714 static char *SHLLV_S_W(uint64 instruction, Dis_info *info)
13715 {
13716     uint64 rt_value = extract_rt_25_24_23_22_21(instruction);
13717     uint64 rs_value = extract_rs_20_19_18_17_16(instruction);
13718     uint64 rd_value = extract_rd_15_14_13_12_11(instruction);
13719 
13720     const char *rd = GPR(rd_value, info);
13721     const char *rt = GPR(rt_value, info);
13722     const char *rs = GPR(rs_value, info);
13723 
13724     return img_format("SHLLV_S.W %s, %s, %s", rd, rt, rs);
13725 }
13726 
13727 
13728 /*
13729  *
13730  *
13731  *   3         2         1
13732  *  10987654321098765432109876543210
13733  *  001000               01001001101
13734  *     rt -----
13735  *          rs -----
13736  *               rd -----
13737  */
13738 static char *SHRA_PH(uint64 instruction, Dis_info *info)
13739 {
13740     uint64 rt_value = extract_rt_25_24_23_22_21(instruction);
13741     uint64 rs_value = extract_rs_20_19_18_17_16(instruction);
13742     uint64 sa_value = extract_sa_15_14_13_12(instruction);
13743 
13744     const char *rt = GPR(rt_value, info);
13745     const char *rs = GPR(rs_value, info);
13746 
13747     return img_format("SHRA.PH %s, %s, 0x%" PRIx64, rt, rs, sa_value);
13748 }
13749 
13750 
13751 /*
13752  *
13753  *
13754  *   3         2         1
13755  *  10987654321098765432109876543210
13756  *  001000               01001001101
13757  *     rt -----
13758  *          rs -----
13759  *               rd -----
13760  */
13761 static char *SHRA_QB(uint64 instruction, Dis_info *info)
13762 {
13763     uint64 rt_value = extract_rt_25_24_23_22_21(instruction);
13764     uint64 rs_value = extract_rs_20_19_18_17_16(instruction);
13765     uint64 sa_value = extract_sa_15_14_13(instruction);
13766 
13767     const char *rt = GPR(rt_value, info);
13768     const char *rs = GPR(rs_value, info);
13769 
13770     return img_format("SHRA.QB %s, %s, 0x%" PRIx64, rt, rs, sa_value);
13771 }
13772 
13773 
13774 /*
13775  *
13776  *
13777  *   3         2         1
13778  *  10987654321098765432109876543210
13779  *  001000               01001001101
13780  *     rt -----
13781  *          rs -----
13782  *               rd -----
13783  */
13784 static char *SHRA_R_PH(uint64 instruction, Dis_info *info)
13785 {
13786     uint64 rt_value = extract_rt_25_24_23_22_21(instruction);
13787     uint64 rs_value = extract_rs_20_19_18_17_16(instruction);
13788     uint64 sa_value = extract_sa_15_14_13_12(instruction);
13789 
13790     const char *rt = GPR(rt_value, info);
13791     const char *rs = GPR(rs_value, info);
13792 
13793     return img_format("SHRA_R.PH %s, %s, 0x%" PRIx64, rt, rs, sa_value);
13794 }
13795 
13796 
13797 /*
13798  *
13799  *
13800  *   3         2         1
13801  *  10987654321098765432109876543210
13802  *  001000               01001001101
13803  *     rt -----
13804  *          rs -----
13805  *               rd -----
13806  */
13807 static char *SHRA_R_QB(uint64 instruction, Dis_info *info)
13808 {
13809     uint64 rt_value = extract_rt_25_24_23_22_21(instruction);
13810     uint64 rs_value = extract_rs_20_19_18_17_16(instruction);
13811     uint64 sa_value = extract_sa_15_14_13(instruction);
13812 
13813     const char *rt = GPR(rt_value, info);
13814     const char *rs = GPR(rs_value, info);
13815 
13816     return img_format("SHRA_R.QB %s, %s, 0x%" PRIx64, rt, rs, sa_value);
13817 }
13818 
13819 
13820 /*
13821  *
13822  *
13823  *   3         2         1
13824  *  10987654321098765432109876543210
13825  *  001000               01001001101
13826  *     rt -----
13827  *          rs -----
13828  *               rd -----
13829  */
13830 static char *SHRA_R_W(uint64 instruction, Dis_info *info)
13831 {
13832     uint64 rt_value = extract_rt_25_24_23_22_21(instruction);
13833     uint64 rs_value = extract_rs_20_19_18_17_16(instruction);
13834     uint64 sa_value = extract_sa_15_14_13_12_11(instruction);
13835 
13836     const char *rt = GPR(rt_value, info);
13837     const char *rs = GPR(rs_value, info);
13838 
13839     return img_format("SHRA_R.W %s, %s, 0x%" PRIx64, rt, rs, sa_value);
13840 }
13841 
13842 
13843 /*
13844  *
13845  *
13846  *   3         2         1
13847  *  10987654321098765432109876543210
13848  *  001000               01001001101
13849  *     rt -----
13850  *          rs -----
13851  *               rd -----
13852  */
13853 static char *SHRAV_PH(uint64 instruction, Dis_info *info)
13854 {
13855     uint64 rt_value = extract_rt_25_24_23_22_21(instruction);
13856     uint64 rs_value = extract_rs_20_19_18_17_16(instruction);
13857     uint64 rd_value = extract_rd_15_14_13_12_11(instruction);
13858 
13859     const char *rd = GPR(rd_value, info);
13860     const char *rt = GPR(rt_value, info);
13861     const char *rs = GPR(rs_value, info);
13862 
13863     return img_format("SHRAV.PH %s, %s, %s", rd, rt, rs);
13864 }
13865 
13866 
13867 /*
13868  *
13869  *
13870  *   3         2         1
13871  *  10987654321098765432109876543210
13872  *  001000               01001001101
13873  *     rt -----
13874  *          rs -----
13875  *               rd -----
13876  */
13877 static char *SHRAV_QB(uint64 instruction, Dis_info *info)
13878 {
13879     uint64 rt_value = extract_rt_25_24_23_22_21(instruction);
13880     uint64 rs_value = extract_rs_20_19_18_17_16(instruction);
13881     uint64 rd_value = extract_rd_15_14_13_12_11(instruction);
13882 
13883     const char *rd = GPR(rd_value, info);
13884     const char *rt = GPR(rt_value, info);
13885     const char *rs = GPR(rs_value, info);
13886 
13887     return img_format("SHRAV.QB %s, %s, %s", rd, rt, rs);
13888 }
13889 
13890 
13891 /*
13892  *
13893  *
13894  *   3         2         1
13895  *  10987654321098765432109876543210
13896  *  001000               01001001101
13897  *     rt -----
13898  *          rs -----
13899  *               rd -----
13900  */
13901 static char *SHRAV_R_PH(uint64 instruction, Dis_info *info)
13902 {
13903     uint64 rt_value = extract_rt_25_24_23_22_21(instruction);
13904     uint64 rs_value = extract_rs_20_19_18_17_16(instruction);
13905     uint64 rd_value = extract_rd_15_14_13_12_11(instruction);
13906 
13907     const char *rd = GPR(rd_value, info);
13908     const char *rt = GPR(rt_value, info);
13909     const char *rs = GPR(rs_value, info);
13910 
13911     return img_format("SHRAV_R.PH %s, %s, %s", rd, rt, rs);
13912 }
13913 
13914 
13915 /*
13916  *
13917  *
13918  *   3         2         1
13919  *  10987654321098765432109876543210
13920  *  001000               01001001101
13921  *     rt -----
13922  *          rs -----
13923  *               rd -----
13924  */
13925 static char *SHRAV_R_QB(uint64 instruction, Dis_info *info)
13926 {
13927     uint64 rt_value = extract_rt_25_24_23_22_21(instruction);
13928     uint64 rs_value = extract_rs_20_19_18_17_16(instruction);
13929     uint64 rd_value = extract_rd_15_14_13_12_11(instruction);
13930 
13931     const char *rd = GPR(rd_value, info);
13932     const char *rt = GPR(rt_value, info);
13933     const char *rs = GPR(rs_value, info);
13934 
13935     return img_format("SHRAV_R.QB %s, %s, %s", rd, rt, rs);
13936 }
13937 
13938 
13939 /*
13940  *
13941  *
13942  *   3         2         1
13943  *  10987654321098765432109876543210
13944  *  001000               01001001101
13945  *     rt -----
13946  *          rs -----
13947  *               rd -----
13948  */
13949 static char *SHRAV_R_W(uint64 instruction, Dis_info *info)
13950 {
13951     uint64 rt_value = extract_rt_25_24_23_22_21(instruction);
13952     uint64 rs_value = extract_rs_20_19_18_17_16(instruction);
13953     uint64 rd_value = extract_rd_15_14_13_12_11(instruction);
13954 
13955     const char *rd = GPR(rd_value, info);
13956     const char *rt = GPR(rt_value, info);
13957     const char *rs = GPR(rs_value, info);
13958 
13959     return img_format("SHRAV_R.W %s, %s, %s", rd, rt, rs);
13960 }
13961 
13962 
13963 /*
13964  * [DSP] SHRL.PH rt, rs, sa - Shift right logical two halfwords
13965  *
13966  *   3         2         1
13967  *  10987654321098765432109876543210
13968  *  001000              001111111111
13969  *     rt -----
13970  *          rs -----
13971  *               sa ----
13972  */
13973 static char *SHRL_PH(uint64 instruction, Dis_info *info)
13974 {
13975     uint64 rt_value = extract_rt_25_24_23_22_21(instruction);
13976     uint64 rs_value = extract_rs_20_19_18_17_16(instruction);
13977     uint64 sa_value = extract_sa_15_14_13_12(instruction);
13978 
13979     const char *rt = GPR(rt_value, info);
13980     const char *rs = GPR(rs_value, info);
13981 
13982     return img_format("SHRL.PH %s, %s, 0x%" PRIx64, rt, rs, sa_value);
13983 }
13984 
13985 
13986 /*
13987  * [DSP] SHRL.QB rt, rs, sa - Shift right logical vector quad bytes
13988  *
13989  *   3         2         1
13990  *  10987654321098765432109876543210
13991  *  001000             1100001111111
13992  *     rt -----
13993  *          rs -----
13994  *               sa ---
13995  */
13996 static char *SHRL_QB(uint64 instruction, Dis_info *info)
13997 {
13998     uint64 rt_value = extract_rt_25_24_23_22_21(instruction);
13999     uint64 rs_value = extract_rs_20_19_18_17_16(instruction);
14000     uint64 sa_value = extract_sa_15_14_13(instruction);
14001 
14002     const char *rt = GPR(rt_value, info);
14003     const char *rs = GPR(rs_value, info);
14004 
14005     return img_format("SHRL.QB %s, %s, 0x%" PRIx64, rt, rs, sa_value);
14006 }
14007 
14008 
14009 /*
14010  * [DSP] SHLLV.PH rd, rt, rs - Shift right logical variable vector pair of
14011  *   halfwords
14012  *
14013  *   3         2         1
14014  *  10987654321098765432109876543210
14015  *  001000               x1100010101
14016  *     rt -----
14017  *          rs -----
14018  *               rd -----
14019  */
14020 static char *SHRLV_PH(uint64 instruction, Dis_info *info)
14021 {
14022     uint64 rt_value = extract_rt_25_24_23_22_21(instruction);
14023     uint64 rs_value = extract_rs_20_19_18_17_16(instruction);
14024     uint64 rd_value = extract_rd_15_14_13_12_11(instruction);
14025 
14026     const char *rd = GPR(rd_value, info);
14027     const char *rt = GPR(rt_value, info);
14028     const char *rs = GPR(rs_value, info);
14029 
14030     return img_format("SHRLV.PH %s, %s, %s", rd, rt, rs);
14031 }
14032 
14033 
14034 /*
14035  * [DSP] SHLLV.QB rd, rt, rs - Shift right logical variable vector quad bytes
14036  *
14037  *   3         2         1
14038  *  10987654321098765432109876543210
14039  *  001000               x1101010101
14040  *     rt -----
14041  *          rs -----
14042  *               rd -----
14043  */
14044 static char *SHRLV_QB(uint64 instruction, Dis_info *info)
14045 {
14046     uint64 rt_value = extract_rt_25_24_23_22_21(instruction);
14047     uint64 rs_value = extract_rs_20_19_18_17_16(instruction);
14048     uint64 rd_value = extract_rd_15_14_13_12_11(instruction);
14049 
14050     const char *rd = GPR(rd_value, info);
14051     const char *rt = GPR(rt_value, info);
14052     const char *rs = GPR(rs_value, info);
14053 
14054     return img_format("SHRLV.QB %s, %s, %s", rd, rt, rs);
14055 }
14056 
14057 
14058 /*
14059  *
14060  *
14061  *   3         2         1
14062  *  10987654321098765432109876543210
14063  *  001000               01001001101
14064  *     rt -----
14065  *          rs -----
14066  *               rd -----
14067  */
14068 static char *SHX(uint64 instruction, Dis_info *info)
14069 {
14070     uint64 rt_value = extract_rt_25_24_23_22_21(instruction);
14071     uint64 rs_value = extract_rs_20_19_18_17_16(instruction);
14072     uint64 rd_value = extract_rd_15_14_13_12_11(instruction);
14073 
14074     const char *rd = GPR(rd_value, info);
14075     const char *rs = GPR(rs_value, info);
14076     const char *rt = GPR(rt_value, info);
14077 
14078     return img_format("SHX %s, %s(%s)", rd, rs, rt);
14079 }
14080 
14081 
14082 /*
14083  *
14084  *
14085  *   3         2         1
14086  *  10987654321098765432109876543210
14087  *  001000               01001001101
14088  *     rt -----
14089  *          rs -----
14090  *               rd -----
14091  */
14092 static char *SHXS(uint64 instruction, Dis_info *info)
14093 {
14094     uint64 rt_value = extract_rt_25_24_23_22_21(instruction);
14095     uint64 rs_value = extract_rs_20_19_18_17_16(instruction);
14096     uint64 rd_value = extract_rd_15_14_13_12_11(instruction);
14097 
14098     const char *rd = GPR(rd_value, info);
14099     const char *rs = GPR(rs_value, info);
14100     const char *rt = GPR(rt_value, info);
14101 
14102     return img_format("SHXS %s, %s(%s)", rd, rs, rt);
14103 }
14104 
14105 
14106 /*
14107  *
14108  *
14109  *   3         2         1
14110  *  10987654321098765432109876543210
14111  *  001000               01001001101
14112  *     rt -----
14113  *          rs -----
14114  *               rd -----
14115  */
14116 static char *SIGRIE(uint64 instruction, Dis_info *info)
14117 {
14118     uint64 code_value = extract_code_18_to_0(instruction);
14119 
14120 
14121     return img_format("SIGRIE 0x%" PRIx64, code_value);
14122 }
14123 
14124 
14125 /*
14126  *
14127  *
14128  *   3         2         1
14129  *  10987654321098765432109876543210
14130  *  001000               01001001101
14131  *     rt -----
14132  *          rs -----
14133  *               rd -----
14134  */
14135 static char *SLL_16_(uint64 instruction, Dis_info *info)
14136 {
14137     uint64 rt3_value = extract_rt3_9_8_7(instruction);
14138     uint64 rs3_value = extract_rs3_6_5_4(instruction);
14139     uint64 shift3_value = extract_shift3_2_1_0(instruction);
14140 
14141     const char *rt3 = GPR(decode_gpr_gpr3(rt3_value, info), info);
14142     const char *rs3 = GPR(decode_gpr_gpr3(rs3_value, info), info);
14143     uint64 shift3 = encode_shift3_from_shift(shift3_value);
14144 
14145     return img_format("SLL %s, %s, 0x%" PRIx64, rt3, rs3, shift3);
14146 }
14147 
14148 
14149 /*
14150  *
14151  *
14152  *   3         2         1
14153  *  10987654321098765432109876543210
14154  *  001000               01001001101
14155  *     rt -----
14156  *          rs -----
14157  *               rd -----
14158  */
14159 static char *SLL_32_(uint64 instruction, Dis_info *info)
14160 {
14161     uint64 rt_value = extract_rt_25_24_23_22_21(instruction);
14162     uint64 rs_value = extract_rs_20_19_18_17_16(instruction);
14163     uint64 shift_value = extract_shift_4_3_2_1_0(instruction);
14164 
14165     const char *rt = GPR(rt_value, info);
14166     const char *rs = GPR(rs_value, info);
14167 
14168     return img_format("SLL %s, %s, 0x%" PRIx64, rt, rs, shift_value);
14169 }
14170 
14171 
14172 /*
14173  *
14174  *
14175  *   3         2         1
14176  *  10987654321098765432109876543210
14177  *  001000               01001001101
14178  *     rt -----
14179  *          rs -----
14180  *               rd -----
14181  */
14182 static char *SLLV(uint64 instruction, Dis_info *info)
14183 {
14184     uint64 rt_value = extract_rt_25_24_23_22_21(instruction);
14185     uint64 rs_value = extract_rs_20_19_18_17_16(instruction);
14186     uint64 rd_value = extract_rd_15_14_13_12_11(instruction);
14187 
14188     const char *rd = GPR(rd_value, info);
14189     const char *rs = GPR(rs_value, info);
14190     const char *rt = GPR(rt_value, info);
14191 
14192     return img_format("SLLV %s, %s, %s", rd, rs, rt);
14193 }
14194 
14195 
14196 /*
14197  *
14198  *
14199  *   3         2         1
14200  *  10987654321098765432109876543210
14201  *  001000               01001001101
14202  *     rt -----
14203  *          rs -----
14204  *               rd -----
14205  */
14206 static char *SLT(uint64 instruction, Dis_info *info)
14207 {
14208     uint64 rt_value = extract_rt_25_24_23_22_21(instruction);
14209     uint64 rs_value = extract_rs_20_19_18_17_16(instruction);
14210     uint64 rd_value = extract_rd_15_14_13_12_11(instruction);
14211 
14212     const char *rd = GPR(rd_value, info);
14213     const char *rs = GPR(rs_value, info);
14214     const char *rt = GPR(rt_value, info);
14215 
14216     return img_format("SLT %s, %s, %s", rd, rs, rt);
14217 }
14218 
14219 
14220 /*
14221  *
14222  *
14223  *   3         2         1
14224  *  10987654321098765432109876543210
14225  *  001000               01001001101
14226  *     rt -----
14227  *          rs -----
14228  *               rd -----
14229  */
14230 static char *SLTI(uint64 instruction, Dis_info *info)
14231 {
14232     uint64 rt_value = extract_rt_25_24_23_22_21(instruction);
14233     uint64 rs_value = extract_rs_20_19_18_17_16(instruction);
14234     uint64 u_value = extract_u_11_10_9_8_7_6_5_4_3_2_1_0(instruction);
14235 
14236     const char *rt = GPR(rt_value, info);
14237     const char *rs = GPR(rs_value, info);
14238 
14239     return img_format("SLTI %s, %s, 0x%" PRIx64, rt, rs, u_value);
14240 }
14241 
14242 
14243 /*
14244  *
14245  *
14246  *   3         2         1
14247  *  10987654321098765432109876543210
14248  *  001000               01001001101
14249  *     rt -----
14250  *          rs -----
14251  *               rd -----
14252  */
14253 static char *SLTIU(uint64 instruction, Dis_info *info)
14254 {
14255     uint64 rt_value = extract_rt_25_24_23_22_21(instruction);
14256     uint64 rs_value = extract_rs_20_19_18_17_16(instruction);
14257     uint64 u_value = extract_u_11_10_9_8_7_6_5_4_3_2_1_0(instruction);
14258 
14259     const char *rt = GPR(rt_value, info);
14260     const char *rs = GPR(rs_value, info);
14261 
14262     return img_format("SLTIU %s, %s, 0x%" PRIx64, rt, rs, u_value);
14263 }
14264 
14265 
14266 /*
14267  *
14268  *
14269  *   3         2         1
14270  *  10987654321098765432109876543210
14271  *  001000               01001001101
14272  *     rt -----
14273  *          rs -----
14274  *               rd -----
14275  */
14276 static char *SLTU(uint64 instruction, Dis_info *info)
14277 {
14278     uint64 rt_value = extract_rt_25_24_23_22_21(instruction);
14279     uint64 rs_value = extract_rs_20_19_18_17_16(instruction);
14280     uint64 rd_value = extract_rd_15_14_13_12_11(instruction);
14281 
14282     const char *rd = GPR(rd_value, info);
14283     const char *rs = GPR(rs_value, info);
14284     const char *rt = GPR(rt_value, info);
14285 
14286     return img_format("SLTU %s, %s, %s", rd, rs, rt);
14287 }
14288 
14289 
14290 /*
14291  *
14292  *
14293  *   3         2         1
14294  *  10987654321098765432109876543210
14295  *  001000               01001001101
14296  *     rt -----
14297  *          rs -----
14298  *               rd -----
14299  */
14300 static char *SOV(uint64 instruction, Dis_info *info)
14301 {
14302     uint64 rt_value = extract_rt_25_24_23_22_21(instruction);
14303     uint64 rs_value = extract_rs_20_19_18_17_16(instruction);
14304     uint64 rd_value = extract_rd_15_14_13_12_11(instruction);
14305 
14306     const char *rd = GPR(rd_value, info);
14307     const char *rs = GPR(rs_value, info);
14308     const char *rt = GPR(rt_value, info);
14309 
14310     return img_format("SOV %s, %s, %s", rd, rs, rt);
14311 }
14312 
14313 
14314 /*
14315  *
14316  *
14317  *   3         2         1
14318  *  10987654321098765432109876543210
14319  *  001000               01001001101
14320  *     rt -----
14321  *          rs -----
14322  *               rd -----
14323  */
14324 static char *SPECIAL2(uint64 instruction, Dis_info *info)
14325 {
14326     uint64 op_value = extract_op_25_to_3(instruction);
14327 
14328 
14329     return img_format("SPECIAL2 0x%" PRIx64, op_value);
14330 }
14331 
14332 
14333 /*
14334  *
14335  *
14336  *   3         2         1
14337  *  10987654321098765432109876543210
14338  *  001000               01001001101
14339  *     rt -----
14340  *          rs -----
14341  *               rd -----
14342  */
14343 static char *SQRT_D(uint64 instruction, Dis_info *info)
14344 {
14345     uint64 ft_value = extract_ft_25_24_23_22_21(instruction);
14346     uint64 fs_value = extract_fs_20_19_18_17_16(instruction);
14347 
14348     const char *ft = FPR(ft_value, info);
14349     const char *fs = FPR(fs_value, info);
14350 
14351     return img_format("SQRT.D %s, %s", ft, fs);
14352 }
14353 
14354 
14355 /*
14356  *
14357  *
14358  *   3         2         1
14359  *  10987654321098765432109876543210
14360  *  001000               01001001101
14361  *     rt -----
14362  *          rs -----
14363  *               rd -----
14364  */
14365 static char *SQRT_S(uint64 instruction, Dis_info *info)
14366 {
14367     uint64 ft_value = extract_ft_25_24_23_22_21(instruction);
14368     uint64 fs_value = extract_fs_20_19_18_17_16(instruction);
14369 
14370     const char *ft = FPR(ft_value, info);
14371     const char *fs = FPR(fs_value, info);
14372 
14373     return img_format("SQRT.S %s, %s", ft, fs);
14374 }
14375 
14376 
14377 /*
14378  * SRA rd, rt, sa - Shift Word Right Arithmetic
14379  *
14380  *   3         2         1
14381  *  10987654321098765432109876543210
14382  *  00000000000               000011
14383  *          rt -----
14384  *               rd -----
14385  *                    sa -----
14386  */
14387 static char *SRA(uint64 instruction, Dis_info *info)
14388 {
14389     uint64 rt_value = extract_rt_25_24_23_22_21(instruction);
14390     uint64 rs_value = extract_rs_20_19_18_17_16(instruction);
14391     uint64 shift_value = extract_shift_4_3_2_1_0(instruction);
14392 
14393     const char *rt = GPR(rt_value, info);
14394     const char *rs = GPR(rs_value, info);
14395 
14396     return img_format("SRA %s, %s, 0x%" PRIx64, rt, rs, shift_value);
14397 }
14398 
14399 
14400 /*
14401  * SRAV rd, rt, rs - Shift Word Right Arithmetic Variable
14402  *
14403  *   3         2         1
14404  *  10987654321098765432109876543210
14405  *  001000               00000000111
14406  *     rs -----
14407  *          rt -----
14408  *               rd -----
14409  */
14410 static char *SRAV(uint64 instruction, Dis_info *info)
14411 {
14412     uint64 rt_value = extract_rt_25_24_23_22_21(instruction);
14413     uint64 rs_value = extract_rs_20_19_18_17_16(instruction);
14414     uint64 rd_value = extract_rd_15_14_13_12_11(instruction);
14415 
14416     const char *rd = GPR(rd_value, info);
14417     const char *rs = GPR(rs_value, info);
14418     const char *rt = GPR(rt_value, info);
14419 
14420     return img_format("SRAV %s, %s, %s", rd, rs, rt);
14421 }
14422 
14423 
14424 /*
14425  *
14426  *
14427  *   3         2         1
14428  *  10987654321098765432109876543210
14429  *  001000               00000000111
14430  *     rs -----
14431  *          rt -----
14432  *               rd -----
14433  */
14434 static char *SRL_16_(uint64 instruction, Dis_info *info)
14435 {
14436     uint64 rt3_value = extract_rt3_9_8_7(instruction);
14437     uint64 rs3_value = extract_rs3_6_5_4(instruction);
14438     uint64 shift3_value = extract_shift3_2_1_0(instruction);
14439 
14440     const char *rt3 = GPR(decode_gpr_gpr3(rt3_value, info), info);
14441     const char *rs3 = GPR(decode_gpr_gpr3(rs3_value, info), info);
14442     uint64 shift3 = encode_shift3_from_shift(shift3_value);
14443 
14444     return img_format("SRL %s, %s, 0x%" PRIx64, rt3, rs3, shift3);
14445 }
14446 
14447 
14448 /*
14449  *
14450  *
14451  *   3         2         1
14452  *  10987654321098765432109876543210
14453  *  001000               01001001101
14454  *     rt -----
14455  *          rs -----
14456  *               rd -----
14457  */
14458 static char *SRL_32_(uint64 instruction, Dis_info *info)
14459 {
14460     uint64 rt_value = extract_rt_25_24_23_22_21(instruction);
14461     uint64 rs_value = extract_rs_20_19_18_17_16(instruction);
14462     uint64 shift_value = extract_shift_4_3_2_1_0(instruction);
14463 
14464     const char *rt = GPR(rt_value, info);
14465     const char *rs = GPR(rs_value, info);
14466 
14467     return img_format("SRL %s, %s, 0x%" PRIx64, rt, rs, shift_value);
14468 }
14469 
14470 
14471 /*
14472  *
14473  *
14474  *   3         2         1
14475  *  10987654321098765432109876543210
14476  *  001000               01001001101
14477  *     rt -----
14478  *          rs -----
14479  *               rd -----
14480  */
14481 static char *SRLV(uint64 instruction, Dis_info *info)
14482 {
14483     uint64 rt_value = extract_rt_25_24_23_22_21(instruction);
14484     uint64 rs_value = extract_rs_20_19_18_17_16(instruction);
14485     uint64 rd_value = extract_rd_15_14_13_12_11(instruction);
14486 
14487     const char *rd = GPR(rd_value, info);
14488     const char *rs = GPR(rs_value, info);
14489     const char *rt = GPR(rt_value, info);
14490 
14491     return img_format("SRLV %s, %s, %s", rd, rs, rt);
14492 }
14493 
14494 
14495 /*
14496  *
14497  *
14498  *   3         2         1
14499  *  10987654321098765432109876543210
14500  *  001000               01001001101
14501  *     rt -----
14502  *          rs -----
14503  *               rd -----
14504  */
14505 static char *SUB(uint64 instruction, Dis_info *info)
14506 {
14507     uint64 rt_value = extract_rt_25_24_23_22_21(instruction);
14508     uint64 rs_value = extract_rs_20_19_18_17_16(instruction);
14509     uint64 rd_value = extract_rd_15_14_13_12_11(instruction);
14510 
14511     const char *rd = GPR(rd_value, info);
14512     const char *rs = GPR(rs_value, info);
14513     const char *rt = GPR(rt_value, info);
14514 
14515     return img_format("SUB %s, %s, %s", rd, rs, rt);
14516 }
14517 
14518 
14519 /*
14520  *
14521  *
14522  *   3         2         1
14523  *  10987654321098765432109876543210
14524  *  001000               01001001101
14525  *     rt -----
14526  *          rs -----
14527  *               rd -----
14528  */
14529 static char *SUB_D(uint64 instruction, Dis_info *info)
14530 {
14531     uint64 ft_value = extract_ft_25_24_23_22_21(instruction);
14532     uint64 fs_value = extract_fs_20_19_18_17_16(instruction);
14533     uint64 fd_value = extract_fd_15_14_13_12_11(instruction);
14534 
14535     const char *fd = FPR(fd_value, info);
14536     const char *fs = FPR(fs_value, info);
14537     const char *ft = FPR(ft_value, info);
14538 
14539     return img_format("SUB.D %s, %s, %s", fd, fs, ft);
14540 }
14541 
14542 
14543 /*
14544  *
14545  *
14546  *   3         2         1
14547  *  10987654321098765432109876543210
14548  *  001000               01001001101
14549  *     rt -----
14550  *          rs -----
14551  *               rd -----
14552  */
14553 static char *SUB_S(uint64 instruction, Dis_info *info)
14554 {
14555     uint64 ft_value = extract_ft_25_24_23_22_21(instruction);
14556     uint64 fs_value = extract_fs_20_19_18_17_16(instruction);
14557     uint64 fd_value = extract_fd_15_14_13_12_11(instruction);
14558 
14559     const char *fd = FPR(fd_value, info);
14560     const char *fs = FPR(fs_value, info);
14561     const char *ft = FPR(ft_value, info);
14562 
14563     return img_format("SUB.S %s, %s, %s", fd, fs, ft);
14564 }
14565 
14566 
14567 /*
14568  *
14569  *
14570  *   3         2         1
14571  *  10987654321098765432109876543210
14572  *  001000               01001001101
14573  *     rt -----
14574  *          rs -----
14575  *               rd -----
14576  */
14577 static char *SUBQ_PH(uint64 instruction, Dis_info *info)
14578 {
14579     uint64 rt_value = extract_rt_25_24_23_22_21(instruction);
14580     uint64 rs_value = extract_rs_20_19_18_17_16(instruction);
14581     uint64 rd_value = extract_rd_15_14_13_12_11(instruction);
14582 
14583     const char *rd = GPR(rd_value, info);
14584     const char *rs = GPR(rs_value, info);
14585     const char *rt = GPR(rt_value, info);
14586 
14587     return img_format("SUBQ.PH %s, %s, %s", rd, rs, rt);
14588 }
14589 
14590 
14591 /*
14592  * [DSP] SUBQ.S.PH rd, rt, rs - Subtract fractional halfword vectors and shift
14593  *   right to halve results
14594  *
14595  *   3         2         1
14596  *  10987654321098765432109876543210
14597  *  001000               01001001101
14598  *     rt -----
14599  *          rs -----
14600  *               rd -----
14601  */
14602 static char *SUBQ_S_PH(uint64 instruction, Dis_info *info)
14603 {
14604     uint64 rt_value = extract_rt_25_24_23_22_21(instruction);
14605     uint64 rs_value = extract_rs_20_19_18_17_16(instruction);
14606     uint64 rd_value = extract_rd_15_14_13_12_11(instruction);
14607 
14608     const char *rd = GPR(rd_value, info);
14609     const char *rs = GPR(rs_value, info);
14610     const char *rt = GPR(rt_value, info);
14611 
14612     return img_format("SUBQ_S.PH %s, %s, %s", rd, rs, rt);
14613 }
14614 
14615 
14616 /*
14617  * [DSP] SUBQ.S.W rd, rt, rs - Subtract fractional halfword vectors and shift
14618  *   right to halve results
14619  *
14620  *   3         2         1
14621  *  10987654321098765432109876543210
14622  *  001000               01001001101
14623  *     rt -----
14624  *          rs -----
14625  *               rd -----
14626  */
14627 static char *SUBQ_S_W(uint64 instruction, Dis_info *info)
14628 {
14629     uint64 rt_value = extract_rt_25_24_23_22_21(instruction);
14630     uint64 rs_value = extract_rs_20_19_18_17_16(instruction);
14631     uint64 rd_value = extract_rd_15_14_13_12_11(instruction);
14632 
14633     const char *rd = GPR(rd_value, info);
14634     const char *rs = GPR(rs_value, info);
14635     const char *rt = GPR(rt_value, info);
14636 
14637     return img_format("SUBQ_S.W %s, %s, %s", rd, rs, rt);
14638 }
14639 
14640 
14641 /*
14642  * [DSP] SUBQH.PH rd, rt, rs - Subtract fractional halfword vectors and shift
14643  *   right to halve results
14644  *
14645  *   3         2         1
14646  *  10987654321098765432109876543210
14647  *  001000               01001001101
14648  *     rt -----
14649  *          rs -----
14650  *               rd -----
14651  */
14652 static char *SUBQH_PH(uint64 instruction, Dis_info *info)
14653 {
14654     uint64 rt_value = extract_rt_25_24_23_22_21(instruction);
14655     uint64 rs_value = extract_rs_20_19_18_17_16(instruction);
14656     uint64 rd_value = extract_rd_15_14_13_12_11(instruction);
14657 
14658     const char *rd = GPR(rd_value, info);
14659     const char *rs = GPR(rs_value, info);
14660     const char *rt = GPR(rt_value, info);
14661 
14662     return img_format("SUBQH.PH %s, %s, %s", rd, rs, rt);
14663 }
14664 
14665 
14666 /*
14667  * [DSP] SUBQH_R.PH rd, rt, rs - Subtract fractional halfword vectors and shift
14668  *   right to halve results
14669  *
14670  *   3         2         1
14671  *  10987654321098765432109876543210
14672  *  001000               01001001101
14673  *     rt -----
14674  *          rs -----
14675  *               rd -----
14676  */
14677 static char *SUBQH_R_PH(uint64 instruction, Dis_info *info)
14678 {
14679     uint64 rt_value = extract_rt_25_24_23_22_21(instruction);
14680     uint64 rs_value = extract_rs_20_19_18_17_16(instruction);
14681     uint64 rd_value = extract_rd_15_14_13_12_11(instruction);
14682 
14683     const char *rd = GPR(rd_value, info);
14684     const char *rs = GPR(rs_value, info);
14685     const char *rt = GPR(rt_value, info);
14686 
14687     return img_format("SUBQH_R.PH %s, %s, %s", rd, rs, rt);
14688 }
14689 
14690 
14691 /*
14692  * [DSP] SUBQH_R.W rd, rt, rs - Subtract fractional halfword vectors and shift
14693  *   right to halve results with rounding
14694  *
14695  *   3         2         1
14696  *  10987654321098765432109876543210
14697  *  001000               11001001101
14698  *     rt -----
14699  *          rs -----
14700  *               rd -----
14701  */
14702 static char *SUBQH_R_W(uint64 instruction, Dis_info *info)
14703 {
14704     uint64 rt_value = extract_rt_25_24_23_22_21(instruction);
14705     uint64 rs_value = extract_rs_20_19_18_17_16(instruction);
14706     uint64 rd_value = extract_rd_15_14_13_12_11(instruction);
14707 
14708     const char *rd = GPR(rd_value, info);
14709     const char *rs = GPR(rs_value, info);
14710     const char *rt = GPR(rt_value, info);
14711 
14712     return img_format("SUBQH_R.W %s, %s, %s", rd, rs, rt);
14713 }
14714 
14715 
14716 /*
14717  * [DSP] SUBQH.W rd, rs, rt - Subtract fractional words and shift right to
14718  *   halve results
14719  *
14720  *   3         2         1
14721  *  10987654321098765432109876543210
14722  *  001000               01010001101
14723  *     rt -----
14724  *          rs -----
14725  *               rd -----
14726  */
14727 static char *SUBQH_W(uint64 instruction, Dis_info *info)
14728 {
14729     uint64 rt_value = extract_rt_25_24_23_22_21(instruction);
14730     uint64 rs_value = extract_rs_20_19_18_17_16(instruction);
14731     uint64 rd_value = extract_rd_15_14_13_12_11(instruction);
14732 
14733     const char *rd = GPR(rd_value, info);
14734     const char *rs = GPR(rs_value, info);
14735     const char *rt = GPR(rt_value, info);
14736 
14737     return img_format("SUBQH.W %s, %s, %s", rd, rs, rt);
14738 }
14739 
14740 
14741 /*
14742  * ADDQH_R.W rd, rt, rs - Add Fractional Words And Shift Right to Halve Results
14743  *
14744  *   3         2         1
14745  *  10987654321098765432109876543210
14746  *  001000               00010001101
14747  *     rt -----
14748  *          rs -----
14749  *               rd -----
14750  */
14751 static char *SUBU_16_(uint64 instruction, Dis_info *info)
14752 {
14753     uint64 rt3_value = extract_rt3_9_8_7(instruction);
14754     uint64 rs3_value = extract_rs3_6_5_4(instruction);
14755     uint64 rd3_value = extract_rd3_3_2_1(instruction);
14756 
14757     const char *rd3 = GPR(decode_gpr_gpr3(rd3_value, info), info);
14758     const char *rs3 = GPR(decode_gpr_gpr3(rs3_value, info), info);
14759     const char *rt3 = GPR(decode_gpr_gpr3(rt3_value, info), info);
14760 
14761     return img_format("SUBU %s, %s, %s", rd3, rs3, rt3);
14762 }
14763 
14764 
14765 /*
14766  * ADDQH_R.W rd, rt, rs - Add Fractional Words And Shift Right to Halve Results
14767  *
14768  *   3         2         1
14769  *  10987654321098765432109876543210
14770  *  001000               00010001101
14771  *     rt -----
14772  *          rs -----
14773  *               rd -----
14774  */
14775 static char *SUBU_32_(uint64 instruction, Dis_info *info)
14776 {
14777     uint64 rt_value = extract_rt_25_24_23_22_21(instruction);
14778     uint64 rs_value = extract_rs_20_19_18_17_16(instruction);
14779     uint64 rd_value = extract_rd_15_14_13_12_11(instruction);
14780 
14781     const char *rd = GPR(rd_value, info);
14782     const char *rs = GPR(rs_value, info);
14783     const char *rt = GPR(rt_value, info);
14784 
14785     return img_format("SUBU %s, %s, %s", rd, rs, rt);
14786 }
14787 
14788 
14789 /*
14790  * [DSP] SUBU.PH rd, rs, rt - Subtract unsigned unsigned halfwords
14791  *
14792  *   3         2         1
14793  *  10987654321098765432109876543210
14794  *  001000               01100001101
14795  *     rt -----
14796  *          rs -----
14797  *               rd -----
14798  */
14799 static char *SUBU_PH(uint64 instruction, Dis_info *info)
14800 {
14801     uint64 rt_value = extract_rt_25_24_23_22_21(instruction);
14802     uint64 rs_value = extract_rs_20_19_18_17_16(instruction);
14803     uint64 rd_value = extract_rd_15_14_13_12_11(instruction);
14804 
14805     const char *rd = GPR(rd_value, info);
14806     const char *rs = GPR(rs_value, info);
14807     const char *rt = GPR(rt_value, info);
14808 
14809     return img_format("SUBU.PH %s, %s, %s", rd, rs, rt);
14810 }
14811 
14812 
14813 /*
14814  * [DSP] SUBU.QB rd, rs, rt - Subtract unsigned quad byte vectors
14815  *
14816  *   3         2         1
14817  *  10987654321098765432109876543210
14818  *  001000               01011001101
14819  *     rt -----
14820  *          rs -----
14821  *               rd -----
14822  */
14823 static char *SUBU_QB(uint64 instruction, Dis_info *info)
14824 {
14825     uint64 rt_value = extract_rt_25_24_23_22_21(instruction);
14826     uint64 rs_value = extract_rs_20_19_18_17_16(instruction);
14827     uint64 rd_value = extract_rd_15_14_13_12_11(instruction);
14828 
14829     const char *rd = GPR(rd_value, info);
14830     const char *rs = GPR(rs_value, info);
14831     const char *rt = GPR(rt_value, info);
14832 
14833     return img_format("SUBU.QB %s, %s, %s", rd, rs, rt);
14834 }
14835 
14836 
14837 /*
14838  * [DSP] SUBU_S.PH rd, rs, rt - Subtract unsigned unsigned halfwords with
14839  *   8-bit saturation
14840  *
14841  *   3         2         1
14842  *  10987654321098765432109876543210
14843  *  001000               11100001101
14844  *     rt -----
14845  *          rs -----
14846  *               rd -----
14847  */
14848 static char *SUBU_S_PH(uint64 instruction, Dis_info *info)
14849 {
14850     uint64 rt_value = extract_rt_25_24_23_22_21(instruction);
14851     uint64 rs_value = extract_rs_20_19_18_17_16(instruction);
14852     uint64 rd_value = extract_rd_15_14_13_12_11(instruction);
14853 
14854     const char *rd = GPR(rd_value, info);
14855     const char *rs = GPR(rs_value, info);
14856     const char *rt = GPR(rt_value, info);
14857 
14858     return img_format("SUBU_S.PH %s, %s, %s", rd, rs, rt);
14859 }
14860 
14861 
14862 /*
14863  * [DSP] SUBU_S.QB rd, rs, rt - Subtract unsigned quad byte vectors with
14864  *   8-bit saturation
14865  *
14866  *   3         2         1
14867  *  10987654321098765432109876543210
14868  *  001000               11011001101
14869  *     rt -----
14870  *          rs -----
14871  *               rd -----
14872  */
14873 static char *SUBU_S_QB(uint64 instruction, Dis_info *info)
14874 {
14875     uint64 rt_value = extract_rt_25_24_23_22_21(instruction);
14876     uint64 rs_value = extract_rs_20_19_18_17_16(instruction);
14877     uint64 rd_value = extract_rd_15_14_13_12_11(instruction);
14878 
14879     const char *rd = GPR(rd_value, info);
14880     const char *rs = GPR(rs_value, info);
14881     const char *rt = GPR(rt_value, info);
14882 
14883     return img_format("SUBU_S.QB %s, %s, %s", rd, rs, rt);
14884 }
14885 
14886 
14887 /*
14888  * [DSP] SUBUH.QB rd, rs, rt - Subtract unsigned bytes and right shift
14889  *   to halve results
14890  *
14891  *   3         2         1
14892  *  10987654321098765432109876543210
14893  *  001000               01101001101
14894  *     rt -----
14895  *          rs -----
14896  *               rd -----
14897  */
14898 static char *SUBUH_QB(uint64 instruction, Dis_info *info)
14899 {
14900     uint64 rt_value = extract_rt_25_24_23_22_21(instruction);
14901     uint64 rs_value = extract_rs_20_19_18_17_16(instruction);
14902     uint64 rd_value = extract_rd_15_14_13_12_11(instruction);
14903 
14904     const char *rd = GPR(rd_value, info);
14905     const char *rs = GPR(rs_value, info);
14906     const char *rt = GPR(rt_value, info);
14907 
14908     return img_format("SUBUH.QB %s, %s, %s", rd, rs, rt);
14909 }
14910 
14911 
14912 /*
14913  * [DSP] SUBUH_R.QB rd, rs, rt - Subtract unsigned bytes and right shift
14914  *   to halve results with rounding
14915  *
14916  *   3         2         1
14917  *  10987654321098765432109876543210
14918  *  001000               11101001101
14919  *     rt -----
14920  *          rs -----
14921  *               rd -----
14922  */
14923 static char *SUBUH_R_QB(uint64 instruction, Dis_info *info)
14924 {
14925     uint64 rt_value = extract_rt_25_24_23_22_21(instruction);
14926     uint64 rs_value = extract_rs_20_19_18_17_16(instruction);
14927     uint64 rd_value = extract_rd_15_14_13_12_11(instruction);
14928 
14929     const char *rd = GPR(rd_value, info);
14930     const char *rs = GPR(rs_value, info);
14931     const char *rt = GPR(rt_value, info);
14932 
14933     return img_format("SUBUH_R.QB %s, %s, %s", rd, rs, rt);
14934 }
14935 
14936 
14937 /*
14938  * ADDQH_R.W rd, rt, rs - Add Fractional Words And Shift Right to Halve Results
14939  *
14940  *   3         2         1
14941  *  10987654321098765432109876543210
14942  *  001000               00010001101
14943  *     rt -----
14944  *          rs -----
14945  *               rd -----
14946  */
14947 static char *SW_16_(uint64 instruction, Dis_info *info)
14948 {
14949     uint64 rtz3_value = extract_rtz3_9_8_7(instruction);
14950     uint64 rs3_value = extract_rs3_6_5_4(instruction);
14951     uint64 u_value = extract_u_3_2_1_0__s2(instruction);
14952 
14953     const char *rtz3 = GPR(decode_gpr_gpr3_src_store(rtz3_value, info), info);
14954     const char *rs3 = GPR(decode_gpr_gpr3(rs3_value, info), info);
14955 
14956     return img_format("SW %s, 0x%" PRIx64 "(%s)", rtz3, u_value, rs3);
14957 }
14958 
14959 
14960 /*
14961  * ADDQH_R.W rd, rt, rs - Add Fractional Words And Shift Right to Halve Results
14962  *
14963  *   3         2         1
14964  *  10987654321098765432109876543210
14965  *  001000               00010001101
14966  *     rt -----
14967  *          rs -----
14968  *               rd -----
14969  */
14970 static char *SW_4X4_(uint64 instruction, Dis_info *info)
14971 {
14972     uint64 rtz4_value = extract_rtz4_9_7_6_5(instruction);
14973     uint64 rs4_value = extract_rs4_4_2_1_0(instruction);
14974     uint64 u_value = extract_u_3_8__s2(instruction);
14975 
14976     const char *rtz4 = GPR(decode_gpr_gpr4_zero(rtz4_value, info), info);
14977     const char *rs4 = GPR(decode_gpr_gpr4(rs4_value, info), info);
14978 
14979     return img_format("SW %s, 0x%" PRIx64 "(%s)", rtz4, u_value, rs4);
14980 }
14981 
14982 
14983 /*
14984  * ADDQH_R.W rd, rt, rs - Add Fractional Words And Shift Right to Halve Results
14985  *
14986  *   3         2         1
14987  *  10987654321098765432109876543210
14988  *  001000               00010001101
14989  *     rt -----
14990  *          rs -----
14991  *               rd -----
14992  */
14993 static char *SW_GP16_(uint64 instruction, Dis_info *info)
14994 {
14995     uint64 u_value = extract_u_6_5_4_3_2_1_0__s2(instruction);
14996     uint64 rtz3_value = extract_rtz3_9_8_7(instruction);
14997 
14998     const char *rtz3 = GPR(decode_gpr_gpr3_src_store(rtz3_value, info), info);
14999 
15000     return img_format("SW %s, 0x%" PRIx64 "($%d)", rtz3, u_value, 28);
15001 }
15002 
15003 
15004 /*
15005  * ADDQH_R.W rd, rt, rs - Add Fractional Words And Shift Right to Halve Results
15006  *
15007  *   3         2         1
15008  *  10987654321098765432109876543210
15009  *  001000               00010001101
15010  *     rt -----
15011  *          rs -----
15012  *               rd -----
15013  */
15014 static char *SW_GP_(uint64 instruction, Dis_info *info)
15015 {
15016     uint64 rt_value = extract_rt_25_24_23_22_21(instruction);
15017     uint64 u_value = extract_u_20_to_2__s2(instruction);
15018 
15019     const char *rt = GPR(rt_value, info);
15020 
15021     return img_format("SW %s, 0x%" PRIx64 "($%d)", rt, u_value, 28);
15022 }
15023 
15024 
15025 /*
15026  * ADDQH_R.W rd, rt, rs - Add Fractional Words And Shift Right to Halve Results
15027  *
15028  *   3         2         1
15029  *  10987654321098765432109876543210
15030  *  001000               00010001101
15031  *     rt -----
15032  *          rs -----
15033  *               rd -----
15034  */
15035 static char *SW_S9_(uint64 instruction, Dis_info *info)
15036 {
15037     uint64 rt_value = extract_rt_25_24_23_22_21(instruction);
15038     int64 s_value = extract_s__se8_15_7_6_5_4_3_2_1_0(instruction);
15039     uint64 rs_value = extract_rs_20_19_18_17_16(instruction);
15040 
15041     const char *rt = GPR(rt_value, info);
15042     const char *rs = GPR(rs_value, info);
15043 
15044     return img_format("SW %s, %" PRId64 "(%s)", rt, s_value, rs);
15045 }
15046 
15047 
15048 /*
15049  * ADDQH_R.W rd, rt, rs - Add Fractional Words And Shift Right to Halve Results
15050  *
15051  *   3         2         1
15052  *  10987654321098765432109876543210
15053  *  001000               00010001101
15054  *     rt -----
15055  *          rs -----
15056  *               rd -----
15057  */
15058 static char *SW_SP_(uint64 instruction, Dis_info *info)
15059 {
15060     uint64 rt_value = extract_rt_9_8_7_6_5(instruction);
15061     uint64 u_value = extract_u_4_3_2_1_0__s2(instruction);
15062 
15063     const char *rt = GPR(rt_value, info);
15064 
15065     return img_format("SW %s, 0x%" PRIx64 "($%d)", rt, u_value, 29);
15066 }
15067 
15068 
15069 /*
15070  * ADDQH_R.W rd, rt, rs - Add Fractional Words And Shift Right to Halve Results
15071  *
15072  *   3         2         1
15073  *  10987654321098765432109876543210
15074  *  001000               00010001101
15075  *     rt -----
15076  *          rs -----
15077  *               rd -----
15078  */
15079 static char *SW_U12_(uint64 instruction, Dis_info *info)
15080 {
15081     uint64 rt_value = extract_rt_25_24_23_22_21(instruction);
15082     uint64 rs_value = extract_rs_20_19_18_17_16(instruction);
15083     uint64 u_value = extract_u_11_10_9_8_7_6_5_4_3_2_1_0(instruction);
15084 
15085     const char *rt = GPR(rt_value, info);
15086     const char *rs = GPR(rs_value, info);
15087 
15088     return img_format("SW %s, 0x%" PRIx64 "(%s)", rt, u_value, rs);
15089 }
15090 
15091 
15092 /*
15093  * ADDQH_R.W rd, rt, rs - Add Fractional Words And Shift Right to Halve Results
15094  *
15095  *   3         2         1
15096  *  10987654321098765432109876543210
15097  *  001000               00010001101
15098  *     rt -----
15099  *          rs -----
15100  *               rd -----
15101  */
15102 static char *SWC1_GP_(uint64 instruction, Dis_info *info)
15103 {
15104     uint64 ft_value = extract_ft_25_24_23_22_21(instruction);
15105     uint64 u_value = extract_u_17_to_2__s2(instruction);
15106 
15107     const char *ft = FPR(ft_value, info);
15108 
15109     return img_format("SWC1 %s, 0x%" PRIx64 "($%d)", ft, u_value, 28);
15110 }
15111 
15112 
15113 /*
15114  * ADDQH_R.W rd, rt, rs - Add Fractional Words And Shift Right to Halve Results
15115  *
15116  *   3         2         1
15117  *  10987654321098765432109876543210
15118  *  001000               00010001101
15119  *     rt -----
15120  *          rs -----
15121  *               rd -----
15122  */
15123 static char *SWC1_S9_(uint64 instruction, Dis_info *info)
15124 {
15125     uint64 ft_value = extract_ft_25_24_23_22_21(instruction);
15126     uint64 rs_value = extract_rs_20_19_18_17_16(instruction);
15127     int64 s_value = extract_s__se8_15_7_6_5_4_3_2_1_0(instruction);
15128 
15129     const char *ft = FPR(ft_value, info);
15130     const char *rs = GPR(rs_value, info);
15131 
15132     return img_format("SWC1 %s, %" PRId64 "(%s)", ft, s_value, rs);
15133 }
15134 
15135 
15136 /*
15137  * ADDQH_R.W rd, rt, rs - Add Fractional Words And Shift Right to Halve Results
15138  *
15139  *   3         2         1
15140  *  10987654321098765432109876543210
15141  *  001000               00010001101
15142  *     rt -----
15143  *          rs -----
15144  *               rd -----
15145  */
15146 static char *SWC1_U12_(uint64 instruction, Dis_info *info)
15147 {
15148     uint64 ft_value = extract_ft_25_24_23_22_21(instruction);
15149     uint64 rs_value = extract_rs_20_19_18_17_16(instruction);
15150     uint64 u_value = extract_u_11_10_9_8_7_6_5_4_3_2_1_0(instruction);
15151 
15152     const char *ft = FPR(ft_value, info);
15153     const char *rs = GPR(rs_value, info);
15154 
15155     return img_format("SWC1 %s, 0x%" PRIx64 "(%s)", ft, u_value, rs);
15156 }
15157 
15158 
15159 /*
15160  * ADDQH_R.W rd, rt, rs - Add Fractional Words And Shift Right to Halve Results
15161  *
15162  *   3         2         1
15163  *  10987654321098765432109876543210
15164  *  001000               00010001101
15165  *     rt -----
15166  *          rs -----
15167  *               rd -----
15168  */
15169 static char *SWC1X(uint64 instruction, Dis_info *info)
15170 {
15171     uint64 rt_value = extract_rt_25_24_23_22_21(instruction);
15172     uint64 rs_value = extract_rs_20_19_18_17_16(instruction);
15173     uint64 ft_value = extract_ft_15_14_13_12_11(instruction);
15174 
15175     const char *ft = FPR(ft_value, info);
15176     const char *rs = GPR(rs_value, info);
15177     const char *rt = GPR(rt_value, info);
15178 
15179     return img_format("SWC1X %s, %s(%s)", ft, rs, rt);
15180 }
15181 
15182 
15183 /*
15184  * ADDQH_R.W rd, rt, rs - Add Fractional Words And Shift Right to Halve Results
15185  *
15186  *   3         2         1
15187  *  10987654321098765432109876543210
15188  *  001000               00010001101
15189  *     rt -----
15190  *          rs -----
15191  *               rd -----
15192  */
15193 static char *SWC1XS(uint64 instruction, Dis_info *info)
15194 {
15195     uint64 rt_value = extract_rt_25_24_23_22_21(instruction);
15196     uint64 rs_value = extract_rs_20_19_18_17_16(instruction);
15197     uint64 ft_value = extract_ft_15_14_13_12_11(instruction);
15198 
15199     const char *ft = FPR(ft_value, info);
15200     const char *rs = GPR(rs_value, info);
15201     const char *rt = GPR(rt_value, info);
15202 
15203     return img_format("SWC1XS %s, %s(%s)", ft, rs, rt);
15204 }
15205 
15206 
15207 /*
15208  * ADDQH_R.W rd, rt, rs - Add Fractional Words And Shift Right to Halve Results
15209  *
15210  *   3         2         1
15211  *  10987654321098765432109876543210
15212  *  001000               00010001101
15213  *     rt -----
15214  *          rs -----
15215  *               rd -----
15216  */
15217 static char *SWC2(uint64 instruction, Dis_info *info)
15218 {
15219     uint64 cs_value = extract_cs_25_24_23_22_21(instruction);
15220     uint64 rs_value = extract_rs_20_19_18_17_16(instruction);
15221     int64 s_value = extract_s__se8_15_7_6_5_4_3_2_1_0(instruction);
15222 
15223     const char *rs = GPR(rs_value, info);
15224 
15225     return img_format("SWC2 CP%" PRIu64 ", %" PRId64 "(%s)",
15226                       cs_value, s_value, rs);
15227 }
15228 
15229 
15230 /*
15231  * ADDQH_R.W rd, rt, rs - Add Fractional Words And Shift Right to Halve Results
15232  *
15233  *   3         2         1
15234  *  10987654321098765432109876543210
15235  *  001000               00010001101
15236  *     rt -----
15237  *          rs -----
15238  *               rd -----
15239  */
15240 static char *SWE(uint64 instruction, Dis_info *info)
15241 {
15242     uint64 rt_value = extract_rt_25_24_23_22_21(instruction);
15243     uint64 rs_value = extract_rs_20_19_18_17_16(instruction);
15244     int64 s_value = extract_s__se8_15_7_6_5_4_3_2_1_0(instruction);
15245 
15246     const char *rt = GPR(rt_value, info);
15247     const char *rs = GPR(rs_value, info);
15248 
15249     return img_format("SWE %s, %" PRId64 "(%s)", rt, s_value, rs);
15250 }
15251 
15252 
15253 /*
15254  * ADDQH_R.W rd, rt, rs - Add Fractional Words And Shift Right to Halve Results
15255  *
15256  *   3         2         1
15257  *  10987654321098765432109876543210
15258  *  001000               00010001101
15259  *     rt -----
15260  *          rs -----
15261  *               rd -----
15262  */
15263 static char *SWM(uint64 instruction, Dis_info *info)
15264 {
15265     uint64 rt_value = extract_rt_25_24_23_22_21(instruction);
15266     uint64 rs_value = extract_rs_20_19_18_17_16(instruction);
15267     int64 s_value = extract_s__se8_15_7_6_5_4_3_2_1_0(instruction);
15268     uint64 count3_value = extract_count3_14_13_12(instruction);
15269 
15270     const char *rt = GPR(rt_value, info);
15271     const char *rs = GPR(rs_value, info);
15272     uint64 count3 = encode_count3_from_count(count3_value);
15273 
15274     return img_format("SWM %s, %" PRId64 "(%s), 0x%" PRIx64,
15275                       rt, s_value, rs, count3);
15276 }
15277 
15278 
15279 /*
15280  * ADDQH_R.W rd, rt, rs - Add Fractional Words And Shift Right to Halve Results
15281  *
15282  *   3         2         1
15283  *  10987654321098765432109876543210
15284  *  001000               00010001101
15285  *     rt -----
15286  *          rs -----
15287  *               rd -----
15288  */
15289 static char *SWPC_48_(uint64 instruction, Dis_info *info)
15290 {
15291     uint64 rt_value = extract_rt_41_40_39_38_37(instruction);
15292     int64 s_value = extract_s__se31_15_to_0_31_to_16(instruction);
15293 
15294     const char *rt = GPR(rt_value, info);
15295     g_autofree char *s = ADDRESS(s_value, 6, info);
15296 
15297     return img_format("SWPC %s, %s", rt, s);
15298 }
15299 
15300 
15301 /*
15302  * ADDQH_R.W rd, rt, rs - Add Fractional Words And Shift Right to Halve Results
15303  *
15304  *   3         2         1
15305  *  10987654321098765432109876543210
15306  *  001000               00010001101
15307  *     rt -----
15308  *          rs -----
15309  *               rd -----
15310  */
15311 static char *SWX(uint64 instruction, Dis_info *info)
15312 {
15313     uint64 rt_value = extract_rt_25_24_23_22_21(instruction);
15314     uint64 rs_value = extract_rs_20_19_18_17_16(instruction);
15315     uint64 rd_value = extract_rd_15_14_13_12_11(instruction);
15316 
15317     const char *rd = GPR(rd_value, info);
15318     const char *rs = GPR(rs_value, info);
15319     const char *rt = GPR(rt_value, info);
15320 
15321     return img_format("SWX %s, %s(%s)", rd, rs, rt);
15322 }
15323 
15324 
15325 /*
15326  * ADDQH_R.W rd, rt, rs - Add Fractional Words And Shift Right to Halve Results
15327  *
15328  *   3         2         1
15329  *  10987654321098765432109876543210
15330  *  001000               00010001101
15331  *     rt -----
15332  *          rs -----
15333  *               rd -----
15334  */
15335 static char *SWXS(uint64 instruction, Dis_info *info)
15336 {
15337     uint64 rt_value = extract_rt_25_24_23_22_21(instruction);
15338     uint64 rs_value = extract_rs_20_19_18_17_16(instruction);
15339     uint64 rd_value = extract_rd_15_14_13_12_11(instruction);
15340 
15341     const char *rd = GPR(rd_value, info);
15342     const char *rs = GPR(rs_value, info);
15343     const char *rt = GPR(rt_value, info);
15344 
15345     return img_format("SWXS %s, %s(%s)", rd, rs, rt);
15346 }
15347 
15348 
15349 /*
15350  * ADDQH_R.W rd, rt, rs - Add Fractional Words And Shift Right to Halve Results
15351  *
15352  *   3         2         1
15353  *  10987654321098765432109876543210
15354  *  001000               00010001101
15355  *     rt -----
15356  *          rs -----
15357  *               rd -----
15358  */
15359 static char *SYNC(uint64 instruction, Dis_info *info)
15360 {
15361     uint64 stype_value = extract_stype_20_19_18_17_16(instruction);
15362 
15363 
15364     return img_format("SYNC 0x%" PRIx64, stype_value);
15365 }
15366 
15367 
15368 /*
15369  * ADDQH_R.W rd, rt, rs - Add Fractional Words And Shift Right to Halve Results
15370  *
15371  *   3         2         1
15372  *  10987654321098765432109876543210
15373  *  001000               00010001101
15374  *     rt -----
15375  *          rs -----
15376  *               rd -----
15377  */
15378 static char *SYNCI(uint64 instruction, Dis_info *info)
15379 {
15380     uint64 rs_value = extract_rs_20_19_18_17_16(instruction);
15381     int64 s_value = extract_s__se8_15_7_6_5_4_3_2_1_0(instruction);
15382 
15383     const char *rs = GPR(rs_value, info);
15384 
15385     return img_format("SYNCI %" PRId64 "(%s)", s_value, rs);
15386 }
15387 
15388 
15389 /*
15390  * ADDQH_R.W rd, rt, rs - Add Fractional Words And Shift Right to Halve Results
15391  *
15392  *   3         2         1
15393  *  10987654321098765432109876543210
15394  *  001000               00010001101
15395  *     rt -----
15396  *          rs -----
15397  *               rd -----
15398  */
15399 static char *SYNCIE(uint64 instruction, Dis_info *info)
15400 {
15401     uint64 rs_value = extract_rs_20_19_18_17_16(instruction);
15402     int64 s_value = extract_s__se8_15_7_6_5_4_3_2_1_0(instruction);
15403 
15404     const char *rs = GPR(rs_value, info);
15405 
15406     return img_format("SYNCIE %" PRId64 "(%s)", s_value, rs);
15407 }
15408 
15409 
15410 /*
15411  * ADDQH_R.W rd, rt, rs - Add Fractional Words And Shift Right to Halve Results
15412  *
15413  *   3         2         1
15414  *  10987654321098765432109876543210
15415  *  001000               00010001101
15416  *     rt -----
15417  *          rs -----
15418  *               rd -----
15419  */
15420 static char *SYSCALL_16_(uint64 instruction, Dis_info *info)
15421 {
15422     uint64 code_value = extract_code_1_0(instruction);
15423 
15424 
15425     return img_format("SYSCALL 0x%" PRIx64, code_value);
15426 }
15427 
15428 
15429 /*
15430  * SYSCALL code - System Call. Cause a System Call Exception
15431  *
15432  *   3         2         1
15433  *  10987654321098765432109876543210
15434  *  00000000000010
15435  *           code ------------------
15436  */
15437 static char *SYSCALL_32_(uint64 instruction, Dis_info *info)
15438 {
15439     uint64 code_value = extract_code_17_to_0(instruction);
15440 
15441 
15442     return img_format("SYSCALL 0x%" PRIx64, code_value);
15443 }
15444 
15445 
15446 /*
15447  * ADDQH_R.W rd, rt, rs - Add Fractional Words And Shift Right to Halve Results
15448  *
15449  *   3         2         1
15450  *  10987654321098765432109876543210
15451  *  001000               00010001101
15452  *     rt -----
15453  *          rs -----
15454  *               rd -----
15455  */
15456 static char *TEQ(uint64 instruction, Dis_info *info)
15457 {
15458     uint64 rt_value = extract_rt_25_24_23_22_21(instruction);
15459     uint64 rs_value = extract_rs_20_19_18_17_16(instruction);
15460 
15461     const char *rs = GPR(rs_value, info);
15462     const char *rt = GPR(rt_value, info);
15463 
15464     return img_format("TEQ %s, %s", rs, rt);
15465 }
15466 
15467 
15468 /*
15469  * ADDQH_R.W rd, rt, rs - Add Fractional Words And Shift Right to Halve Results
15470  *
15471  *   3         2         1
15472  *  10987654321098765432109876543210
15473  *  001000               00010001101
15474  *     rt -----
15475  *          rs -----
15476  *               rd -----
15477  */
15478 static char *TLBGINV(uint64 instruction, Dis_info *info)
15479 {
15480     (void)instruction;
15481 
15482     return g_strdup("TLBGINV ");
15483 }
15484 
15485 
15486 /*
15487  * ADDQH_R.W rd, rt, rs - Add Fractional Words And Shift Right to Halve Results
15488  *
15489  *   3         2         1
15490  *  10987654321098765432109876543210
15491  *  001000               00010001101
15492  *     rt -----
15493  *          rs -----
15494  *               rd -----
15495  */
15496 static char *TLBGINVF(uint64 instruction, Dis_info *info)
15497 {
15498     (void)instruction;
15499 
15500     return g_strdup("TLBGINVF ");
15501 }
15502 
15503 
15504 /*
15505  * ADDQH_R.W rd, rt, rs - Add Fractional Words And Shift Right to Halve Results
15506  *
15507  *   3         2         1
15508  *  10987654321098765432109876543210
15509  *  001000               00010001101
15510  *     rt -----
15511  *          rs -----
15512  *               rd -----
15513  */
15514 static char *TLBGP(uint64 instruction, Dis_info *info)
15515 {
15516     (void)instruction;
15517 
15518     return g_strdup("TLBGP ");
15519 }
15520 
15521 
15522 /*
15523  * ADDQH_R.W rd, rt, rs - Add Fractional Words And Shift Right to Halve Results
15524  *
15525  *   3         2         1
15526  *  10987654321098765432109876543210
15527  *  001000               00010001101
15528  *     rt -----
15529  *          rs -----
15530  *               rd -----
15531  */
15532 static char *TLBGR(uint64 instruction, Dis_info *info)
15533 {
15534     (void)instruction;
15535 
15536     return g_strdup("TLBGR ");
15537 }
15538 
15539 
15540 /*
15541  * ADDQH_R.W rd, rt, rs - Add Fractional Words And Shift Right to Halve Results
15542  *
15543  *   3         2         1
15544  *  10987654321098765432109876543210
15545  *  001000               00010001101
15546  *     rt -----
15547  *          rs -----
15548  *               rd -----
15549  */
15550 static char *TLBGWI(uint64 instruction, Dis_info *info)
15551 {
15552     (void)instruction;
15553 
15554     return g_strdup("TLBGWI ");
15555 }
15556 
15557 
15558 /*
15559  * ADDQH_R.W rd, rt, rs - Add Fractional Words And Shift Right to Halve Results
15560  *
15561  *   3         2         1
15562  *  10987654321098765432109876543210
15563  *  001000               00010001101
15564  *     rt -----
15565  *          rs -----
15566  *               rd -----
15567  */
15568 static char *TLBGWR(uint64 instruction, Dis_info *info)
15569 {
15570     (void)instruction;
15571 
15572     return g_strdup("TLBGWR ");
15573 }
15574 
15575 
15576 /*
15577  * ADDQH_R.W rd, rt, rs - Add Fractional Words And Shift Right to Halve Results
15578  *
15579  *   3         2         1
15580  *  10987654321098765432109876543210
15581  *  001000               00010001101
15582  *     rt -----
15583  *          rs -----
15584  *               rd -----
15585  */
15586 static char *TLBINV(uint64 instruction, Dis_info *info)
15587 {
15588     (void)instruction;
15589 
15590     return g_strdup("TLBINV ");
15591 }
15592 
15593 
15594 /*
15595  * ADDQH_R.W rd, rt, rs - Add Fractional Words And Shift Right to Halve Results
15596  *
15597  *   3         2         1
15598  *  10987654321098765432109876543210
15599  *  001000               00010001101
15600  *     rt -----
15601  *          rs -----
15602  *               rd -----
15603  */
15604 static char *TLBINVF(uint64 instruction, Dis_info *info)
15605 {
15606     (void)instruction;
15607 
15608     return g_strdup("TLBINVF ");
15609 }
15610 
15611 
15612 /*
15613  * ADDQH_R.W rd, rt, rs - Add Fractional Words And Shift Right to Halve Results
15614  *
15615  *   3         2         1
15616  *  10987654321098765432109876543210
15617  *  001000               00010001101
15618  *     rt -----
15619  *          rs -----
15620  *               rd -----
15621  */
15622 static char *TLBP(uint64 instruction, Dis_info *info)
15623 {
15624     (void)instruction;
15625 
15626     return g_strdup("TLBP ");
15627 }
15628 
15629 
15630 /*
15631  * ADDQH_R.W rd, rt, rs - Add Fractional Words And Shift Right to Halve Results
15632  *
15633  *   3         2         1
15634  *  10987654321098765432109876543210
15635  *  001000               00010001101
15636  *     rt -----
15637  *          rs -----
15638  *               rd -----
15639  */
15640 static char *TLBR(uint64 instruction, Dis_info *info)
15641 {
15642     (void)instruction;
15643 
15644     return g_strdup("TLBR ");
15645 }
15646 
15647 
15648 /*
15649  * ADDQH_R.W rd, rt, rs - Add Fractional Words And Shift Right to Halve Results
15650  *
15651  *   3         2         1
15652  *  10987654321098765432109876543210
15653  *  001000               00010001101
15654  *     rt -----
15655  *          rs -----
15656  *               rd -----
15657  */
15658 static char *TLBWI(uint64 instruction, Dis_info *info)
15659 {
15660     (void)instruction;
15661 
15662     return g_strdup("TLBWI ");
15663 }
15664 
15665 
15666 /*
15667  * ADDQH_R.W rd, rt, rs - Add Fractional Words And Shift Right to Halve Results
15668  *
15669  *   3         2         1
15670  *  10987654321098765432109876543210
15671  *  001000               00010001101
15672  *     rt -----
15673  *          rs -----
15674  *               rd -----
15675  */
15676 static char *TLBWR(uint64 instruction, Dis_info *info)
15677 {
15678     (void)instruction;
15679 
15680     return g_strdup("TLBWR ");
15681 }
15682 
15683 
15684 /*
15685  * ADDQH_R.W rd, rt, rs - Add Fractional Words And Shift Right to Halve Results
15686  *
15687  *   3         2         1
15688  *  10987654321098765432109876543210
15689  *  001000               00010001101
15690  *     rt -----
15691  *          rs -----
15692  *               rd -----
15693  */
15694 static char *TNE(uint64 instruction, Dis_info *info)
15695 {
15696     uint64 rt_value = extract_rt_25_24_23_22_21(instruction);
15697     uint64 rs_value = extract_rs_20_19_18_17_16(instruction);
15698 
15699     const char *rs = GPR(rs_value, info);
15700     const char *rt = GPR(rt_value, info);
15701 
15702     return img_format("TNE %s, %s", rs, rt);
15703 }
15704 
15705 
15706 /*
15707  * ADDQH_R.W rd, rt, rs - Add Fractional Words And Shift Right to Halve Results
15708  *
15709  *   3         2         1
15710  *  10987654321098765432109876543210
15711  *  001000               00010001101
15712  *     rt -----
15713  *          rs -----
15714  *               rd -----
15715  */
15716 static char *TRUNC_L_D(uint64 instruction, Dis_info *info)
15717 {
15718     uint64 ft_value = extract_ft_25_24_23_22_21(instruction);
15719     uint64 fs_value = extract_fs_20_19_18_17_16(instruction);
15720 
15721     const char *ft = FPR(ft_value, info);
15722     const char *fs = FPR(fs_value, info);
15723 
15724     return img_format("TRUNC.L.D %s, %s", ft, fs);
15725 }
15726 
15727 
15728 /*
15729  * ADDQH_R.W rd, rt, rs - Add Fractional Words And Shift Right to Halve Results
15730  *
15731  *   3         2         1
15732  *  10987654321098765432109876543210
15733  *  001000               00010001101
15734  *     rt -----
15735  *          rs -----
15736  *               rd -----
15737  */
15738 static char *TRUNC_L_S(uint64 instruction, Dis_info *info)
15739 {
15740     uint64 ft_value = extract_ft_25_24_23_22_21(instruction);
15741     uint64 fs_value = extract_fs_20_19_18_17_16(instruction);
15742 
15743     const char *ft = FPR(ft_value, info);
15744     const char *fs = FPR(fs_value, info);
15745 
15746     return img_format("TRUNC.L.S %s, %s", ft, fs);
15747 }
15748 
15749 
15750 /*
15751  * ADDQH_R.W rd, rt, rs - Add Fractional Words And Shift Right to Halve Results
15752  *
15753  *   3         2         1
15754  *  10987654321098765432109876543210
15755  *  001000               00010001101
15756  *     rt -----
15757  *          rs -----
15758  *               rd -----
15759  */
15760 static char *TRUNC_W_D(uint64 instruction, Dis_info *info)
15761 {
15762     uint64 ft_value = extract_ft_25_24_23_22_21(instruction);
15763     uint64 fs_value = extract_fs_20_19_18_17_16(instruction);
15764 
15765     const char *ft = FPR(ft_value, info);
15766     const char *fs = FPR(fs_value, info);
15767 
15768     return img_format("TRUNC.W.D %s, %s", ft, fs);
15769 }
15770 
15771 
15772 /*
15773  * ADDQH_R.W rd, rt, rs - Add Fractional Words And Shift Right to Halve Results
15774  *
15775  *   3         2         1
15776  *  10987654321098765432109876543210
15777  *  001000               00010001101
15778  *     rt -----
15779  *          rs -----
15780  *               rd -----
15781  */
15782 static char *TRUNC_W_S(uint64 instruction, Dis_info *info)
15783 {
15784     uint64 ft_value = extract_ft_25_24_23_22_21(instruction);
15785     uint64 fs_value = extract_fs_20_19_18_17_16(instruction);
15786 
15787     const char *ft = FPR(ft_value, info);
15788     const char *fs = FPR(fs_value, info);
15789 
15790     return img_format("TRUNC.W.S %s, %s", ft, fs);
15791 }
15792 
15793 
15794 /*
15795  * ADDQH_R.W rd, rt, rs - Add Fractional Words And Shift Right to Halve Results
15796  *
15797  *   3         2         1
15798  *  10987654321098765432109876543210
15799  *  001000               00010001101
15800  *     rt -----
15801  *          rs -----
15802  *               rd -----
15803  */
15804 static char *UALDM(uint64 instruction, Dis_info *info)
15805 {
15806     uint64 rt_value = extract_rt_25_24_23_22_21(instruction);
15807     uint64 rs_value = extract_rs_20_19_18_17_16(instruction);
15808     int64 s_value = extract_s__se8_15_7_6_5_4_3_2_1_0(instruction);
15809     uint64 count3_value = extract_count3_14_13_12(instruction);
15810 
15811     const char *rt = GPR(rt_value, info);
15812     const char *rs = GPR(rs_value, info);
15813     uint64 count3 = encode_count3_from_count(count3_value);
15814 
15815     return img_format("UALDM %s, %" PRId64 "(%s), 0x%" PRIx64,
15816                       rt, s_value, rs, count3);
15817 }
15818 
15819 
15820 /*
15821  * ADDQH_R.W rd, rt, rs - Add Fractional Words And Shift Right to Halve Results
15822  *
15823  *   3         2         1
15824  *  10987654321098765432109876543210
15825  *  001000               00010001101
15826  *     rt -----
15827  *          rs -----
15828  *               rd -----
15829  */
15830 static char *UALH(uint64 instruction, Dis_info *info)
15831 {
15832     uint64 rt_value = extract_rt_25_24_23_22_21(instruction);
15833     uint64 rs_value = extract_rs_20_19_18_17_16(instruction);
15834     int64 s_value = extract_s__se8_15_7_6_5_4_3_2_1_0(instruction);
15835 
15836     const char *rt = GPR(rt_value, info);
15837     const char *rs = GPR(rs_value, info);
15838 
15839     return img_format("UALH %s, %" PRId64 "(%s)", rt, s_value, rs);
15840 }
15841 
15842 
15843 /*
15844  * ADDQH_R.W rd, rt, rs - Add Fractional Words And Shift Right to Halve Results
15845  *
15846  *   3         2         1
15847  *  10987654321098765432109876543210
15848  *  001000               00010001101
15849  *     rt -----
15850  *          rs -----
15851  *               rd -----
15852  */
15853 static char *UALWM(uint64 instruction, Dis_info *info)
15854 {
15855     uint64 rt_value = extract_rt_25_24_23_22_21(instruction);
15856     uint64 rs_value = extract_rs_20_19_18_17_16(instruction);
15857     int64 s_value = extract_s__se8_15_7_6_5_4_3_2_1_0(instruction);
15858     uint64 count3_value = extract_count3_14_13_12(instruction);
15859 
15860     const char *rt = GPR(rt_value, info);
15861     const char *rs = GPR(rs_value, info);
15862     uint64 count3 = encode_count3_from_count(count3_value);
15863 
15864     return img_format("UALWM %s, %" PRId64 "(%s), 0x%" PRIx64,
15865                       rt, s_value, rs, count3);
15866 }
15867 
15868 
15869 /*
15870  * ADDQH_R.W rd, rt, rs - Add Fractional Words And Shift Right to Halve Results
15871  *
15872  *   3         2         1
15873  *  10987654321098765432109876543210
15874  *  001000               00010001101
15875  *     rt -----
15876  *          rs -----
15877  *               rd -----
15878  */
15879 static char *UASDM(uint64 instruction, Dis_info *info)
15880 {
15881     uint64 rt_value = extract_rt_25_24_23_22_21(instruction);
15882     uint64 rs_value = extract_rs_20_19_18_17_16(instruction);
15883     int64 s_value = extract_s__se8_15_7_6_5_4_3_2_1_0(instruction);
15884     uint64 count3_value = extract_count3_14_13_12(instruction);
15885 
15886     const char *rt = GPR(rt_value, info);
15887     const char *rs = GPR(rs_value, info);
15888     uint64 count3 = encode_count3_from_count(count3_value);
15889 
15890     return img_format("UASDM %s, %" PRId64 "(%s), 0x%" PRIx64,
15891                       rt, s_value, rs, count3);
15892 }
15893 
15894 
15895 /*
15896  * ADDQH_R.W rd, rt, rs - Add Fractional Words And Shift Right to Halve Results
15897  *
15898  *   3         2         1
15899  *  10987654321098765432109876543210
15900  *  001000               00010001101
15901  *     rt -----
15902  *          rs -----
15903  *               rd -----
15904  */
15905 static char *UASH(uint64 instruction, Dis_info *info)
15906 {
15907     uint64 rt_value = extract_rt_25_24_23_22_21(instruction);
15908     uint64 rs_value = extract_rs_20_19_18_17_16(instruction);
15909     int64 s_value = extract_s__se8_15_7_6_5_4_3_2_1_0(instruction);
15910 
15911     const char *rt = GPR(rt_value, info);
15912     const char *rs = GPR(rs_value, info);
15913 
15914     return img_format("UASH %s, %" PRId64 "(%s)", rt, s_value, rs);
15915 }
15916 
15917 
15918 /*
15919  * ADDQH_R.W rd, rt, rs - Add Fractional Words And Shift Right to Halve Results
15920  *
15921  *   3         2         1
15922  *  10987654321098765432109876543210
15923  *  001000               00010001101
15924  *     rt -----
15925  *          rs -----
15926  *               rd -----
15927  */
15928 static char *UASWM(uint64 instruction, Dis_info *info)
15929 {
15930     uint64 rt_value = extract_rt_25_24_23_22_21(instruction);
15931     uint64 rs_value = extract_rs_20_19_18_17_16(instruction);
15932     int64 s_value = extract_s__se8_15_7_6_5_4_3_2_1_0(instruction);
15933     uint64 count3_value = extract_count3_14_13_12(instruction);
15934 
15935     const char *rt = GPR(rt_value, info);
15936     const char *rs = GPR(rs_value, info);
15937     uint64 count3 = encode_count3_from_count(count3_value);
15938 
15939     return img_format("UASWM %s, %" PRId64 "(%s), 0x%" PRIx64,
15940                       rt, s_value, rs, count3);
15941 }
15942 
15943 
15944 /*
15945  * ADDQH_R.W rd, rt, rs - Add Fractional Words And Shift Right to Halve Results
15946  *
15947  *   3         2         1
15948  *  10987654321098765432109876543210
15949  *  001000               00010001101
15950  *     rt -----
15951  *          rs -----
15952  *               rd -----
15953  */
15954 static char *UDI(uint64 instruction, Dis_info *info)
15955 {
15956     uint64 op_value = extract_op_25_to_3(instruction);
15957 
15958 
15959     return img_format("UDI 0x%" PRIx64, op_value);
15960 }
15961 
15962 
15963 /*
15964  * WAIT code - Enter Wait State
15965  *
15966  *   3         2         1
15967  *  10987654321098765432109876543210
15968  *  001000          1100001101111111
15969  *   code ----------
15970  */
15971 static char *WAIT(uint64 instruction, Dis_info *info)
15972 {
15973     uint64 code_value = extract_code_25_24_23_22_21_20_19_18_17_16(instruction);
15974 
15975 
15976     return img_format("WAIT 0x%" PRIx64, code_value);
15977 }
15978 
15979 
15980 /*
15981  * [DSP] WRDSP rt, mask - Write selected fields from a GPR to the DSPControl
15982  *         register
15983  *
15984  *   3         2         1
15985  *  10987654321098765432109876543210
15986  *  001000            01011001111111
15987  *     rt -----
15988  *        mask -------
15989  */
15990 static char *WRDSP(uint64 instruction, Dis_info *info)
15991 {
15992     uint64 rt_value = extract_rt_25_24_23_22_21(instruction);
15993     uint64 mask_value = extract_mask_20_19_18_17_16_15_14(instruction);
15994 
15995     const char *rt = GPR(rt_value, info);
15996 
15997     return img_format("WRDSP %s, 0x%" PRIx64, rt, mask_value);
15998 }
15999 
16000 
16001 /*
16002  * ADDQH_R.W rd, rt, rs - Add Fractional Words And Shift Right to Halve Results
16003  *
16004  *   3         2         1
16005  *  10987654321098765432109876543210
16006  *  001000               00010001101
16007  *     rt -----
16008  *          rs -----
16009  *               rd -----
16010  */
16011 static char *WRPGPR(uint64 instruction, Dis_info *info)
16012 {
16013     uint64 rt_value = extract_rt_25_24_23_22_21(instruction);
16014     uint64 rs_value = extract_rs_20_19_18_17_16(instruction);
16015 
16016     const char *rt = GPR(rt_value, info);
16017     const char *rs = GPR(rs_value, info);
16018 
16019     return img_format("WRPGPR %s, %s", rt, rs);
16020 }
16021 
16022 
16023 /*
16024  * ADDQH_R.W rd, rt, rs - Add Fractional Words And Shift Right to Halve Results
16025  *
16026  *   3         2         1
16027  *  10987654321098765432109876543210
16028  *  001000               00010001101
16029  *     rt -----
16030  *          rs -----
16031  *               rd -----
16032  */
16033 static char *XOR_16_(uint64 instruction, Dis_info *info)
16034 {
16035     uint64 rt3_value = extract_rt3_9_8_7(instruction);
16036     uint64 rs3_value = extract_rs3_6_5_4(instruction);
16037 
16038     const char *rs3 = GPR(decode_gpr_gpr3(rs3_value, info), info);
16039     const char *rt3 = GPR(decode_gpr_gpr3(rt3_value, info), info);
16040 
16041     return img_format("XOR %s, %s", rs3, rt3);
16042 }
16043 
16044 
16045 /*
16046  * ADDQH_R.W rd, rt, rs - Add Fractional Words And Shift Right to Halve Results
16047  *
16048  *   3         2         1
16049  *  10987654321098765432109876543210
16050  *  001000               00010001101
16051  *     rt -----
16052  *          rs -----
16053  *               rd -----
16054  */
16055 static char *XOR_32_(uint64 instruction, Dis_info *info)
16056 {
16057     uint64 rt_value = extract_rt_25_24_23_22_21(instruction);
16058     uint64 rs_value = extract_rs_20_19_18_17_16(instruction);
16059     uint64 rd_value = extract_rd_15_14_13_12_11(instruction);
16060 
16061     const char *rd = GPR(rd_value, info);
16062     const char *rs = GPR(rs_value, info);
16063     const char *rt = GPR(rt_value, info);
16064 
16065     return img_format("XOR %s, %s, %s", rd, rs, rt);
16066 }
16067 
16068 
16069 /*
16070  * ADDQH_R.W rd, rt, rs - Add Fractional Words And Shift Right to Halve Results
16071  *
16072  *   3         2         1
16073  *  10987654321098765432109876543210
16074  *  001000               00010001101
16075  *     rt -----
16076  *          rs -----
16077  *               rd -----
16078  */
16079 static char *XORI(uint64 instruction, Dis_info *info)
16080 {
16081     uint64 rt_value = extract_rt_25_24_23_22_21(instruction);
16082     uint64 rs_value = extract_rs_20_19_18_17_16(instruction);
16083     uint64 u_value = extract_u_11_10_9_8_7_6_5_4_3_2_1_0(instruction);
16084 
16085     const char *rt = GPR(rt_value, info);
16086     const char *rs = GPR(rs_value, info);
16087 
16088     return img_format("XORI %s, %s, 0x%" PRIx64, rt, rs, u_value);
16089 }
16090 
16091 
16092 /*
16093  * YIELD rt, rs -
16094  *
16095  *   3         2         1
16096  *  10987654321098765432109876543210
16097  *  001000               00010001101
16098  *     rt -----
16099  *          rs -----
16100  */
16101 static char *YIELD(uint64 instruction, Dis_info *info)
16102 {
16103     uint64 rt_value = extract_rt_25_24_23_22_21(instruction);
16104     uint64 rs_value = extract_rs_20_19_18_17_16(instruction);
16105 
16106     const char *rt = GPR(rt_value, info);
16107     const char *rs = GPR(rs_value, info);
16108 
16109     return img_format("YIELD %s, %s", rt, rs);
16110 }
16111 
16112 
16113 
16114 /*
16115  *                nanoMIPS instruction pool organization
16116  *                ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
16117  *
16118  *
16119  *                 ┌─ P.ADDIU ─── P.RI ─── P.SYSCALL
16120  *                 │
16121  *                 │                                      ┌─ P.TRAP
16122  *                 │                                      │
16123  *                 │                      ┌─ _POOL32A0_0 ─┼─ P.CMOVE
16124  *                 │                      │               │
16125  *                 │                      │               └─ P.SLTU
16126  *                 │        ┌─ _POOL32A0 ─┤
16127  *                 │        │             │
16128  *                 │        │             │
16129  *                 │        │             └─ _POOL32A0_1 ─── CRC32
16130  *                 │        │
16131  *                 ├─ P32A ─┤
16132  *                 │        │                           ┌─ PP.LSX
16133  *                 │        │             ┌─ P.LSX ─────┤
16134  *                 │        │             │             └─ PP.LSXS
16135  *                 │        └─ _POOL32A7 ─┤
16136  *                 │                      │             ┌─ POOL32Axf_4
16137  *                 │                      └─ POOL32Axf ─┤
16138  *                 │                                    └─ POOL32Axf_5
16139  *                 │
16140  *                 ├─ PBAL
16141  *                 │
16142  *                 ├─ P.GP.W   ┌─ PP.LSX
16143  *         ┌─ P32 ─┤           │
16144  *         │       ├─ P.GP.BH ─┴─ PP.LSXS
16145  *         │       │
16146  *         │       ├─ P.J ─────── PP.BALRSC
16147  *         │       │
16148  *         │       ├─ P48I
16149  *         │       │           ┌─ P.SR
16150  *         │       │           │
16151  *         │       │           ├─ P.SHIFT
16152  *         │       │           │
16153  *         │       ├─ P.U12 ───┼─ P.ROTX
16154  *         │       │           │
16155  *         │       │           ├─ P.INS
16156  *         │       │           │
16157  *         │       │           └─ P.EXT
16158  *         │       │
16159  *         │       ├─ P.LS.U12 ── P.PREF.U12
16160  *         │       │
16161  *         │       ├─ P.BR1 ───── P.BR3A
16162  *         │       │
16163  *         │       │           ┌─ P.LS.S0 ─── P16.SYSCALL
16164  *         │       │           │
16165  *         │       │           │           ┌─ P.LL
16166  *         │       │           ├─ P.LS.S1 ─┤
16167  *         │       │           │           └─ P.SC
16168  *         │       │           │
16169  *         │       │           │           ┌─ P.PREFE
16170  *  MAJOR ─┤       ├─ P.LS.S9 ─┤           │
16171  *         │       │           ├─ P.LS.E0 ─┼─ P.LLE
16172  *         │       │           │           │
16173  *         │       │           │           └─ P.SCE
16174  *         │       │           │
16175  *         │       │           ├─ P.LS.WM
16176  *         │       │           │
16177  *         │       │           └─ P.LS.UAWM
16178  *         │       │
16179  *         │       │
16180  *         │       ├─ P.BR2
16181  *         │       │
16182  *         │       ├─ P.BRI
16183  *         │       │
16184  *         │       └─ P.LUI
16185  *         │
16186  *         │
16187  *         │       ┌─ P16.MV ──── P16.RI ─── P16.SYSCALL
16188  *         │       │
16189  *         │       ├─ P16.SR
16190  *         │       │
16191  *         │       ├─ P16.SHIFT
16192  *         │       │
16193  *         │       ├─ P16.4x4
16194  *         │       │
16195  *         │       ├─ P16C ────── POOL16C_0 ── POOL16C_00
16196  *         │       │
16197  *         └─ P16 ─┼─ P16.LB
16198  *                 │
16199  *                 ├─ P16.A1
16200  *                 │
16201  *                 ├─ P16.LH
16202  *                 │
16203  *                 ├─ P16.A2 ──── P.ADDIU[RS5]
16204  *                 │
16205  *                 ├─ P16.ADDU
16206  *                 │
16207  *                 └─ P16.BR ──┬─ P16.JRC
16208  *                             │
16209  *                             └─ P16.BR1
16210  *
16211  *
16212  *  (FP, DPS, and some minor instruction pools are omitted from the diagram)
16213  *
16214  */
16215 
16216 static const Pool P_SYSCALL[2] = {
16217     { instruction         , 0                   , 0   , 32,
16218        0xfffc0000, 0x00080000, &SYSCALL_32_      , 0,
16219        0x0                 },        /* SYSCALL[32] */
16220     { instruction         , 0                   , 0   , 32,
16221        0xfffc0000, 0x000c0000, &HYPCALL          , 0,
16222        CP0_ | VZ_          },        /* HYPCALL */
16223 };
16224 
16225 
16226 static const Pool P_RI[4] = {
16227     { instruction         , 0                   , 0   , 32,
16228        0xfff80000, 0x00000000, &SIGRIE           , 0,
16229        0x0                 },        /* SIGRIE */
16230     { pool                , P_SYSCALL           , 2   , 32,
16231        0xfff80000, 0x00080000, 0                      , 0,
16232        0x0                 },        /* P.SYSCALL */
16233     { instruction         , 0                   , 0   , 32,
16234        0xfff80000, 0x00100000, &BREAK_32_        , 0,
16235        0x0                 },        /* BREAK[32] */
16236     { instruction         , 0                   , 0   , 32,
16237        0xfff80000, 0x00180000, &SDBBP_32_        , 0,
16238        EJTAG_              },        /* SDBBP[32] */
16239 };
16240 
16241 
16242 static const Pool P_ADDIU[2] = {
16243     { pool                , P_RI                , 4   , 32,
16244        0xffe00000, 0x00000000, 0                      , 0,
16245        0x0                 },        /* P.RI */
16246     { instruction         , 0                   , 0   , 32,
16247        0xfc000000, 0x00000000, &ADDIU_32_        , &ADDIU_32__cond   ,
16248        0x0                 },        /* ADDIU[32] */
16249 };
16250 
16251 
16252 static const Pool P_TRAP[2] = {
16253     { instruction         , 0                   , 0   , 32,
16254        0xfc0007ff, 0x20000000, &TEQ              , 0,
16255        XMMS_               },        /* TEQ */
16256     { instruction         , 0                   , 0   , 32,
16257        0xfc0007ff, 0x20000400, &TNE              , 0,
16258        XMMS_               },        /* TNE */
16259 };
16260 
16261 
16262 static const Pool P_CMOVE[2] = {
16263     { instruction         , 0                   , 0   , 32,
16264        0xfc0007ff, 0x20000210, &MOVZ             , 0,
16265        0x0                 },        /* MOVZ */
16266     { instruction         , 0                   , 0   , 32,
16267        0xfc0007ff, 0x20000610, &MOVN             , 0,
16268        0x0                 },        /* MOVN */
16269 };
16270 
16271 
16272 static const Pool P_D_MT_VPE[2] = {
16273     { instruction         , 0                   , 0   , 32,
16274        0xfc1f3fff, 0x20010ab0, &DMT              , 0,
16275        MT_                 },        /* DMT */
16276     { instruction         , 0                   , 0   , 32,
16277        0xfc1f3fff, 0x20000ab0, &DVPE             , 0,
16278        MT_                 },        /* DVPE */
16279 };
16280 
16281 
16282 static const Pool P_E_MT_VPE[2] = {
16283     { instruction         , 0                   , 0   , 32,
16284        0xfc1f3fff, 0x20010eb0, &EMT              , 0,
16285        MT_                 },        /* EMT */
16286     { instruction         , 0                   , 0   , 32,
16287        0xfc1f3fff, 0x20000eb0, &EVPE             , 0,
16288        MT_                 },        /* EVPE */
16289 };
16290 
16291 
16292 static const Pool _P_MT_VPE[2] = {
16293     { pool                , P_D_MT_VPE          , 2   , 32,
16294        0xfc003fff, 0x20000ab0, 0                      , 0,
16295        0x0                 },        /* P.D_MT_VPE */
16296     { pool                , P_E_MT_VPE          , 2   , 32,
16297        0xfc003fff, 0x20000eb0, 0                      , 0,
16298        0x0                 },        /* P.E_MT_VPE */
16299 };
16300 
16301 
16302 static const Pool P_MT_VPE[8] = {
16303     { reserved_block      , 0                   , 0   , 32,
16304        0xfc003bff, 0x200002b0, 0                      , 0,
16305        0x0                 },        /* P.MT_VPE~*(0) */
16306     { pool                , _P_MT_VPE           , 2   , 32,
16307        0xfc003bff, 0x20000ab0, 0                      , 0,
16308        0x0                 },        /* _P.MT_VPE */
16309     { reserved_block      , 0                   , 0   , 32,
16310        0xfc003bff, 0x200012b0, 0                      , 0,
16311        0x0                 },        /* P.MT_VPE~*(2) */
16312     { reserved_block      , 0                   , 0   , 32,
16313        0xfc003bff, 0x20001ab0, 0                      , 0,
16314        0x0                 },        /* P.MT_VPE~*(3) */
16315     { reserved_block      , 0                   , 0   , 32,
16316        0xfc003bff, 0x200022b0, 0                      , 0,
16317        0x0                 },        /* P.MT_VPE~*(4) */
16318     { reserved_block      , 0                   , 0   , 32,
16319        0xfc003bff, 0x20002ab0, 0                      , 0,
16320        0x0                 },        /* P.MT_VPE~*(5) */
16321     { reserved_block      , 0                   , 0   , 32,
16322        0xfc003bff, 0x200032b0, 0                      , 0,
16323        0x0                 },        /* P.MT_VPE~*(6) */
16324     { reserved_block      , 0                   , 0   , 32,
16325        0xfc003bff, 0x20003ab0, 0                      , 0,
16326        0x0                 },        /* P.MT_VPE~*(7) */
16327 };
16328 
16329 
16330 static const Pool P_DVP[2] = {
16331     { instruction         , 0                   , 0   , 32,
16332        0xfc00ffff, 0x20000390, &DVP              , 0,
16333        0x0                 },        /* DVP */
16334     { instruction         , 0                   , 0   , 32,
16335        0xfc00ffff, 0x20000790, &EVP              , 0,
16336        0x0                 },        /* EVP */
16337 };
16338 
16339 
16340 static const Pool P_SLTU[2] = {
16341     { pool                , P_DVP               , 2   , 32,
16342        0xfc00fbff, 0x20000390, 0                      , 0,
16343        0x0                 },        /* P.DVP */
16344     { instruction         , 0                   , 0   , 32,
16345        0xfc0003ff, 0x20000390, &SLTU             , &SLTU_cond        ,
16346        0x0                 },        /* SLTU */
16347 };
16348 
16349 
16350 static const Pool _POOL32A0[128] = {
16351     { pool                , P_TRAP              , 2   , 32,
16352        0xfc0003ff, 0x20000000, 0                      , 0,
16353        0x0                 },        /* P.TRAP */
16354     { instruction         , 0                   , 0   , 32,
16355        0xfc0003ff, 0x20000008, &SEB              , 0,
16356        XMMS_               },        /* SEB */
16357     { instruction         , 0                   , 0   , 32,
16358        0xfc0003ff, 0x20000010, &SLLV             , 0,
16359        0x0                 },        /* SLLV */
16360     { instruction         , 0                   , 0   , 32,
16361        0xfc0003ff, 0x20000018, &MUL_32_          , 0,
16362        0x0                 },        /* MUL[32] */
16363     { reserved_block      , 0                   , 0   , 32,
16364        0xfc0003ff, 0x20000020, 0                      , 0,
16365        0x0                 },        /* _POOL32A0~*(4) */
16366     { reserved_block      , 0                   , 0   , 32,
16367        0xfc0003ff, 0x20000028, 0                      , 0,
16368        0x0                 },        /* _POOL32A0~*(5) */
16369     { instruction         , 0                   , 0   , 32,
16370        0xfc0003ff, 0x20000030, &MFC0             , 0,
16371        0x0                 },        /* MFC0 */
16372     { instruction         , 0                   , 0   , 32,
16373        0xfc0003ff, 0x20000038, &MFHC0            , 0,
16374        CP0_ | MVH_         },        /* MFHC0 */
16375     { reserved_block      , 0                   , 0   , 32,
16376        0xfc0003ff, 0x20000040, 0                      , 0,
16377        0x0                 },        /* _POOL32A0~*(8) */
16378     { instruction         , 0                   , 0   , 32,
16379        0xfc0003ff, 0x20000048, &SEH              , 0,
16380        0x0                 },        /* SEH */
16381     { instruction         , 0                   , 0   , 32,
16382        0xfc0003ff, 0x20000050, &SRLV             , 0,
16383        0x0                 },        /* SRLV */
16384     { instruction         , 0                   , 0   , 32,
16385        0xfc0003ff, 0x20000058, &MUH              , 0,
16386        0x0                 },        /* MUH */
16387     { reserved_block      , 0                   , 0   , 32,
16388        0xfc0003ff, 0x20000060, 0                      , 0,
16389        0x0                 },        /* _POOL32A0~*(12) */
16390     { reserved_block      , 0                   , 0   , 32,
16391        0xfc0003ff, 0x20000068, 0                      , 0,
16392        0x0                 },        /* _POOL32A0~*(13) */
16393     { instruction         , 0                   , 0   , 32,
16394        0xfc0003ff, 0x20000070, &MTC0             , 0,
16395        CP0_                },        /* MTC0 */
16396     { instruction         , 0                   , 0   , 32,
16397        0xfc0003ff, 0x20000078, &MTHC0            , 0,
16398        CP0_ | MVH_         },        /* MTHC0 */
16399     { reserved_block      , 0                   , 0   , 32,
16400        0xfc0003ff, 0x20000080, 0                      , 0,
16401        0x0                 },        /* _POOL32A0~*(16) */
16402     { reserved_block      , 0                   , 0   , 32,
16403        0xfc0003ff, 0x20000088, 0                      , 0,
16404        0x0                 },        /* _POOL32A0~*(17) */
16405     { instruction         , 0                   , 0   , 32,
16406        0xfc0003ff, 0x20000090, &SRAV             , 0,
16407        0x0                 },        /* SRAV */
16408     { instruction         , 0                   , 0   , 32,
16409        0xfc0003ff, 0x20000098, &MULU             , 0,
16410        0x0                 },        /* MULU */
16411     { reserved_block      , 0                   , 0   , 32,
16412        0xfc0003ff, 0x200000a0, 0                      , 0,
16413        0x0                 },        /* _POOL32A0~*(20) */
16414     { reserved_block      , 0                   , 0   , 32,
16415        0xfc0003ff, 0x200000a8, 0                      , 0,
16416        0x0                 },        /* _POOL32A0~*(21) */
16417     { instruction         , 0                   , 0   , 32,
16418        0xfc0003ff, 0x200000b0, &MFGC0            , 0,
16419        CP0_ | VZ_          },        /* MFGC0 */
16420     { instruction         , 0                   , 0   , 32,
16421        0xfc0003ff, 0x200000b8, &MFHGC0           , 0,
16422        CP0_ | VZ_ | MVH_   },        /* MFHGC0 */
16423     { reserved_block      , 0                   , 0   , 32,
16424        0xfc0003ff, 0x200000c0, 0                      , 0,
16425        0x0                 },        /* _POOL32A0~*(24) */
16426     { reserved_block      , 0                   , 0   , 32,
16427        0xfc0003ff, 0x200000c8, 0                      , 0,
16428        0x0                 },        /* _POOL32A0~*(25) */
16429     { instruction         , 0                   , 0   , 32,
16430        0xfc0003ff, 0x200000d0, &ROTRV            , 0,
16431        0x0                 },        /* ROTRV */
16432     { instruction         , 0                   , 0   , 32,
16433        0xfc0003ff, 0x200000d8, &MUHU             , 0,
16434        0x0                 },        /* MUHU */
16435     { reserved_block      , 0                   , 0   , 32,
16436        0xfc0003ff, 0x200000e0, 0                      , 0,
16437        0x0                 },        /* _POOL32A0~*(28) */
16438     { reserved_block      , 0                   , 0   , 32,
16439        0xfc0003ff, 0x200000e8, 0                      , 0,
16440        0x0                 },        /* _POOL32A0~*(29) */
16441     { instruction         , 0                   , 0   , 32,
16442        0xfc0003ff, 0x200000f0, &MTGC0            , 0,
16443        CP0_ | VZ_          },        /* MTGC0 */
16444     { instruction         , 0                   , 0   , 32,
16445        0xfc0003ff, 0x200000f8, &MTHGC0           , 0,
16446        CP0_ | VZ_ | MVH_   },        /* MTHGC0 */
16447     { reserved_block      , 0                   , 0   , 32,
16448        0xfc0003ff, 0x20000100, 0                      , 0,
16449        0x0                 },        /* _POOL32A0~*(32) */
16450     { reserved_block      , 0                   , 0   , 32,
16451        0xfc0003ff, 0x20000108, 0                      , 0,
16452        0x0                 },        /* _POOL32A0~*(33) */
16453     { instruction         , 0                   , 0   , 32,
16454        0xfc0003ff, 0x20000110, &ADD              , 0,
16455        XMMS_               },        /* ADD */
16456     { instruction         , 0                   , 0   , 32,
16457        0xfc0003ff, 0x20000118, &DIV              , 0,
16458        0x0                 },        /* DIV */
16459     { reserved_block      , 0                   , 0   , 32,
16460        0xfc0003ff, 0x20000120, 0                      , 0,
16461        0x0                 },        /* _POOL32A0~*(36) */
16462     { reserved_block      , 0                   , 0   , 32,
16463        0xfc0003ff, 0x20000128, 0                      , 0,
16464        0x0                 },        /* _POOL32A0~*(37) */
16465     { instruction         , 0                   , 0   , 32,
16466        0xfc0003ff, 0x20000130, &DMFC0            , 0,
16467        CP0_ | MIPS64_      },        /* DMFC0 */
16468     { reserved_block      , 0                   , 0   , 32,
16469        0xfc0003ff, 0x20000138, 0                      , 0,
16470        0x0                 },        /* _POOL32A0~*(39) */
16471     { reserved_block      , 0                   , 0   , 32,
16472        0xfc0003ff, 0x20000140, 0                      , 0,
16473        0x0                 },        /* _POOL32A0~*(40) */
16474     { reserved_block      , 0                   , 0   , 32,
16475        0xfc0003ff, 0x20000148, 0                      , 0,
16476        0x0                 },        /* _POOL32A0~*(41) */
16477     { instruction         , 0                   , 0   , 32,
16478        0xfc0003ff, 0x20000150, &ADDU_32_         , 0,
16479        0x0                 },        /* ADDU[32] */
16480     { instruction         , 0                   , 0   , 32,
16481        0xfc0003ff, 0x20000158, &MOD              , 0,
16482        0x0                 },        /* MOD */
16483     { reserved_block      , 0                   , 0   , 32,
16484        0xfc0003ff, 0x20000160, 0                      , 0,
16485        0x0                 },        /* _POOL32A0~*(44) */
16486     { reserved_block      , 0                   , 0   , 32,
16487        0xfc0003ff, 0x20000168, 0                      , 0,
16488        0x0                 },        /* _POOL32A0~*(45) */
16489     { instruction         , 0                   , 0   , 32,
16490        0xfc0003ff, 0x20000170, &DMTC0            , 0,
16491        CP0_ | MIPS64_      },        /* DMTC0 */
16492     { reserved_block      , 0                   , 0   , 32,
16493        0xfc0003ff, 0x20000178, 0                      , 0,
16494        0x0                 },        /* _POOL32A0~*(47) */
16495     { reserved_block      , 0                   , 0   , 32,
16496        0xfc0003ff, 0x20000180, 0                      , 0,
16497        0x0                 },        /* _POOL32A0~*(48) */
16498     { reserved_block      , 0                   , 0   , 32,
16499        0xfc0003ff, 0x20000188, 0                      , 0,
16500        0x0                 },        /* _POOL32A0~*(49) */
16501     { instruction         , 0                   , 0   , 32,
16502        0xfc0003ff, 0x20000190, &SUB              , 0,
16503        XMMS_               },        /* SUB */
16504     { instruction         , 0                   , 0   , 32,
16505        0xfc0003ff, 0x20000198, &DIVU             , 0,
16506        0x0                 },        /* DIVU */
16507     { reserved_block      , 0                   , 0   , 32,
16508        0xfc0003ff, 0x200001a0, 0                      , 0,
16509        0x0                 },        /* _POOL32A0~*(52) */
16510     { reserved_block      , 0                   , 0   , 32,
16511        0xfc0003ff, 0x200001a8, 0                      , 0,
16512        0x0                 },        /* _POOL32A0~*(53) */
16513     { instruction         , 0                   , 0   , 32,
16514        0xfc0003ff, 0x200001b0, &DMFGC0           , 0,
16515        CP0_ | MIPS64_ | VZ_},        /* DMFGC0 */
16516     { reserved_block      , 0                   , 0   , 32,
16517        0xfc0003ff, 0x200001b8, 0                      , 0,
16518        0x0                 },        /* _POOL32A0~*(55) */
16519     { instruction         , 0                   , 0   , 32,
16520        0xfc0003ff, 0x200001c0, &RDHWR            , 0,
16521        XMMS_               },        /* RDHWR */
16522     { reserved_block      , 0                   , 0   , 32,
16523        0xfc0003ff, 0x200001c8, 0                      , 0,
16524        0x0                 },        /* _POOL32A0~*(57) */
16525     { instruction         , 0                   , 0   , 32,
16526        0xfc0003ff, 0x200001d0, &SUBU_32_         , 0,
16527        0x0                 },        /* SUBU[32] */
16528     { instruction         , 0                   , 0   , 32,
16529        0xfc0003ff, 0x200001d8, &MODU             , 0,
16530        0x0                 },        /* MODU */
16531     { reserved_block      , 0                   , 0   , 32,
16532        0xfc0003ff, 0x200001e0, 0                      , 0,
16533        0x0                 },        /* _POOL32A0~*(60) */
16534     { reserved_block      , 0                   , 0   , 32,
16535        0xfc0003ff, 0x200001e8, 0                      , 0,
16536        0x0                 },        /* _POOL32A0~*(61) */
16537     { instruction         , 0                   , 0   , 32,
16538        0xfc0003ff, 0x200001f0, &DMTGC0           , 0,
16539        CP0_ | MIPS64_ | VZ_},        /* DMTGC0 */
16540     { reserved_block      , 0                   , 0   , 32,
16541        0xfc0003ff, 0x200001f8, 0                      , 0,
16542        0x0                 },        /* _POOL32A0~*(63) */
16543     { reserved_block      , 0                   , 0   , 32,
16544        0xfc0003ff, 0x20000200, 0                      , 0,
16545        0x0                 },        /* _POOL32A0~*(64) */
16546     { reserved_block      , 0                   , 0   , 32,
16547        0xfc0003ff, 0x20000208, 0                      , 0,
16548        0x0                 },        /* _POOL32A0~*(65) */
16549     { pool                , P_CMOVE             , 2   , 32,
16550        0xfc0003ff, 0x20000210, 0                      , 0,
16551        0x0                 },        /* P.CMOVE */
16552     { reserved_block      , 0                   , 0   , 32,
16553        0xfc0003ff, 0x20000218, 0                      , 0,
16554        0x0                 },        /* _POOL32A0~*(67) */
16555     { reserved_block      , 0                   , 0   , 32,
16556        0xfc0003ff, 0x20000220, 0                      , 0,
16557        0x0                 },        /* _POOL32A0~*(68) */
16558     { instruction         , 0                   , 0   , 32,
16559        0xfc0003ff, 0x20000228, &FORK             , 0,
16560        MT_                 },        /* FORK */
16561     { instruction         , 0                   , 0   , 32,
16562        0xfc0003ff, 0x20000230, &MFTR             , 0,
16563        MT_                 },        /* MFTR */
16564     { instruction         , 0                   , 0   , 32,
16565        0xfc0003ff, 0x20000238, &MFHTR            , 0,
16566        MT_                 },        /* MFHTR */
16567     { reserved_block      , 0                   , 0   , 32,
16568        0xfc0003ff, 0x20000240, 0                      , 0,
16569        0x0                 },        /* _POOL32A0~*(72) */
16570     { reserved_block      , 0                   , 0   , 32,
16571        0xfc0003ff, 0x20000248, 0                      , 0,
16572        0x0                 },        /* _POOL32A0~*(73) */
16573     { instruction         , 0                   , 0   , 32,
16574        0xfc0003ff, 0x20000250, &AND_32_          , 0,
16575        0x0                 },        /* AND[32] */
16576     { reserved_block      , 0                   , 0   , 32,
16577        0xfc0003ff, 0x20000258, 0                      , 0,
16578        0x0                 },        /* _POOL32A0~*(75) */
16579     { reserved_block      , 0                   , 0   , 32,
16580        0xfc0003ff, 0x20000260, 0                      , 0,
16581        0x0                 },        /* _POOL32A0~*(76) */
16582     { instruction         , 0                   , 0   , 32,
16583        0xfc0003ff, 0x20000268, &YIELD            , 0,
16584        MT_                 },        /* YIELD */
16585     { instruction         , 0                   , 0   , 32,
16586        0xfc0003ff, 0x20000270, &MTTR             , 0,
16587        MT_                 },        /* MTTR */
16588     { instruction         , 0                   , 0   , 32,
16589        0xfc0003ff, 0x20000278, &MTHTR            , 0,
16590        MT_                 },        /* MTHTR */
16591     { reserved_block      , 0                   , 0   , 32,
16592        0xfc0003ff, 0x20000280, 0                      , 0,
16593        0x0                 },        /* _POOL32A0~*(80) */
16594     { reserved_block      , 0                   , 0   , 32,
16595        0xfc0003ff, 0x20000288, 0                      , 0,
16596        0x0                 },        /* _POOL32A0~*(81) */
16597     { instruction         , 0                   , 0   , 32,
16598        0xfc0003ff, 0x20000290, &OR_32_           , 0,
16599        0x0                 },        /* OR[32] */
16600     { reserved_block      , 0                   , 0   , 32,
16601        0xfc0003ff, 0x20000298, 0                      , 0,
16602        0x0                 },        /* _POOL32A0~*(83) */
16603     { reserved_block      , 0                   , 0   , 32,
16604        0xfc0003ff, 0x200002a0, 0                      , 0,
16605        0x0                 },        /* _POOL32A0~*(84) */
16606     { reserved_block      , 0                   , 0   , 32,
16607        0xfc0003ff, 0x200002a8, 0                      , 0,
16608        0x0                 },        /* _POOL32A0~*(85) */
16609     { pool                , P_MT_VPE            , 8   , 32,
16610        0xfc0003ff, 0x200002b0, 0                      , 0,
16611        0x0                 },        /* P.MT_VPE */
16612     { reserved_block      , 0                   , 0   , 32,
16613        0xfc0003ff, 0x200002b8, 0                      , 0,
16614        0x0                 },        /* _POOL32A0~*(87) */
16615     { reserved_block      , 0                   , 0   , 32,
16616        0xfc0003ff, 0x200002c0, 0                      , 0,
16617        0x0                 },        /* _POOL32A0~*(88) */
16618     { reserved_block      , 0                   , 0   , 32,
16619        0xfc0003ff, 0x200002c8, 0                      , 0,
16620        0x0                 },        /* _POOL32A0~*(89) */
16621     { instruction         , 0                   , 0   , 32,
16622        0xfc0003ff, 0x200002d0, &NOR              , 0,
16623        0x0                 },        /* NOR */
16624     { reserved_block      , 0                   , 0   , 32,
16625        0xfc0003ff, 0x200002d8, 0                      , 0,
16626        0x0                 },        /* _POOL32A0~*(91) */
16627     { reserved_block      , 0                   , 0   , 32,
16628        0xfc0003ff, 0x200002e0, 0                      , 0,
16629        0x0                 },        /* _POOL32A0~*(92) */
16630     { reserved_block      , 0                   , 0   , 32,
16631        0xfc0003ff, 0x200002e8, 0                      , 0,
16632        0x0                 },        /* _POOL32A0~*(93) */
16633     { reserved_block      , 0                   , 0   , 32,
16634        0xfc0003ff, 0x200002f0, 0                      , 0,
16635        0x0                 },        /* _POOL32A0~*(94) */
16636     { reserved_block      , 0                   , 0   , 32,
16637        0xfc0003ff, 0x200002f8, 0                      , 0,
16638        0x0                 },        /* _POOL32A0~*(95) */
16639     { reserved_block      , 0                   , 0   , 32,
16640        0xfc0003ff, 0x20000300, 0                      , 0,
16641        0x0                 },        /* _POOL32A0~*(96) */
16642     { reserved_block      , 0                   , 0   , 32,
16643        0xfc0003ff, 0x20000308, 0                      , 0,
16644        0x0                 },        /* _POOL32A0~*(97) */
16645     { instruction         , 0                   , 0   , 32,
16646        0xfc0003ff, 0x20000310, &XOR_32_          , 0,
16647        0x0                 },        /* XOR[32] */
16648     { reserved_block      , 0                   , 0   , 32,
16649        0xfc0003ff, 0x20000318, 0                      , 0,
16650        0x0                 },        /* _POOL32A0~*(99) */
16651     { reserved_block      , 0                   , 0   , 32,
16652        0xfc0003ff, 0x20000320, 0                      , 0,
16653        0x0                 },        /* _POOL32A0~*(100) */
16654     { reserved_block      , 0                   , 0   , 32,
16655        0xfc0003ff, 0x20000328, 0                      , 0,
16656        0x0                 },        /* _POOL32A0~*(101) */
16657     { reserved_block      , 0                   , 0   , 32,
16658        0xfc0003ff, 0x20000330, 0                      , 0,
16659        0x0                 },        /* _POOL32A0~*(102) */
16660     { reserved_block      , 0                   , 0   , 32,
16661        0xfc0003ff, 0x20000338, 0                      , 0,
16662        0x0                 },        /* _POOL32A0~*(103) */
16663     { reserved_block      , 0                   , 0   , 32,
16664        0xfc0003ff, 0x20000340, 0                      , 0,
16665        0x0                 },        /* _POOL32A0~*(104) */
16666     { reserved_block      , 0                   , 0   , 32,
16667        0xfc0003ff, 0x20000348, 0                      , 0,
16668        0x0                 },        /* _POOL32A0~*(105) */
16669     { instruction         , 0                   , 0   , 32,
16670        0xfc0003ff, 0x20000350, &SLT              , 0,
16671        0x0                 },        /* SLT */
16672     { reserved_block      , 0                   , 0   , 32,
16673        0xfc0003ff, 0x20000358, 0                      , 0,
16674        0x0                 },        /* _POOL32A0~*(107) */
16675     { reserved_block      , 0                   , 0   , 32,
16676        0xfc0003ff, 0x20000360, 0                      , 0,
16677        0x0                 },        /* _POOL32A0~*(108) */
16678     { reserved_block      , 0                   , 0   , 32,
16679        0xfc0003ff, 0x20000368, 0                      , 0,
16680        0x0                 },        /* _POOL32A0~*(109) */
16681     { reserved_block      , 0                   , 0   , 32,
16682        0xfc0003ff, 0x20000370, 0                      , 0,
16683        0x0                 },        /* _POOL32A0~*(110) */
16684     { reserved_block      , 0                   , 0   , 32,
16685        0xfc0003ff, 0x20000378, 0                      , 0,
16686        0x0                 },        /* _POOL32A0~*(111) */
16687     { reserved_block      , 0                   , 0   , 32,
16688        0xfc0003ff, 0x20000380, 0                      , 0,
16689        0x0                 },        /* _POOL32A0~*(112) */
16690     { reserved_block      , 0                   , 0   , 32,
16691        0xfc0003ff, 0x20000388, 0                      , 0,
16692        0x0                 },        /* _POOL32A0~*(113) */
16693     { pool                , P_SLTU              , 2   , 32,
16694        0xfc0003ff, 0x20000390, 0                      , 0,
16695        0x0                 },        /* P.SLTU */
16696     { reserved_block      , 0                   , 0   , 32,
16697        0xfc0003ff, 0x20000398, 0                      , 0,
16698        0x0                 },        /* _POOL32A0~*(115) */
16699     { reserved_block      , 0                   , 0   , 32,
16700        0xfc0003ff, 0x200003a0, 0                      , 0,
16701        0x0                 },        /* _POOL32A0~*(116) */
16702     { reserved_block      , 0                   , 0   , 32,
16703        0xfc0003ff, 0x200003a8, 0                      , 0,
16704        0x0                 },        /* _POOL32A0~*(117) */
16705     { reserved_block      , 0                   , 0   , 32,
16706        0xfc0003ff, 0x200003b0, 0                      , 0,
16707        0x0                 },        /* _POOL32A0~*(118) */
16708     { reserved_block      , 0                   , 0   , 32,
16709        0xfc0003ff, 0x200003b8, 0                      , 0,
16710        0x0                 },        /* _POOL32A0~*(119) */
16711     { reserved_block      , 0                   , 0   , 32,
16712        0xfc0003ff, 0x200003c0, 0                      , 0,
16713        0x0                 },        /* _POOL32A0~*(120) */
16714     { reserved_block      , 0                   , 0   , 32,
16715        0xfc0003ff, 0x200003c8, 0                      , 0,
16716        0x0                 },        /* _POOL32A0~*(121) */
16717     { instruction         , 0                   , 0   , 32,
16718        0xfc0003ff, 0x200003d0, &SOV              , 0,
16719        0x0                 },        /* SOV */
16720     { reserved_block      , 0                   , 0   , 32,
16721        0xfc0003ff, 0x200003d8, 0                      , 0,
16722        0x0                 },        /* _POOL32A0~*(123) */
16723     { reserved_block      , 0                   , 0   , 32,
16724        0xfc0003ff, 0x200003e0, 0                      , 0,
16725        0x0                 },        /* _POOL32A0~*(124) */
16726     { reserved_block      , 0                   , 0   , 32,
16727        0xfc0003ff, 0x200003e8, 0                      , 0,
16728        0x0                 },        /* _POOL32A0~*(125) */
16729     { reserved_block      , 0                   , 0   , 32,
16730        0xfc0003ff, 0x200003f0, 0                      , 0,
16731        0x0                 },        /* _POOL32A0~*(126) */
16732     { reserved_block      , 0                   , 0   , 32,
16733        0xfc0003ff, 0x200003f8, 0                      , 0,
16734        0x0                 },        /* _POOL32A0~*(127) */
16735 };
16736 
16737 
16738 static const Pool ADDQ__S__PH[2] = {
16739     { instruction         , 0                   , 0   , 32,
16740        0xfc0007ff, 0x2000000d, &ADDQ_PH          , 0,
16741        DSP_                },        /* ADDQ.PH */
16742     { instruction         , 0                   , 0   , 32,
16743        0xfc0007ff, 0x2000040d, &ADDQ_S_PH        , 0,
16744        DSP_                },        /* ADDQ_S.PH */
16745 };
16746 
16747 
16748 static const Pool MUL__S__PH[2] = {
16749     { instruction         , 0                   , 0   , 32,
16750        0xfc0007ff, 0x2000002d, &MUL_PH           , 0,
16751        DSP_                },        /* MUL.PH */
16752     { instruction         , 0                   , 0   , 32,
16753        0xfc0007ff, 0x2000042d, &MUL_S_PH         , 0,
16754        DSP_                },        /* MUL_S.PH */
16755 };
16756 
16757 
16758 static const Pool ADDQH__R__PH[2] = {
16759     { instruction         , 0                   , 0   , 32,
16760        0xfc0007ff, 0x2000004d, &ADDQH_PH         , 0,
16761        DSP_                },        /* ADDQH.PH */
16762     { instruction         , 0                   , 0   , 32,
16763        0xfc0007ff, 0x2000044d, &ADDQH_R_PH       , 0,
16764        DSP_                },        /* ADDQH_R.PH */
16765 };
16766 
16767 
16768 static const Pool ADDQH__R__W[2] = {
16769     { instruction         , 0                   , 0   , 32,
16770        0xfc0007ff, 0x2000008d, &ADDQH_W          , 0,
16771        DSP_                },        /* ADDQH.W */
16772     { instruction         , 0                   , 0   , 32,
16773        0xfc0007ff, 0x2000048d, &ADDQH_R_W        , 0,
16774        DSP_                },        /* ADDQH_R.W */
16775 };
16776 
16777 
16778 static const Pool ADDU__S__QB[2] = {
16779     { instruction         , 0                   , 0   , 32,
16780        0xfc0007ff, 0x200000cd, &ADDU_QB          , 0,
16781        DSP_                },        /* ADDU.QB */
16782     { instruction         , 0                   , 0   , 32,
16783        0xfc0007ff, 0x200004cd, &ADDU_S_QB        , 0,
16784        DSP_                },        /* ADDU_S.QB */
16785 };
16786 
16787 
16788 static const Pool ADDU__S__PH[2] = {
16789     { instruction         , 0                   , 0   , 32,
16790        0xfc0007ff, 0x2000010d, &ADDU_PH          , 0,
16791        DSP_                },        /* ADDU.PH */
16792     { instruction         , 0                   , 0   , 32,
16793        0xfc0007ff, 0x2000050d, &ADDU_S_PH        , 0,
16794        DSP_                },        /* ADDU_S.PH */
16795 };
16796 
16797 
16798 static const Pool ADDUH__R__QB[2] = {
16799     { instruction         , 0                   , 0   , 32,
16800        0xfc0007ff, 0x2000014d, &ADDUH_QB         , 0,
16801        DSP_                },        /* ADDUH.QB */
16802     { instruction         , 0                   , 0   , 32,
16803        0xfc0007ff, 0x2000054d, &ADDUH_R_QB       , 0,
16804        DSP_                },        /* ADDUH_R.QB */
16805 };
16806 
16807 
16808 static const Pool SHRAV__R__PH[2] = {
16809     { instruction         , 0                   , 0   , 32,
16810        0xfc0007ff, 0x2000018d, &SHRAV_PH         , 0,
16811        DSP_                },        /* SHRAV.PH */
16812     { instruction         , 0                   , 0   , 32,
16813        0xfc0007ff, 0x2000058d, &SHRAV_R_PH       , 0,
16814        DSP_                },        /* SHRAV_R.PH */
16815 };
16816 
16817 
16818 static const Pool SHRAV__R__QB[2] = {
16819     { instruction         , 0                   , 0   , 32,
16820        0xfc0007ff, 0x200001cd, &SHRAV_QB         , 0,
16821        DSP_                },        /* SHRAV.QB */
16822     { instruction         , 0                   , 0   , 32,
16823        0xfc0007ff, 0x200005cd, &SHRAV_R_QB       , 0,
16824        DSP_                },        /* SHRAV_R.QB */
16825 };
16826 
16827 
16828 static const Pool SUBQ__S__PH[2] = {
16829     { instruction         , 0                   , 0   , 32,
16830        0xfc0007ff, 0x2000020d, &SUBQ_PH          , 0,
16831        DSP_                },        /* SUBQ.PH */
16832     { instruction         , 0                   , 0   , 32,
16833        0xfc0007ff, 0x2000060d, &SUBQ_S_PH        , 0,
16834        DSP_                },        /* SUBQ_S.PH */
16835 };
16836 
16837 
16838 static const Pool SUBQH__R__PH[2] = {
16839     { instruction         , 0                   , 0   , 32,
16840        0xfc0007ff, 0x2000024d, &SUBQH_PH         , 0,
16841        DSP_                },        /* SUBQH.PH */
16842     { instruction         , 0                   , 0   , 32,
16843        0xfc0007ff, 0x2000064d, &SUBQH_R_PH       , 0,
16844        DSP_                },        /* SUBQH_R.PH */
16845 };
16846 
16847 
16848 static const Pool SUBQH__R__W[2] = {
16849     { instruction         , 0                   , 0   , 32,
16850        0xfc0007ff, 0x2000028d, &SUBQH_W          , 0,
16851        DSP_                },        /* SUBQH.W */
16852     { instruction         , 0                   , 0   , 32,
16853        0xfc0007ff, 0x2000068d, &SUBQH_R_W        , 0,
16854        DSP_                },        /* SUBQH_R.W */
16855 };
16856 
16857 
16858 static const Pool SUBU__S__QB[2] = {
16859     { instruction         , 0                   , 0   , 32,
16860        0xfc0007ff, 0x200002cd, &SUBU_QB          , 0,
16861        DSP_                },        /* SUBU.QB */
16862     { instruction         , 0                   , 0   , 32,
16863        0xfc0007ff, 0x200006cd, &SUBU_S_QB        , 0,
16864        DSP_                },        /* SUBU_S.QB */
16865 };
16866 
16867 
16868 static const Pool SUBU__S__PH[2] = {
16869     { instruction         , 0                   , 0   , 32,
16870        0xfc0007ff, 0x2000030d, &SUBU_PH          , 0,
16871        DSP_                },        /* SUBU.PH */
16872     { instruction         , 0                   , 0   , 32,
16873        0xfc0007ff, 0x2000070d, &SUBU_S_PH        , 0,
16874        DSP_                },        /* SUBU_S.PH */
16875 };
16876 
16877 
16878 static const Pool SHRA__R__PH[2] = {
16879     { instruction         , 0                   , 0   , 32,
16880        0xfc0007ff, 0x20000335, &SHRA_PH          , 0,
16881        DSP_                },        /* SHRA.PH */
16882     { instruction         , 0                   , 0   , 32,
16883        0xfc0007ff, 0x20000735, &SHRA_R_PH        , 0,
16884        DSP_                },        /* SHRA_R.PH */
16885 };
16886 
16887 
16888 static const Pool SUBUH__R__QB[2] = {
16889     { instruction         , 0                   , 0   , 32,
16890        0xfc0007ff, 0x2000034d, &SUBUH_QB         , 0,
16891        DSP_                },        /* SUBUH.QB */
16892     { instruction         , 0                   , 0   , 32,
16893        0xfc0007ff, 0x2000074d, &SUBUH_R_QB       , 0,
16894        DSP_                },        /* SUBUH_R.QB */
16895 };
16896 
16897 
16898 static const Pool SHLLV__S__PH[2] = {
16899     { instruction         , 0                   , 0   , 32,
16900        0xfc0007ff, 0x2000038d, &SHLLV_PH         , 0,
16901        DSP_                },        /* SHLLV.PH */
16902     { instruction         , 0                   , 0   , 32,
16903        0xfc0007ff, 0x2000078d, &SHLLV_S_PH       , 0,
16904        DSP_                },        /* SHLLV_S.PH */
16905 };
16906 
16907 
16908 static const Pool SHLL__S__PH[4] = {
16909     { instruction         , 0                   , 0   , 32,
16910        0xfc000fff, 0x200003b5, &SHLL_PH          , 0,
16911        DSP_                },        /* SHLL.PH */
16912     { reserved_block      , 0                   , 0   , 32,
16913        0xfc000fff, 0x200007b5, 0                      , 0,
16914        0x0                 },        /* SHLL[_S].PH~*(1) */
16915     { instruction         , 0                   , 0   , 32,
16916        0xfc000fff, 0x20000bb5, &SHLL_S_PH        , 0,
16917        DSP_                },        /* SHLL_S.PH */
16918     { reserved_block      , 0                   , 0   , 32,
16919        0xfc000fff, 0x20000fb5, 0                      , 0,
16920        0x0                 },        /* SHLL[_S].PH~*(3) */
16921 };
16922 
16923 
16924 static const Pool PRECR_SRA__R__PH_W[2] = {
16925     { instruction         , 0                   , 0   , 32,
16926        0xfc0007ff, 0x200003cd, &PRECR_SRA_PH_W   , 0,
16927        DSP_                },        /* PRECR_SRA.PH.W */
16928     { instruction         , 0                   , 0   , 32,
16929        0xfc0007ff, 0x200007cd, &PRECR_SRA_R_PH_W , 0,
16930        DSP_                },        /* PRECR_SRA_R.PH.W */
16931 };
16932 
16933 
16934 static const Pool _POOL32A5[128] = {
16935     { instruction         , 0                   , 0   , 32,
16936        0xfc0003ff, 0x20000005, &CMP_EQ_PH        , 0,
16937        DSP_                },        /* CMP.EQ.PH */
16938     { pool                , ADDQ__S__PH         , 2   , 32,
16939        0xfc0003ff, 0x2000000d, 0                      , 0,
16940        0x0                 },        /* ADDQ[_S].PH */
16941     { reserved_block      , 0                   , 0   , 32,
16942        0xfc0003ff, 0x20000015, 0                      , 0,
16943        0x0                 },        /* _POOL32A5~*(2) */
16944     { instruction         , 0                   , 0   , 32,
16945        0xfc0003ff, 0x2000001d, &SHILO            , 0,
16946        DSP_                },        /* SHILO */
16947     { instruction         , 0                   , 0   , 32,
16948        0xfc0003ff, 0x20000025, &MULEQ_S_W_PHL    , 0,
16949        DSP_                },        /* MULEQ_S.W.PHL */
16950     { pool                , MUL__S__PH          , 2   , 32,
16951        0xfc0003ff, 0x2000002d, 0                      , 0,
16952        0x0                 },        /* MUL[_S].PH */
16953     { reserved_block      , 0                   , 0   , 32,
16954        0xfc0003ff, 0x20000035, 0                      , 0,
16955        0x0                 },        /* _POOL32A5~*(6) */
16956     { instruction         , 0                   , 0   , 32,
16957        0xfc0003ff, 0x2000003d, &REPL_PH          , 0,
16958        DSP_                },        /* REPL.PH */
16959     { instruction         , 0                   , 0   , 32,
16960        0xfc0003ff, 0x20000045, &CMP_LT_PH        , 0,
16961        DSP_                },        /* CMP.LT.PH */
16962     { pool                , ADDQH__R__PH        , 2   , 32,
16963        0xfc0003ff, 0x2000004d, 0                      , 0,
16964        0x0                 },        /* ADDQH[_R].PH */
16965     { reserved_block      , 0                   , 0   , 32,
16966        0xfc0003ff, 0x20000055, 0                      , 0,
16967        0x0                 },        /* _POOL32A5~*(10) */
16968     { reserved_block      , 0                   , 0   , 32,
16969        0xfc0003ff, 0x2000005d, 0                      , 0,
16970        0x0                 },        /* _POOL32A5~*(11) */
16971     { instruction         , 0                   , 0   , 32,
16972        0xfc0003ff, 0x20000065, &MULEQ_S_W_PHR    , 0,
16973        DSP_                },        /* MULEQ_S.W.PHR */
16974     { instruction         , 0                   , 0   , 32,
16975        0xfc0003ff, 0x2000006d, &PRECR_QB_PH      , 0,
16976        DSP_                },        /* PRECR.QB.PH */
16977     { reserved_block      , 0                   , 0   , 32,
16978        0xfc0003ff, 0x20000075, 0                      , 0,
16979        0x0                 },        /* _POOL32A5~*(14) */
16980     { reserved_block      , 0                   , 0   , 32,
16981        0xfc0003ff, 0x2000007d, 0                      , 0,
16982        0x0                 },        /* _POOL32A5~*(15) */
16983     { instruction         , 0                   , 0   , 32,
16984        0xfc0003ff, 0x20000085, &CMP_LE_PH        , 0,
16985        DSP_                },        /* CMP.LE.PH */
16986     { pool                , ADDQH__R__W         , 2   , 32,
16987        0xfc0003ff, 0x2000008d, 0                      , 0,
16988        0x0                 },        /* ADDQH[_R].W */
16989     { instruction         , 0                   , 0   , 32,
16990        0xfc0003ff, 0x20000095, &MULEU_S_PH_QBL   , 0,
16991        DSP_                },        /* MULEU_S.PH.QBL */
16992     { reserved_block      , 0                   , 0   , 32,
16993        0xfc0003ff, 0x2000009d, 0                      , 0,
16994        0x0                 },        /* _POOL32A5~*(19) */
16995     { reserved_block      , 0                   , 0   , 32,
16996        0xfc0003ff, 0x200000a5, 0                      , 0,
16997        0x0                 },        /* _POOL32A5~*(20) */
16998     { instruction         , 0                   , 0   , 32,
16999        0xfc0003ff, 0x200000ad, &PRECRQ_QB_PH     , 0,
17000        DSP_                },        /* PRECRQ.QB.PH */
17001     { reserved_block      , 0                   , 0   , 32,
17002        0xfc0003ff, 0x200000b5, 0                      , 0,
17003        0x0                 },        /* _POOL32A5~*(22) */
17004     { reserved_block      , 0                   , 0   , 32,
17005        0xfc0003ff, 0x200000bd, 0                      , 0,
17006        0x0                 },        /* _POOL32A5~*(23) */
17007     { instruction         , 0                   , 0   , 32,
17008        0xfc0003ff, 0x200000c5, &CMPGU_EQ_QB      , 0,
17009        DSP_                },        /* CMPGU.EQ.QB */
17010     { pool                , ADDU__S__QB         , 2   , 32,
17011        0xfc0003ff, 0x200000cd, 0                      , 0,
17012        0x0                 },        /* ADDU[_S].QB */
17013     { instruction         , 0                   , 0   , 32,
17014        0xfc0003ff, 0x200000d5, &MULEU_S_PH_QBR   , 0,
17015        DSP_                },        /* MULEU_S.PH.QBR */
17016     { reserved_block      , 0                   , 0   , 32,
17017        0xfc0003ff, 0x200000dd, 0                      , 0,
17018        0x0                 },        /* _POOL32A5~*(27) */
17019     { reserved_block      , 0                   , 0   , 32,
17020        0xfc0003ff, 0x200000e5, 0                      , 0,
17021        0x0                 },        /* _POOL32A5~*(28) */
17022     { instruction         , 0                   , 0   , 32,
17023        0xfc0003ff, 0x200000ed, &PRECRQ_PH_W      , 0,
17024        DSP_                },        /* PRECRQ.PH.W */
17025     { reserved_block      , 0                   , 0   , 32,
17026        0xfc0003ff, 0x200000f5, 0                      , 0,
17027        0x0                 },        /* _POOL32A5~*(30) */
17028     { reserved_block      , 0                   , 0   , 32,
17029        0xfc0003ff, 0x200000fd, 0                      , 0,
17030        0x0                 },        /* _POOL32A5~*(31) */
17031     { instruction         , 0                   , 0   , 32,
17032        0xfc0003ff, 0x20000105, &CMPGU_LT_QB      , 0,
17033        DSP_                },        /* CMPGU.LT.QB */
17034     { pool                , ADDU__S__PH         , 2   , 32,
17035        0xfc0003ff, 0x2000010d, 0                      , 0,
17036        0x0                 },        /* ADDU[_S].PH */
17037     { instruction         , 0                   , 0   , 32,
17038        0xfc0003ff, 0x20000115, &MULQ_RS_PH       , 0,
17039        DSP_                },        /* MULQ_RS.PH */
17040     { reserved_block      , 0                   , 0   , 32,
17041        0xfc0003ff, 0x2000011d, 0                      , 0,
17042        0x0                 },        /* _POOL32A5~*(35) */
17043     { reserved_block      , 0                   , 0   , 32,
17044        0xfc0003ff, 0x20000125, 0                      , 0,
17045        0x0                 },        /* _POOL32A5~*(36) */
17046     { instruction         , 0                   , 0   , 32,
17047        0xfc0003ff, 0x2000012d, &PRECRQ_RS_PH_W   , 0,
17048        DSP_                },        /* PRECRQ_RS.PH.W */
17049     { reserved_block      , 0                   , 0   , 32,
17050        0xfc0003ff, 0x20000135, 0                      , 0,
17051        0x0                 },        /* _POOL32A5~*(38) */
17052     { reserved_block      , 0                   , 0   , 32,
17053        0xfc0003ff, 0x2000013d, 0                      , 0,
17054        0x0                 },        /* _POOL32A5~*(39) */
17055     { instruction         , 0                   , 0   , 32,
17056        0xfc0003ff, 0x20000145, &CMPGU_LE_QB      , 0,
17057        DSP_                },        /* CMPGU.LE.QB */
17058     { pool                , ADDUH__R__QB        , 2   , 32,
17059        0xfc0003ff, 0x2000014d, 0                      , 0,
17060        0x0                 },        /* ADDUH[_R].QB */
17061     { instruction         , 0                   , 0   , 32,
17062        0xfc0003ff, 0x20000155, &MULQ_S_PH        , 0,
17063        DSP_                },        /* MULQ_S.PH */
17064     { reserved_block      , 0                   , 0   , 32,
17065        0xfc0003ff, 0x2000015d, 0                      , 0,
17066        0x0                 },        /* _POOL32A5~*(43) */
17067     { reserved_block      , 0                   , 0   , 32,
17068        0xfc0003ff, 0x20000165, 0                      , 0,
17069        0x0                 },        /* _POOL32A5~*(44) */
17070     { instruction         , 0                   , 0   , 32,
17071        0xfc0003ff, 0x2000016d, &PRECRQU_S_QB_PH  , 0,
17072        DSP_                },        /* PRECRQU_S.QB.PH */
17073     { reserved_block      , 0                   , 0   , 32,
17074        0xfc0003ff, 0x20000175, 0                      , 0,
17075        0x0                 },        /* _POOL32A5~*(46) */
17076     { reserved_block      , 0                   , 0   , 32,
17077        0xfc0003ff, 0x2000017d, 0                      , 0,
17078        0x0                 },        /* _POOL32A5~*(47) */
17079     { instruction         , 0                   , 0   , 32,
17080        0xfc0003ff, 0x20000185, &CMPGDU_EQ_QB     , 0,
17081        DSP_                },        /* CMPGDU.EQ.QB */
17082     { pool                , SHRAV__R__PH        , 2   , 32,
17083        0xfc0003ff, 0x2000018d, 0                      , 0,
17084        0x0                 },        /* SHRAV[_R].PH */
17085     { instruction         , 0                   , 0   , 32,
17086        0xfc0003ff, 0x20000195, &MULQ_RS_W        , 0,
17087        DSP_                },        /* MULQ_RS.W */
17088     { reserved_block      , 0                   , 0   , 32,
17089        0xfc0003ff, 0x2000019d, 0                      , 0,
17090        0x0                 },        /* _POOL32A5~*(51) */
17091     { reserved_block      , 0                   , 0   , 32,
17092        0xfc0003ff, 0x200001a5, 0                      , 0,
17093        0x0                 },        /* _POOL32A5~*(52) */
17094     { instruction         , 0                   , 0   , 32,
17095        0xfc0003ff, 0x200001ad, &PACKRL_PH        , 0,
17096        DSP_                },        /* PACKRL.PH */
17097     { reserved_block      , 0                   , 0   , 32,
17098        0xfc0003ff, 0x200001b5, 0                      , 0,
17099        0x0                 },        /* _POOL32A5~*(54) */
17100     { reserved_block      , 0                   , 0   , 32,
17101        0xfc0003ff, 0x200001bd, 0                      , 0,
17102        0x0                 },        /* _POOL32A5~*(55) */
17103     { instruction         , 0                   , 0   , 32,
17104        0xfc0003ff, 0x200001c5, &CMPGDU_LT_QB     , 0,
17105        DSP_                },        /* CMPGDU.LT.QB */
17106     { pool                , SHRAV__R__QB        , 2   , 32,
17107        0xfc0003ff, 0x200001cd, 0                      , 0,
17108        0x0                 },        /* SHRAV[_R].QB */
17109     { instruction         , 0                   , 0   , 32,
17110        0xfc0003ff, 0x200001d5, &MULQ_S_W         , 0,
17111        DSP_                },        /* MULQ_S.W */
17112     { reserved_block      , 0                   , 0   , 32,
17113        0xfc0003ff, 0x200001dd, 0                      , 0,
17114        0x0                 },        /* _POOL32A5~*(59) */
17115     { reserved_block      , 0                   , 0   , 32,
17116        0xfc0003ff, 0x200001e5, 0                      , 0,
17117        0x0                 },        /* _POOL32A5~*(60) */
17118     { instruction         , 0                   , 0   , 32,
17119        0xfc0003ff, 0x200001ed, &PICK_QB          , 0,
17120        DSP_                },        /* PICK.QB */
17121     { reserved_block      , 0                   , 0   , 32,
17122        0xfc0003ff, 0x200001f5, 0                      , 0,
17123        0x0                 },        /* _POOL32A5~*(62) */
17124     { reserved_block      , 0                   , 0   , 32,
17125        0xfc0003ff, 0x200001fd, 0                      , 0,
17126        0x0                 },        /* _POOL32A5~*(63) */
17127     { instruction         , 0                   , 0   , 32,
17128        0xfc0003ff, 0x20000205, &CMPGDU_LE_QB     , 0,
17129        DSP_                },        /* CMPGDU.LE.QB */
17130     { pool                , SUBQ__S__PH         , 2   , 32,
17131        0xfc0003ff, 0x2000020d, 0                      , 0,
17132        0x0                 },        /* SUBQ[_S].PH */
17133     { instruction         , 0                   , 0   , 32,
17134        0xfc0003ff, 0x20000215, &APPEND           , 0,
17135        DSP_                },        /* APPEND */
17136     { reserved_block      , 0                   , 0   , 32,
17137        0xfc0003ff, 0x2000021d, 0                      , 0,
17138        0x0                 },        /* _POOL32A5~*(67) */
17139     { reserved_block      , 0                   , 0   , 32,
17140        0xfc0003ff, 0x20000225, 0                      , 0,
17141        0x0                 },        /* _POOL32A5~*(68) */
17142     { instruction         , 0                   , 0   , 32,
17143        0xfc0003ff, 0x2000022d, &PICK_PH          , 0,
17144        DSP_                },        /* PICK.PH */
17145     { reserved_block      , 0                   , 0   , 32,
17146        0xfc0003ff, 0x20000235, 0                      , 0,
17147        0x0                 },        /* _POOL32A5~*(70) */
17148     { reserved_block      , 0                   , 0   , 32,
17149        0xfc0003ff, 0x2000023d, 0                      , 0,
17150        0x0                 },        /* _POOL32A5~*(71) */
17151     { instruction         , 0                   , 0   , 32,
17152        0xfc0003ff, 0x20000245, &CMPU_EQ_QB       , 0,
17153        DSP_                },        /* CMPU.EQ.QB */
17154     { pool                , SUBQH__R__PH        , 2   , 32,
17155        0xfc0003ff, 0x2000024d, 0                      , 0,
17156        0x0                 },        /* SUBQH[_R].PH */
17157     { instruction         , 0                   , 0   , 32,
17158        0xfc0003ff, 0x20000255, &PREPEND          , 0,
17159        DSP_                },        /* PREPEND */
17160     { reserved_block      , 0                   , 0   , 32,
17161        0xfc0003ff, 0x2000025d, 0                      , 0,
17162        0x0                 },        /* _POOL32A5~*(75) */
17163     { reserved_block      , 0                   , 0   , 32,
17164        0xfc0003ff, 0x20000265, 0                      , 0,
17165        0x0                 },        /* _POOL32A5~*(76) */
17166     { reserved_block      , 0                   , 0   , 32,
17167        0xfc0003ff, 0x2000026d, 0                      , 0,
17168        0x0                 },        /* _POOL32A5~*(77) */
17169     { reserved_block      , 0                   , 0   , 32,
17170        0xfc0003ff, 0x20000275, 0                      , 0,
17171        0x0                 },        /* _POOL32A5~*(78) */
17172     { reserved_block      , 0                   , 0   , 32,
17173        0xfc0003ff, 0x2000027d, 0                      , 0,
17174        0x0                 },        /* _POOL32A5~*(79) */
17175     { instruction         , 0                   , 0   , 32,
17176        0xfc0003ff, 0x20000285, &CMPU_LT_QB       , 0,
17177        DSP_                },        /* CMPU.LT.QB */
17178     { pool                , SUBQH__R__W         , 2   , 32,
17179        0xfc0003ff, 0x2000028d, 0                      , 0,
17180        0x0                 },        /* SUBQH[_R].W */
17181     { instruction         , 0                   , 0   , 32,
17182        0xfc0003ff, 0x20000295, &MODSUB           , 0,
17183        DSP_                },        /* MODSUB */
17184     { reserved_block      , 0                   , 0   , 32,
17185        0xfc0003ff, 0x2000029d, 0                      , 0,
17186        0x0                 },        /* _POOL32A5~*(83) */
17187     { reserved_block      , 0                   , 0   , 32,
17188        0xfc0003ff, 0x200002a5, 0                      , 0,
17189        0x0                 },        /* _POOL32A5~*(84) */
17190     { reserved_block      , 0                   , 0   , 32,
17191        0xfc0003ff, 0x200002ad, 0                      , 0,
17192        0x0                 },        /* _POOL32A5~*(85) */
17193     { reserved_block      , 0                   , 0   , 32,
17194        0xfc0003ff, 0x200002b5, 0                      , 0,
17195        0x0                 },        /* _POOL32A5~*(86) */
17196     { reserved_block      , 0                   , 0   , 32,
17197        0xfc0003ff, 0x200002bd, 0                      , 0,
17198        0x0                 },        /* _POOL32A5~*(87) */
17199     { instruction         , 0                   , 0   , 32,
17200        0xfc0003ff, 0x200002c5, &CMPU_LE_QB       , 0,
17201        DSP_                },        /* CMPU.LE.QB */
17202     { pool                , SUBU__S__QB         , 2   , 32,
17203        0xfc0003ff, 0x200002cd, 0                      , 0,
17204        0x0                 },        /* SUBU[_S].QB */
17205     { instruction         , 0                   , 0   , 32,
17206        0xfc0003ff, 0x200002d5, &SHRAV_R_W        , 0,
17207        DSP_                },        /* SHRAV_R.W */
17208     { reserved_block      , 0                   , 0   , 32,
17209        0xfc0003ff, 0x200002dd, 0                      , 0,
17210        0x0                 },        /* _POOL32A5~*(91) */
17211     { reserved_block      , 0                   , 0   , 32,
17212        0xfc0003ff, 0x200002e5, 0                      , 0,
17213        0x0                 },        /* _POOL32A5~*(92) */
17214     { reserved_block      , 0                   , 0   , 32,
17215        0xfc0003ff, 0x200002ed, 0                      , 0,
17216        0x0                 },        /* _POOL32A5~*(93) */
17217     { instruction         , 0                   , 0   , 32,
17218        0xfc0003ff, 0x200002f5, &SHRA_R_W         , 0,
17219        DSP_                },        /* SHRA_R.W */
17220     { reserved_block      , 0                   , 0   , 32,
17221        0xfc0003ff, 0x200002fd, 0                      , 0,
17222        0x0                 },        /* _POOL32A5~*(95) */
17223     { instruction         , 0                   , 0   , 32,
17224        0xfc0003ff, 0x20000305, &ADDQ_S_W         , 0,
17225        DSP_                },        /* ADDQ_S.W */
17226     { pool                , SUBU__S__PH         , 2   , 32,
17227        0xfc0003ff, 0x2000030d, 0                      , 0,
17228        0x0                 },        /* SUBU[_S].PH */
17229     { instruction         , 0                   , 0   , 32,
17230        0xfc0003ff, 0x20000315, &SHRLV_PH         , 0,
17231        DSP_                },        /* SHRLV.PH */
17232     { reserved_block      , 0                   , 0   , 32,
17233        0xfc0003ff, 0x2000031d, 0                      , 0,
17234        0x0                 },        /* _POOL32A5~*(99) */
17235     { reserved_block      , 0                   , 0   , 32,
17236        0xfc0003ff, 0x20000325, 0                      , 0,
17237        0x0                 },        /* _POOL32A5~*(100) */
17238     { reserved_block      , 0                   , 0   , 32,
17239        0xfc0003ff, 0x2000032d, 0                      , 0,
17240        0x0                 },        /* _POOL32A5~*(101) */
17241     { pool                , SHRA__R__PH         , 2   , 32,
17242        0xfc0003ff, 0x20000335, 0                      , 0,
17243        0x0                 },        /* SHRA[_R].PH */
17244     { reserved_block      , 0                   , 0   , 32,
17245        0xfc0003ff, 0x2000033d, 0                      , 0,
17246        0x0                 },        /* _POOL32A5~*(103) */
17247     { instruction         , 0                   , 0   , 32,
17248        0xfc0003ff, 0x20000345, &SUBQ_S_W         , 0,
17249        DSP_                },        /* SUBQ_S.W */
17250     { pool                , SUBUH__R__QB        , 2   , 32,
17251        0xfc0003ff, 0x2000034d, 0                      , 0,
17252        0x0                 },        /* SUBUH[_R].QB */
17253     { instruction         , 0                   , 0   , 32,
17254        0xfc0003ff, 0x20000355, &SHRLV_QB         , 0,
17255        DSP_                },        /* SHRLV.QB */
17256     { reserved_block      , 0                   , 0   , 32,
17257        0xfc0003ff, 0x2000035d, 0                      , 0,
17258        0x0                 },        /* _POOL32A5~*(107) */
17259     { reserved_block      , 0                   , 0   , 32,
17260        0xfc0003ff, 0x20000365, 0                      , 0,
17261        0x0                 },        /* _POOL32A5~*(108) */
17262     { reserved_block      , 0                   , 0   , 32,
17263        0xfc0003ff, 0x2000036d, 0                      , 0,
17264        0x0                 },        /* _POOL32A5~*(109) */
17265     { reserved_block      , 0                   , 0   , 32,
17266        0xfc0003ff, 0x20000375, 0                      , 0,
17267        0x0                 },        /* _POOL32A5~*(110) */
17268     { reserved_block      , 0                   , 0   , 32,
17269        0xfc0003ff, 0x2000037d, 0                      , 0,
17270        0x0                 },        /* _POOL32A5~*(111) */
17271     { instruction         , 0                   , 0   , 32,
17272        0xfc0003ff, 0x20000385, &ADDSC            , 0,
17273        DSP_                },        /* ADDSC */
17274     { pool                , SHLLV__S__PH        , 2   , 32,
17275        0xfc0003ff, 0x2000038d, 0                      , 0,
17276        0x0                 },        /* SHLLV[_S].PH */
17277     { instruction         , 0                   , 0   , 32,
17278        0xfc0003ff, 0x20000395, &SHLLV_QB         , 0,
17279        DSP_                },        /* SHLLV.QB */
17280     { reserved_block      , 0                   , 0   , 32,
17281        0xfc0003ff, 0x2000039d, 0                      , 0,
17282        0x0                 },        /* _POOL32A5~*(115) */
17283     { reserved_block      , 0                   , 0   , 32,
17284        0xfc0003ff, 0x200003a5, 0                      , 0,
17285        0x0                 },        /* _POOL32A5~*(116) */
17286     { reserved_block      , 0                   , 0   , 32,
17287        0xfc0003ff, 0x200003ad, 0                      , 0,
17288        0x0                 },        /* _POOL32A5~*(117) */
17289     { pool                , SHLL__S__PH         , 4   , 32,
17290        0xfc0003ff, 0x200003b5, 0                      , 0,
17291        0x0                 },        /* SHLL[_S].PH */
17292     { reserved_block      , 0                   , 0   , 32,
17293        0xfc0003ff, 0x200003bd, 0                      , 0,
17294        0x0                 },        /* _POOL32A5~*(119) */
17295     { instruction         , 0                   , 0   , 32,
17296        0xfc0003ff, 0x200003c5, &ADDWC            , 0,
17297        DSP_                },        /* ADDWC */
17298     { pool                , PRECR_SRA__R__PH_W  , 2   , 32,
17299        0xfc0003ff, 0x200003cd, 0                      , 0,
17300        0x0                 },        /* PRECR_SRA[_R].PH.W */
17301     { instruction         , 0                   , 0   , 32,
17302        0xfc0003ff, 0x200003d5, &SHLLV_S_W        , 0,
17303        DSP_                },        /* SHLLV_S.W */
17304     { reserved_block      , 0                   , 0   , 32,
17305        0xfc0003ff, 0x200003dd, 0                      , 0,
17306        0x0                 },        /* _POOL32A5~*(123) */
17307     { reserved_block      , 0                   , 0   , 32,
17308        0xfc0003ff, 0x200003e5, 0                      , 0,
17309        0x0                 },        /* _POOL32A5~*(124) */
17310     { reserved_block      , 0                   , 0   , 32,
17311        0xfc0003ff, 0x200003ed, 0                      , 0,
17312        0x0                 },        /* _POOL32A5~*(125) */
17313     { instruction         , 0                   , 0   , 32,
17314        0xfc0003ff, 0x200003f5, &SHLL_S_W         , 0,
17315        DSP_                },        /* SHLL_S.W */
17316     { reserved_block      , 0                   , 0   , 32,
17317        0xfc0003ff, 0x200003fd, 0                      , 0,
17318        0x0                 },        /* _POOL32A5~*(127) */
17319 };
17320 
17321 
17322 static const Pool PP_LSX[16] = {
17323     { instruction         , 0                   , 0   , 32,
17324        0xfc0007ff, 0x20000007, &LBX              , 0,
17325        0x0                 },        /* LBX */
17326     { instruction         , 0                   , 0   , 32,
17327        0xfc0007ff, 0x20000087, &SBX              , 0,
17328        XMMS_               },        /* SBX */
17329     { instruction         , 0                   , 0   , 32,
17330        0xfc0007ff, 0x20000107, &LBUX             , 0,
17331        0x0                 },        /* LBUX */
17332     { reserved_block      , 0                   , 0   , 32,
17333        0xfc0007ff, 0x20000187, 0                      , 0,
17334        0x0                 },        /* PP.LSX~*(3) */
17335     { instruction         , 0                   , 0   , 32,
17336        0xfc0007ff, 0x20000207, &LHX              , 0,
17337        0x0                 },        /* LHX */
17338     { instruction         , 0                   , 0   , 32,
17339        0xfc0007ff, 0x20000287, &SHX              , 0,
17340        XMMS_               },        /* SHX */
17341     { instruction         , 0                   , 0   , 32,
17342        0xfc0007ff, 0x20000307, &LHUX             , 0,
17343        0x0                 },        /* LHUX */
17344     { instruction         , 0                   , 0   , 32,
17345        0xfc0007ff, 0x20000387, &LWUX             , 0,
17346        MIPS64_             },        /* LWUX */
17347     { instruction         , 0                   , 0   , 32,
17348        0xfc0007ff, 0x20000407, &LWX              , 0,
17349        0x0                 },        /* LWX */
17350     { instruction         , 0                   , 0   , 32,
17351        0xfc0007ff, 0x20000487, &SWX              , 0,
17352        XMMS_               },        /* SWX */
17353     { instruction         , 0                   , 0   , 32,
17354        0xfc0007ff, 0x20000507, &LWC1X            , 0,
17355        CP1_                },        /* LWC1X */
17356     { instruction         , 0                   , 0   , 32,
17357        0xfc0007ff, 0x20000587, &SWC1X            , 0,
17358        CP1_                },        /* SWC1X */
17359     { instruction         , 0                   , 0   , 32,
17360        0xfc0007ff, 0x20000607, &LDX              , 0,
17361        MIPS64_             },        /* LDX */
17362     { instruction         , 0                   , 0   , 32,
17363        0xfc0007ff, 0x20000687, &SDX              , 0,
17364        MIPS64_             },        /* SDX */
17365     { instruction         , 0                   , 0   , 32,
17366        0xfc0007ff, 0x20000707, &LDC1X            , 0,
17367        CP1_                },        /* LDC1X */
17368     { instruction         , 0                   , 0   , 32,
17369        0xfc0007ff, 0x20000787, &SDC1X            , 0,
17370        CP1_                },        /* SDC1X */
17371 };
17372 
17373 
17374 static const Pool PP_LSXS[16] = {
17375     { reserved_block      , 0                   , 0   , 32,
17376        0xfc0007ff, 0x20000047, 0                      , 0,
17377        0x0                 },        /* PP.LSXS~*(0) */
17378     { reserved_block      , 0                   , 0   , 32,
17379        0xfc0007ff, 0x200000c7, 0                      , 0,
17380        0x0                 },        /* PP.LSXS~*(1) */
17381     { reserved_block      , 0                   , 0   , 32,
17382        0xfc0007ff, 0x20000147, 0                      , 0,
17383        0x0                 },        /* PP.LSXS~*(2) */
17384     { reserved_block      , 0                   , 0   , 32,
17385        0xfc0007ff, 0x200001c7, 0                      , 0,
17386        0x0                 },        /* PP.LSXS~*(3) */
17387     { instruction         , 0                   , 0   , 32,
17388        0xfc0007ff, 0x20000247, &LHXS             , 0,
17389        0x0                 },        /* LHXS */
17390     { instruction         , 0                   , 0   , 32,
17391        0xfc0007ff, 0x200002c7, &SHXS             , 0,
17392        XMMS_               },        /* SHXS */
17393     { instruction         , 0                   , 0   , 32,
17394        0xfc0007ff, 0x20000347, &LHUXS            , 0,
17395        0x0                 },        /* LHUXS */
17396     { instruction         , 0                   , 0   , 32,
17397        0xfc0007ff, 0x200003c7, &LWUXS            , 0,
17398        MIPS64_             },        /* LWUXS */
17399     { instruction         , 0                   , 0   , 32,
17400        0xfc0007ff, 0x20000447, &LWXS_32_         , 0,
17401        0x0                 },        /* LWXS[32] */
17402     { instruction         , 0                   , 0   , 32,
17403        0xfc0007ff, 0x200004c7, &SWXS             , 0,
17404        XMMS_               },        /* SWXS */
17405     { instruction         , 0                   , 0   , 32,
17406        0xfc0007ff, 0x20000547, &LWC1XS           , 0,
17407        CP1_                },        /* LWC1XS */
17408     { instruction         , 0                   , 0   , 32,
17409        0xfc0007ff, 0x200005c7, &SWC1XS           , 0,
17410        CP1_                },        /* SWC1XS */
17411     { instruction         , 0                   , 0   , 32,
17412        0xfc0007ff, 0x20000647, &LDXS             , 0,
17413        MIPS64_             },        /* LDXS */
17414     { instruction         , 0                   , 0   , 32,
17415        0xfc0007ff, 0x200006c7, &SDXS             , 0,
17416        MIPS64_             },        /* SDXS */
17417     { instruction         , 0                   , 0   , 32,
17418        0xfc0007ff, 0x20000747, &LDC1XS           , 0,
17419        CP1_                },        /* LDC1XS */
17420     { instruction         , 0                   , 0   , 32,
17421        0xfc0007ff, 0x200007c7, &SDC1XS           , 0,
17422        CP1_                },        /* SDC1XS */
17423 };
17424 
17425 
17426 static const Pool P_LSX[2] = {
17427     { pool                , PP_LSX              , 16  , 32,
17428        0xfc00007f, 0x20000007, 0                      , 0,
17429        0x0                 },        /* PP.LSX */
17430     { pool                , PP_LSXS             , 16  , 32,
17431        0xfc00007f, 0x20000047, 0                      , 0,
17432        0x0                 },        /* PP.LSXS */
17433 };
17434 
17435 
17436 static const Pool POOL32Axf_1_0[4] = {
17437     { instruction         , 0                   , 0   , 32,
17438        0xfc003fff, 0x2000007f, &MFHI_DSP_        , 0,
17439        DSP_                },        /* MFHI[DSP] */
17440     { instruction         , 0                   , 0   , 32,
17441        0xfc003fff, 0x2000107f, &MFLO_DSP_        , 0,
17442        DSP_                },        /* MFLO[DSP] */
17443     { instruction         , 0                   , 0   , 32,
17444        0xfc003fff, 0x2000207f, &MTHI_DSP_        , 0,
17445        DSP_                },        /* MTHI[DSP] */
17446     { instruction         , 0                   , 0   , 32,
17447        0xfc003fff, 0x2000307f, &MTLO_DSP_        , 0,
17448        DSP_                },        /* MTLO[DSP] */
17449 };
17450 
17451 
17452 static const Pool POOL32Axf_1_1[4] = {
17453     { instruction         , 0                   , 0   , 32,
17454        0xfc003fff, 0x2000027f, &MTHLIP           , 0,
17455        DSP_                },        /* MTHLIP */
17456     { instruction         , 0                   , 0   , 32,
17457        0xfc003fff, 0x2000127f, &SHILOV           , 0,
17458        DSP_                },        /* SHILOV */
17459     { reserved_block      , 0                   , 0   , 32,
17460        0xfc003fff, 0x2000227f, 0                      , 0,
17461        0x0                 },        /* POOL32Axf_1_1~*(2) */
17462     { reserved_block      , 0                   , 0   , 32,
17463        0xfc003fff, 0x2000327f, 0                      , 0,
17464        0x0                 },        /* POOL32Axf_1_1~*(3) */
17465 };
17466 
17467 
17468 static const Pool POOL32Axf_1_3[4] = {
17469     { instruction         , 0                   , 0   , 32,
17470        0xfc003fff, 0x2000067f, &RDDSP            , 0,
17471        DSP_                },        /* RDDSP */
17472     { instruction         , 0                   , 0   , 32,
17473        0xfc003fff, 0x2000167f, &WRDSP            , 0,
17474        DSP_                },        /* WRDSP */
17475     { instruction         , 0                   , 0   , 32,
17476        0xfc003fff, 0x2000267f, &EXTP             , 0,
17477        DSP_                },        /* EXTP */
17478     { instruction         , 0                   , 0   , 32,
17479        0xfc003fff, 0x2000367f, &EXTPDP           , 0,
17480        DSP_                },        /* EXTPDP */
17481 };
17482 
17483 
17484 static const Pool POOL32Axf_1_4[2] = {
17485     { instruction         , 0                   , 0   , 32,
17486        0xfc001fff, 0x2000087f, &SHLL_QB          , 0,
17487        DSP_                },        /* SHLL.QB */
17488     { instruction         , 0                   , 0   , 32,
17489        0xfc001fff, 0x2000187f, &SHRL_QB          , 0,
17490        DSP_                },        /* SHRL.QB */
17491 };
17492 
17493 
17494 static const Pool MAQ_S_A__W_PHR[2] = {
17495     { instruction         , 0                   , 0   , 32,
17496        0xfc003fff, 0x20000a7f, &MAQ_S_W_PHR      , 0,
17497        DSP_                },        /* MAQ_S.W.PHR */
17498     { instruction         , 0                   , 0   , 32,
17499        0xfc003fff, 0x20002a7f, &MAQ_SA_W_PHR     , 0,
17500        DSP_                },        /* MAQ_SA.W.PHR */
17501 };
17502 
17503 
17504 static const Pool MAQ_S_A__W_PHL[2] = {
17505     { instruction         , 0                   , 0   , 32,
17506        0xfc003fff, 0x20001a7f, &MAQ_S_W_PHL      , 0,
17507        DSP_                },        /* MAQ_S.W.PHL */
17508     { instruction         , 0                   , 0   , 32,
17509        0xfc003fff, 0x20003a7f, &MAQ_SA_W_PHL     , 0,
17510        DSP_                },        /* MAQ_SA.W.PHL */
17511 };
17512 
17513 
17514 static const Pool POOL32Axf_1_5[2] = {
17515     { pool                , MAQ_S_A__W_PHR      , 2   , 32,
17516        0xfc001fff, 0x20000a7f, 0                      , 0,
17517        0x0                 },        /* MAQ_S[A].W.PHR */
17518     { pool                , MAQ_S_A__W_PHL      , 2   , 32,
17519        0xfc001fff, 0x20001a7f, 0                      , 0,
17520        0x0                 },        /* MAQ_S[A].W.PHL */
17521 };
17522 
17523 
17524 static const Pool POOL32Axf_1_7[4] = {
17525     { instruction         , 0                   , 0   , 32,
17526        0xfc003fff, 0x20000e7f, &EXTR_W           , 0,
17527        DSP_                },        /* EXTR.W */
17528     { instruction         , 0                   , 0   , 32,
17529        0xfc003fff, 0x20001e7f, &EXTR_R_W         , 0,
17530        DSP_                },        /* EXTR_R.W */
17531     { instruction         , 0                   , 0   , 32,
17532        0xfc003fff, 0x20002e7f, &EXTR_RS_W        , 0,
17533        DSP_                },        /* EXTR_RS.W */
17534     { instruction         , 0                   , 0   , 32,
17535        0xfc003fff, 0x20003e7f, &EXTR_S_H         , 0,
17536        DSP_                },        /* EXTR_S.H */
17537 };
17538 
17539 
17540 static const Pool POOL32Axf_1[8] = {
17541     { pool                , POOL32Axf_1_0       , 4   , 32,
17542        0xfc000fff, 0x2000007f, 0                      , 0,
17543        0x0                 },        /* POOL32Axf_1_0 */
17544     { pool                , POOL32Axf_1_1       , 4   , 32,
17545        0xfc000fff, 0x2000027f, 0                      , 0,
17546        0x0                 },        /* POOL32Axf_1_1 */
17547     { reserved_block      , 0                   , 0   , 32,
17548        0xfc000fff, 0x2000047f, 0                      , 0,
17549        0x0                 },        /* POOL32Axf_1~*(2) */
17550     { pool                , POOL32Axf_1_3       , 4   , 32,
17551        0xfc000fff, 0x2000067f, 0                      , 0,
17552        0x0                 },        /* POOL32Axf_1_3 */
17553     { pool                , POOL32Axf_1_4       , 2   , 32,
17554        0xfc000fff, 0x2000087f, 0                      , 0,
17555        0x0                 },        /* POOL32Axf_1_4 */
17556     { pool                , POOL32Axf_1_5       , 2   , 32,
17557        0xfc000fff, 0x20000a7f, 0                      , 0,
17558        0x0                 },        /* POOL32Axf_1_5 */
17559     { reserved_block      , 0                   , 0   , 32,
17560        0xfc000fff, 0x20000c7f, 0                      , 0,
17561        0x0                 },        /* POOL32Axf_1~*(6) */
17562     { pool                , POOL32Axf_1_7       , 4   , 32,
17563        0xfc000fff, 0x20000e7f, 0                      , 0,
17564        0x0                 },        /* POOL32Axf_1_7 */
17565 };
17566 
17567 
17568 static const Pool POOL32Axf_2_DSP__0_7[8] = {
17569     { instruction         , 0                   , 0   , 32,
17570        0xfc003fff, 0x200000bf, &DPA_W_PH         , 0,
17571        DSP_                },        /* DPA.W.PH */
17572     { instruction         , 0                   , 0   , 32,
17573        0xfc003fff, 0x200002bf, &DPAQ_S_W_PH      , 0,
17574        DSP_                },        /* DPAQ_S.W.PH */
17575     { instruction         , 0                   , 0   , 32,
17576        0xfc003fff, 0x200004bf, &DPS_W_PH         , 0,
17577        DSP_                },        /* DPS.W.PH */
17578     { instruction         , 0                   , 0   , 32,
17579        0xfc003fff, 0x200006bf, &DPSQ_S_W_PH      , 0,
17580        DSP_                },        /* DPSQ_S.W.PH */
17581     { reserved_block      , 0                   , 0   , 32,
17582        0xfc003fff, 0x200008bf, 0                      , 0,
17583        0x0                 },        /* POOL32Axf_2(DSP)_0_7~*(4) */
17584     { instruction         , 0                   , 0   , 32,
17585        0xfc003fff, 0x20000abf, &MADD_DSP_        , 0,
17586        DSP_                },        /* MADD[DSP] */
17587     { instruction         , 0                   , 0   , 32,
17588        0xfc003fff, 0x20000cbf, &MULT_DSP_        , 0,
17589        DSP_                },        /* MULT[DSP] */
17590     { instruction         , 0                   , 0   , 32,
17591        0xfc003fff, 0x20000ebf, &EXTRV_W          , 0,
17592        DSP_                },        /* EXTRV.W */
17593 };
17594 
17595 
17596 static const Pool POOL32Axf_2_DSP__8_15[8] = {
17597     { instruction         , 0                   , 0   , 32,
17598        0xfc003fff, 0x200010bf, &DPAX_W_PH        , 0,
17599        DSP_                },        /* DPAX.W.PH */
17600     { instruction         , 0                   , 0   , 32,
17601        0xfc003fff, 0x200012bf, &DPAQ_SA_L_W      , 0,
17602        DSP_                },        /* DPAQ_SA.L.W */
17603     { instruction         , 0                   , 0   , 32,
17604        0xfc003fff, 0x200014bf, &DPSX_W_PH        , 0,
17605        DSP_                },        /* DPSX.W.PH */
17606     { instruction         , 0                   , 0   , 32,
17607        0xfc003fff, 0x200016bf, &DPSQ_SA_L_W      , 0,
17608        DSP_                },        /* DPSQ_SA.L.W */
17609     { reserved_block      , 0                   , 0   , 32,
17610        0xfc003fff, 0x200018bf, 0                      , 0,
17611        0x0                 },        /* POOL32Axf_2(DSP)_8_15~*(4) */
17612     { instruction         , 0                   , 0   , 32,
17613        0xfc003fff, 0x20001abf, &MADDU_DSP_       , 0,
17614        DSP_                },        /* MADDU[DSP] */
17615     { instruction         , 0                   , 0   , 32,
17616        0xfc003fff, 0x20001cbf, &MULTU_DSP_       , 0,
17617        DSP_                },        /* MULTU[DSP] */
17618     { instruction         , 0                   , 0   , 32,
17619        0xfc003fff, 0x20001ebf, &EXTRV_R_W        , 0,
17620        DSP_                },        /* EXTRV_R.W */
17621 };
17622 
17623 
17624 static const Pool POOL32Axf_2_DSP__16_23[8] = {
17625     { instruction         , 0                   , 0   , 32,
17626        0xfc003fff, 0x200020bf, &DPAU_H_QBL       , 0,
17627        DSP_                },        /* DPAU.H.QBL */
17628     { instruction         , 0                   , 0   , 32,
17629        0xfc003fff, 0x200022bf, &DPAQX_S_W_PH     , 0,
17630        DSP_                },        /* DPAQX_S.W.PH */
17631     { instruction         , 0                   , 0   , 32,
17632        0xfc003fff, 0x200024bf, &DPSU_H_QBL       , 0,
17633        DSP_                },        /* DPSU.H.QBL */
17634     { instruction         , 0                   , 0   , 32,
17635        0xfc003fff, 0x200026bf, &DPSQX_S_W_PH     , 0,
17636        DSP_                },        /* DPSQX_S.W.PH */
17637     { instruction         , 0                   , 0   , 32,
17638        0xfc003fff, 0x200028bf, &EXTPV            , 0,
17639        DSP_                },        /* EXTPV */
17640     { instruction         , 0                   , 0   , 32,
17641        0xfc003fff, 0x20002abf, &MSUB_DSP_        , 0,
17642        DSP_                },        /* MSUB[DSP] */
17643     { instruction         , 0                   , 0   , 32,
17644        0xfc003fff, 0x20002cbf, &MULSA_W_PH       , 0,
17645        DSP_                },        /* MULSA.W.PH */
17646     { instruction         , 0                   , 0   , 32,
17647        0xfc003fff, 0x20002ebf, &EXTRV_RS_W       , 0,
17648        DSP_                },        /* EXTRV_RS.W */
17649 };
17650 
17651 
17652 static const Pool POOL32Axf_2_DSP__24_31[8] = {
17653     { instruction         , 0                   , 0   , 32,
17654        0xfc003fff, 0x200030bf, &DPAU_H_QBR       , 0,
17655        DSP_                },        /* DPAU.H.QBR */
17656     { instruction         , 0                   , 0   , 32,
17657        0xfc003fff, 0x200032bf, &DPAQX_SA_W_PH    , 0,
17658        DSP_                },        /* DPAQX_SA.W.PH */
17659     { instruction         , 0                   , 0   , 32,
17660        0xfc003fff, 0x200034bf, &DPSU_H_QBR       , 0,
17661        DSP_                },        /* DPSU.H.QBR */
17662     { instruction         , 0                   , 0   , 32,
17663        0xfc003fff, 0x200036bf, &DPSQX_SA_W_PH    , 0,
17664        DSP_                },        /* DPSQX_SA.W.PH */
17665     { instruction         , 0                   , 0   , 32,
17666        0xfc003fff, 0x200038bf, &EXTPDPV          , 0,
17667        DSP_                },        /* EXTPDPV */
17668     { instruction         , 0                   , 0   , 32,
17669        0xfc003fff, 0x20003abf, &MSUBU_DSP_       , 0,
17670        DSP_                },        /* MSUBU[DSP] */
17671     { instruction         , 0                   , 0   , 32,
17672        0xfc003fff, 0x20003cbf, &MULSAQ_S_W_PH    , 0,
17673        DSP_                },        /* MULSAQ_S.W.PH */
17674     { instruction         , 0                   , 0   , 32,
17675        0xfc003fff, 0x20003ebf, &EXTRV_S_H        , 0,
17676        DSP_                },        /* EXTRV_S.H */
17677 };
17678 
17679 
17680 static const Pool POOL32Axf_2[4] = {
17681     { pool                , POOL32Axf_2_DSP__0_7, 8   , 32,
17682        0xfc0031ff, 0x200000bf, 0                      , 0,
17683        0x0                 },        /* POOL32Axf_2(DSP)_0_7 */
17684     { pool                , POOL32Axf_2_DSP__8_15, 8   , 32,
17685        0xfc0031ff, 0x200010bf, 0                      , 0,
17686        0x0                 },        /* POOL32Axf_2(DSP)_8_15 */
17687     { pool                , POOL32Axf_2_DSP__16_23, 8   , 32,
17688        0xfc0031ff, 0x200020bf, 0                      , 0,
17689        0x0                 },        /* POOL32Axf_2(DSP)_16_23 */
17690     { pool                , POOL32Axf_2_DSP__24_31, 8   , 32,
17691        0xfc0031ff, 0x200030bf, 0                      , 0,
17692        0x0                 },        /* POOL32Axf_2(DSP)_24_31 */
17693 };
17694 
17695 
17696 static const Pool POOL32Axf_4[128] = {
17697     { instruction         , 0                   , 0   , 32,
17698        0xfc00ffff, 0x2000013f, &ABSQ_S_QB        , 0,
17699        DSP_                },        /* ABSQ_S.QB */
17700     { instruction         , 0                   , 0   , 32,
17701        0xfc00ffff, 0x2000033f, &REPLV_PH         , 0,
17702        DSP_                },        /* REPLV.PH */
17703     { reserved_block      , 0                   , 0   , 32,
17704        0xfc00ffff, 0x2000053f, 0                      , 0,
17705        0x0                 },        /* POOL32Axf_4~*(2) */
17706     { reserved_block      , 0                   , 0   , 32,
17707        0xfc00ffff, 0x2000073f, 0                      , 0,
17708        0x0                 },        /* POOL32Axf_4~*(3) */
17709     { reserved_block      , 0                   , 0   , 32,
17710        0xfc00ffff, 0x2000093f, 0                      , 0,
17711        0x0                 },        /* POOL32Axf_4~*(4) */
17712     { reserved_block      , 0                   , 0   , 32,
17713        0xfc00ffff, 0x20000b3f, 0                      , 0,
17714        0x0                 },        /* POOL32Axf_4~*(5) */
17715     { reserved_block      , 0                   , 0   , 32,
17716        0xfc00ffff, 0x20000d3f, 0                      , 0,
17717        0x0                 },        /* POOL32Axf_4~*(6) */
17718     { reserved_block      , 0                   , 0   , 32,
17719        0xfc00ffff, 0x20000f3f, 0                      , 0,
17720        0x0                 },        /* POOL32Axf_4~*(7) */
17721     { instruction         , 0                   , 0   , 32,
17722        0xfc00ffff, 0x2000113f, &ABSQ_S_PH        , 0,
17723        DSP_                },        /* ABSQ_S.PH */
17724     { instruction         , 0                   , 0   , 32,
17725        0xfc00ffff, 0x2000133f, &REPLV_QB         , 0,
17726        DSP_                },        /* REPLV.QB */
17727     { reserved_block      , 0                   , 0   , 32,
17728        0xfc00ffff, 0x2000153f, 0                      , 0,
17729        0x0                 },        /* POOL32Axf_4~*(10) */
17730     { reserved_block      , 0                   , 0   , 32,
17731        0xfc00ffff, 0x2000173f, 0                      , 0,
17732        0x0                 },        /* POOL32Axf_4~*(11) */
17733     { reserved_block      , 0                   , 0   , 32,
17734        0xfc00ffff, 0x2000193f, 0                      , 0,
17735        0x0                 },        /* POOL32Axf_4~*(12) */
17736     { reserved_block      , 0                   , 0   , 32,
17737        0xfc00ffff, 0x20001b3f, 0                      , 0,
17738        0x0                 },        /* POOL32Axf_4~*(13) */
17739     { reserved_block      , 0                   , 0   , 32,
17740        0xfc00ffff, 0x20001d3f, 0                      , 0,
17741        0x0                 },        /* POOL32Axf_4~*(14) */
17742     { reserved_block      , 0                   , 0   , 32,
17743        0xfc00ffff, 0x20001f3f, 0                      , 0,
17744        0x0                 },        /* POOL32Axf_4~*(15) */
17745     { instruction         , 0                   , 0   , 32,
17746        0xfc00ffff, 0x2000213f, &ABSQ_S_W         , 0,
17747        DSP_                },        /* ABSQ_S.W */
17748     { reserved_block      , 0                   , 0   , 32,
17749        0xfc00ffff, 0x2000233f, 0                      , 0,
17750        0x0                 },        /* POOL32Axf_4~*(17) */
17751     { reserved_block      , 0                   , 0   , 32,
17752        0xfc00ffff, 0x2000253f, 0                      , 0,
17753        0x0                 },        /* POOL32Axf_4~*(18) */
17754     { reserved_block      , 0                   , 0   , 32,
17755        0xfc00ffff, 0x2000273f, 0                      , 0,
17756        0x0                 },        /* POOL32Axf_4~*(19) */
17757     { reserved_block      , 0                   , 0   , 32,
17758        0xfc00ffff, 0x2000293f, 0                      , 0,
17759        0x0                 },        /* POOL32Axf_4~*(20) */
17760     { reserved_block      , 0                   , 0   , 32,
17761        0xfc00ffff, 0x20002b3f, 0                      , 0,
17762        0x0                 },        /* POOL32Axf_4~*(21) */
17763     { reserved_block      , 0                   , 0   , 32,
17764        0xfc00ffff, 0x20002d3f, 0                      , 0,
17765        0x0                 },        /* POOL32Axf_4~*(22) */
17766     { reserved_block      , 0                   , 0   , 32,
17767        0xfc00ffff, 0x20002f3f, 0                      , 0,
17768        0x0                 },        /* POOL32Axf_4~*(23) */
17769     { reserved_block      , 0                   , 0   , 32,
17770        0xfc00ffff, 0x2000313f, 0                      , 0,
17771        0x0                 },        /* POOL32Axf_4~*(24) */
17772     { reserved_block      , 0                   , 0   , 32,
17773        0xfc00ffff, 0x2000333f, 0                      , 0,
17774        0x0                 },        /* POOL32Axf_4~*(25) */
17775     { reserved_block      , 0                   , 0   , 32,
17776        0xfc00ffff, 0x2000353f, 0                      , 0,
17777        0x0                 },        /* POOL32Axf_4~*(26) */
17778     { reserved_block      , 0                   , 0   , 32,
17779        0xfc00ffff, 0x2000373f, 0                      , 0,
17780        0x0                 },        /* POOL32Axf_4~*(27) */
17781     { reserved_block      , 0                   , 0   , 32,
17782        0xfc00ffff, 0x2000393f, 0                      , 0,
17783        0x0                 },        /* POOL32Axf_4~*(28) */
17784     { reserved_block      , 0                   , 0   , 32,
17785        0xfc00ffff, 0x20003b3f, 0                      , 0,
17786        0x0                 },        /* POOL32Axf_4~*(29) */
17787     { reserved_block      , 0                   , 0   , 32,
17788        0xfc00ffff, 0x20003d3f, 0                      , 0,
17789        0x0                 },        /* POOL32Axf_4~*(30) */
17790     { reserved_block      , 0                   , 0   , 32,
17791        0xfc00ffff, 0x20003f3f, 0                      , 0,
17792        0x0                 },        /* POOL32Axf_4~*(31) */
17793     { instruction         , 0                   , 0   , 32,
17794        0xfc00ffff, 0x2000413f, &INSV             , 0,
17795        DSP_                },        /* INSV */
17796     { reserved_block      , 0                   , 0   , 32,
17797        0xfc00ffff, 0x2000433f, 0                      , 0,
17798        0x0                 },        /* POOL32Axf_4~*(33) */
17799     { reserved_block      , 0                   , 0   , 32,
17800        0xfc00ffff, 0x2000453f, 0                      , 0,
17801        0x0                 },        /* POOL32Axf_4~*(34) */
17802     { reserved_block      , 0                   , 0   , 32,
17803        0xfc00ffff, 0x2000473f, 0                      , 0,
17804        0x0                 },        /* POOL32Axf_4~*(35) */
17805     { reserved_block      , 0                   , 0   , 32,
17806        0xfc00ffff, 0x2000493f, 0                      , 0,
17807        0x0                 },        /* POOL32Axf_4~*(36) */
17808     { instruction         , 0                   , 0   , 32,
17809        0xfc00ffff, 0x20004b3f, &CLO              , 0,
17810        XMMS_               },        /* CLO */
17811     { instruction         , 0                   , 0   , 32,
17812        0xfc00ffff, 0x20004d3f, &MFC2             , 0,
17813        CP2_                },        /* MFC2 */
17814     { reserved_block      , 0                   , 0   , 32,
17815        0xfc00ffff, 0x20004f3f, 0                      , 0,
17816        0x0                 },        /* POOL32Axf_4~*(39) */
17817     { instruction         , 0                   , 0   , 32,
17818        0xfc00ffff, 0x2000513f, &PRECEQ_W_PHL     , 0,
17819        DSP_                },        /* PRECEQ.W.PHL */
17820     { reserved_block      , 0                   , 0   , 32,
17821        0xfc00ffff, 0x2000533f, 0                      , 0,
17822        0x0                 },        /* POOL32Axf_4~*(41) */
17823     { reserved_block      , 0                   , 0   , 32,
17824        0xfc00ffff, 0x2000553f, 0                      , 0,
17825        0x0                 },        /* POOL32Axf_4~*(42) */
17826     { reserved_block      , 0                   , 0   , 32,
17827        0xfc00ffff, 0x2000573f, 0                      , 0,
17828        0x0                 },        /* POOL32Axf_4~*(43) */
17829     { reserved_block      , 0                   , 0   , 32,
17830        0xfc00ffff, 0x2000593f, 0                      , 0,
17831        0x0                 },        /* POOL32Axf_4~*(44) */
17832     { instruction         , 0                   , 0   , 32,
17833        0xfc00ffff, 0x20005b3f, &CLZ              , 0,
17834        XMMS_               },        /* CLZ */
17835     { instruction         , 0                   , 0   , 32,
17836        0xfc00ffff, 0x20005d3f, &MTC2             , 0,
17837        CP2_                },        /* MTC2 */
17838     { reserved_block      , 0                   , 0   , 32,
17839        0xfc00ffff, 0x20005f3f, 0                      , 0,
17840        0x0                 },        /* POOL32Axf_4~*(47) */
17841     { instruction         , 0                   , 0   , 32,
17842        0xfc00ffff, 0x2000613f, &PRECEQ_W_PHR     , 0,
17843        DSP_                },        /* PRECEQ.W.PHR */
17844     { reserved_block      , 0                   , 0   , 32,
17845        0xfc00ffff, 0x2000633f, 0                      , 0,
17846        0x0                 },        /* POOL32Axf_4~*(49) */
17847     { reserved_block      , 0                   , 0   , 32,
17848        0xfc00ffff, 0x2000653f, 0                      , 0,
17849        0x0                 },        /* POOL32Axf_4~*(50) */
17850     { reserved_block      , 0                   , 0   , 32,
17851        0xfc00ffff, 0x2000673f, 0                      , 0,
17852        0x0                 },        /* POOL32Axf_4~*(51) */
17853     { reserved_block      , 0                   , 0   , 32,
17854        0xfc00ffff, 0x2000693f, 0                      , 0,
17855        0x0                 },        /* POOL32Axf_4~*(52) */
17856     { reserved_block      , 0                   , 0   , 32,
17857        0xfc00ffff, 0x20006b3f, 0                      , 0,
17858        0x0                 },        /* POOL32Axf_4~*(53) */
17859     { instruction         , 0                   , 0   , 32,
17860        0xfc00ffff, 0x20006d3f, &DMFC2            , 0,
17861        CP2_                },        /* DMFC2 */
17862     { reserved_block      , 0                   , 0   , 32,
17863        0xfc00ffff, 0x20006f3f, 0                      , 0,
17864        0x0                 },        /* POOL32Axf_4~*(55) */
17865     { instruction         , 0                   , 0   , 32,
17866        0xfc00ffff, 0x2000713f, &PRECEQU_PH_QBL   , 0,
17867        DSP_                },        /* PRECEQU.PH.QBL */
17868     { instruction         , 0                   , 0   , 32,
17869        0xfc00ffff, 0x2000733f, &PRECEQU_PH_QBLA  , 0,
17870        DSP_                },        /* PRECEQU.PH.QBLA */
17871     { reserved_block      , 0                   , 0   , 32,
17872        0xfc00ffff, 0x2000753f, 0                      , 0,
17873        0x0                 },        /* POOL32Axf_4~*(58) */
17874     { reserved_block      , 0                   , 0   , 32,
17875        0xfc00ffff, 0x2000773f, 0                      , 0,
17876        0x0                 },        /* POOL32Axf_4~*(59) */
17877     { reserved_block      , 0                   , 0   , 32,
17878        0xfc00ffff, 0x2000793f, 0                      , 0,
17879        0x0                 },        /* POOL32Axf_4~*(60) */
17880     { reserved_block      , 0                   , 0   , 32,
17881        0xfc00ffff, 0x20007b3f, 0                      , 0,
17882        0x0                 },        /* POOL32Axf_4~*(61) */
17883     { instruction         , 0                   , 0   , 32,
17884        0xfc00ffff, 0x20007d3f, &DMTC2            , 0,
17885        CP2_                },        /* DMTC2 */
17886     { reserved_block      , 0                   , 0   , 32,
17887        0xfc00ffff, 0x20007f3f, 0                      , 0,
17888        0x0                 },        /* POOL32Axf_4~*(63) */
17889     { reserved_block      , 0                   , 0   , 32,
17890        0xfc00ffff, 0x2000813f, 0                      , 0,
17891        0x0                 },        /* POOL32Axf_4~*(64) */
17892     { reserved_block      , 0                   , 0   , 32,
17893        0xfc00ffff, 0x2000833f, 0                      , 0,
17894        0x0                 },        /* POOL32Axf_4~*(65) */
17895     { reserved_block      , 0                   , 0   , 32,
17896        0xfc00ffff, 0x2000853f, 0                      , 0,
17897        0x0                 },        /* POOL32Axf_4~*(66) */
17898     { reserved_block      , 0                   , 0   , 32,
17899        0xfc00ffff, 0x2000873f, 0                      , 0,
17900        0x0                 },        /* POOL32Axf_4~*(67) */
17901     { reserved_block      , 0                   , 0   , 32,
17902        0xfc00ffff, 0x2000893f, 0                      , 0,
17903        0x0                 },        /* POOL32Axf_4~*(68) */
17904     { reserved_block      , 0                   , 0   , 32,
17905        0xfc00ffff, 0x20008b3f, 0                      , 0,
17906        0x0                 },        /* POOL32Axf_4~*(69) */
17907     { instruction         , 0                   , 0   , 32,
17908        0xfc00ffff, 0x20008d3f, &MFHC2            , 0,
17909        CP2_                },        /* MFHC2 */
17910     { reserved_block      , 0                   , 0   , 32,
17911        0xfc00ffff, 0x20008f3f, 0                      , 0,
17912        0x0                 },        /* POOL32Axf_4~*(71) */
17913     { instruction         , 0                   , 0   , 32,
17914        0xfc00ffff, 0x2000913f, &PRECEQU_PH_QBR   , 0,
17915        DSP_                },        /* PRECEQU.PH.QBR */
17916     { instruction         , 0                   , 0   , 32,
17917        0xfc00ffff, 0x2000933f, &PRECEQU_PH_QBRA  , 0,
17918        DSP_                },        /* PRECEQU.PH.QBRA */
17919     { reserved_block      , 0                   , 0   , 32,
17920        0xfc00ffff, 0x2000953f, 0                      , 0,
17921        0x0                 },        /* POOL32Axf_4~*(74) */
17922     { reserved_block      , 0                   , 0   , 32,
17923        0xfc00ffff, 0x2000973f, 0                      , 0,
17924        0x0                 },        /* POOL32Axf_4~*(75) */
17925     { reserved_block      , 0                   , 0   , 32,
17926        0xfc00ffff, 0x2000993f, 0                      , 0,
17927        0x0                 },        /* POOL32Axf_4~*(76) */
17928     { reserved_block      , 0                   , 0   , 32,
17929        0xfc00ffff, 0x20009b3f, 0                      , 0,
17930        0x0                 },        /* POOL32Axf_4~*(77) */
17931     { instruction         , 0                   , 0   , 32,
17932        0xfc00ffff, 0x20009d3f, &MTHC2            , 0,
17933        CP2_                },        /* MTHC2 */
17934     { reserved_block      , 0                   , 0   , 32,
17935        0xfc00ffff, 0x20009f3f, 0                      , 0,
17936        0x0                 },        /* POOL32Axf_4~*(79) */
17937     { reserved_block      , 0                   , 0   , 32,
17938        0xfc00ffff, 0x2000a13f, 0                      , 0,
17939        0x0                 },        /* POOL32Axf_4~*(80) */
17940     { reserved_block      , 0                   , 0   , 32,
17941        0xfc00ffff, 0x2000a33f, 0                      , 0,
17942        0x0                 },        /* POOL32Axf_4~*(81) */
17943     { reserved_block      , 0                   , 0   , 32,
17944        0xfc00ffff, 0x2000a53f, 0                      , 0,
17945        0x0                 },        /* POOL32Axf_4~*(82) */
17946     { reserved_block      , 0                   , 0   , 32,
17947        0xfc00ffff, 0x2000a73f, 0                      , 0,
17948        0x0                 },        /* POOL32Axf_4~*(83) */
17949     { reserved_block      , 0                   , 0   , 32,
17950        0xfc00ffff, 0x2000a93f, 0                      , 0,
17951        0x0                 },        /* POOL32Axf_4~*(84) */
17952     { reserved_block      , 0                   , 0   , 32,
17953        0xfc00ffff, 0x2000ab3f, 0                      , 0,
17954        0x0                 },        /* POOL32Axf_4~*(85) */
17955     { reserved_block      , 0                   , 0   , 32,
17956        0xfc00ffff, 0x2000ad3f, 0                      , 0,
17957        0x0                 },        /* POOL32Axf_4~*(86) */
17958     { reserved_block      , 0                   , 0   , 32,
17959        0xfc00ffff, 0x2000af3f, 0                      , 0,
17960        0x0                 },        /* POOL32Axf_4~*(87) */
17961     { instruction         , 0                   , 0   , 32,
17962        0xfc00ffff, 0x2000b13f, &PRECEU_PH_QBL    , 0,
17963        DSP_                },        /* PRECEU.PH.QBL */
17964     { instruction         , 0                   , 0   , 32,
17965        0xfc00ffff, 0x2000b33f, &PRECEU_PH_QBLA   , 0,
17966        DSP_                },        /* PRECEU.PH.QBLA */
17967     { reserved_block      , 0                   , 0   , 32,
17968        0xfc00ffff, 0x2000b53f, 0                      , 0,
17969        0x0                 },        /* POOL32Axf_4~*(90) */
17970     { reserved_block      , 0                   , 0   , 32,
17971        0xfc00ffff, 0x2000b73f, 0                      , 0,
17972        0x0                 },        /* POOL32Axf_4~*(91) */
17973     { reserved_block      , 0                   , 0   , 32,
17974        0xfc00ffff, 0x2000b93f, 0                      , 0,
17975        0x0                 },        /* POOL32Axf_4~*(92) */
17976     { reserved_block      , 0                   , 0   , 32,
17977        0xfc00ffff, 0x2000bb3f, 0                      , 0,
17978        0x0                 },        /* POOL32Axf_4~*(93) */
17979     { reserved_block      , 0                   , 0   , 32,
17980        0xfc00ffff, 0x2000bd3f, 0                      , 0,
17981        0x0                 },        /* POOL32Axf_4~*(94) */
17982     { reserved_block      , 0                   , 0   , 32,
17983        0xfc00ffff, 0x2000bf3f, 0                      , 0,
17984        0x0                 },        /* POOL32Axf_4~*(95) */
17985     { reserved_block      , 0                   , 0   , 32,
17986        0xfc00ffff, 0x2000c13f, 0                      , 0,
17987        0x0                 },        /* POOL32Axf_4~*(96) */
17988     { reserved_block      , 0                   , 0   , 32,
17989        0xfc00ffff, 0x2000c33f, 0                      , 0,
17990        0x0                 },        /* POOL32Axf_4~*(97) */
17991     { reserved_block      , 0                   , 0   , 32,
17992        0xfc00ffff, 0x2000c53f, 0                      , 0,
17993        0x0                 },        /* POOL32Axf_4~*(98) */
17994     { reserved_block      , 0                   , 0   , 32,
17995        0xfc00ffff, 0x2000c73f, 0                      , 0,
17996        0x0                 },        /* POOL32Axf_4~*(99) */
17997     { reserved_block      , 0                   , 0   , 32,
17998        0xfc00ffff, 0x2000c93f, 0                      , 0,
17999        0x0                 },        /* POOL32Axf_4~*(100) */
18000     { reserved_block      , 0                   , 0   , 32,
18001        0xfc00ffff, 0x2000cb3f, 0                      , 0,
18002        0x0                 },        /* POOL32Axf_4~*(101) */
18003     { instruction         , 0                   , 0   , 32,
18004        0xfc00ffff, 0x2000cd3f, &CFC2             , 0,
18005        CP2_                },        /* CFC2 */
18006     { reserved_block      , 0                   , 0   , 32,
18007        0xfc00ffff, 0x2000cf3f, 0                      , 0,
18008        0x0                 },        /* POOL32Axf_4~*(103) */
18009     { instruction         , 0                   , 0   , 32,
18010        0xfc00ffff, 0x2000d13f, &PRECEU_PH_QBR    , 0,
18011        DSP_                },        /* PRECEU.PH.QBR */
18012     { instruction         , 0                   , 0   , 32,
18013        0xfc00ffff, 0x2000d33f, &PRECEU_PH_QBRA   , 0,
18014        DSP_                },        /* PRECEU.PH.QBRA */
18015     { reserved_block      , 0                   , 0   , 32,
18016        0xfc00ffff, 0x2000d53f, 0                      , 0,
18017        0x0                 },        /* POOL32Axf_4~*(106) */
18018     { reserved_block      , 0                   , 0   , 32,
18019        0xfc00ffff, 0x2000d73f, 0                      , 0,
18020        0x0                 },        /* POOL32Axf_4~*(107) */
18021     { reserved_block      , 0                   , 0   , 32,
18022        0xfc00ffff, 0x2000d93f, 0                      , 0,
18023        0x0                 },        /* POOL32Axf_4~*(108) */
18024     { reserved_block      , 0                   , 0   , 32,
18025        0xfc00ffff, 0x2000db3f, 0                      , 0,
18026        0x0                 },        /* POOL32Axf_4~*(109) */
18027     { instruction         , 0                   , 0   , 32,
18028        0xfc00ffff, 0x2000dd3f, &CTC2             , 0,
18029        CP2_                },        /* CTC2 */
18030     { reserved_block      , 0                   , 0   , 32,
18031        0xfc00ffff, 0x2000df3f, 0                      , 0,
18032        0x0                 },        /* POOL32Axf_4~*(111) */
18033     { reserved_block      , 0                   , 0   , 32,
18034        0xfc00ffff, 0x2000e13f, 0                      , 0,
18035        0x0                 },        /* POOL32Axf_4~*(112) */
18036     { reserved_block      , 0                   , 0   , 32,
18037        0xfc00ffff, 0x2000e33f, 0                      , 0,
18038        0x0                 },        /* POOL32Axf_4~*(113) */
18039     { reserved_block      , 0                   , 0   , 32,
18040        0xfc00ffff, 0x2000e53f, 0                      , 0,
18041        0x0                 },        /* POOL32Axf_4~*(114) */
18042     { reserved_block      , 0                   , 0   , 32,
18043        0xfc00ffff, 0x2000e73f, 0                      , 0,
18044        0x0                 },        /* POOL32Axf_4~*(115) */
18045     { reserved_block      , 0                   , 0   , 32,
18046        0xfc00ffff, 0x2000e93f, 0                      , 0,
18047        0x0                 },        /* POOL32Axf_4~*(116) */
18048     { reserved_block      , 0                   , 0   , 32,
18049        0xfc00ffff, 0x2000eb3f, 0                      , 0,
18050        0x0                 },        /* POOL32Axf_4~*(117) */
18051     { reserved_block      , 0                   , 0   , 32,
18052        0xfc00ffff, 0x2000ed3f, 0                      , 0,
18053        0x0                 },        /* POOL32Axf_4~*(118) */
18054     { reserved_block      , 0                   , 0   , 32,
18055        0xfc00ffff, 0x2000ef3f, 0                      , 0,
18056        0x0                 },        /* POOL32Axf_4~*(119) */
18057     { instruction         , 0                   , 0   , 32,
18058        0xfc00ffff, 0x2000f13f, &RADDU_W_QB       , 0,
18059        DSP_                },        /* RADDU.W.QB */
18060     { reserved_block      , 0                   , 0   , 32,
18061        0xfc00ffff, 0x2000f33f, 0                      , 0,
18062        0x0                 },        /* POOL32Axf_4~*(121) */
18063     { reserved_block      , 0                   , 0   , 32,
18064        0xfc00ffff, 0x2000f53f, 0                      , 0,
18065        0x0                 },        /* POOL32Axf_4~*(122) */
18066     { reserved_block      , 0                   , 0   , 32,
18067        0xfc00ffff, 0x2000f73f, 0                      , 0,
18068        0x0                 },        /* POOL32Axf_4~*(123) */
18069     { reserved_block      , 0                   , 0   , 32,
18070        0xfc00ffff, 0x2000f93f, 0                      , 0,
18071        0x0                 },        /* POOL32Axf_4~*(124) */
18072     { reserved_block      , 0                   , 0   , 32,
18073        0xfc00ffff, 0x2000fb3f, 0                      , 0,
18074        0x0                 },        /* POOL32Axf_4~*(125) */
18075     { reserved_block      , 0                   , 0   , 32,
18076        0xfc00ffff, 0x2000fd3f, 0                      , 0,
18077        0x0                 },        /* POOL32Axf_4~*(126) */
18078     { reserved_block      , 0                   , 0   , 32,
18079        0xfc00ffff, 0x2000ff3f, 0                      , 0,
18080        0x0                 },        /* POOL32Axf_4~*(127) */
18081 };
18082 
18083 
18084 static const Pool POOL32Axf_5_group0[32] = {
18085     { instruction         , 0                   , 0   , 32,
18086        0xfc00ffff, 0x2000017f, &TLBGP            , 0,
18087        CP0_ | VZ_ | TLB_   },        /* TLBGP */
18088     { instruction         , 0                   , 0   , 32,
18089        0xfc00ffff, 0x2000037f, &TLBP             , 0,
18090        CP0_ | TLB_         },        /* TLBP */
18091     { instruction         , 0                   , 0   , 32,
18092        0xfc00ffff, 0x2000057f, &TLBGINV          , 0,
18093        CP0_ | VZ_ | TLB_ | TLBINV_},        /* TLBGINV */
18094     { instruction         , 0                   , 0   , 32,
18095        0xfc00ffff, 0x2000077f, &TLBINV           , 0,
18096        CP0_ | TLB_ | TLBINV_},        /* TLBINV */
18097     { reserved_block      , 0                   , 0   , 32,
18098        0xfc00ffff, 0x2000097f, 0                      , 0,
18099        0x0                 },        /* POOL32Axf_5_group0~*(4) */
18100     { reserved_block      , 0                   , 0   , 32,
18101        0xfc00ffff, 0x20000b7f, 0                      , 0,
18102        0x0                 },        /* POOL32Axf_5_group0~*(5) */
18103     { reserved_block      , 0                   , 0   , 32,
18104        0xfc00ffff, 0x20000d7f, 0                      , 0,
18105        0x0                 },        /* POOL32Axf_5_group0~*(6) */
18106     { reserved_block      , 0                   , 0   , 32,
18107        0xfc00ffff, 0x20000f7f, 0                      , 0,
18108        0x0                 },        /* POOL32Axf_5_group0~*(7) */
18109     { instruction         , 0                   , 0   , 32,
18110        0xfc00ffff, 0x2000117f, &TLBGR            , 0,
18111        CP0_ | VZ_ | TLB_   },        /* TLBGR */
18112     { instruction         , 0                   , 0   , 32,
18113        0xfc00ffff, 0x2000137f, &TLBR             , 0,
18114        CP0_ | TLB_         },        /* TLBR */
18115     { instruction         , 0                   , 0   , 32,
18116        0xfc00ffff, 0x2000157f, &TLBGINVF         , 0,
18117        CP0_ | VZ_ | TLB_ | TLBINV_},        /* TLBGINVF */
18118     { instruction         , 0                   , 0   , 32,
18119        0xfc00ffff, 0x2000177f, &TLBINVF          , 0,
18120        CP0_ | TLB_ | TLBINV_},        /* TLBINVF */
18121     { reserved_block      , 0                   , 0   , 32,
18122        0xfc00ffff, 0x2000197f, 0                      , 0,
18123        0x0                 },        /* POOL32Axf_5_group0~*(12) */
18124     { reserved_block      , 0                   , 0   , 32,
18125        0xfc00ffff, 0x20001b7f, 0                      , 0,
18126        0x0                 },        /* POOL32Axf_5_group0~*(13) */
18127     { reserved_block      , 0                   , 0   , 32,
18128        0xfc00ffff, 0x20001d7f, 0                      , 0,
18129        0x0                 },        /* POOL32Axf_5_group0~*(14) */
18130     { reserved_block      , 0                   , 0   , 32,
18131        0xfc00ffff, 0x20001f7f, 0                      , 0,
18132        0x0                 },        /* POOL32Axf_5_group0~*(15) */
18133     { instruction         , 0                   , 0   , 32,
18134        0xfc00ffff, 0x2000217f, &TLBGWI           , 0,
18135        CP0_ | VZ_ | TLB_   },        /* TLBGWI */
18136     { instruction         , 0                   , 0   , 32,
18137        0xfc00ffff, 0x2000237f, &TLBWI            , 0,
18138        CP0_ | TLB_         },        /* TLBWI */
18139     { reserved_block      , 0                   , 0   , 32,
18140        0xfc00ffff, 0x2000257f, 0                      , 0,
18141        0x0                 },        /* POOL32Axf_5_group0~*(18) */
18142     { reserved_block      , 0                   , 0   , 32,
18143        0xfc00ffff, 0x2000277f, 0                      , 0,
18144        0x0                 },        /* POOL32Axf_5_group0~*(19) */
18145     { reserved_block      , 0                   , 0   , 32,
18146        0xfc00ffff, 0x2000297f, 0                      , 0,
18147        0x0                 },        /* POOL32Axf_5_group0~*(20) */
18148     { reserved_block      , 0                   , 0   , 32,
18149        0xfc00ffff, 0x20002b7f, 0                      , 0,
18150        0x0                 },        /* POOL32Axf_5_group0~*(21) */
18151     { reserved_block      , 0                   , 0   , 32,
18152        0xfc00ffff, 0x20002d7f, 0                      , 0,
18153        0x0                 },        /* POOL32Axf_5_group0~*(22) */
18154     { reserved_block      , 0                   , 0   , 32,
18155        0xfc00ffff, 0x20002f7f, 0                      , 0,
18156        0x0                 },        /* POOL32Axf_5_group0~*(23) */
18157     { instruction         , 0                   , 0   , 32,
18158        0xfc00ffff, 0x2000317f, &TLBGWR           , 0,
18159        CP0_ | VZ_ | TLB_   },        /* TLBGWR */
18160     { instruction         , 0                   , 0   , 32,
18161        0xfc00ffff, 0x2000337f, &TLBWR            , 0,
18162        CP0_ | TLB_         },        /* TLBWR */
18163     { reserved_block      , 0                   , 0   , 32,
18164        0xfc00ffff, 0x2000357f, 0                      , 0,
18165        0x0                 },        /* POOL32Axf_5_group0~*(26) */
18166     { reserved_block      , 0                   , 0   , 32,
18167        0xfc00ffff, 0x2000377f, 0                      , 0,
18168        0x0                 },        /* POOL32Axf_5_group0~*(27) */
18169     { reserved_block      , 0                   , 0   , 32,
18170        0xfc00ffff, 0x2000397f, 0                      , 0,
18171        0x0                 },        /* POOL32Axf_5_group0~*(28) */
18172     { reserved_block      , 0                   , 0   , 32,
18173        0xfc00ffff, 0x20003b7f, 0                      , 0,
18174        0x0                 },        /* POOL32Axf_5_group0~*(29) */
18175     { reserved_block      , 0                   , 0   , 32,
18176        0xfc00ffff, 0x20003d7f, 0                      , 0,
18177        0x0                 },        /* POOL32Axf_5_group0~*(30) */
18178     { reserved_block      , 0                   , 0   , 32,
18179        0xfc00ffff, 0x20003f7f, 0                      , 0,
18180        0x0                 },        /* POOL32Axf_5_group0~*(31) */
18181 };
18182 
18183 
18184 static const Pool POOL32Axf_5_group1[32] = {
18185     { reserved_block      , 0                   , 0   , 32,
18186        0xfc00ffff, 0x2000417f, 0                      , 0,
18187        0x0                 },        /* POOL32Axf_5_group1~*(0) */
18188     { reserved_block      , 0                   , 0   , 32,
18189        0xfc00ffff, 0x2000437f, 0                      , 0,
18190        0x0                 },        /* POOL32Axf_5_group1~*(1) */
18191     { reserved_block      , 0                   , 0   , 32,
18192        0xfc00ffff, 0x2000457f, 0                      , 0,
18193        0x0                 },        /* POOL32Axf_5_group1~*(2) */
18194     { instruction         , 0                   , 0   , 32,
18195        0xfc00ffff, 0x2000477f, &DI               , 0,
18196        0x0                 },        /* DI */
18197     { reserved_block      , 0                   , 0   , 32,
18198        0xfc00ffff, 0x2000497f, 0                      , 0,
18199        0x0                 },        /* POOL32Axf_5_group1~*(4) */
18200     { reserved_block      , 0                   , 0   , 32,
18201        0xfc00ffff, 0x20004b7f, 0                      , 0,
18202        0x0                 },        /* POOL32Axf_5_group1~*(5) */
18203     { reserved_block      , 0                   , 0   , 32,
18204        0xfc00ffff, 0x20004d7f, 0                      , 0,
18205        0x0                 },        /* POOL32Axf_5_group1~*(6) */
18206     { reserved_block      , 0                   , 0   , 32,
18207        0xfc00ffff, 0x20004f7f, 0                      , 0,
18208        0x0                 },        /* POOL32Axf_5_group1~*(7) */
18209     { reserved_block      , 0                   , 0   , 32,
18210        0xfc00ffff, 0x2000517f, 0                      , 0,
18211        0x0                 },        /* POOL32Axf_5_group1~*(8) */
18212     { reserved_block      , 0                   , 0   , 32,
18213        0xfc00ffff, 0x2000537f, 0                      , 0,
18214        0x0                 },        /* POOL32Axf_5_group1~*(9) */
18215     { reserved_block      , 0                   , 0   , 32,
18216        0xfc00ffff, 0x2000557f, 0                      , 0,
18217        0x0                 },        /* POOL32Axf_5_group1~*(10) */
18218     { instruction         , 0                   , 0   , 32,
18219        0xfc00ffff, 0x2000577f, &EI               , 0,
18220        0x0                 },        /* EI */
18221     { reserved_block      , 0                   , 0   , 32,
18222        0xfc00ffff, 0x2000597f, 0                      , 0,
18223        0x0                 },        /* POOL32Axf_5_group1~*(12) */
18224     { reserved_block      , 0                   , 0   , 32,
18225        0xfc00ffff, 0x20005b7f, 0                      , 0,
18226        0x0                 },        /* POOL32Axf_5_group1~*(13) */
18227     { reserved_block      , 0                   , 0   , 32,
18228        0xfc00ffff, 0x20005d7f, 0                      , 0,
18229        0x0                 },        /* POOL32Axf_5_group1~*(14) */
18230     { reserved_block      , 0                   , 0   , 32,
18231        0xfc00ffff, 0x20005f7f, 0                      , 0,
18232        0x0                 },        /* POOL32Axf_5_group1~*(15) */
18233     { reserved_block      , 0                   , 0   , 32,
18234        0xfc00ffff, 0x2000617f, 0                      , 0,
18235        0x0                 },        /* POOL32Axf_5_group1~*(16) */
18236     { reserved_block      , 0                   , 0   , 32,
18237        0xfc00ffff, 0x2000637f, 0                      , 0,
18238        0x0                 },        /* POOL32Axf_5_group1~*(17) */
18239     { reserved_block      , 0                   , 0   , 32,
18240        0xfc00ffff, 0x2000657f, 0                      , 0,
18241        0x0                 },        /* POOL32Axf_5_group1~*(18) */
18242     { reserved_block      , 0                   , 0   , 32,
18243        0xfc00ffff, 0x2000677f, 0                      , 0,
18244        0x0                 },        /* POOL32Axf_5_group1~*(19) */
18245     { reserved_block      , 0                   , 0   , 32,
18246        0xfc00ffff, 0x2000697f, 0                      , 0,
18247        0x0                 },        /* POOL32Axf_5_group1~*(20) */
18248     { reserved_block      , 0                   , 0   , 32,
18249        0xfc00ffff, 0x20006b7f, 0                      , 0,
18250        0x0                 },        /* POOL32Axf_5_group1~*(21) */
18251     { reserved_block      , 0                   , 0   , 32,
18252        0xfc00ffff, 0x20006d7f, 0                      , 0,
18253        0x0                 },        /* POOL32Axf_5_group1~*(22) */
18254     { reserved_block      , 0                   , 0   , 32,
18255        0xfc00ffff, 0x20006f7f, 0                      , 0,
18256        0x0                 },        /* POOL32Axf_5_group1~*(23) */
18257     { reserved_block      , 0                   , 0   , 32,
18258        0xfc00ffff, 0x2000717f, 0                      , 0,
18259        0x0                 },        /* POOL32Axf_5_group1~*(24) */
18260     { reserved_block      , 0                   , 0   , 32,
18261        0xfc00ffff, 0x2000737f, 0                      , 0,
18262        0x0                 },        /* POOL32Axf_5_group1~*(25) */
18263     { reserved_block      , 0                   , 0   , 32,
18264        0xfc00ffff, 0x2000757f, 0                      , 0,
18265        0x0                 },        /* POOL32Axf_5_group1~*(26) */
18266     { reserved_block      , 0                   , 0   , 32,
18267        0xfc00ffff, 0x2000777f, 0                      , 0,
18268        0x0                 },        /* POOL32Axf_5_group1~*(27) */
18269     { reserved_block      , 0                   , 0   , 32,
18270        0xfc00ffff, 0x2000797f, 0                      , 0,
18271        0x0                 },        /* POOL32Axf_5_group1~*(28) */
18272     { reserved_block      , 0                   , 0   , 32,
18273        0xfc00ffff, 0x20007b7f, 0                      , 0,
18274        0x0                 },        /* POOL32Axf_5_group1~*(29) */
18275     { reserved_block      , 0                   , 0   , 32,
18276        0xfc00ffff, 0x20007d7f, 0                      , 0,
18277        0x0                 },        /* POOL32Axf_5_group1~*(30) */
18278     { reserved_block      , 0                   , 0   , 32,
18279        0xfc00ffff, 0x20007f7f, 0                      , 0,
18280        0x0                 },        /* POOL32Axf_5_group1~*(31) */
18281 };
18282 
18283 
18284 static const Pool ERETx[2] = {
18285     { instruction         , 0                   , 0   , 32,
18286        0xfc01ffff, 0x2000f37f, &ERET             , 0,
18287        0x0                 },        /* ERET */
18288     { instruction         , 0                   , 0   , 32,
18289        0xfc01ffff, 0x2001f37f, &ERETNC           , 0,
18290        0x0                 },        /* ERETNC */
18291 };
18292 
18293 
18294 static const Pool POOL32Axf_5_group3[32] = {
18295     { reserved_block      , 0                   , 0   , 32,
18296        0xfc00ffff, 0x2000c17f, 0                      , 0,
18297        0x0                 },        /* POOL32Axf_5_group3~*(0) */
18298     { instruction         , 0                   , 0   , 32,
18299        0xfc00ffff, 0x2000c37f, &WAIT             , 0,
18300        0x0                 },        /* WAIT */
18301     { reserved_block      , 0                   , 0   , 32,
18302        0xfc00ffff, 0x2000c57f, 0                      , 0,
18303        0x0                 },        /* POOL32Axf_5_group3~*(2) */
18304     { reserved_block      , 0                   , 0   , 32,
18305        0xfc00ffff, 0x2000c77f, 0                      , 0,
18306        0x0                 },        /* POOL32Axf_5_group3~*(3) */
18307     { reserved_block      , 0                   , 0   , 32,
18308        0xfc00ffff, 0x2000c97f, 0                      , 0,
18309        0x0                 },        /* POOL32Axf_5_group3~*(4) */
18310     { reserved_block      , 0                   , 0   , 32,
18311        0xfc00ffff, 0x2000cb7f, 0                      , 0,
18312        0x0                 },        /* POOL32Axf_5_group3~*(5) */
18313     { reserved_block      , 0                   , 0   , 32,
18314        0xfc00ffff, 0x2000cd7f, 0                      , 0,
18315        0x0                 },        /* POOL32Axf_5_group3~*(6) */
18316     { reserved_block      , 0                   , 0   , 32,
18317        0xfc00ffff, 0x2000cf7f, 0                      , 0,
18318        0x0                 },        /* POOL32Axf_5_group3~*(7) */
18319     { reserved_block      , 0                   , 0   , 32,
18320        0xfc00ffff, 0x2000d17f, 0                      , 0,
18321        0x0                 },        /* POOL32Axf_5_group3~*(8) */
18322     { instruction         , 0                   , 0   , 32,
18323        0xfc00ffff, 0x2000d37f, &IRET             , 0,
18324        MCU_                },        /* IRET */
18325     { reserved_block      , 0                   , 0   , 32,
18326        0xfc00ffff, 0x2000d57f, 0                      , 0,
18327        0x0                 },        /* POOL32Axf_5_group3~*(10) */
18328     { reserved_block      , 0                   , 0   , 32,
18329        0xfc00ffff, 0x2000d77f, 0                      , 0,
18330        0x0                 },        /* POOL32Axf_5_group3~*(11) */
18331     { reserved_block      , 0                   , 0   , 32,
18332        0xfc00ffff, 0x2000d97f, 0                      , 0,
18333        0x0                 },        /* POOL32Axf_5_group3~*(12) */
18334     { reserved_block      , 0                   , 0   , 32,
18335        0xfc00ffff, 0x2000db7f, 0                      , 0,
18336        0x0                 },        /* POOL32Axf_5_group3~*(13) */
18337     { reserved_block      , 0                   , 0   , 32,
18338        0xfc00ffff, 0x2000dd7f, 0                      , 0,
18339        0x0                 },        /* POOL32Axf_5_group3~*(14) */
18340     { reserved_block      , 0                   , 0   , 32,
18341        0xfc00ffff, 0x2000df7f, 0                      , 0,
18342        0x0                 },        /* POOL32Axf_5_group3~*(15) */
18343     { instruction         , 0                   , 0   , 32,
18344        0xfc00ffff, 0x2000e17f, &RDPGPR           , 0,
18345        CP0_                },        /* RDPGPR */
18346     { instruction         , 0                   , 0   , 32,
18347        0xfc00ffff, 0x2000e37f, &DERET            , 0,
18348        EJTAG_              },        /* DERET */
18349     { reserved_block      , 0                   , 0   , 32,
18350        0xfc00ffff, 0x2000e57f, 0                      , 0,
18351        0x0                 },        /* POOL32Axf_5_group3~*(18) */
18352     { reserved_block      , 0                   , 0   , 32,
18353        0xfc00ffff, 0x2000e77f, 0                      , 0,
18354        0x0                 },        /* POOL32Axf_5_group3~*(19) */
18355     { reserved_block      , 0                   , 0   , 32,
18356        0xfc00ffff, 0x2000e97f, 0                      , 0,
18357        0x0                 },        /* POOL32Axf_5_group3~*(20) */
18358     { reserved_block      , 0                   , 0   , 32,
18359        0xfc00ffff, 0x2000eb7f, 0                      , 0,
18360        0x0                 },        /* POOL32Axf_5_group3~*(21) */
18361     { reserved_block      , 0                   , 0   , 32,
18362        0xfc00ffff, 0x2000ed7f, 0                      , 0,
18363        0x0                 },        /* POOL32Axf_5_group3~*(22) */
18364     { reserved_block      , 0                   , 0   , 32,
18365        0xfc00ffff, 0x2000ef7f, 0                      , 0,
18366        0x0                 },        /* POOL32Axf_5_group3~*(23) */
18367     { instruction         , 0                   , 0   , 32,
18368        0xfc00ffff, 0x2000f17f, &WRPGPR           , 0,
18369        CP0_                },        /* WRPGPR */
18370     { pool                , ERETx               , 2   , 32,
18371        0xfc00ffff, 0x2000f37f, 0                      , 0,
18372        0x0                 },        /* ERETx */
18373     { reserved_block      , 0                   , 0   , 32,
18374        0xfc00ffff, 0x2000f57f, 0                      , 0,
18375        0x0                 },        /* POOL32Axf_5_group3~*(26) */
18376     { reserved_block      , 0                   , 0   , 32,
18377        0xfc00ffff, 0x2000f77f, 0                      , 0,
18378        0x0                 },        /* POOL32Axf_5_group3~*(27) */
18379     { reserved_block      , 0                   , 0   , 32,
18380        0xfc00ffff, 0x2000f97f, 0                      , 0,
18381        0x0                 },        /* POOL32Axf_5_group3~*(28) */
18382     { reserved_block      , 0                   , 0   , 32,
18383        0xfc00ffff, 0x2000fb7f, 0                      , 0,
18384        0x0                 },        /* POOL32Axf_5_group3~*(29) */
18385     { reserved_block      , 0                   , 0   , 32,
18386        0xfc00ffff, 0x2000fd7f, 0                      , 0,
18387        0x0                 },        /* POOL32Axf_5_group3~*(30) */
18388     { reserved_block      , 0                   , 0   , 32,
18389        0xfc00ffff, 0x2000ff7f, 0                      , 0,
18390        0x0                 },        /* POOL32Axf_5_group3~*(31) */
18391 };
18392 
18393 
18394 static const Pool POOL32Axf_5[4] = {
18395     { pool                , POOL32Axf_5_group0  , 32  , 32,
18396        0xfc00c1ff, 0x2000017f, 0                      , 0,
18397        0x0                 },        /* POOL32Axf_5_group0 */
18398     { pool                , POOL32Axf_5_group1  , 32  , 32,
18399        0xfc00c1ff, 0x2000417f, 0                      , 0,
18400        0x0                 },        /* POOL32Axf_5_group1 */
18401     { reserved_block      , 0                   , 0   , 32,
18402        0xfc00c1ff, 0x2000817f, 0                      , 0,
18403        0x0                 },        /* POOL32Axf_5~*(2) */
18404     { pool                , POOL32Axf_5_group3  , 32  , 32,
18405        0xfc00c1ff, 0x2000c17f, 0                      , 0,
18406        0x0                 },        /* POOL32Axf_5_group3 */
18407 };
18408 
18409 
18410 static const Pool SHRA__R__QB[2] = {
18411     { instruction         , 0                   , 0   , 32,
18412        0xfc001fff, 0x200001ff, &SHRA_QB          , 0,
18413        DSP_                },        /* SHRA.QB */
18414     { instruction         , 0                   , 0   , 32,
18415        0xfc001fff, 0x200011ff, &SHRA_R_QB        , 0,
18416        DSP_                },        /* SHRA_R.QB */
18417 };
18418 
18419 
18420 static const Pool POOL32Axf_7[8] = {
18421     { pool                , SHRA__R__QB         , 2   , 32,
18422        0xfc000fff, 0x200001ff, 0                      , 0,
18423        0x0                 },        /* SHRA[_R].QB */
18424     { instruction         , 0                   , 0   , 32,
18425        0xfc000fff, 0x200003ff, &SHRL_PH          , 0,
18426        DSP_                },        /* SHRL.PH */
18427     { instruction         , 0                   , 0   , 32,
18428        0xfc000fff, 0x200005ff, &REPL_QB          , 0,
18429        DSP_                },        /* REPL.QB */
18430     { reserved_block      , 0                   , 0   , 32,
18431        0xfc000fff, 0x200007ff, 0                      , 0,
18432        0x0                 },        /* POOL32Axf_7~*(3) */
18433     { reserved_block      , 0                   , 0   , 32,
18434        0xfc000fff, 0x200009ff, 0                      , 0,
18435        0x0                 },        /* POOL32Axf_7~*(4) */
18436     { reserved_block      , 0                   , 0   , 32,
18437        0xfc000fff, 0x20000bff, 0                      , 0,
18438        0x0                 },        /* POOL32Axf_7~*(5) */
18439     { reserved_block      , 0                   , 0   , 32,
18440        0xfc000fff, 0x20000dff, 0                      , 0,
18441        0x0                 },        /* POOL32Axf_7~*(6) */
18442     { reserved_block      , 0                   , 0   , 32,
18443        0xfc000fff, 0x20000fff, 0                      , 0,
18444        0x0                 },        /* POOL32Axf_7~*(7) */
18445 };
18446 
18447 
18448 static const Pool POOL32Axf[8] = {
18449     { reserved_block      , 0                   , 0   , 32,
18450        0xfc0001ff, 0x2000003f, 0                      , 0,
18451        0x0                 },        /* POOL32Axf~*(0) */
18452     { pool                , POOL32Axf_1         , 8   , 32,
18453        0xfc0001ff, 0x2000007f, 0                      , 0,
18454        0x0                 },        /* POOL32Axf_1 */
18455     { pool                , POOL32Axf_2         , 4   , 32,
18456        0xfc0001ff, 0x200000bf, 0                      , 0,
18457        0x0                 },        /* POOL32Axf_2 */
18458     { reserved_block      , 0                   , 0   , 32,
18459        0xfc0001ff, 0x200000ff, 0                      , 0,
18460        0x0                 },        /* POOL32Axf~*(3) */
18461     { pool                , POOL32Axf_4         , 128 , 32,
18462        0xfc0001ff, 0x2000013f, 0                      , 0,
18463        0x0                 },        /* POOL32Axf_4 */
18464     { pool                , POOL32Axf_5         , 4   , 32,
18465        0xfc0001ff, 0x2000017f, 0                      , 0,
18466        0x0                 },        /* POOL32Axf_5 */
18467     { reserved_block      , 0                   , 0   , 32,
18468        0xfc0001ff, 0x200001bf, 0                      , 0,
18469        0x0                 },        /* POOL32Axf~*(6) */
18470     { pool                , POOL32Axf_7         , 8   , 32,
18471        0xfc0001ff, 0x200001ff, 0                      , 0,
18472        0x0                 },        /* POOL32Axf_7 */
18473 };
18474 
18475 
18476 static const Pool _POOL32A7[8] = {
18477     { pool                , P_LSX               , 2   , 32,
18478        0xfc00003f, 0x20000007, 0                      , 0,
18479        0x0                 },        /* P.LSX */
18480     { instruction         , 0                   , 0   , 32,
18481        0xfc00003f, 0x2000000f, &LSA              , 0,
18482        0x0                 },        /* LSA */
18483     { reserved_block      , 0                   , 0   , 32,
18484        0xfc00003f, 0x20000017, 0                      , 0,
18485        0x0                 },        /* _POOL32A7~*(2) */
18486     { instruction         , 0                   , 0   , 32,
18487        0xfc00003f, 0x2000001f, &EXTW             , 0,
18488        0x0                 },        /* EXTW */
18489     { reserved_block      , 0                   , 0   , 32,
18490        0xfc00003f, 0x20000027, 0                      , 0,
18491        0x0                 },        /* _POOL32A7~*(4) */
18492     { reserved_block      , 0                   , 0   , 32,
18493        0xfc00003f, 0x2000002f, 0                      , 0,
18494        0x0                 },        /* _POOL32A7~*(5) */
18495     { reserved_block      , 0                   , 0   , 32,
18496        0xfc00003f, 0x20000037, 0                      , 0,
18497        0x0                 },        /* _POOL32A7~*(6) */
18498     { pool                , POOL32Axf           , 8   , 32,
18499        0xfc00003f, 0x2000003f, 0                      , 0,
18500        0x0                 },        /* POOL32Axf */
18501 };
18502 
18503 
18504 static const Pool P32A[8] = {
18505     { pool                , _POOL32A0           , 128 , 32,
18506        0xfc000007, 0x20000000, 0                      , 0,
18507        0x0                 },        /* _POOL32A0 */
18508     { instruction         , 0                   , 0   , 32,
18509        0xfc000007, 0x20000001, &SPECIAL2         , 0,
18510        UDI_                },        /* SPECIAL2 */
18511     { instruction         , 0                   , 0   , 32,
18512        0xfc000007, 0x20000002, &COP2_1           , 0,
18513        CP2_                },        /* COP2_1 */
18514     { instruction         , 0                   , 0   , 32,
18515        0xfc000007, 0x20000003, &UDI              , 0,
18516        UDI_                },        /* UDI */
18517     { reserved_block      , 0                   , 0   , 32,
18518        0xfc000007, 0x20000004, 0                      , 0,
18519        0x0                 },        /* P32A~*(4) */
18520     { pool                , _POOL32A5           , 128 , 32,
18521        0xfc000007, 0x20000005, 0                      , 0,
18522        0x0                 },        /* _POOL32A5 */
18523     { reserved_block      , 0                   , 0   , 32,
18524        0xfc000007, 0x20000006, 0                      , 0,
18525        0x0                 },        /* P32A~*(6) */
18526     { pool                , _POOL32A7           , 8   , 32,
18527        0xfc000007, 0x20000007, 0                      , 0,
18528        0x0                 },        /* _POOL32A7 */
18529 };
18530 
18531 
18532 static const Pool P_GP_D[2] = {
18533     { instruction         , 0                   , 0   , 32,
18534        0xfc000007, 0x40000001, &LD_GP_           , 0,
18535        MIPS64_             },        /* LD[GP] */
18536     { instruction         , 0                   , 0   , 32,
18537        0xfc000007, 0x40000005, &SD_GP_           , 0,
18538        MIPS64_             },        /* SD[GP] */
18539 };
18540 
18541 
18542 static const Pool P_GP_W[4] = {
18543     { instruction         , 0                   , 0   , 32,
18544        0xfc000003, 0x40000000, &ADDIU_GP_W_      , 0,
18545        0x0                 },        /* ADDIU[GP.W] */
18546     { pool                , P_GP_D              , 2   , 32,
18547        0xfc000003, 0x40000001, 0                      , 0,
18548        0x0                 },        /* P.GP.D */
18549     { instruction         , 0                   , 0   , 32,
18550        0xfc000003, 0x40000002, &LW_GP_           , 0,
18551        0x0                 },        /* LW[GP] */
18552     { instruction         , 0                   , 0   , 32,
18553        0xfc000003, 0x40000003, &SW_GP_           , 0,
18554        0x0                 },        /* SW[GP] */
18555 };
18556 
18557 
18558 static const Pool POOL48I[32] = {
18559     { instruction         , 0                   , 0   , 48,
18560        0xfc1f00000000ull, 0x600000000000ull, &LI_48_           , 0,
18561        XMMS_               },        /* LI[48] */
18562     { instruction         , 0                   , 0   , 48,
18563        0xfc1f00000000ull, 0x600100000000ull, &ADDIU_48_        , 0,
18564        XMMS_               },        /* ADDIU[48] */
18565     { instruction         , 0                   , 0   , 48,
18566        0xfc1f00000000ull, 0x600200000000ull, &ADDIU_GP48_      , 0,
18567        XMMS_               },        /* ADDIU[GP48] */
18568     { instruction         , 0                   , 0   , 48,
18569        0xfc1f00000000ull, 0x600300000000ull, &ADDIUPC_48_      , 0,
18570        XMMS_               },        /* ADDIUPC[48] */
18571     { reserved_block      , 0                   , 0   , 48,
18572        0xfc1f00000000ull, 0x600400000000ull, 0                      , 0,
18573        0x0                 },        /* POOL48I~*(4) */
18574     { reserved_block      , 0                   , 0   , 48,
18575        0xfc1f00000000ull, 0x600500000000ull, 0                      , 0,
18576        0x0                 },        /* POOL48I~*(5) */
18577     { reserved_block      , 0                   , 0   , 48,
18578        0xfc1f00000000ull, 0x600600000000ull, 0                      , 0,
18579        0x0                 },        /* POOL48I~*(6) */
18580     { reserved_block      , 0                   , 0   , 48,
18581        0xfc1f00000000ull, 0x600700000000ull, 0                      , 0,
18582        0x0                 },        /* POOL48I~*(7) */
18583     { reserved_block      , 0                   , 0   , 48,
18584        0xfc1f00000000ull, 0x600800000000ull, 0                      , 0,
18585        0x0                 },        /* POOL48I~*(8) */
18586     { reserved_block      , 0                   , 0   , 48,
18587        0xfc1f00000000ull, 0x600900000000ull, 0                      , 0,
18588        0x0                 },        /* POOL48I~*(9) */
18589     { reserved_block      , 0                   , 0   , 48,
18590        0xfc1f00000000ull, 0x600a00000000ull, 0                      , 0,
18591        0x0                 },        /* POOL48I~*(10) */
18592     { instruction         , 0                   , 0   , 48,
18593        0xfc1f00000000ull, 0x600b00000000ull, &LWPC_48_         , 0,
18594        XMMS_               },        /* LWPC[48] */
18595     { reserved_block      , 0                   , 0   , 48,
18596        0xfc1f00000000ull, 0x600c00000000ull, 0                      , 0,
18597        0x0                 },        /* POOL48I~*(12) */
18598     { reserved_block      , 0                   , 0   , 48,
18599        0xfc1f00000000ull, 0x600d00000000ull, 0                      , 0,
18600        0x0                 },        /* POOL48I~*(13) */
18601     { reserved_block      , 0                   , 0   , 48,
18602        0xfc1f00000000ull, 0x600e00000000ull, 0                      , 0,
18603        0x0                 },        /* POOL48I~*(14) */
18604     { instruction         , 0                   , 0   , 48,
18605        0xfc1f00000000ull, 0x600f00000000ull, &SWPC_48_         , 0,
18606        XMMS_               },        /* SWPC[48] */
18607     { reserved_block      , 0                   , 0   , 48,
18608        0xfc1f00000000ull, 0x601000000000ull, 0                      , 0,
18609        0x0                 },        /* POOL48I~*(16) */
18610     { instruction         , 0                   , 0   , 48,
18611        0xfc1f00000000ull, 0x601100000000ull, &DADDIU_48_       , 0,
18612        MIPS64_             },        /* DADDIU[48] */
18613     { reserved_block      , 0                   , 0   , 48,
18614        0xfc1f00000000ull, 0x601200000000ull, 0                      , 0,
18615        0x0                 },        /* POOL48I~*(18) */
18616     { reserved_block      , 0                   , 0   , 48,
18617        0xfc1f00000000ull, 0x601300000000ull, 0                      , 0,
18618        0x0                 },        /* POOL48I~*(19) */
18619     { instruction         , 0                   , 0   , 48,
18620        0xfc1f00000000ull, 0x601400000000ull, &DLUI_48_         , 0,
18621        MIPS64_             },        /* DLUI[48] */
18622     { reserved_block      , 0                   , 0   , 48,
18623        0xfc1f00000000ull, 0x601500000000ull, 0                      , 0,
18624        0x0                 },        /* POOL48I~*(21) */
18625     { reserved_block      , 0                   , 0   , 48,
18626        0xfc1f00000000ull, 0x601600000000ull, 0                      , 0,
18627        0x0                 },        /* POOL48I~*(22) */
18628     { reserved_block      , 0                   , 0   , 48,
18629        0xfc1f00000000ull, 0x601700000000ull, 0                      , 0,
18630        0x0                 },        /* POOL48I~*(23) */
18631     { reserved_block      , 0                   , 0   , 48,
18632        0xfc1f00000000ull, 0x601800000000ull, 0                      , 0,
18633        0x0                 },        /* POOL48I~*(24) */
18634     { reserved_block      , 0                   , 0   , 48,
18635        0xfc1f00000000ull, 0x601900000000ull, 0                      , 0,
18636        0x0                 },        /* POOL48I~*(25) */
18637     { reserved_block      , 0                   , 0   , 48,
18638        0xfc1f00000000ull, 0x601a00000000ull, 0                      , 0,
18639        0x0                 },        /* POOL48I~*(26) */
18640     { instruction         , 0                   , 0   , 48,
18641        0xfc1f00000000ull, 0x601b00000000ull, &LDPC_48_         , 0,
18642        MIPS64_             },        /* LDPC[48] */
18643     { reserved_block      , 0                   , 0   , 48,
18644        0xfc1f00000000ull, 0x601c00000000ull, 0                      , 0,
18645        0x0                 },        /* POOL48I~*(28) */
18646     { reserved_block      , 0                   , 0   , 48,
18647        0xfc1f00000000ull, 0x601d00000000ull, 0                      , 0,
18648        0x0                 },        /* POOL48I~*(29) */
18649     { reserved_block      , 0                   , 0   , 48,
18650        0xfc1f00000000ull, 0x601e00000000ull, 0                      , 0,
18651        0x0                 },        /* POOL48I~*(30) */
18652     { instruction         , 0                   , 0   , 48,
18653        0xfc1f00000000ull, 0x601f00000000ull, &SDPC_48_         , 0,
18654        MIPS64_             },        /* SDPC[48] */
18655 };
18656 
18657 
18658 static const Pool PP_SR[4] = {
18659     { instruction         , 0                   , 0   , 32,
18660        0xfc10f003, 0x80003000, &SAVE_32_         , 0,
18661        0x0                 },        /* SAVE[32] */
18662     { reserved_block      , 0                   , 0   , 32,
18663        0xfc10f003, 0x80003001, 0                      , 0,
18664        0x0                 },        /* PP.SR~*(1) */
18665     { instruction         , 0                   , 0   , 32,
18666        0xfc10f003, 0x80003002, &RESTORE_32_      , 0,
18667        0x0                 },        /* RESTORE[32] */
18668     { return_instruction  , 0                   , 0   , 32,
18669        0xfc10f003, 0x80003003, &RESTORE_JRC_32_  , 0,
18670        0x0                 },        /* RESTORE.JRC[32] */
18671 };
18672 
18673 
18674 static const Pool P_SR_F[8] = {
18675     { instruction         , 0                   , 0   , 32,
18676        0xfc10f007, 0x80103000, &SAVEF            , 0,
18677        CP1_                },        /* SAVEF */
18678     { instruction         , 0                   , 0   , 32,
18679        0xfc10f007, 0x80103001, &RESTOREF         , 0,
18680        CP1_                },        /* RESTOREF */
18681     { reserved_block      , 0                   , 0   , 32,
18682        0xfc10f007, 0x80103002, 0                      , 0,
18683        0x0                 },        /* P.SR.F~*(2) */
18684     { reserved_block      , 0                   , 0   , 32,
18685        0xfc10f007, 0x80103003, 0                      , 0,
18686        0x0                 },        /* P.SR.F~*(3) */
18687     { reserved_block      , 0                   , 0   , 32,
18688        0xfc10f007, 0x80103004, 0                      , 0,
18689        0x0                 },        /* P.SR.F~*(4) */
18690     { reserved_block      , 0                   , 0   , 32,
18691        0xfc10f007, 0x80103005, 0                      , 0,
18692        0x0                 },        /* P.SR.F~*(5) */
18693     { reserved_block      , 0                   , 0   , 32,
18694        0xfc10f007, 0x80103006, 0                      , 0,
18695        0x0                 },        /* P.SR.F~*(6) */
18696     { reserved_block      , 0                   , 0   , 32,
18697        0xfc10f007, 0x80103007, 0                      , 0,
18698        0x0                 },        /* P.SR.F~*(7) */
18699 };
18700 
18701 
18702 static const Pool P_SR[2] = {
18703     { pool                , PP_SR               , 4   , 32,
18704        0xfc10f000, 0x80003000, 0                      , 0,
18705        0x0                 },        /* PP.SR */
18706     { pool                , P_SR_F              , 8   , 32,
18707        0xfc10f000, 0x80103000, 0                      , 0,
18708        0x0                 },        /* P.SR.F */
18709 };
18710 
18711 
18712 static const Pool P_SLL[5] = {
18713     { instruction         , 0                   , 0   , 32,
18714        0xffe0f1ff, 0x8000c000, &NOP_32_          , 0,
18715        0x0                 },        /* NOP[32] */
18716     { instruction         , 0                   , 0   , 32,
18717        0xffe0f1ff, 0x8000c003, &EHB              , 0,
18718        0x0                 },        /* EHB */
18719     { instruction         , 0                   , 0   , 32,
18720        0xffe0f1ff, 0x8000c005, &PAUSE            , 0,
18721        0x0                 },        /* PAUSE */
18722     { instruction         , 0                   , 0   , 32,
18723        0xffe0f1ff, 0x8000c006, &SYNC             , 0,
18724        0x0                 },        /* SYNC */
18725     { instruction         , 0                   , 0   , 32,
18726        0xfc00f1e0, 0x8000c000, &SLL_32_          , 0,
18727        0x0                 },        /* SLL[32] */
18728 };
18729 
18730 
18731 static const Pool P_SHIFT[16] = {
18732     { pool                , P_SLL               , 5   , 32,
18733        0xfc00f1e0, 0x8000c000, 0                      , 0,
18734        0x0                 },        /* P.SLL */
18735     { reserved_block      , 0                   , 0   , 32,
18736        0xfc00f1e0, 0x8000c020, 0                      , 0,
18737        0x0                 },        /* P.SHIFT~*(1) */
18738     { instruction         , 0                   , 0   , 32,
18739        0xfc00f1e0, 0x8000c040, &SRL_32_          , 0,
18740        0x0                 },        /* SRL[32] */
18741     { reserved_block      , 0                   , 0   , 32,
18742        0xfc00f1e0, 0x8000c060, 0                      , 0,
18743        0x0                 },        /* P.SHIFT~*(3) */
18744     { instruction         , 0                   , 0   , 32,
18745        0xfc00f1e0, 0x8000c080, &SRA              , 0,
18746        0x0                 },        /* SRA */
18747     { reserved_block      , 0                   , 0   , 32,
18748        0xfc00f1e0, 0x8000c0a0, 0                      , 0,
18749        0x0                 },        /* P.SHIFT~*(5) */
18750     { instruction         , 0                   , 0   , 32,
18751        0xfc00f1e0, 0x8000c0c0, &ROTR             , 0,
18752        0x0                 },        /* ROTR */
18753     { reserved_block      , 0                   , 0   , 32,
18754        0xfc00f1e0, 0x8000c0e0, 0                      , 0,
18755        0x0                 },        /* P.SHIFT~*(7) */
18756     { instruction         , 0                   , 0   , 32,
18757        0xfc00f1e0, 0x8000c100, &DSLL             , 0,
18758        MIPS64_             },        /* DSLL */
18759     { instruction         , 0                   , 0   , 32,
18760        0xfc00f1e0, 0x8000c120, &DSLL32           , 0,
18761        MIPS64_             },        /* DSLL32 */
18762     { instruction         , 0                   , 0   , 32,
18763        0xfc00f1e0, 0x8000c140, &DSRL             , 0,
18764        MIPS64_             },        /* DSRL */
18765     { instruction         , 0                   , 0   , 32,
18766        0xfc00f1e0, 0x8000c160, &DSRL32           , 0,
18767        MIPS64_             },        /* DSRL32 */
18768     { instruction         , 0                   , 0   , 32,
18769        0xfc00f1e0, 0x8000c180, &DSRA             , 0,
18770        MIPS64_             },        /* DSRA */
18771     { instruction         , 0                   , 0   , 32,
18772        0xfc00f1e0, 0x8000c1a0, &DSRA32           , 0,
18773        MIPS64_             },        /* DSRA32 */
18774     { instruction         , 0                   , 0   , 32,
18775        0xfc00f1e0, 0x8000c1c0, &DROTR            , 0,
18776        MIPS64_             },        /* DROTR */
18777     { instruction         , 0                   , 0   , 32,
18778        0xfc00f1e0, 0x8000c1e0, &DROTR32          , 0,
18779        MIPS64_             },        /* DROTR32 */
18780 };
18781 
18782 
18783 static const Pool P_ROTX[4] = {
18784     { instruction         , 0                   , 0   , 32,
18785        0xfc00f820, 0x8000d000, &ROTX             , 0,
18786        XMMS_               },        /* ROTX */
18787     { reserved_block      , 0                   , 0   , 32,
18788        0xfc00f820, 0x8000d020, 0                      , 0,
18789        0x0                 },        /* P.ROTX~*(1) */
18790     { reserved_block      , 0                   , 0   , 32,
18791        0xfc00f820, 0x8000d800, 0                      , 0,
18792        0x0                 },        /* P.ROTX~*(2) */
18793     { reserved_block      , 0                   , 0   , 32,
18794        0xfc00f820, 0x8000d820, 0                      , 0,
18795        0x0                 },        /* P.ROTX~*(3) */
18796 };
18797 
18798 
18799 static const Pool P_INS[4] = {
18800     { instruction         , 0                   , 0   , 32,
18801        0xfc00f820, 0x8000e000, &INS              , 0,
18802        XMMS_               },        /* INS */
18803     { instruction         , 0                   , 0   , 32,
18804        0xfc00f820, 0x8000e020, &DINSU            , 0,
18805        MIPS64_             },        /* DINSU */
18806     { instruction         , 0                   , 0   , 32,
18807        0xfc00f820, 0x8000e800, &DINSM            , 0,
18808        MIPS64_             },        /* DINSM */
18809     { instruction         , 0                   , 0   , 32,
18810        0xfc00f820, 0x8000e820, &DINS             , 0,
18811        MIPS64_             },        /* DINS */
18812 };
18813 
18814 
18815 static const Pool P_EXT[4] = {
18816     { instruction         , 0                   , 0   , 32,
18817        0xfc00f820, 0x8000f000, &EXT              , 0,
18818        XMMS_               },        /* EXT */
18819     { instruction         , 0                   , 0   , 32,
18820        0xfc00f820, 0x8000f020, &DEXTU            , 0,
18821        MIPS64_             },        /* DEXTU */
18822     { instruction         , 0                   , 0   , 32,
18823        0xfc00f820, 0x8000f800, &DEXTM            , 0,
18824        MIPS64_             },        /* DEXTM */
18825     { instruction         , 0                   , 0   , 32,
18826        0xfc00f820, 0x8000f820, &DEXT             , 0,
18827        MIPS64_             },        /* DEXT */
18828 };
18829 
18830 
18831 static const Pool P_U12[16] = {
18832     { instruction         , 0                   , 0   , 32,
18833        0xfc00f000, 0x80000000, &ORI              , 0,
18834        0x0                 },        /* ORI */
18835     { instruction         , 0                   , 0   , 32,
18836        0xfc00f000, 0x80001000, &XORI             , 0,
18837        0x0                 },        /* XORI */
18838     { instruction         , 0                   , 0   , 32,
18839        0xfc00f000, 0x80002000, &ANDI_32_         , 0,
18840        0x0                 },        /* ANDI[32] */
18841     { pool                , P_SR                , 2   , 32,
18842        0xfc00f000, 0x80003000, 0                      , 0,
18843        0x0                 },        /* P.SR */
18844     { instruction         , 0                   , 0   , 32,
18845        0xfc00f000, 0x80004000, &SLTI             , 0,
18846        0x0                 },        /* SLTI */
18847     { instruction         , 0                   , 0   , 32,
18848        0xfc00f000, 0x80005000, &SLTIU            , 0,
18849        0x0                 },        /* SLTIU */
18850     { instruction         , 0                   , 0   , 32,
18851        0xfc00f000, 0x80006000, &SEQI             , 0,
18852        0x0                 },        /* SEQI */
18853     { reserved_block      , 0                   , 0   , 32,
18854        0xfc00f000, 0x80007000, 0                      , 0,
18855        0x0                 },        /* P.U12~*(7) */
18856     { instruction         , 0                   , 0   , 32,
18857        0xfc00f000, 0x80008000, &ADDIU_NEG_       , 0,
18858        0x0                 },        /* ADDIU[NEG] */
18859     { instruction         , 0                   , 0   , 32,
18860        0xfc00f000, 0x80009000, &DADDIU_U12_      , 0,
18861        MIPS64_             },        /* DADDIU[U12] */
18862     { instruction         , 0                   , 0   , 32,
18863        0xfc00f000, 0x8000a000, &DADDIU_NEG_      , 0,
18864        MIPS64_             },        /* DADDIU[NEG] */
18865     { instruction         , 0                   , 0   , 32,
18866        0xfc00f000, 0x8000b000, &DROTX            , 0,
18867        MIPS64_             },        /* DROTX */
18868     { pool                , P_SHIFT             , 16  , 32,
18869        0xfc00f000, 0x8000c000, 0                      , 0,
18870        0x0                 },        /* P.SHIFT */
18871     { pool                , P_ROTX              , 4   , 32,
18872        0xfc00f000, 0x8000d000, 0                      , 0,
18873        0x0                 },        /* P.ROTX */
18874     { pool                , P_INS               , 4   , 32,
18875        0xfc00f000, 0x8000e000, 0                      , 0,
18876        0x0                 },        /* P.INS */
18877     { pool                , P_EXT               , 4   , 32,
18878        0xfc00f000, 0x8000f000, 0                      , 0,
18879        0x0                 },        /* P.EXT */
18880 };
18881 
18882 
18883 static const Pool RINT_fmt[2] = {
18884     { instruction         , 0                   , 0   , 32,
18885        0xfc0003ff, 0xa0000020, &RINT_S           , 0,
18886        CP1_                },        /* RINT.S */
18887     { instruction         , 0                   , 0   , 32,
18888        0xfc0003ff, 0xa0000220, &RINT_D           , 0,
18889        CP1_                },        /* RINT.D */
18890 };
18891 
18892 
18893 static const Pool ADD_fmt0[2] = {
18894     { instruction         , 0                   , 0   , 32,
18895        0xfc0003ff, 0xa0000030, &ADD_S            , 0,
18896        CP1_                },        /* ADD.S */
18897     { reserved_block      , 0                   , 0   , 32,
18898        0xfc0003ff, 0xa0000230, 0                      , 0,
18899        CP1_                },        /* ADD.fmt0~*(1) */
18900 };
18901 
18902 
18903 static const Pool SELEQZ_fmt[2] = {
18904     { instruction         , 0                   , 0   , 32,
18905        0xfc0003ff, 0xa0000038, &SELEQZ_S         , 0,
18906        CP1_                },        /* SELEQZ.S */
18907     { instruction         , 0                   , 0   , 32,
18908        0xfc0003ff, 0xa0000238, &SELEQZ_D         , 0,
18909        CP1_                },        /* SELEQZ.D */
18910 };
18911 
18912 
18913 static const Pool CLASS_fmt[2] = {
18914     { instruction         , 0                   , 0   , 32,
18915        0xfc0003ff, 0xa0000060, &CLASS_S          , 0,
18916        CP1_                },        /* CLASS.S */
18917     { instruction         , 0                   , 0   , 32,
18918        0xfc0003ff, 0xa0000260, &CLASS_D          , 0,
18919        CP1_                },        /* CLASS.D */
18920 };
18921 
18922 
18923 static const Pool SUB_fmt0[2] = {
18924     { instruction         , 0                   , 0   , 32,
18925        0xfc0003ff, 0xa0000070, &SUB_S            , 0,
18926        CP1_                },        /* SUB.S */
18927     { reserved_block      , 0                   , 0   , 32,
18928        0xfc0003ff, 0xa0000270, 0                      , 0,
18929        CP1_                },        /* SUB.fmt0~*(1) */
18930 };
18931 
18932 
18933 static const Pool SELNEZ_fmt[2] = {
18934     { instruction         , 0                   , 0   , 32,
18935        0xfc0003ff, 0xa0000078, &SELNEZ_S         , 0,
18936        CP1_                },        /* SELNEZ.S */
18937     { instruction         , 0                   , 0   , 32,
18938        0xfc0003ff, 0xa0000278, &SELNEZ_D         , 0,
18939        CP1_                },        /* SELNEZ.D */
18940 };
18941 
18942 
18943 static const Pool MUL_fmt0[2] = {
18944     { instruction         , 0                   , 0   , 32,
18945        0xfc0003ff, 0xa00000b0, &MUL_S            , 0,
18946        CP1_                },        /* MUL.S */
18947     { reserved_block      , 0                   , 0   , 32,
18948        0xfc0003ff, 0xa00002b0, 0                      , 0,
18949        CP1_                },        /* MUL.fmt0~*(1) */
18950 };
18951 
18952 
18953 static const Pool SEL_fmt[2] = {
18954     { instruction         , 0                   , 0   , 32,
18955        0xfc0003ff, 0xa00000b8, &SEL_S            , 0,
18956        CP1_                },        /* SEL.S */
18957     { instruction         , 0                   , 0   , 32,
18958        0xfc0003ff, 0xa00002b8, &SEL_D            , 0,
18959        CP1_                },        /* SEL.D */
18960 };
18961 
18962 
18963 static const Pool DIV_fmt0[2] = {
18964     { instruction         , 0                   , 0   , 32,
18965        0xfc0003ff, 0xa00000f0, &DIV_S            , 0,
18966        CP1_                },        /* DIV.S */
18967     { reserved_block      , 0                   , 0   , 32,
18968        0xfc0003ff, 0xa00002f0, 0                      , 0,
18969        CP1_                },        /* DIV.fmt0~*(1) */
18970 };
18971 
18972 
18973 static const Pool ADD_fmt1[2] = {
18974     { instruction         , 0                   , 0   , 32,
18975        0xfc0003ff, 0xa0000130, &ADD_D            , 0,
18976        CP1_                },        /* ADD.D */
18977     { reserved_block      , 0                   , 0   , 32,
18978        0xfc0003ff, 0xa0000330, 0                      , 0,
18979        CP1_                },        /* ADD.fmt1~*(1) */
18980 };
18981 
18982 
18983 static const Pool SUB_fmt1[2] = {
18984     { instruction         , 0                   , 0   , 32,
18985        0xfc0003ff, 0xa0000170, &SUB_D            , 0,
18986        CP1_                },        /* SUB.D */
18987     { reserved_block      , 0                   , 0   , 32,
18988        0xfc0003ff, 0xa0000370, 0                      , 0,
18989        CP1_                },        /* SUB.fmt1~*(1) */
18990 };
18991 
18992 
18993 static const Pool MUL_fmt1[2] = {
18994     { instruction         , 0                   , 0   , 32,
18995        0xfc0003ff, 0xa00001b0, &MUL_D            , 0,
18996        CP1_                },        /* MUL.D */
18997     { reserved_block      , 0                   , 0   , 32,
18998        0xfc0003ff, 0xa00003b0, 0                      , 0,
18999        CP1_                },        /* MUL.fmt1~*(1) */
19000 };
19001 
19002 
19003 static const Pool MADDF_fmt[2] = {
19004     { instruction         , 0                   , 0   , 32,
19005        0xfc0003ff, 0xa00001b8, &MADDF_S          , 0,
19006        CP1_                },        /* MADDF.S */
19007     { instruction         , 0                   , 0   , 32,
19008        0xfc0003ff, 0xa00003b8, &MADDF_D          , 0,
19009        CP1_                },        /* MADDF.D */
19010 };
19011 
19012 
19013 static const Pool DIV_fmt1[2] = {
19014     { instruction         , 0                   , 0   , 32,
19015        0xfc0003ff, 0xa00001f0, &DIV_D            , 0,
19016        CP1_                },        /* DIV.D */
19017     { reserved_block      , 0                   , 0   , 32,
19018        0xfc0003ff, 0xa00003f0, 0                      , 0,
19019        CP1_                },        /* DIV.fmt1~*(1) */
19020 };
19021 
19022 
19023 static const Pool MSUBF_fmt[2] = {
19024     { instruction         , 0                   , 0   , 32,
19025        0xfc0003ff, 0xa00001f8, &MSUBF_S          , 0,
19026        CP1_                },        /* MSUBF.S */
19027     { instruction         , 0                   , 0   , 32,
19028        0xfc0003ff, 0xa00003f8, &MSUBF_D          , 0,
19029        CP1_                },        /* MSUBF.D */
19030 };
19031 
19032 
19033 static const Pool POOL32F_0[64] = {
19034     { reserved_block      , 0                   , 0   , 32,
19035        0xfc0001ff, 0xa0000000, 0                      , 0,
19036        CP1_                },        /* POOL32F_0~*(0) */
19037     { reserved_block      , 0                   , 0   , 32,
19038        0xfc0001ff, 0xa0000008, 0                      , 0,
19039        CP1_                },        /* POOL32F_0~*(1) */
19040     { reserved_block      , 0                   , 0   , 32,
19041        0xfc0001ff, 0xa0000010, 0                      , 0,
19042        CP1_                },        /* POOL32F_0~*(2) */
19043     { reserved_block      , 0                   , 0   , 32,
19044        0xfc0001ff, 0xa0000018, 0                      , 0,
19045        CP1_                },        /* POOL32F_0~*(3) */
19046     { pool                , RINT_fmt            , 2   , 32,
19047        0xfc0001ff, 0xa0000020, 0                      , 0,
19048        CP1_                },        /* RINT.fmt */
19049     { reserved_block      , 0                   , 0   , 32,
19050        0xfc0001ff, 0xa0000028, 0                      , 0,
19051        CP1_                },        /* POOL32F_0~*(5) */
19052     { pool                , ADD_fmt0            , 2   , 32,
19053        0xfc0001ff, 0xa0000030, 0                      , 0,
19054        CP1_                },        /* ADD.fmt0 */
19055     { pool                , SELEQZ_fmt          , 2   , 32,
19056        0xfc0001ff, 0xa0000038, 0                      , 0,
19057        CP1_                },        /* SELEQZ.fmt */
19058     { reserved_block      , 0                   , 0   , 32,
19059        0xfc0001ff, 0xa0000040, 0                      , 0,
19060        CP1_                },        /* POOL32F_0~*(8) */
19061     { reserved_block      , 0                   , 0   , 32,
19062        0xfc0001ff, 0xa0000048, 0                      , 0,
19063        CP1_                },        /* POOL32F_0~*(9) */
19064     { reserved_block      , 0                   , 0   , 32,
19065        0xfc0001ff, 0xa0000050, 0                      , 0,
19066        CP1_                },        /* POOL32F_0~*(10) */
19067     { reserved_block      , 0                   , 0   , 32,
19068        0xfc0001ff, 0xa0000058, 0                      , 0,
19069        CP1_                },        /* POOL32F_0~*(11) */
19070     { pool                , CLASS_fmt           , 2   , 32,
19071        0xfc0001ff, 0xa0000060, 0                      , 0,
19072        CP1_                },        /* CLASS.fmt */
19073     { reserved_block      , 0                   , 0   , 32,
19074        0xfc0001ff, 0xa0000068, 0                      , 0,
19075        CP1_                },        /* POOL32F_0~*(13) */
19076     { pool                , SUB_fmt0            , 2   , 32,
19077        0xfc0001ff, 0xa0000070, 0                      , 0,
19078        CP1_                },        /* SUB.fmt0 */
19079     { pool                , SELNEZ_fmt          , 2   , 32,
19080        0xfc0001ff, 0xa0000078, 0                      , 0,
19081        CP1_                },        /* SELNEZ.fmt */
19082     { reserved_block      , 0                   , 0   , 32,
19083        0xfc0001ff, 0xa0000080, 0                      , 0,
19084        CP1_                },        /* POOL32F_0~*(16) */
19085     { reserved_block      , 0                   , 0   , 32,
19086        0xfc0001ff, 0xa0000088, 0                      , 0,
19087        CP1_                },        /* POOL32F_0~*(17) */
19088     { reserved_block      , 0                   , 0   , 32,
19089        0xfc0001ff, 0xa0000090, 0                      , 0,
19090        CP1_                },        /* POOL32F_0~*(18) */
19091     { reserved_block      , 0                   , 0   , 32,
19092        0xfc0001ff, 0xa0000098, 0                      , 0,
19093        CP1_                },        /* POOL32F_0~*(19) */
19094     { reserved_block      , 0                   , 0   , 32,
19095        0xfc0001ff, 0xa00000a0, 0                      , 0,
19096        CP1_                },        /* POOL32F_0~*(20) */
19097     { reserved_block      , 0                   , 0   , 32,
19098        0xfc0001ff, 0xa00000a8, 0                      , 0,
19099        CP1_                },        /* POOL32F_0~*(21) */
19100     { pool                , MUL_fmt0            , 2   , 32,
19101        0xfc0001ff, 0xa00000b0, 0                      , 0,
19102        CP1_                },        /* MUL.fmt0 */
19103     { pool                , SEL_fmt             , 2   , 32,
19104        0xfc0001ff, 0xa00000b8, 0                      , 0,
19105        CP1_                },        /* SEL.fmt */
19106     { reserved_block      , 0                   , 0   , 32,
19107        0xfc0001ff, 0xa00000c0, 0                      , 0,
19108        CP1_                },        /* POOL32F_0~*(24) */
19109     { reserved_block      , 0                   , 0   , 32,
19110        0xfc0001ff, 0xa00000c8, 0                      , 0,
19111        CP1_                },        /* POOL32F_0~*(25) */
19112     { reserved_block      , 0                   , 0   , 32,
19113        0xfc0001ff, 0xa00000d0, 0                      , 0,
19114        CP1_                },        /* POOL32F_0~*(26) */
19115     { reserved_block      , 0                   , 0   , 32,
19116        0xfc0001ff, 0xa00000d8, 0                      , 0,
19117        CP1_                },        /* POOL32F_0~*(27) */
19118     { reserved_block      , 0                   , 0   , 32,
19119        0xfc0001ff, 0xa00000e0, 0                      , 0,
19120        CP1_                },        /* POOL32F_0~*(28) */
19121     { reserved_block      , 0                   , 0   , 32,
19122        0xfc0001ff, 0xa00000e8, 0                      , 0,
19123        CP1_                },        /* POOL32F_0~*(29) */
19124     { pool                , DIV_fmt0            , 2   , 32,
19125        0xfc0001ff, 0xa00000f0, 0                      , 0,
19126        CP1_                },        /* DIV.fmt0 */
19127     { reserved_block      , 0                   , 0   , 32,
19128        0xfc0001ff, 0xa00000f8, 0                      , 0,
19129        CP1_                },        /* POOL32F_0~*(31) */
19130     { reserved_block      , 0                   , 0   , 32,
19131        0xfc0001ff, 0xa0000100, 0                      , 0,
19132        CP1_                },        /* POOL32F_0~*(32) */
19133     { reserved_block      , 0                   , 0   , 32,
19134        0xfc0001ff, 0xa0000108, 0                      , 0,
19135        CP1_                },        /* POOL32F_0~*(33) */
19136     { reserved_block      , 0                   , 0   , 32,
19137        0xfc0001ff, 0xa0000110, 0                      , 0,
19138        CP1_                },        /* POOL32F_0~*(34) */
19139     { reserved_block      , 0                   , 0   , 32,
19140        0xfc0001ff, 0xa0000118, 0                      , 0,
19141        CP1_                },        /* POOL32F_0~*(35) */
19142     { reserved_block      , 0                   , 0   , 32,
19143        0xfc0001ff, 0xa0000120, 0                      , 0,
19144        CP1_                },        /* POOL32F_0~*(36) */
19145     { reserved_block      , 0                   , 0   , 32,
19146        0xfc0001ff, 0xa0000128, 0                      , 0,
19147        CP1_                },        /* POOL32F_0~*(37) */
19148     { pool                , ADD_fmt1            , 2   , 32,
19149        0xfc0001ff, 0xa0000130, 0                      , 0,
19150        CP1_                },        /* ADD.fmt1 */
19151     { reserved_block      , 0                   , 0   , 32,
19152        0xfc0001ff, 0xa0000138, 0                      , 0,
19153        CP1_                },        /* POOL32F_0~*(39) */
19154     { reserved_block      , 0                   , 0   , 32,
19155        0xfc0001ff, 0xa0000140, 0                      , 0,
19156        CP1_                },        /* POOL32F_0~*(40) */
19157     { reserved_block      , 0                   , 0   , 32,
19158        0xfc0001ff, 0xa0000148, 0                      , 0,
19159        CP1_                },        /* POOL32F_0~*(41) */
19160     { reserved_block      , 0                   , 0   , 32,
19161        0xfc0001ff, 0xa0000150, 0                      , 0,
19162        CP1_                },        /* POOL32F_0~*(42) */
19163     { reserved_block      , 0                   , 0   , 32,
19164        0xfc0001ff, 0xa0000158, 0                      , 0,
19165        CP1_                },        /* POOL32F_0~*(43) */
19166     { reserved_block      , 0                   , 0   , 32,
19167        0xfc0001ff, 0xa0000160, 0                      , 0,
19168        CP1_                },        /* POOL32F_0~*(44) */
19169     { reserved_block      , 0                   , 0   , 32,
19170        0xfc0001ff, 0xa0000168, 0                      , 0,
19171        CP1_                },        /* POOL32F_0~*(45) */
19172     { pool                , SUB_fmt1            , 2   , 32,
19173        0xfc0001ff, 0xa0000170, 0                      , 0,
19174        CP1_                },        /* SUB.fmt1 */
19175     { reserved_block      , 0                   , 0   , 32,
19176        0xfc0001ff, 0xa0000178, 0                      , 0,
19177        CP1_                },        /* POOL32F_0~*(47) */
19178     { reserved_block      , 0                   , 0   , 32,
19179        0xfc0001ff, 0xa0000180, 0                      , 0,
19180        CP1_                },        /* POOL32F_0~*(48) */
19181     { reserved_block      , 0                   , 0   , 32,
19182        0xfc0001ff, 0xa0000188, 0                      , 0,
19183        CP1_                },        /* POOL32F_0~*(49) */
19184     { reserved_block      , 0                   , 0   , 32,
19185        0xfc0001ff, 0xa0000190, 0                      , 0,
19186        CP1_                },        /* POOL32F_0~*(50) */
19187     { reserved_block      , 0                   , 0   , 32,
19188        0xfc0001ff, 0xa0000198, 0                      , 0,
19189        CP1_                },        /* POOL32F_0~*(51) */
19190     { reserved_block      , 0                   , 0   , 32,
19191        0xfc0001ff, 0xa00001a0, 0                      , 0,
19192        CP1_                },        /* POOL32F_0~*(52) */
19193     { reserved_block      , 0                   , 0   , 32,
19194        0xfc0001ff, 0xa00001a8, 0                      , 0,
19195        CP1_                },        /* POOL32F_0~*(53) */
19196     { pool                , MUL_fmt1            , 2   , 32,
19197        0xfc0001ff, 0xa00001b0, 0                      , 0,
19198        CP1_                },        /* MUL.fmt1 */
19199     { pool                , MADDF_fmt           , 2   , 32,
19200        0xfc0001ff, 0xa00001b8, 0                      , 0,
19201        CP1_                },        /* MADDF.fmt */
19202     { reserved_block      , 0                   , 0   , 32,
19203        0xfc0001ff, 0xa00001c0, 0                      , 0,
19204        CP1_                },        /* POOL32F_0~*(56) */
19205     { reserved_block      , 0                   , 0   , 32,
19206        0xfc0001ff, 0xa00001c8, 0                      , 0,
19207        CP1_                },        /* POOL32F_0~*(57) */
19208     { reserved_block      , 0                   , 0   , 32,
19209        0xfc0001ff, 0xa00001d0, 0                      , 0,
19210        CP1_                },        /* POOL32F_0~*(58) */
19211     { reserved_block      , 0                   , 0   , 32,
19212        0xfc0001ff, 0xa00001d8, 0                      , 0,
19213        CP1_                },        /* POOL32F_0~*(59) */
19214     { reserved_block      , 0                   , 0   , 32,
19215        0xfc0001ff, 0xa00001e0, 0                      , 0,
19216        CP1_                },        /* POOL32F_0~*(60) */
19217     { reserved_block      , 0                   , 0   , 32,
19218        0xfc0001ff, 0xa00001e8, 0                      , 0,
19219        CP1_                },        /* POOL32F_0~*(61) */
19220     { pool                , DIV_fmt1            , 2   , 32,
19221        0xfc0001ff, 0xa00001f0, 0                      , 0,
19222        CP1_                },        /* DIV.fmt1 */
19223     { pool                , MSUBF_fmt           , 2   , 32,
19224        0xfc0001ff, 0xa00001f8, 0                      , 0,
19225        CP1_                },        /* MSUBF.fmt */
19226 };
19227 
19228 
19229 static const Pool MIN_fmt[2] = {
19230     { instruction         , 0                   , 0   , 32,
19231        0xfc00023f, 0xa0000003, &MIN_S            , 0,
19232        CP1_                },        /* MIN.S */
19233     { instruction         , 0                   , 0   , 32,
19234        0xfc00023f, 0xa0000203, &MIN_D            , 0,
19235        CP1_                },        /* MIN.D */
19236 };
19237 
19238 
19239 static const Pool MAX_fmt[2] = {
19240     { instruction         , 0                   , 0   , 32,
19241        0xfc00023f, 0xa000000b, &MAX_S            , 0,
19242        CP1_                },        /* MAX.S */
19243     { instruction         , 0                   , 0   , 32,
19244        0xfc00023f, 0xa000020b, &MAX_D            , 0,
19245        CP1_                },        /* MAX.D */
19246 };
19247 
19248 
19249 static const Pool MINA_fmt[2] = {
19250     { instruction         , 0                   , 0   , 32,
19251        0xfc00023f, 0xa0000023, &MINA_S           , 0,
19252        CP1_                },        /* MINA.S */
19253     { instruction         , 0                   , 0   , 32,
19254        0xfc00023f, 0xa0000223, &MINA_D           , 0,
19255        CP1_                },        /* MINA.D */
19256 };
19257 
19258 
19259 static const Pool MAXA_fmt[2] = {
19260     { instruction         , 0                   , 0   , 32,
19261        0xfc00023f, 0xa000002b, &MAXA_S           , 0,
19262        CP1_                },        /* MAXA.S */
19263     { instruction         , 0                   , 0   , 32,
19264        0xfc00023f, 0xa000022b, &MAXA_D           , 0,
19265        CP1_                },        /* MAXA.D */
19266 };
19267 
19268 
19269 static const Pool CVT_L_fmt[2] = {
19270     { instruction         , 0                   , 0   , 32,
19271        0xfc007fff, 0xa000013b, &CVT_L_S          , 0,
19272        CP1_                },        /* CVT.L.S */
19273     { instruction         , 0                   , 0   , 32,
19274        0xfc007fff, 0xa000413b, &CVT_L_D          , 0,
19275        CP1_                },        /* CVT.L.D */
19276 };
19277 
19278 
19279 static const Pool RSQRT_fmt[2] = {
19280     { instruction         , 0                   , 0   , 32,
19281        0xfc007fff, 0xa000023b, &RSQRT_S          , 0,
19282        CP1_                },        /* RSQRT.S */
19283     { instruction         , 0                   , 0   , 32,
19284        0xfc007fff, 0xa000423b, &RSQRT_D          , 0,
19285        CP1_                },        /* RSQRT.D */
19286 };
19287 
19288 
19289 static const Pool FLOOR_L_fmt[2] = {
19290     { instruction         , 0                   , 0   , 32,
19291        0xfc007fff, 0xa000033b, &FLOOR_L_S        , 0,
19292        CP1_                },        /* FLOOR.L.S */
19293     { instruction         , 0                   , 0   , 32,
19294        0xfc007fff, 0xa000433b, &FLOOR_L_D        , 0,
19295        CP1_                },        /* FLOOR.L.D */
19296 };
19297 
19298 
19299 static const Pool CVT_W_fmt[2] = {
19300     { instruction         , 0                   , 0   , 32,
19301        0xfc007fff, 0xa000093b, &CVT_W_S          , 0,
19302        CP1_                },        /* CVT.W.S */
19303     { instruction         , 0                   , 0   , 32,
19304        0xfc007fff, 0xa000493b, &CVT_W_D          , 0,
19305        CP1_                },        /* CVT.W.D */
19306 };
19307 
19308 
19309 static const Pool SQRT_fmt[2] = {
19310     { instruction         , 0                   , 0   , 32,
19311        0xfc007fff, 0xa0000a3b, &SQRT_S           , 0,
19312        CP1_                },        /* SQRT.S */
19313     { instruction         , 0                   , 0   , 32,
19314        0xfc007fff, 0xa0004a3b, &SQRT_D           , 0,
19315        CP1_                },        /* SQRT.D */
19316 };
19317 
19318 
19319 static const Pool FLOOR_W_fmt[2] = {
19320     { instruction         , 0                   , 0   , 32,
19321        0xfc007fff, 0xa0000b3b, &FLOOR_W_S        , 0,
19322        CP1_                },        /* FLOOR.W.S */
19323     { instruction         , 0                   , 0   , 32,
19324        0xfc007fff, 0xa0004b3b, &FLOOR_W_D        , 0,
19325        CP1_                },        /* FLOOR.W.D */
19326 };
19327 
19328 
19329 static const Pool RECIP_fmt[2] = {
19330     { instruction         , 0                   , 0   , 32,
19331        0xfc007fff, 0xa000123b, &RECIP_S          , 0,
19332        CP1_                },        /* RECIP.S */
19333     { instruction         , 0                   , 0   , 32,
19334        0xfc007fff, 0xa000523b, &RECIP_D          , 0,
19335        CP1_                },        /* RECIP.D */
19336 };
19337 
19338 
19339 static const Pool CEIL_L_fmt[2] = {
19340     { instruction         , 0                   , 0   , 32,
19341        0xfc007fff, 0xa000133b, &CEIL_L_S         , 0,
19342        CP1_                },        /* CEIL.L.S */
19343     { instruction         , 0                   , 0   , 32,
19344        0xfc007fff, 0xa000533b, &CEIL_L_D         , 0,
19345        CP1_                },        /* CEIL.L.D */
19346 };
19347 
19348 
19349 static const Pool CEIL_W_fmt[2] = {
19350     { instruction         , 0                   , 0   , 32,
19351        0xfc007fff, 0xa0001b3b, &CEIL_W_S         , 0,
19352        CP1_                },        /* CEIL.W.S */
19353     { instruction         , 0                   , 0   , 32,
19354        0xfc007fff, 0xa0005b3b, &CEIL_W_D         , 0,
19355        CP1_                },        /* CEIL.W.D */
19356 };
19357 
19358 
19359 static const Pool TRUNC_L_fmt[2] = {
19360     { instruction         , 0                   , 0   , 32,
19361        0xfc007fff, 0xa000233b, &TRUNC_L_S        , 0,
19362        CP1_                },        /* TRUNC.L.S */
19363     { instruction         , 0                   , 0   , 32,
19364        0xfc007fff, 0xa000633b, &TRUNC_L_D        , 0,
19365        CP1_                },        /* TRUNC.L.D */
19366 };
19367 
19368 
19369 static const Pool TRUNC_W_fmt[2] = {
19370     { instruction         , 0                   , 0   , 32,
19371        0xfc007fff, 0xa0002b3b, &TRUNC_W_S        , 0,
19372        CP1_                },        /* TRUNC.W.S */
19373     { instruction         , 0                   , 0   , 32,
19374        0xfc007fff, 0xa0006b3b, &TRUNC_W_D        , 0,
19375        CP1_                },        /* TRUNC.W.D */
19376 };
19377 
19378 
19379 static const Pool ROUND_L_fmt[2] = {
19380     { instruction         , 0                   , 0   , 32,
19381        0xfc007fff, 0xa000333b, &ROUND_L_S        , 0,
19382        CP1_                },        /* ROUND.L.S */
19383     { instruction         , 0                   , 0   , 32,
19384        0xfc007fff, 0xa000733b, &ROUND_L_D        , 0,
19385        CP1_                },        /* ROUND.L.D */
19386 };
19387 
19388 
19389 static const Pool ROUND_W_fmt[2] = {
19390     { instruction         , 0                   , 0   , 32,
19391        0xfc007fff, 0xa0003b3b, &ROUND_W_S        , 0,
19392        CP1_                },        /* ROUND.W.S */
19393     { instruction         , 0                   , 0   , 32,
19394        0xfc007fff, 0xa0007b3b, &ROUND_W_D        , 0,
19395        CP1_                },        /* ROUND.W.D */
19396 };
19397 
19398 
19399 static const Pool POOL32Fxf_0[64] = {
19400     { reserved_block      , 0                   , 0   , 32,
19401        0xfc003fff, 0xa000003b, 0                      , 0,
19402        CP1_                },        /* POOL32Fxf_0~*(0) */
19403     { pool                , CVT_L_fmt           , 2   , 32,
19404        0xfc003fff, 0xa000013b, 0                      , 0,
19405        CP1_                },        /* CVT.L.fmt */
19406     { pool                , RSQRT_fmt           , 2   , 32,
19407        0xfc003fff, 0xa000023b, 0                      , 0,
19408        CP1_                },        /* RSQRT.fmt */
19409     { pool                , FLOOR_L_fmt         , 2   , 32,
19410        0xfc003fff, 0xa000033b, 0                      , 0,
19411        CP1_                },        /* FLOOR.L.fmt */
19412     { reserved_block      , 0                   , 0   , 32,
19413        0xfc003fff, 0xa000043b, 0                      , 0,
19414        CP1_                },        /* POOL32Fxf_0~*(4) */
19415     { reserved_block      , 0                   , 0   , 32,
19416        0xfc003fff, 0xa000053b, 0                      , 0,
19417        CP1_                },        /* POOL32Fxf_0~*(5) */
19418     { reserved_block      , 0                   , 0   , 32,
19419        0xfc003fff, 0xa000063b, 0                      , 0,
19420        CP1_                },        /* POOL32Fxf_0~*(6) */
19421     { reserved_block      , 0                   , 0   , 32,
19422        0xfc003fff, 0xa000073b, 0                      , 0,
19423        CP1_                },        /* POOL32Fxf_0~*(7) */
19424     { reserved_block      , 0                   , 0   , 32,
19425        0xfc003fff, 0xa000083b, 0                      , 0,
19426        CP1_                },        /* POOL32Fxf_0~*(8) */
19427     { pool                , CVT_W_fmt           , 2   , 32,
19428        0xfc003fff, 0xa000093b, 0                      , 0,
19429        CP1_                },        /* CVT.W.fmt */
19430     { pool                , SQRT_fmt            , 2   , 32,
19431        0xfc003fff, 0xa0000a3b, 0                      , 0,
19432        CP1_                },        /* SQRT.fmt */
19433     { pool                , FLOOR_W_fmt         , 2   , 32,
19434        0xfc003fff, 0xa0000b3b, 0                      , 0,
19435        CP1_                },        /* FLOOR.W.fmt */
19436     { reserved_block      , 0                   , 0   , 32,
19437        0xfc003fff, 0xa0000c3b, 0                      , 0,
19438        CP1_                },        /* POOL32Fxf_0~*(12) */
19439     { reserved_block      , 0                   , 0   , 32,
19440        0xfc003fff, 0xa0000d3b, 0                      , 0,
19441        CP1_                },        /* POOL32Fxf_0~*(13) */
19442     { reserved_block      , 0                   , 0   , 32,
19443        0xfc003fff, 0xa0000e3b, 0                      , 0,
19444        CP1_                },        /* POOL32Fxf_0~*(14) */
19445     { reserved_block      , 0                   , 0   , 32,
19446        0xfc003fff, 0xa0000f3b, 0                      , 0,
19447        CP1_                },        /* POOL32Fxf_0~*(15) */
19448     { instruction         , 0                   , 0   , 32,
19449        0xfc003fff, 0xa000103b, &CFC1             , 0,
19450        CP1_                },        /* CFC1 */
19451     { reserved_block      , 0                   , 0   , 32,
19452        0xfc003fff, 0xa000113b, 0                      , 0,
19453        CP1_                },        /* POOL32Fxf_0~*(17) */
19454     { pool                , RECIP_fmt           , 2   , 32,
19455        0xfc003fff, 0xa000123b, 0                      , 0,
19456        CP1_                },        /* RECIP.fmt */
19457     { pool                , CEIL_L_fmt          , 2   , 32,
19458        0xfc003fff, 0xa000133b, 0                      , 0,
19459        CP1_                },        /* CEIL.L.fmt */
19460     { reserved_block      , 0                   , 0   , 32,
19461        0xfc003fff, 0xa000143b, 0                      , 0,
19462        CP1_                },        /* POOL32Fxf_0~*(20) */
19463     { reserved_block      , 0                   , 0   , 32,
19464        0xfc003fff, 0xa000153b, 0                      , 0,
19465        CP1_                },        /* POOL32Fxf_0~*(21) */
19466     { reserved_block      , 0                   , 0   , 32,
19467        0xfc003fff, 0xa000163b, 0                      , 0,
19468        CP1_                },        /* POOL32Fxf_0~*(22) */
19469     { reserved_block      , 0                   , 0   , 32,
19470        0xfc003fff, 0xa000173b, 0                      , 0,
19471        CP1_                },        /* POOL32Fxf_0~*(23) */
19472     { instruction         , 0                   , 0   , 32,
19473        0xfc003fff, 0xa000183b, &CTC1             , 0,
19474        CP1_                },        /* CTC1 */
19475     { reserved_block      , 0                   , 0   , 32,
19476        0xfc003fff, 0xa000193b, 0                      , 0,
19477        CP1_                },        /* POOL32Fxf_0~*(25) */
19478     { reserved_block      , 0                   , 0   , 32,
19479        0xfc003fff, 0xa0001a3b, 0                      , 0,
19480        CP1_                },        /* POOL32Fxf_0~*(26) */
19481     { pool                , CEIL_W_fmt          , 2   , 32,
19482        0xfc003fff, 0xa0001b3b, 0                      , 0,
19483        CP1_                },        /* CEIL.W.fmt */
19484     { reserved_block      , 0                   , 0   , 32,
19485        0xfc003fff, 0xa0001c3b, 0                      , 0,
19486        CP1_                },        /* POOL32Fxf_0~*(28) */
19487     { reserved_block      , 0                   , 0   , 32,
19488        0xfc003fff, 0xa0001d3b, 0                      , 0,
19489        CP1_                },        /* POOL32Fxf_0~*(29) */
19490     { reserved_block      , 0                   , 0   , 32,
19491        0xfc003fff, 0xa0001e3b, 0                      , 0,
19492        CP1_                },        /* POOL32Fxf_0~*(30) */
19493     { reserved_block      , 0                   , 0   , 32,
19494        0xfc003fff, 0xa0001f3b, 0                      , 0,
19495        CP1_                },        /* POOL32Fxf_0~*(31) */
19496     { instruction         , 0                   , 0   , 32,
19497        0xfc003fff, 0xa000203b, &MFC1             , 0,
19498        CP1_                },        /* MFC1 */
19499     { instruction         , 0                   , 0   , 32,
19500        0xfc003fff, 0xa000213b, &CVT_S_PL         , 0,
19501        CP1_                },        /* CVT.S.PL */
19502     { reserved_block      , 0                   , 0   , 32,
19503        0xfc003fff, 0xa000223b, 0                      , 0,
19504        CP1_                },        /* POOL32Fxf_0~*(34) */
19505     { pool                , TRUNC_L_fmt         , 2   , 32,
19506        0xfc003fff, 0xa000233b, 0                      , 0,
19507        CP1_                },        /* TRUNC.L.fmt */
19508     { instruction         , 0                   , 0   , 32,
19509        0xfc003fff, 0xa000243b, &DMFC1            , 0,
19510        CP1_ | MIPS64_      },        /* DMFC1 */
19511     { reserved_block      , 0                   , 0   , 32,
19512        0xfc003fff, 0xa000253b, 0                      , 0,
19513        CP1_                },        /* POOL32Fxf_0~*(37) */
19514     { reserved_block      , 0                   , 0   , 32,
19515        0xfc003fff, 0xa000263b, 0                      , 0,
19516        CP1_                },        /* POOL32Fxf_0~*(38) */
19517     { reserved_block      , 0                   , 0   , 32,
19518        0xfc003fff, 0xa000273b, 0                      , 0,
19519        CP1_                },        /* POOL32Fxf_0~*(39) */
19520     { instruction         , 0                   , 0   , 32,
19521        0xfc003fff, 0xa000283b, &MTC1             , 0,
19522        CP1_                },        /* MTC1 */
19523     { instruction         , 0                   , 0   , 32,
19524        0xfc003fff, 0xa000293b, &CVT_S_PU         , 0,
19525        CP1_                },        /* CVT.S.PU */
19526     { reserved_block      , 0                   , 0   , 32,
19527        0xfc003fff, 0xa0002a3b, 0                      , 0,
19528        CP1_                },        /* POOL32Fxf_0~*(42) */
19529     { pool                , TRUNC_W_fmt         , 2   , 32,
19530        0xfc003fff, 0xa0002b3b, 0                      , 0,
19531        CP1_                },        /* TRUNC.W.fmt */
19532     { instruction         , 0                   , 0   , 32,
19533        0xfc003fff, 0xa0002c3b, &DMTC1            , 0,
19534        CP1_ | MIPS64_      },        /* DMTC1 */
19535     { reserved_block      , 0                   , 0   , 32,
19536        0xfc003fff, 0xa0002d3b, 0                      , 0,
19537        CP1_                },        /* POOL32Fxf_0~*(45) */
19538     { reserved_block      , 0                   , 0   , 32,
19539        0xfc003fff, 0xa0002e3b, 0                      , 0,
19540        CP1_                },        /* POOL32Fxf_0~*(46) */
19541     { reserved_block      , 0                   , 0   , 32,
19542        0xfc003fff, 0xa0002f3b, 0                      , 0,
19543        CP1_                },        /* POOL32Fxf_0~*(47) */
19544     { instruction         , 0                   , 0   , 32,
19545        0xfc003fff, 0xa000303b, &MFHC1            , 0,
19546        CP1_                },        /* MFHC1 */
19547     { reserved_block      , 0                   , 0   , 32,
19548        0xfc003fff, 0xa000313b, 0                      , 0,
19549        CP1_                },        /* POOL32Fxf_0~*(49) */
19550     { reserved_block      , 0                   , 0   , 32,
19551        0xfc003fff, 0xa000323b, 0                      , 0,
19552        CP1_                },        /* POOL32Fxf_0~*(50) */
19553     { pool                , ROUND_L_fmt         , 2   , 32,
19554        0xfc003fff, 0xa000333b, 0                      , 0,
19555        CP1_                },        /* ROUND.L.fmt */
19556     { reserved_block      , 0                   , 0   , 32,
19557        0xfc003fff, 0xa000343b, 0                      , 0,
19558        CP1_                },        /* POOL32Fxf_0~*(52) */
19559     { reserved_block      , 0                   , 0   , 32,
19560        0xfc003fff, 0xa000353b, 0                      , 0,
19561        CP1_                },        /* POOL32Fxf_0~*(53) */
19562     { reserved_block      , 0                   , 0   , 32,
19563        0xfc003fff, 0xa000363b, 0                      , 0,
19564        CP1_                },        /* POOL32Fxf_0~*(54) */
19565     { reserved_block      , 0                   , 0   , 32,
19566        0xfc003fff, 0xa000373b, 0                      , 0,
19567        CP1_                },        /* POOL32Fxf_0~*(55) */
19568     { instruction         , 0                   , 0   , 32,
19569        0xfc003fff, 0xa000383b, &MTHC1            , 0,
19570        CP1_                },        /* MTHC1 */
19571     { reserved_block      , 0                   , 0   , 32,
19572        0xfc003fff, 0xa000393b, 0                      , 0,
19573        CP1_                },        /* POOL32Fxf_0~*(57) */
19574     { reserved_block      , 0                   , 0   , 32,
19575        0xfc003fff, 0xa0003a3b, 0                      , 0,
19576        CP1_                },        /* POOL32Fxf_0~*(58) */
19577     { pool                , ROUND_W_fmt         , 2   , 32,
19578        0xfc003fff, 0xa0003b3b, 0                      , 0,
19579        CP1_                },        /* ROUND.W.fmt */
19580     { reserved_block      , 0                   , 0   , 32,
19581        0xfc003fff, 0xa0003c3b, 0                      , 0,
19582        CP1_                },        /* POOL32Fxf_0~*(60) */
19583     { reserved_block      , 0                   , 0   , 32,
19584        0xfc003fff, 0xa0003d3b, 0                      , 0,
19585        CP1_                },        /* POOL32Fxf_0~*(61) */
19586     { reserved_block      , 0                   , 0   , 32,
19587        0xfc003fff, 0xa0003e3b, 0                      , 0,
19588        CP1_                },        /* POOL32Fxf_0~*(62) */
19589     { reserved_block      , 0                   , 0   , 32,
19590        0xfc003fff, 0xa0003f3b, 0                      , 0,
19591        CP1_                },        /* POOL32Fxf_0~*(63) */
19592 };
19593 
19594 
19595 static const Pool MOV_fmt[4] = {
19596     { instruction         , 0                   , 0   , 32,
19597        0xfc007fff, 0xa000007b, &MOV_S            , 0,
19598        CP1_                },        /* MOV.S */
19599     { instruction         , 0                   , 0   , 32,
19600        0xfc007fff, 0xa000207b, &MOV_D            , 0,
19601        CP1_                },        /* MOV.D */
19602     { reserved_block      , 0                   , 0   , 32,
19603        0xfc007fff, 0xa000407b, 0                      , 0,
19604        CP1_                },        /* MOV.fmt~*(2) */
19605     { reserved_block      , 0                   , 0   , 32,
19606        0xfc007fff, 0xa000607b, 0                      , 0,
19607        CP1_                },        /* MOV.fmt~*(3) */
19608 };
19609 
19610 
19611 static const Pool ABS_fmt[4] = {
19612     { instruction         , 0                   , 0   , 32,
19613        0xfc007fff, 0xa000037b, &ABS_S            , 0,
19614        CP1_                },        /* ABS.S */
19615     { instruction         , 0                   , 0   , 32,
19616        0xfc007fff, 0xa000237b, &ABS_D            , 0,
19617        CP1_                },        /* ABS.D */
19618     { reserved_block      , 0                   , 0   , 32,
19619        0xfc007fff, 0xa000437b, 0                      , 0,
19620        CP1_                },        /* ABS.fmt~*(2) */
19621     { reserved_block      , 0                   , 0   , 32,
19622        0xfc007fff, 0xa000637b, 0                      , 0,
19623        CP1_                },        /* ABS.fmt~*(3) */
19624 };
19625 
19626 
19627 static const Pool NEG_fmt[4] = {
19628     { instruction         , 0                   , 0   , 32,
19629        0xfc007fff, 0xa0000b7b, &NEG_S            , 0,
19630        CP1_                },        /* NEG.S */
19631     { instruction         , 0                   , 0   , 32,
19632        0xfc007fff, 0xa0002b7b, &NEG_D            , 0,
19633        CP1_                },        /* NEG.D */
19634     { reserved_block      , 0                   , 0   , 32,
19635        0xfc007fff, 0xa0004b7b, 0                      , 0,
19636        CP1_                },        /* NEG.fmt~*(2) */
19637     { reserved_block      , 0                   , 0   , 32,
19638        0xfc007fff, 0xa0006b7b, 0                      , 0,
19639        CP1_                },        /* NEG.fmt~*(3) */
19640 };
19641 
19642 
19643 static const Pool CVT_D_fmt[4] = {
19644     { instruction         , 0                   , 0   , 32,
19645        0xfc007fff, 0xa000137b, &CVT_D_S          , 0,
19646        CP1_                },        /* CVT.D.S */
19647     { instruction         , 0                   , 0   , 32,
19648        0xfc007fff, 0xa000337b, &CVT_D_W          , 0,
19649        CP1_                },        /* CVT.D.W */
19650     { instruction         , 0                   , 0   , 32,
19651        0xfc007fff, 0xa000537b, &CVT_D_L          , 0,
19652        CP1_                },        /* CVT.D.L */
19653     { reserved_block      , 0                   , 0   , 32,
19654        0xfc007fff, 0xa000737b, 0                      , 0,
19655        CP1_                },        /* CVT.D.fmt~*(3) */
19656 };
19657 
19658 
19659 static const Pool CVT_S_fmt[4] = {
19660     { instruction         , 0                   , 0   , 32,
19661        0xfc007fff, 0xa0001b7b, &CVT_S_D          , 0,
19662        CP1_                },        /* CVT.S.D */
19663     { instruction         , 0                   , 0   , 32,
19664        0xfc007fff, 0xa0003b7b, &CVT_S_W          , 0,
19665        CP1_                },        /* CVT.S.W */
19666     { instruction         , 0                   , 0   , 32,
19667        0xfc007fff, 0xa0005b7b, &CVT_S_L          , 0,
19668        CP1_                },        /* CVT.S.L */
19669     { reserved_block      , 0                   , 0   , 32,
19670        0xfc007fff, 0xa0007b7b, 0                      , 0,
19671        CP1_                },        /* CVT.S.fmt~*(3) */
19672 };
19673 
19674 
19675 static const Pool POOL32Fxf_1[32] = {
19676     { pool                , MOV_fmt             , 4   , 32,
19677        0xfc001fff, 0xa000007b, 0                      , 0,
19678        CP1_                },        /* MOV.fmt */
19679     { reserved_block      , 0                   , 0   , 32,
19680        0xfc001fff, 0xa000017b, 0                      , 0,
19681        CP1_                },        /* POOL32Fxf_1~*(1) */
19682     { reserved_block      , 0                   , 0   , 32,
19683        0xfc001fff, 0xa000027b, 0                      , 0,
19684        CP1_                },        /* POOL32Fxf_1~*(2) */
19685     { pool                , ABS_fmt             , 4   , 32,
19686        0xfc001fff, 0xa000037b, 0                      , 0,
19687        CP1_                },        /* ABS.fmt */
19688     { reserved_block      , 0                   , 0   , 32,
19689        0xfc001fff, 0xa000047b, 0                      , 0,
19690        CP1_                },        /* POOL32Fxf_1~*(4) */
19691     { reserved_block      , 0                   , 0   , 32,
19692        0xfc001fff, 0xa000057b, 0                      , 0,
19693        CP1_                },        /* POOL32Fxf_1~*(5) */
19694     { reserved_block      , 0                   , 0   , 32,
19695        0xfc001fff, 0xa000067b, 0                      , 0,
19696        CP1_                },        /* POOL32Fxf_1~*(6) */
19697     { reserved_block      , 0                   , 0   , 32,
19698        0xfc001fff, 0xa000077b, 0                      , 0,
19699        CP1_                },        /* POOL32Fxf_1~*(7) */
19700     { reserved_block      , 0                   , 0   , 32,
19701        0xfc001fff, 0xa000087b, 0                      , 0,
19702        CP1_                },        /* POOL32Fxf_1~*(8) */
19703     { reserved_block      , 0                   , 0   , 32,
19704        0xfc001fff, 0xa000097b, 0                      , 0,
19705        CP1_                },        /* POOL32Fxf_1~*(9) */
19706     { reserved_block      , 0                   , 0   , 32,
19707        0xfc001fff, 0xa0000a7b, 0                      , 0,
19708        CP1_                },        /* POOL32Fxf_1~*(10) */
19709     { pool                , NEG_fmt             , 4   , 32,
19710        0xfc001fff, 0xa0000b7b, 0                      , 0,
19711        CP1_                },        /* NEG.fmt */
19712     { reserved_block      , 0                   , 0   , 32,
19713        0xfc001fff, 0xa0000c7b, 0                      , 0,
19714        CP1_                },        /* POOL32Fxf_1~*(12) */
19715     { reserved_block      , 0                   , 0   , 32,
19716        0xfc001fff, 0xa0000d7b, 0                      , 0,
19717        CP1_                },        /* POOL32Fxf_1~*(13) */
19718     { reserved_block      , 0                   , 0   , 32,
19719        0xfc001fff, 0xa0000e7b, 0                      , 0,
19720        CP1_                },        /* POOL32Fxf_1~*(14) */
19721     { reserved_block      , 0                   , 0   , 32,
19722        0xfc001fff, 0xa0000f7b, 0                      , 0,
19723        CP1_                },        /* POOL32Fxf_1~*(15) */
19724     { reserved_block      , 0                   , 0   , 32,
19725        0xfc001fff, 0xa000107b, 0                      , 0,
19726        CP1_                },        /* POOL32Fxf_1~*(16) */
19727     { reserved_block      , 0                   , 0   , 32,
19728        0xfc001fff, 0xa000117b, 0                      , 0,
19729        CP1_                },        /* POOL32Fxf_1~*(17) */
19730     { reserved_block      , 0                   , 0   , 32,
19731        0xfc001fff, 0xa000127b, 0                      , 0,
19732        CP1_                },        /* POOL32Fxf_1~*(18) */
19733     { pool                , CVT_D_fmt           , 4   , 32,
19734        0xfc001fff, 0xa000137b, 0                      , 0,
19735        CP1_                },        /* CVT.D.fmt */
19736     { reserved_block      , 0                   , 0   , 32,
19737        0xfc001fff, 0xa000147b, 0                      , 0,
19738        CP1_                },        /* POOL32Fxf_1~*(20) */
19739     { reserved_block      , 0                   , 0   , 32,
19740        0xfc001fff, 0xa000157b, 0                      , 0,
19741        CP1_                },        /* POOL32Fxf_1~*(21) */
19742     { reserved_block      , 0                   , 0   , 32,
19743        0xfc001fff, 0xa000167b, 0                      , 0,
19744        CP1_                },        /* POOL32Fxf_1~*(22) */
19745     { reserved_block      , 0                   , 0   , 32,
19746        0xfc001fff, 0xa000177b, 0                      , 0,
19747        CP1_                },        /* POOL32Fxf_1~*(23) */
19748     { reserved_block      , 0                   , 0   , 32,
19749        0xfc001fff, 0xa000187b, 0                      , 0,
19750        CP1_                },        /* POOL32Fxf_1~*(24) */
19751     { reserved_block      , 0                   , 0   , 32,
19752        0xfc001fff, 0xa000197b, 0                      , 0,
19753        CP1_                },        /* POOL32Fxf_1~*(25) */
19754     { reserved_block      , 0                   , 0   , 32,
19755        0xfc001fff, 0xa0001a7b, 0                      , 0,
19756        CP1_                },        /* POOL32Fxf_1~*(26) */
19757     { pool                , CVT_S_fmt           , 4   , 32,
19758        0xfc001fff, 0xa0001b7b, 0                      , 0,
19759        CP1_                },        /* CVT.S.fmt */
19760     { reserved_block      , 0                   , 0   , 32,
19761        0xfc001fff, 0xa0001c7b, 0                      , 0,
19762        CP1_                },        /* POOL32Fxf_1~*(28) */
19763     { reserved_block      , 0                   , 0   , 32,
19764        0xfc001fff, 0xa0001d7b, 0                      , 0,
19765        CP1_                },        /* POOL32Fxf_1~*(29) */
19766     { reserved_block      , 0                   , 0   , 32,
19767        0xfc001fff, 0xa0001e7b, 0                      , 0,
19768        CP1_                },        /* POOL32Fxf_1~*(30) */
19769     { reserved_block      , 0                   , 0   , 32,
19770        0xfc001fff, 0xa0001f7b, 0                      , 0,
19771        CP1_                },        /* POOL32Fxf_1~*(31) */
19772 };
19773 
19774 
19775 static const Pool POOL32Fxf[4] = {
19776     { pool                , POOL32Fxf_0         , 64  , 32,
19777        0xfc0000ff, 0xa000003b, 0                      , 0,
19778        CP1_                },        /* POOL32Fxf_0 */
19779     { pool                , POOL32Fxf_1         , 32  , 32,
19780        0xfc0000ff, 0xa000007b, 0                      , 0,
19781        CP1_                },        /* POOL32Fxf_1 */
19782     { reserved_block      , 0                   , 0   , 32,
19783        0xfc0000ff, 0xa00000bb, 0                      , 0,
19784        CP1_                },        /* POOL32Fxf~*(2) */
19785     { reserved_block      , 0                   , 0   , 32,
19786        0xfc0000ff, 0xa00000fb, 0                      , 0,
19787        CP1_                },        /* POOL32Fxf~*(3) */
19788 };
19789 
19790 
19791 static const Pool POOL32F_3[8] = {
19792     { pool                , MIN_fmt             , 2   , 32,
19793        0xfc00003f, 0xa0000003, 0                      , 0,
19794        CP1_                },        /* MIN.fmt */
19795     { pool                , MAX_fmt             , 2   , 32,
19796        0xfc00003f, 0xa000000b, 0                      , 0,
19797        CP1_                },        /* MAX.fmt */
19798     { reserved_block      , 0                   , 0   , 32,
19799        0xfc00003f, 0xa0000013, 0                      , 0,
19800        CP1_                },        /* POOL32F_3~*(2) */
19801     { reserved_block      , 0                   , 0   , 32,
19802        0xfc00003f, 0xa000001b, 0                      , 0,
19803        CP1_                },        /* POOL32F_3~*(3) */
19804     { pool                , MINA_fmt            , 2   , 32,
19805        0xfc00003f, 0xa0000023, 0                      , 0,
19806        CP1_                },        /* MINA.fmt */
19807     { pool                , MAXA_fmt            , 2   , 32,
19808        0xfc00003f, 0xa000002b, 0                      , 0,
19809        CP1_                },        /* MAXA.fmt */
19810     { reserved_block      , 0                   , 0   , 32,
19811        0xfc00003f, 0xa0000033, 0                      , 0,
19812        CP1_                },        /* POOL32F_3~*(6) */
19813     { pool                , POOL32Fxf           , 4   , 32,
19814        0xfc00003f, 0xa000003b, 0                      , 0,
19815        CP1_                },        /* POOL32Fxf */
19816 };
19817 
19818 
19819 static const Pool CMP_condn_S[32] = {
19820     { instruction         , 0                   , 0   , 32,
19821        0xfc0007ff, 0xa0000005, &CMP_AF_S         , 0,
19822        CP1_                },        /* CMP.AF.S */
19823     { instruction         , 0                   , 0   , 32,
19824        0xfc0007ff, 0xa0000045, &CMP_UN_S         , 0,
19825        CP1_                },        /* CMP.UN.S */
19826     { instruction         , 0                   , 0   , 32,
19827        0xfc0007ff, 0xa0000085, &CMP_EQ_S         , 0,
19828        CP1_                },        /* CMP.EQ.S */
19829     { instruction         , 0                   , 0   , 32,
19830        0xfc0007ff, 0xa00000c5, &CMP_UEQ_S        , 0,
19831        CP1_                },        /* CMP.UEQ.S */
19832     { instruction         , 0                   , 0   , 32,
19833        0xfc0007ff, 0xa0000105, &CMP_LT_S         , 0,
19834        CP1_                },        /* CMP.LT.S */
19835     { instruction         , 0                   , 0   , 32,
19836        0xfc0007ff, 0xa0000145, &CMP_ULT_S        , 0,
19837        CP1_                },        /* CMP.ULT.S */
19838     { instruction         , 0                   , 0   , 32,
19839        0xfc0007ff, 0xa0000185, &CMP_LE_S         , 0,
19840        CP1_                },        /* CMP.LE.S */
19841     { instruction         , 0                   , 0   , 32,
19842        0xfc0007ff, 0xa00001c5, &CMP_ULE_S        , 0,
19843        CP1_                },        /* CMP.ULE.S */
19844     { instruction         , 0                   , 0   , 32,
19845        0xfc0007ff, 0xa0000205, &CMP_SAF_S        , 0,
19846        CP1_                },        /* CMP.SAF.S */
19847     { instruction         , 0                   , 0   , 32,
19848        0xfc0007ff, 0xa0000245, &CMP_SUN_S        , 0,
19849        CP1_                },        /* CMP.SUN.S */
19850     { instruction         , 0                   , 0   , 32,
19851        0xfc0007ff, 0xa0000285, &CMP_SEQ_S        , 0,
19852        CP1_                },        /* CMP.SEQ.S */
19853     { instruction         , 0                   , 0   , 32,
19854        0xfc0007ff, 0xa00002c5, &CMP_SUEQ_S       , 0,
19855        CP1_                },        /* CMP.SUEQ.S */
19856     { instruction         , 0                   , 0   , 32,
19857        0xfc0007ff, 0xa0000305, &CMP_SLT_S        , 0,
19858        CP1_                },        /* CMP.SLT.S */
19859     { instruction         , 0                   , 0   , 32,
19860        0xfc0007ff, 0xa0000345, &CMP_SULT_S       , 0,
19861        CP1_                },        /* CMP.SULT.S */
19862     { instruction         , 0                   , 0   , 32,
19863        0xfc0007ff, 0xa0000385, &CMP_SLE_S        , 0,
19864        CP1_                },        /* CMP.SLE.S */
19865     { instruction         , 0                   , 0   , 32,
19866        0xfc0007ff, 0xa00003c5, &CMP_SULE_S       , 0,
19867        CP1_                },        /* CMP.SULE.S */
19868     { reserved_block      , 0                   , 0   , 32,
19869        0xfc0007ff, 0xa0000405, 0                      , 0,
19870        CP1_                },        /* CMP.condn.S~*(16) */
19871     { instruction         , 0                   , 0   , 32,
19872        0xfc0007ff, 0xa0000445, &CMP_OR_S         , 0,
19873        CP1_                },        /* CMP.OR.S */
19874     { instruction         , 0                   , 0   , 32,
19875        0xfc0007ff, 0xa0000485, &CMP_UNE_S        , 0,
19876        CP1_                },        /* CMP.UNE.S */
19877     { instruction         , 0                   , 0   , 32,
19878        0xfc0007ff, 0xa00004c5, &CMP_NE_S         , 0,
19879        CP1_                },        /* CMP.NE.S */
19880     { reserved_block      , 0                   , 0   , 32,
19881        0xfc0007ff, 0xa0000505, 0                      , 0,
19882        CP1_                },        /* CMP.condn.S~*(20) */
19883     { reserved_block      , 0                   , 0   , 32,
19884        0xfc0007ff, 0xa0000545, 0                      , 0,
19885        CP1_                },        /* CMP.condn.S~*(21) */
19886     { reserved_block      , 0                   , 0   , 32,
19887        0xfc0007ff, 0xa0000585, 0                      , 0,
19888        CP1_                },        /* CMP.condn.S~*(22) */
19889     { reserved_block      , 0                   , 0   , 32,
19890        0xfc0007ff, 0xa00005c5, 0                      , 0,
19891        CP1_                },        /* CMP.condn.S~*(23) */
19892     { reserved_block      , 0                   , 0   , 32,
19893        0xfc0007ff, 0xa0000605, 0                      , 0,
19894        CP1_                },        /* CMP.condn.S~*(24) */
19895     { instruction         , 0                   , 0   , 32,
19896        0xfc0007ff, 0xa0000645, &CMP_SOR_S        , 0,
19897        CP1_                },        /* CMP.SOR.S */
19898     { instruction         , 0                   , 0   , 32,
19899        0xfc0007ff, 0xa0000685, &CMP_SUNE_S       , 0,
19900        CP1_                },        /* CMP.SUNE.S */
19901     { instruction         , 0                   , 0   , 32,
19902        0xfc0007ff, 0xa00006c5, &CMP_SNE_S        , 0,
19903        CP1_                },        /* CMP.SNE.S */
19904     { reserved_block      , 0                   , 0   , 32,
19905        0xfc0007ff, 0xa0000705, 0                      , 0,
19906        CP1_                },        /* CMP.condn.S~*(28) */
19907     { reserved_block      , 0                   , 0   , 32,
19908        0xfc0007ff, 0xa0000745, 0                      , 0,
19909        CP1_                },        /* CMP.condn.S~*(29) */
19910     { reserved_block      , 0                   , 0   , 32,
19911        0xfc0007ff, 0xa0000785, 0                      , 0,
19912        CP1_                },        /* CMP.condn.S~*(30) */
19913     { reserved_block      , 0                   , 0   , 32,
19914        0xfc0007ff, 0xa00007c5, 0                      , 0,
19915        CP1_                },        /* CMP.condn.S~*(31) */
19916 };
19917 
19918 
19919 static const Pool CMP_condn_D[32] = {
19920     { instruction         , 0                   , 0   , 32,
19921        0xfc0007ff, 0xa0000015, &CMP_AF_D         , 0,
19922        CP1_                },        /* CMP.AF.D */
19923     { instruction         , 0                   , 0   , 32,
19924        0xfc0007ff, 0xa0000055, &CMP_UN_D         , 0,
19925        CP1_                },        /* CMP.UN.D */
19926     { instruction         , 0                   , 0   , 32,
19927        0xfc0007ff, 0xa0000095, &CMP_EQ_D         , 0,
19928        CP1_                },        /* CMP.EQ.D */
19929     { instruction         , 0                   , 0   , 32,
19930        0xfc0007ff, 0xa00000d5, &CMP_UEQ_D        , 0,
19931        CP1_                },        /* CMP.UEQ.D */
19932     { instruction         , 0                   , 0   , 32,
19933        0xfc0007ff, 0xa0000115, &CMP_LT_D         , 0,
19934        CP1_                },        /* CMP.LT.D */
19935     { instruction         , 0                   , 0   , 32,
19936        0xfc0007ff, 0xa0000155, &CMP_ULT_D        , 0,
19937        CP1_                },        /* CMP.ULT.D */
19938     { instruction         , 0                   , 0   , 32,
19939        0xfc0007ff, 0xa0000195, &CMP_LE_D         , 0,
19940        CP1_                },        /* CMP.LE.D */
19941     { instruction         , 0                   , 0   , 32,
19942        0xfc0007ff, 0xa00001d5, &CMP_ULE_D        , 0,
19943        CP1_                },        /* CMP.ULE.D */
19944     { instruction         , 0                   , 0   , 32,
19945        0xfc0007ff, 0xa0000215, &CMP_SAF_D        , 0,
19946        CP1_                },        /* CMP.SAF.D */
19947     { instruction         , 0                   , 0   , 32,
19948        0xfc0007ff, 0xa0000255, &CMP_SUN_D        , 0,
19949        CP1_                },        /* CMP.SUN.D */
19950     { instruction         , 0                   , 0   , 32,
19951        0xfc0007ff, 0xa0000295, &CMP_SEQ_D        , 0,
19952        CP1_                },        /* CMP.SEQ.D */
19953     { instruction         , 0                   , 0   , 32,
19954        0xfc0007ff, 0xa00002d5, &CMP_SUEQ_D       , 0,
19955        CP1_                },        /* CMP.SUEQ.D */
19956     { instruction         , 0                   , 0   , 32,
19957        0xfc0007ff, 0xa0000315, &CMP_SLT_D        , 0,
19958        CP1_                },        /* CMP.SLT.D */
19959     { instruction         , 0                   , 0   , 32,
19960        0xfc0007ff, 0xa0000355, &CMP_SULT_D       , 0,
19961        CP1_                },        /* CMP.SULT.D */
19962     { instruction         , 0                   , 0   , 32,
19963        0xfc0007ff, 0xa0000395, &CMP_SLE_D        , 0,
19964        CP1_                },        /* CMP.SLE.D */
19965     { instruction         , 0                   , 0   , 32,
19966        0xfc0007ff, 0xa00003d5, &CMP_SULE_D       , 0,
19967        CP1_                },        /* CMP.SULE.D */
19968     { reserved_block      , 0                   , 0   , 32,
19969        0xfc0007ff, 0xa0000415, 0                      , 0,
19970        CP1_                },        /* CMP.condn.D~*(16) */
19971     { instruction         , 0                   , 0   , 32,
19972        0xfc0007ff, 0xa0000455, &CMP_OR_D         , 0,
19973        CP1_                },        /* CMP.OR.D */
19974     { instruction         , 0                   , 0   , 32,
19975        0xfc0007ff, 0xa0000495, &CMP_UNE_D        , 0,
19976        CP1_                },        /* CMP.UNE.D */
19977     { instruction         , 0                   , 0   , 32,
19978        0xfc0007ff, 0xa00004d5, &CMP_NE_D         , 0,
19979        CP1_                },        /* CMP.NE.D */
19980     { reserved_block      , 0                   , 0   , 32,
19981        0xfc0007ff, 0xa0000515, 0                      , 0,
19982        CP1_                },        /* CMP.condn.D~*(20) */
19983     { reserved_block      , 0                   , 0   , 32,
19984        0xfc0007ff, 0xa0000555, 0                      , 0,
19985        CP1_                },        /* CMP.condn.D~*(21) */
19986     { reserved_block      , 0                   , 0   , 32,
19987        0xfc0007ff, 0xa0000595, 0                      , 0,
19988        CP1_                },        /* CMP.condn.D~*(22) */
19989     { reserved_block      , 0                   , 0   , 32,
19990        0xfc0007ff, 0xa00005d5, 0                      , 0,
19991        CP1_                },        /* CMP.condn.D~*(23) */
19992     { reserved_block      , 0                   , 0   , 32,
19993        0xfc0007ff, 0xa0000615, 0                      , 0,
19994        CP1_                },        /* CMP.condn.D~*(24) */
19995     { instruction         , 0                   , 0   , 32,
19996        0xfc0007ff, 0xa0000655, &CMP_SOR_D        , 0,
19997        CP1_                },        /* CMP.SOR.D */
19998     { instruction         , 0                   , 0   , 32,
19999        0xfc0007ff, 0xa0000695, &CMP_SUNE_D       , 0,
20000        CP1_                },        /* CMP.SUNE.D */
20001     { instruction         , 0                   , 0   , 32,
20002        0xfc0007ff, 0xa00006d5, &CMP_SNE_D        , 0,
20003        CP1_                },        /* CMP.SNE.D */
20004     { reserved_block      , 0                   , 0   , 32,
20005        0xfc0007ff, 0xa0000715, 0                      , 0,
20006        CP1_                },        /* CMP.condn.D~*(28) */
20007     { reserved_block      , 0                   , 0   , 32,
20008        0xfc0007ff, 0xa0000755, 0                      , 0,
20009        CP1_                },        /* CMP.condn.D~*(29) */
20010     { reserved_block      , 0                   , 0   , 32,
20011        0xfc0007ff, 0xa0000795, 0                      , 0,
20012        CP1_                },        /* CMP.condn.D~*(30) */
20013     { reserved_block      , 0                   , 0   , 32,
20014        0xfc0007ff, 0xa00007d5, 0                      , 0,
20015        CP1_                },        /* CMP.condn.D~*(31) */
20016 };
20017 
20018 
20019 static const Pool POOL32F_5[8] = {
20020     { pool                , CMP_condn_S         , 32  , 32,
20021        0xfc00003f, 0xa0000005, 0                      , 0,
20022        CP1_                },        /* CMP.condn.S */
20023     { reserved_block      , 0                   , 0   , 32,
20024        0xfc00003f, 0xa000000d, 0                      , 0,
20025        CP1_                },        /* POOL32F_5~*(1) */
20026     { pool                , CMP_condn_D         , 32  , 32,
20027        0xfc00003f, 0xa0000015, 0                      , 0,
20028        CP1_                },        /* CMP.condn.D */
20029     { reserved_block      , 0                   , 0   , 32,
20030        0xfc00003f, 0xa000001d, 0                      , 0,
20031        CP1_                },        /* POOL32F_5~*(3) */
20032     { reserved_block      , 0                   , 0   , 32,
20033        0xfc00003f, 0xa0000025, 0                      , 0,
20034        CP1_                },        /* POOL32F_5~*(4) */
20035     { reserved_block      , 0                   , 0   , 32,
20036        0xfc00003f, 0xa000002d, 0                      , 0,
20037        CP1_                },        /* POOL32F_5~*(5) */
20038     { reserved_block      , 0                   , 0   , 32,
20039        0xfc00003f, 0xa0000035, 0                      , 0,
20040        CP1_                },        /* POOL32F_5~*(6) */
20041     { reserved_block      , 0                   , 0   , 32,
20042        0xfc00003f, 0xa000003d, 0                      , 0,
20043        CP1_                },        /* POOL32F_5~*(7) */
20044 };
20045 
20046 
20047 static const Pool POOL32F[8] = {
20048     { pool                , POOL32F_0           , 64  , 32,
20049        0xfc000007, 0xa0000000, 0                      , 0,
20050        CP1_                },        /* POOL32F_0 */
20051     { reserved_block      , 0                   , 0   , 32,
20052        0xfc000007, 0xa0000001, 0                      , 0,
20053        CP1_                },        /* POOL32F~*(1) */
20054     { reserved_block      , 0                   , 0   , 32,
20055        0xfc000007, 0xa0000002, 0                      , 0,
20056        CP1_                },        /* POOL32F~*(2) */
20057     { pool                , POOL32F_3           , 8   , 32,
20058        0xfc000007, 0xa0000003, 0                      , 0,
20059        CP1_                },        /* POOL32F_3 */
20060     { reserved_block      , 0                   , 0   , 32,
20061        0xfc000007, 0xa0000004, 0                      , 0,
20062        CP1_                },        /* POOL32F~*(4) */
20063     { pool                , POOL32F_5           , 8   , 32,
20064        0xfc000007, 0xa0000005, 0                      , 0,
20065        CP1_                },        /* POOL32F_5 */
20066     { reserved_block      , 0                   , 0   , 32,
20067        0xfc000007, 0xa0000006, 0                      , 0,
20068        CP1_                },        /* POOL32F~*(6) */
20069     { reserved_block      , 0                   , 0   , 32,
20070        0xfc000007, 0xa0000007, 0                      , 0,
20071        CP1_                },        /* POOL32F~*(7) */
20072 };
20073 
20074 
20075 static const Pool POOL32S_0[64] = {
20076     { reserved_block      , 0                   , 0   , 32,
20077        0xfc0001ff, 0xc0000000, 0                      , 0,
20078        0x0                 },        /* POOL32S_0~*(0) */
20079     { instruction         , 0                   , 0   , 32,
20080        0xfc0001ff, 0xc0000008, &DLSA             , 0,
20081        MIPS64_             },        /* DLSA */
20082     { instruction         , 0                   , 0   , 32,
20083        0xfc0001ff, 0xc0000010, &DSLLV            , 0,
20084        MIPS64_             },        /* DSLLV */
20085     { instruction         , 0                   , 0   , 32,
20086        0xfc0001ff, 0xc0000018, &DMUL             , 0,
20087        MIPS64_             },        /* DMUL */
20088     { reserved_block      , 0                   , 0   , 32,
20089        0xfc0001ff, 0xc0000020, 0                      , 0,
20090        0x0                 },        /* POOL32S_0~*(4) */
20091     { reserved_block      , 0                   , 0   , 32,
20092        0xfc0001ff, 0xc0000028, 0                      , 0,
20093        0x0                 },        /* POOL32S_0~*(5) */
20094     { reserved_block      , 0                   , 0   , 32,
20095        0xfc0001ff, 0xc0000030, 0                      , 0,
20096        0x0                 },        /* POOL32S_0~*(6) */
20097     { reserved_block      , 0                   , 0   , 32,
20098        0xfc0001ff, 0xc0000038, 0                      , 0,
20099        0x0                 },        /* POOL32S_0~*(7) */
20100     { reserved_block      , 0                   , 0   , 32,
20101        0xfc0001ff, 0xc0000040, 0                      , 0,
20102        0x0                 },        /* POOL32S_0~*(8) */
20103     { reserved_block      , 0                   , 0   , 32,
20104        0xfc0001ff, 0xc0000048, 0                      , 0,
20105        0x0                 },        /* POOL32S_0~*(9) */
20106     { instruction         , 0                   , 0   , 32,
20107        0xfc0001ff, 0xc0000050, &DSRLV            , 0,
20108        MIPS64_             },        /* DSRLV */
20109     { instruction         , 0                   , 0   , 32,
20110        0xfc0001ff, 0xc0000058, &DMUH             , 0,
20111        MIPS64_             },        /* DMUH */
20112     { reserved_block      , 0                   , 0   , 32,
20113        0xfc0001ff, 0xc0000060, 0                      , 0,
20114        0x0                 },        /* POOL32S_0~*(12) */
20115     { reserved_block      , 0                   , 0   , 32,
20116        0xfc0001ff, 0xc0000068, 0                      , 0,
20117        0x0                 },        /* POOL32S_0~*(13) */
20118     { reserved_block      , 0                   , 0   , 32,
20119        0xfc0001ff, 0xc0000070, 0                      , 0,
20120        0x0                 },        /* POOL32S_0~*(14) */
20121     { reserved_block      , 0                   , 0   , 32,
20122        0xfc0001ff, 0xc0000078, 0                      , 0,
20123        0x0                 },        /* POOL32S_0~*(15) */
20124     { reserved_block      , 0                   , 0   , 32,
20125        0xfc0001ff, 0xc0000080, 0                      , 0,
20126        0x0                 },        /* POOL32S_0~*(16) */
20127     { reserved_block      , 0                   , 0   , 32,
20128        0xfc0001ff, 0xc0000088, 0                      , 0,
20129        0x0                 },        /* POOL32S_0~*(17) */
20130     { instruction         , 0                   , 0   , 32,
20131        0xfc0001ff, 0xc0000090, &DSRAV            , 0,
20132        MIPS64_             },        /* DSRAV */
20133     { instruction         , 0                   , 0   , 32,
20134        0xfc0001ff, 0xc0000098, &DMULU            , 0,
20135        MIPS64_             },        /* DMULU */
20136     { reserved_block      , 0                   , 0   , 32,
20137        0xfc0001ff, 0xc00000a0, 0                      , 0,
20138        0x0                 },        /* POOL32S_0~*(20) */
20139     { reserved_block      , 0                   , 0   , 32,
20140        0xfc0001ff, 0xc00000a8, 0                      , 0,
20141        0x0                 },        /* POOL32S_0~*(21) */
20142     { reserved_block      , 0                   , 0   , 32,
20143        0xfc0001ff, 0xc00000b0, 0                      , 0,
20144        0x0                 },        /* POOL32S_0~*(22) */
20145     { reserved_block      , 0                   , 0   , 32,
20146        0xfc0001ff, 0xc00000b8, 0                      , 0,
20147        0x0                 },        /* POOL32S_0~*(23) */
20148     { reserved_block      , 0                   , 0   , 32,
20149        0xfc0001ff, 0xc00000c0, 0                      , 0,
20150        0x0                 },        /* POOL32S_0~*(24) */
20151     { reserved_block      , 0                   , 0   , 32,
20152        0xfc0001ff, 0xc00000c8, 0                      , 0,
20153        0x0                 },        /* POOL32S_0~*(25) */
20154     { instruction         , 0                   , 0   , 32,
20155        0xfc0001ff, 0xc00000d0, &DROTRV           , 0,
20156        MIPS64_             },        /* DROTRV */
20157     { instruction         , 0                   , 0   , 32,
20158        0xfc0001ff, 0xc00000d8, &DMUHU            , 0,
20159        MIPS64_             },        /* DMUHU */
20160     { reserved_block      , 0                   , 0   , 32,
20161        0xfc0001ff, 0xc00000e0, 0                      , 0,
20162        0x0                 },        /* POOL32S_0~*(28) */
20163     { reserved_block      , 0                   , 0   , 32,
20164        0xfc0001ff, 0xc00000e8, 0                      , 0,
20165        0x0                 },        /* POOL32S_0~*(29) */
20166     { reserved_block      , 0                   , 0   , 32,
20167        0xfc0001ff, 0xc00000f0, 0                      , 0,
20168        0x0                 },        /* POOL32S_0~*(30) */
20169     { reserved_block      , 0                   , 0   , 32,
20170        0xfc0001ff, 0xc00000f8, 0                      , 0,
20171        0x0                 },        /* POOL32S_0~*(31) */
20172     { reserved_block      , 0                   , 0   , 32,
20173        0xfc0001ff, 0xc0000100, 0                      , 0,
20174        0x0                 },        /* POOL32S_0~*(32) */
20175     { reserved_block      , 0                   , 0   , 32,
20176        0xfc0001ff, 0xc0000108, 0                      , 0,
20177        0x0                 },        /* POOL32S_0~*(33) */
20178     { instruction         , 0                   , 0   , 32,
20179        0xfc0001ff, 0xc0000110, &DADD             , 0,
20180        MIPS64_             },        /* DADD */
20181     { instruction         , 0                   , 0   , 32,
20182        0xfc0001ff, 0xc0000118, &DDIV             , 0,
20183        MIPS64_             },        /* DDIV */
20184     { reserved_block      , 0                   , 0   , 32,
20185        0xfc0001ff, 0xc0000120, 0                      , 0,
20186        0x0                 },        /* POOL32S_0~*(36) */
20187     { reserved_block      , 0                   , 0   , 32,
20188        0xfc0001ff, 0xc0000128, 0                      , 0,
20189        0x0                 },        /* POOL32S_0~*(37) */
20190     { reserved_block      , 0                   , 0   , 32,
20191        0xfc0001ff, 0xc0000130, 0                      , 0,
20192        0x0                 },        /* POOL32S_0~*(38) */
20193     { reserved_block      , 0                   , 0   , 32,
20194        0xfc0001ff, 0xc0000138, 0                      , 0,
20195        0x0                 },        /* POOL32S_0~*(39) */
20196     { reserved_block      , 0                   , 0   , 32,
20197        0xfc0001ff, 0xc0000140, 0                      , 0,
20198        0x0                 },        /* POOL32S_0~*(40) */
20199     { reserved_block      , 0                   , 0   , 32,
20200        0xfc0001ff, 0xc0000148, 0                      , 0,
20201        0x0                 },        /* POOL32S_0~*(41) */
20202     { instruction         , 0                   , 0   , 32,
20203        0xfc0001ff, 0xc0000150, &DADDU            , 0,
20204        MIPS64_             },        /* DADDU */
20205     { instruction         , 0                   , 0   , 32,
20206        0xfc0001ff, 0xc0000158, &DMOD             , 0,
20207        MIPS64_             },        /* DMOD */
20208     { reserved_block      , 0                   , 0   , 32,
20209        0xfc0001ff, 0xc0000160, 0                      , 0,
20210        0x0                 },        /* POOL32S_0~*(44) */
20211     { reserved_block      , 0                   , 0   , 32,
20212        0xfc0001ff, 0xc0000168, 0                      , 0,
20213        0x0                 },        /* POOL32S_0~*(45) */
20214     { reserved_block      , 0                   , 0   , 32,
20215        0xfc0001ff, 0xc0000170, 0                      , 0,
20216        0x0                 },        /* POOL32S_0~*(46) */
20217     { reserved_block      , 0                   , 0   , 32,
20218        0xfc0001ff, 0xc0000178, 0                      , 0,
20219        0x0                 },        /* POOL32S_0~*(47) */
20220     { reserved_block      , 0                   , 0   , 32,
20221        0xfc0001ff, 0xc0000180, 0                      , 0,
20222        0x0                 },        /* POOL32S_0~*(48) */
20223     { reserved_block      , 0                   , 0   , 32,
20224        0xfc0001ff, 0xc0000188, 0                      , 0,
20225        0x0                 },        /* POOL32S_0~*(49) */
20226     { instruction         , 0                   , 0   , 32,
20227        0xfc0001ff, 0xc0000190, &DSUB             , 0,
20228        MIPS64_             },        /* DSUB */
20229     { instruction         , 0                   , 0   , 32,
20230        0xfc0001ff, 0xc0000198, &DDIVU            , 0,
20231        MIPS64_             },        /* DDIVU */
20232     { reserved_block      , 0                   , 0   , 32,
20233        0xfc0001ff, 0xc00001a0, 0                      , 0,
20234        0x0                 },        /* POOL32S_0~*(52) */
20235     { reserved_block      , 0                   , 0   , 32,
20236        0xfc0001ff, 0xc00001a8, 0                      , 0,
20237        0x0                 },        /* POOL32S_0~*(53) */
20238     { reserved_block      , 0                   , 0   , 32,
20239        0xfc0001ff, 0xc00001b0, 0                      , 0,
20240        0x0                 },        /* POOL32S_0~*(54) */
20241     { reserved_block      , 0                   , 0   , 32,
20242        0xfc0001ff, 0xc00001b8, 0                      , 0,
20243        0x0                 },        /* POOL32S_0~*(55) */
20244     { reserved_block      , 0                   , 0   , 32,
20245        0xfc0001ff, 0xc00001c0, 0                      , 0,
20246        0x0                 },        /* POOL32S_0~*(56) */
20247     { reserved_block      , 0                   , 0   , 32,
20248        0xfc0001ff, 0xc00001c8, 0                      , 0,
20249        0x0                 },        /* POOL32S_0~*(57) */
20250     { instruction         , 0                   , 0   , 32,
20251        0xfc0001ff, 0xc00001d0, &DSUBU            , 0,
20252        MIPS64_             },        /* DSUBU */
20253     { instruction         , 0                   , 0   , 32,
20254        0xfc0001ff, 0xc00001d8, &DMODU            , 0,
20255        MIPS64_             },        /* DMODU */
20256     { reserved_block      , 0                   , 0   , 32,
20257        0xfc0001ff, 0xc00001e0, 0                      , 0,
20258        0x0                 },        /* POOL32S_0~*(60) */
20259     { reserved_block      , 0                   , 0   , 32,
20260        0xfc0001ff, 0xc00001e8, 0                      , 0,
20261        0x0                 },        /* POOL32S_0~*(61) */
20262     { reserved_block      , 0                   , 0   , 32,
20263        0xfc0001ff, 0xc00001f0, 0                      , 0,
20264        0x0                 },        /* POOL32S_0~*(62) */
20265     { reserved_block      , 0                   , 0   , 32,
20266        0xfc0001ff, 0xc00001f8, 0                      , 0,
20267        0x0                 },        /* POOL32S_0~*(63) */
20268 };
20269 
20270 
20271 static const Pool POOL32Sxf_4[128] = {
20272     { reserved_block      , 0                   , 0   , 32,
20273        0xfc00ffff, 0xc000013c, 0                      , 0,
20274        0x0                 },        /* POOL32Sxf_4~*(0) */
20275     { reserved_block      , 0                   , 0   , 32,
20276        0xfc00ffff, 0xc000033c, 0                      , 0,
20277        0x0                 },        /* POOL32Sxf_4~*(1) */
20278     { reserved_block      , 0                   , 0   , 32,
20279        0xfc00ffff, 0xc000053c, 0                      , 0,
20280        0x0                 },        /* POOL32Sxf_4~*(2) */
20281     { reserved_block      , 0                   , 0   , 32,
20282        0xfc00ffff, 0xc000073c, 0                      , 0,
20283        0x0                 },        /* POOL32Sxf_4~*(3) */
20284     { reserved_block      , 0                   , 0   , 32,
20285        0xfc00ffff, 0xc000093c, 0                      , 0,
20286        0x0                 },        /* POOL32Sxf_4~*(4) */
20287     { reserved_block      , 0                   , 0   , 32,
20288        0xfc00ffff, 0xc0000b3c, 0                      , 0,
20289        0x0                 },        /* POOL32Sxf_4~*(5) */
20290     { reserved_block      , 0                   , 0   , 32,
20291        0xfc00ffff, 0xc0000d3c, 0                      , 0,
20292        0x0                 },        /* POOL32Sxf_4~*(6) */
20293     { reserved_block      , 0                   , 0   , 32,
20294        0xfc00ffff, 0xc0000f3c, 0                      , 0,
20295        0x0                 },        /* POOL32Sxf_4~*(7) */
20296     { reserved_block      , 0                   , 0   , 32,
20297        0xfc00ffff, 0xc000113c, 0                      , 0,
20298        0x0                 },        /* POOL32Sxf_4~*(8) */
20299     { reserved_block      , 0                   , 0   , 32,
20300        0xfc00ffff, 0xc000133c, 0                      , 0,
20301        0x0                 },        /* POOL32Sxf_4~*(9) */
20302     { reserved_block      , 0                   , 0   , 32,
20303        0xfc00ffff, 0xc000153c, 0                      , 0,
20304        0x0                 },        /* POOL32Sxf_4~*(10) */
20305     { reserved_block      , 0                   , 0   , 32,
20306        0xfc00ffff, 0xc000173c, 0                      , 0,
20307        0x0                 },        /* POOL32Sxf_4~*(11) */
20308     { reserved_block      , 0                   , 0   , 32,
20309        0xfc00ffff, 0xc000193c, 0                      , 0,
20310        0x0                 },        /* POOL32Sxf_4~*(12) */
20311     { reserved_block      , 0                   , 0   , 32,
20312        0xfc00ffff, 0xc0001b3c, 0                      , 0,
20313        0x0                 },        /* POOL32Sxf_4~*(13) */
20314     { reserved_block      , 0                   , 0   , 32,
20315        0xfc00ffff, 0xc0001d3c, 0                      , 0,
20316        0x0                 },        /* POOL32Sxf_4~*(14) */
20317     { reserved_block      , 0                   , 0   , 32,
20318        0xfc00ffff, 0xc0001f3c, 0                      , 0,
20319        0x0                 },        /* POOL32Sxf_4~*(15) */
20320     { reserved_block      , 0                   , 0   , 32,
20321        0xfc00ffff, 0xc000213c, 0                      , 0,
20322        0x0                 },        /* POOL32Sxf_4~*(16) */
20323     { reserved_block      , 0                   , 0   , 32,
20324        0xfc00ffff, 0xc000233c, 0                      , 0,
20325        0x0                 },        /* POOL32Sxf_4~*(17) */
20326     { reserved_block      , 0                   , 0   , 32,
20327        0xfc00ffff, 0xc000253c, 0                      , 0,
20328        0x0                 },        /* POOL32Sxf_4~*(18) */
20329     { reserved_block      , 0                   , 0   , 32,
20330        0xfc00ffff, 0xc000273c, 0                      , 0,
20331        0x0                 },        /* POOL32Sxf_4~*(19) */
20332     { reserved_block      , 0                   , 0   , 32,
20333        0xfc00ffff, 0xc000293c, 0                      , 0,
20334        0x0                 },        /* POOL32Sxf_4~*(20) */
20335     { reserved_block      , 0                   , 0   , 32,
20336        0xfc00ffff, 0xc0002b3c, 0                      , 0,
20337        0x0                 },        /* POOL32Sxf_4~*(21) */
20338     { reserved_block      , 0                   , 0   , 32,
20339        0xfc00ffff, 0xc0002d3c, 0                      , 0,
20340        0x0                 },        /* POOL32Sxf_4~*(22) */
20341     { reserved_block      , 0                   , 0   , 32,
20342        0xfc00ffff, 0xc0002f3c, 0                      , 0,
20343        0x0                 },        /* POOL32Sxf_4~*(23) */
20344     { reserved_block      , 0                   , 0   , 32,
20345        0xfc00ffff, 0xc000313c, 0                      , 0,
20346        0x0                 },        /* POOL32Sxf_4~*(24) */
20347     { reserved_block      , 0                   , 0   , 32,
20348        0xfc00ffff, 0xc000333c, 0                      , 0,
20349        0x0                 },        /* POOL32Sxf_4~*(25) */
20350     { reserved_block      , 0                   , 0   , 32,
20351        0xfc00ffff, 0xc000353c, 0                      , 0,
20352        0x0                 },        /* POOL32Sxf_4~*(26) */
20353     { reserved_block      , 0                   , 0   , 32,
20354        0xfc00ffff, 0xc000373c, 0                      , 0,
20355        0x0                 },        /* POOL32Sxf_4~*(27) */
20356     { reserved_block      , 0                   , 0   , 32,
20357        0xfc00ffff, 0xc000393c, 0                      , 0,
20358        0x0                 },        /* POOL32Sxf_4~*(28) */
20359     { reserved_block      , 0                   , 0   , 32,
20360        0xfc00ffff, 0xc0003b3c, 0                      , 0,
20361        0x0                 },        /* POOL32Sxf_4~*(29) */
20362     { reserved_block      , 0                   , 0   , 32,
20363        0xfc00ffff, 0xc0003d3c, 0                      , 0,
20364        0x0                 },        /* POOL32Sxf_4~*(30) */
20365     { reserved_block      , 0                   , 0   , 32,
20366        0xfc00ffff, 0xc0003f3c, 0                      , 0,
20367        0x0                 },        /* POOL32Sxf_4~*(31) */
20368     { reserved_block      , 0                   , 0   , 32,
20369        0xfc00ffff, 0xc000413c, 0                      , 0,
20370        0x0                 },        /* POOL32Sxf_4~*(32) */
20371     { reserved_block      , 0                   , 0   , 32,
20372        0xfc00ffff, 0xc000433c, 0                      , 0,
20373        0x0                 },        /* POOL32Sxf_4~*(33) */
20374     { reserved_block      , 0                   , 0   , 32,
20375        0xfc00ffff, 0xc000453c, 0                      , 0,
20376        0x0                 },        /* POOL32Sxf_4~*(34) */
20377     { reserved_block      , 0                   , 0   , 32,
20378        0xfc00ffff, 0xc000473c, 0                      , 0,
20379        0x0                 },        /* POOL32Sxf_4~*(35) */
20380     { reserved_block      , 0                   , 0   , 32,
20381        0xfc00ffff, 0xc000493c, 0                      , 0,
20382        0x0                 },        /* POOL32Sxf_4~*(36) */
20383     { instruction         , 0                   , 0   , 32,
20384        0xfc00ffff, 0xc0004b3c, &DCLO             , 0,
20385        MIPS64_             },        /* DCLO */
20386     { reserved_block      , 0                   , 0   , 32,
20387        0xfc00ffff, 0xc0004d3c, 0                      , 0,
20388        0x0                 },        /* POOL32Sxf_4~*(38) */
20389     { reserved_block      , 0                   , 0   , 32,
20390        0xfc00ffff, 0xc0004f3c, 0                      , 0,
20391        0x0                 },        /* POOL32Sxf_4~*(39) */
20392     { reserved_block      , 0                   , 0   , 32,
20393        0xfc00ffff, 0xc000513c, 0                      , 0,
20394        0x0                 },        /* POOL32Sxf_4~*(40) */
20395     { reserved_block      , 0                   , 0   , 32,
20396        0xfc00ffff, 0xc000533c, 0                      , 0,
20397        0x0                 },        /* POOL32Sxf_4~*(41) */
20398     { reserved_block      , 0                   , 0   , 32,
20399        0xfc00ffff, 0xc000553c, 0                      , 0,
20400        0x0                 },        /* POOL32Sxf_4~*(42) */
20401     { reserved_block      , 0                   , 0   , 32,
20402        0xfc00ffff, 0xc000573c, 0                      , 0,
20403        0x0                 },        /* POOL32Sxf_4~*(43) */
20404     { reserved_block      , 0                   , 0   , 32,
20405        0xfc00ffff, 0xc000593c, 0                      , 0,
20406        0x0                 },        /* POOL32Sxf_4~*(44) */
20407     { instruction         , 0                   , 0   , 32,
20408        0xfc00ffff, 0xc0005b3c, &DCLZ             , 0,
20409        MIPS64_             },        /* DCLZ */
20410     { reserved_block      , 0                   , 0   , 32,
20411        0xfc00ffff, 0xc0005d3c, 0                      , 0,
20412        0x0                 },        /* POOL32Sxf_4~*(46) */
20413     { reserved_block      , 0                   , 0   , 32,
20414        0xfc00ffff, 0xc0005f3c, 0                      , 0,
20415        0x0                 },        /* POOL32Sxf_4~*(47) */
20416     { reserved_block      , 0                   , 0   , 32,
20417        0xfc00ffff, 0xc000613c, 0                      , 0,
20418        0x0                 },        /* POOL32Sxf_4~*(48) */
20419     { reserved_block      , 0                   , 0   , 32,
20420        0xfc00ffff, 0xc000633c, 0                      , 0,
20421        0x0                 },        /* POOL32Sxf_4~*(49) */
20422     { reserved_block      , 0                   , 0   , 32,
20423        0xfc00ffff, 0xc000653c, 0                      , 0,
20424        0x0                 },        /* POOL32Sxf_4~*(50) */
20425     { reserved_block      , 0                   , 0   , 32,
20426        0xfc00ffff, 0xc000673c, 0                      , 0,
20427        0x0                 },        /* POOL32Sxf_4~*(51) */
20428     { reserved_block      , 0                   , 0   , 32,
20429        0xfc00ffff, 0xc000693c, 0                      , 0,
20430        0x0                 },        /* POOL32Sxf_4~*(52) */
20431     { reserved_block      , 0                   , 0   , 32,
20432        0xfc00ffff, 0xc0006b3c, 0                      , 0,
20433        0x0                 },        /* POOL32Sxf_4~*(53) */
20434     { reserved_block      , 0                   , 0   , 32,
20435        0xfc00ffff, 0xc0006d3c, 0                      , 0,
20436        0x0                 },        /* POOL32Sxf_4~*(54) */
20437     { reserved_block      , 0                   , 0   , 32,
20438        0xfc00ffff, 0xc0006f3c, 0                      , 0,
20439        0x0                 },        /* POOL32Sxf_4~*(55) */
20440     { reserved_block      , 0                   , 0   , 32,
20441        0xfc00ffff, 0xc000713c, 0                      , 0,
20442        0x0                 },        /* POOL32Sxf_4~*(56) */
20443     { reserved_block      , 0                   , 0   , 32,
20444        0xfc00ffff, 0xc000733c, 0                      , 0,
20445        0x0                 },        /* POOL32Sxf_4~*(57) */
20446     { reserved_block      , 0                   , 0   , 32,
20447        0xfc00ffff, 0xc000753c, 0                      , 0,
20448        0x0                 },        /* POOL32Sxf_4~*(58) */
20449     { reserved_block      , 0                   , 0   , 32,
20450        0xfc00ffff, 0xc000773c, 0                      , 0,
20451        0x0                 },        /* POOL32Sxf_4~*(59) */
20452     { reserved_block      , 0                   , 0   , 32,
20453        0xfc00ffff, 0xc000793c, 0                      , 0,
20454        0x0                 },        /* POOL32Sxf_4~*(60) */
20455     { reserved_block      , 0                   , 0   , 32,
20456        0xfc00ffff, 0xc0007b3c, 0                      , 0,
20457        0x0                 },        /* POOL32Sxf_4~*(61) */
20458     { reserved_block      , 0                   , 0   , 32,
20459        0xfc00ffff, 0xc0007d3c, 0                      , 0,
20460        0x0                 },        /* POOL32Sxf_4~*(62) */
20461     { reserved_block      , 0                   , 0   , 32,
20462        0xfc00ffff, 0xc0007f3c, 0                      , 0,
20463        0x0                 },        /* POOL32Sxf_4~*(63) */
20464     { reserved_block      , 0                   , 0   , 32,
20465        0xfc00ffff, 0xc000813c, 0                      , 0,
20466        0x0                 },        /* POOL32Sxf_4~*(64) */
20467     { reserved_block      , 0                   , 0   , 32,
20468        0xfc00ffff, 0xc000833c, 0                      , 0,
20469        0x0                 },        /* POOL32Sxf_4~*(65) */
20470     { reserved_block      , 0                   , 0   , 32,
20471        0xfc00ffff, 0xc000853c, 0                      , 0,
20472        0x0                 },        /* POOL32Sxf_4~*(66) */
20473     { reserved_block      , 0                   , 0   , 32,
20474        0xfc00ffff, 0xc000873c, 0                      , 0,
20475        0x0                 },        /* POOL32Sxf_4~*(67) */
20476     { reserved_block      , 0                   , 0   , 32,
20477        0xfc00ffff, 0xc000893c, 0                      , 0,
20478        0x0                 },        /* POOL32Sxf_4~*(68) */
20479     { reserved_block      , 0                   , 0   , 32,
20480        0xfc00ffff, 0xc0008b3c, 0                      , 0,
20481        0x0                 },        /* POOL32Sxf_4~*(69) */
20482     { reserved_block      , 0                   , 0   , 32,
20483        0xfc00ffff, 0xc0008d3c, 0                      , 0,
20484        0x0                 },        /* POOL32Sxf_4~*(70) */
20485     { reserved_block      , 0                   , 0   , 32,
20486        0xfc00ffff, 0xc0008f3c, 0                      , 0,
20487        0x0                 },        /* POOL32Sxf_4~*(71) */
20488     { reserved_block      , 0                   , 0   , 32,
20489        0xfc00ffff, 0xc000913c, 0                      , 0,
20490        0x0                 },        /* POOL32Sxf_4~*(72) */
20491     { reserved_block      , 0                   , 0   , 32,
20492        0xfc00ffff, 0xc000933c, 0                      , 0,
20493        0x0                 },        /* POOL32Sxf_4~*(73) */
20494     { reserved_block      , 0                   , 0   , 32,
20495        0xfc00ffff, 0xc000953c, 0                      , 0,
20496        0x0                 },        /* POOL32Sxf_4~*(74) */
20497     { reserved_block      , 0                   , 0   , 32,
20498        0xfc00ffff, 0xc000973c, 0                      , 0,
20499        0x0                 },        /* POOL32Sxf_4~*(75) */
20500     { reserved_block      , 0                   , 0   , 32,
20501        0xfc00ffff, 0xc000993c, 0                      , 0,
20502        0x0                 },        /* POOL32Sxf_4~*(76) */
20503     { reserved_block      , 0                   , 0   , 32,
20504        0xfc00ffff, 0xc0009b3c, 0                      , 0,
20505        0x0                 },        /* POOL32Sxf_4~*(77) */
20506     { reserved_block      , 0                   , 0   , 32,
20507        0xfc00ffff, 0xc0009d3c, 0                      , 0,
20508        0x0                 },        /* POOL32Sxf_4~*(78) */
20509     { reserved_block      , 0                   , 0   , 32,
20510        0xfc00ffff, 0xc0009f3c, 0                      , 0,
20511        0x0                 },        /* POOL32Sxf_4~*(79) */
20512     { reserved_block      , 0                   , 0   , 32,
20513        0xfc00ffff, 0xc000a13c, 0                      , 0,
20514        0x0                 },        /* POOL32Sxf_4~*(80) */
20515     { reserved_block      , 0                   , 0   , 32,
20516        0xfc00ffff, 0xc000a33c, 0                      , 0,
20517        0x0                 },        /* POOL32Sxf_4~*(81) */
20518     { reserved_block      , 0                   , 0   , 32,
20519        0xfc00ffff, 0xc000a53c, 0                      , 0,
20520        0x0                 },        /* POOL32Sxf_4~*(82) */
20521     { reserved_block      , 0                   , 0   , 32,
20522        0xfc00ffff, 0xc000a73c, 0                      , 0,
20523        0x0                 },        /* POOL32Sxf_4~*(83) */
20524     { reserved_block      , 0                   , 0   , 32,
20525        0xfc00ffff, 0xc000a93c, 0                      , 0,
20526        0x0                 },        /* POOL32Sxf_4~*(84) */
20527     { reserved_block      , 0                   , 0   , 32,
20528        0xfc00ffff, 0xc000ab3c, 0                      , 0,
20529        0x0                 },        /* POOL32Sxf_4~*(85) */
20530     { reserved_block      , 0                   , 0   , 32,
20531        0xfc00ffff, 0xc000ad3c, 0                      , 0,
20532        0x0                 },        /* POOL32Sxf_4~*(86) */
20533     { reserved_block      , 0                   , 0   , 32,
20534        0xfc00ffff, 0xc000af3c, 0                      , 0,
20535        0x0                 },        /* POOL32Sxf_4~*(87) */
20536     { reserved_block      , 0                   , 0   , 32,
20537        0xfc00ffff, 0xc000b13c, 0                      , 0,
20538        0x0                 },        /* POOL32Sxf_4~*(88) */
20539     { reserved_block      , 0                   , 0   , 32,
20540        0xfc00ffff, 0xc000b33c, 0                      , 0,
20541        0x0                 },        /* POOL32Sxf_4~*(89) */
20542     { reserved_block      , 0                   , 0   , 32,
20543        0xfc00ffff, 0xc000b53c, 0                      , 0,
20544        0x0                 },        /* POOL32Sxf_4~*(90) */
20545     { reserved_block      , 0                   , 0   , 32,
20546        0xfc00ffff, 0xc000b73c, 0                      , 0,
20547        0x0                 },        /* POOL32Sxf_4~*(91) */
20548     { reserved_block      , 0                   , 0   , 32,
20549        0xfc00ffff, 0xc000b93c, 0                      , 0,
20550        0x0                 },        /* POOL32Sxf_4~*(92) */
20551     { reserved_block      , 0                   , 0   , 32,
20552        0xfc00ffff, 0xc000bb3c, 0                      , 0,
20553        0x0                 },        /* POOL32Sxf_4~*(93) */
20554     { reserved_block      , 0                   , 0   , 32,
20555        0xfc00ffff, 0xc000bd3c, 0                      , 0,
20556        0x0                 },        /* POOL32Sxf_4~*(94) */
20557     { reserved_block      , 0                   , 0   , 32,
20558        0xfc00ffff, 0xc000bf3c, 0                      , 0,
20559        0x0                 },        /* POOL32Sxf_4~*(95) */
20560     { reserved_block      , 0                   , 0   , 32,
20561        0xfc00ffff, 0xc000c13c, 0                      , 0,
20562        0x0                 },        /* POOL32Sxf_4~*(96) */
20563     { reserved_block      , 0                   , 0   , 32,
20564        0xfc00ffff, 0xc000c33c, 0                      , 0,
20565        0x0                 },        /* POOL32Sxf_4~*(97) */
20566     { reserved_block      , 0                   , 0   , 32,
20567        0xfc00ffff, 0xc000c53c, 0                      , 0,
20568        0x0                 },        /* POOL32Sxf_4~*(98) */
20569     { reserved_block      , 0                   , 0   , 32,
20570        0xfc00ffff, 0xc000c73c, 0                      , 0,
20571        0x0                 },        /* POOL32Sxf_4~*(99) */
20572     { reserved_block      , 0                   , 0   , 32,
20573        0xfc00ffff, 0xc000c93c, 0                      , 0,
20574        0x0                 },        /* POOL32Sxf_4~*(100) */
20575     { reserved_block      , 0                   , 0   , 32,
20576        0xfc00ffff, 0xc000cb3c, 0                      , 0,
20577        0x0                 },        /* POOL32Sxf_4~*(101) */
20578     { reserved_block      , 0                   , 0   , 32,
20579        0xfc00ffff, 0xc000cd3c, 0                      , 0,
20580        0x0                 },        /* POOL32Sxf_4~*(102) */
20581     { reserved_block      , 0                   , 0   , 32,
20582        0xfc00ffff, 0xc000cf3c, 0                      , 0,
20583        0x0                 },        /* POOL32Sxf_4~*(103) */
20584     { reserved_block      , 0                   , 0   , 32,
20585        0xfc00ffff, 0xc000d13c, 0                      , 0,
20586        0x0                 },        /* POOL32Sxf_4~*(104) */
20587     { reserved_block      , 0                   , 0   , 32,
20588        0xfc00ffff, 0xc000d33c, 0                      , 0,
20589        0x0                 },        /* POOL32Sxf_4~*(105) */
20590     { reserved_block      , 0                   , 0   , 32,
20591        0xfc00ffff, 0xc000d53c, 0                      , 0,
20592        0x0                 },        /* POOL32Sxf_4~*(106) */
20593     { reserved_block      , 0                   , 0   , 32,
20594        0xfc00ffff, 0xc000d73c, 0                      , 0,
20595        0x0                 },        /* POOL32Sxf_4~*(107) */
20596     { reserved_block      , 0                   , 0   , 32,
20597        0xfc00ffff, 0xc000d93c, 0                      , 0,
20598        0x0                 },        /* POOL32Sxf_4~*(108) */
20599     { reserved_block      , 0                   , 0   , 32,
20600        0xfc00ffff, 0xc000db3c, 0                      , 0,
20601        0x0                 },        /* POOL32Sxf_4~*(109) */
20602     { reserved_block      , 0                   , 0   , 32,
20603        0xfc00ffff, 0xc000dd3c, 0                      , 0,
20604        0x0                 },        /* POOL32Sxf_4~*(110) */
20605     { reserved_block      , 0                   , 0   , 32,
20606        0xfc00ffff, 0xc000df3c, 0                      , 0,
20607        0x0                 },        /* POOL32Sxf_4~*(111) */
20608     { reserved_block      , 0                   , 0   , 32,
20609        0xfc00ffff, 0xc000e13c, 0                      , 0,
20610        0x0                 },        /* POOL32Sxf_4~*(112) */
20611     { reserved_block      , 0                   , 0   , 32,
20612        0xfc00ffff, 0xc000e33c, 0                      , 0,
20613        0x0                 },        /* POOL32Sxf_4~*(113) */
20614     { reserved_block      , 0                   , 0   , 32,
20615        0xfc00ffff, 0xc000e53c, 0                      , 0,
20616        0x0                 },        /* POOL32Sxf_4~*(114) */
20617     { reserved_block      , 0                   , 0   , 32,
20618        0xfc00ffff, 0xc000e73c, 0                      , 0,
20619        0x0                 },        /* POOL32Sxf_4~*(115) */
20620     { reserved_block      , 0                   , 0   , 32,
20621        0xfc00ffff, 0xc000e93c, 0                      , 0,
20622        0x0                 },        /* POOL32Sxf_4~*(116) */
20623     { reserved_block      , 0                   , 0   , 32,
20624        0xfc00ffff, 0xc000eb3c, 0                      , 0,
20625        0x0                 },        /* POOL32Sxf_4~*(117) */
20626     { reserved_block      , 0                   , 0   , 32,
20627        0xfc00ffff, 0xc000ed3c, 0                      , 0,
20628        0x0                 },        /* POOL32Sxf_4~*(118) */
20629     { reserved_block      , 0                   , 0   , 32,
20630        0xfc00ffff, 0xc000ef3c, 0                      , 0,
20631        0x0                 },        /* POOL32Sxf_4~*(119) */
20632     { reserved_block      , 0                   , 0   , 32,
20633        0xfc00ffff, 0xc000f13c, 0                      , 0,
20634        0x0                 },        /* POOL32Sxf_4~*(120) */
20635     { reserved_block      , 0                   , 0   , 32,
20636        0xfc00ffff, 0xc000f33c, 0                      , 0,
20637        0x0                 },        /* POOL32Sxf_4~*(121) */
20638     { reserved_block      , 0                   , 0   , 32,
20639        0xfc00ffff, 0xc000f53c, 0                      , 0,
20640        0x0                 },        /* POOL32Sxf_4~*(122) */
20641     { reserved_block      , 0                   , 0   , 32,
20642        0xfc00ffff, 0xc000f73c, 0                      , 0,
20643        0x0                 },        /* POOL32Sxf_4~*(123) */
20644     { reserved_block      , 0                   , 0   , 32,
20645        0xfc00ffff, 0xc000f93c, 0                      , 0,
20646        0x0                 },        /* POOL32Sxf_4~*(124) */
20647     { reserved_block      , 0                   , 0   , 32,
20648        0xfc00ffff, 0xc000fb3c, 0                      , 0,
20649        0x0                 },        /* POOL32Sxf_4~*(125) */
20650     { reserved_block      , 0                   , 0   , 32,
20651        0xfc00ffff, 0xc000fd3c, 0                      , 0,
20652        0x0                 },        /* POOL32Sxf_4~*(126) */
20653     { reserved_block      , 0                   , 0   , 32,
20654        0xfc00ffff, 0xc000ff3c, 0                      , 0,
20655        0x0                 },        /* POOL32Sxf_4~*(127) */
20656 };
20657 
20658 
20659 static const Pool POOL32Sxf[8] = {
20660     { reserved_block      , 0                   , 0   , 32,
20661        0xfc0001ff, 0xc000003c, 0                      , 0,
20662        0x0                 },        /* POOL32Sxf~*(0) */
20663     { reserved_block      , 0                   , 0   , 32,
20664        0xfc0001ff, 0xc000007c, 0                      , 0,
20665        0x0                 },        /* POOL32Sxf~*(1) */
20666     { reserved_block      , 0                   , 0   , 32,
20667        0xfc0001ff, 0xc00000bc, 0                      , 0,
20668        0x0                 },        /* POOL32Sxf~*(2) */
20669     { reserved_block      , 0                   , 0   , 32,
20670        0xfc0001ff, 0xc00000fc, 0                      , 0,
20671        0x0                 },        /* POOL32Sxf~*(3) */
20672     { pool                , POOL32Sxf_4         , 128 , 32,
20673        0xfc0001ff, 0xc000013c, 0                      , 0,
20674        0x0                 },        /* POOL32Sxf_4 */
20675     { reserved_block      , 0                   , 0   , 32,
20676        0xfc0001ff, 0xc000017c, 0                      , 0,
20677        0x0                 },        /* POOL32Sxf~*(5) */
20678     { reserved_block      , 0                   , 0   , 32,
20679        0xfc0001ff, 0xc00001bc, 0                      , 0,
20680        0x0                 },        /* POOL32Sxf~*(6) */
20681     { reserved_block      , 0                   , 0   , 32,
20682        0xfc0001ff, 0xc00001fc, 0                      , 0,
20683        0x0                 },        /* POOL32Sxf~*(7) */
20684 };
20685 
20686 
20687 static const Pool POOL32S_4[8] = {
20688     { instruction         , 0                   , 0   , 32,
20689        0xfc00003f, 0xc0000004, &EXTD             , 0,
20690        MIPS64_             },        /* EXTD */
20691     { instruction         , 0                   , 0   , 32,
20692        0xfc00003f, 0xc000000c, &EXTD32           , 0,
20693        MIPS64_             },        /* EXTD32 */
20694     { reserved_block      , 0                   , 0   , 32,
20695        0xfc00003f, 0xc0000014, 0                      , 0,
20696        0x0                 },        /* POOL32S_4~*(2) */
20697     { reserved_block      , 0                   , 0   , 32,
20698        0xfc00003f, 0xc000001c, 0                      , 0,
20699        0x0                 },        /* POOL32S_4~*(3) */
20700     { reserved_block      , 0                   , 0   , 32,
20701        0xfc00003f, 0xc0000024, 0                      , 0,
20702        0x0                 },        /* POOL32S_4~*(4) */
20703     { reserved_block      , 0                   , 0   , 32,
20704        0xfc00003f, 0xc000002c, 0                      , 0,
20705        0x0                 },        /* POOL32S_4~*(5) */
20706     { reserved_block      , 0                   , 0   , 32,
20707        0xfc00003f, 0xc0000034, 0                      , 0,
20708        0x0                 },        /* POOL32S_4~*(6) */
20709     { pool                , POOL32Sxf           , 8   , 32,
20710        0xfc00003f, 0xc000003c, 0                      , 0,
20711        0x0                 },        /* POOL32Sxf */
20712 };
20713 
20714 
20715 static const Pool POOL32S[8] = {
20716     { pool                , POOL32S_0           , 64  , 32,
20717        0xfc000007, 0xc0000000, 0                      , 0,
20718        0x0                 },        /* POOL32S_0 */
20719     { reserved_block      , 0                   , 0   , 32,
20720        0xfc000007, 0xc0000001, 0                      , 0,
20721        0x0                 },        /* POOL32S~*(1) */
20722     { reserved_block      , 0                   , 0   , 32,
20723        0xfc000007, 0xc0000002, 0                      , 0,
20724        0x0                 },        /* POOL32S~*(2) */
20725     { reserved_block      , 0                   , 0   , 32,
20726        0xfc000007, 0xc0000003, 0                      , 0,
20727        0x0                 },        /* POOL32S~*(3) */
20728     { pool                , POOL32S_4           , 8   , 32,
20729        0xfc000007, 0xc0000004, 0                      , 0,
20730        0x0                 },        /* POOL32S_4 */
20731     { reserved_block      , 0                   , 0   , 32,
20732        0xfc000007, 0xc0000005, 0                      , 0,
20733        0x0                 },        /* POOL32S~*(5) */
20734     { reserved_block      , 0                   , 0   , 32,
20735        0xfc000007, 0xc0000006, 0                      , 0,
20736        0x0                 },        /* POOL32S~*(6) */
20737     { reserved_block      , 0                   , 0   , 32,
20738        0xfc000007, 0xc0000007, 0                      , 0,
20739        0x0                 },        /* POOL32S~*(7) */
20740 };
20741 
20742 
20743 static const Pool P_LUI[2] = {
20744     { instruction         , 0                   , 0   , 32,
20745        0xfc000002, 0xe0000000, &LUI              , 0,
20746        0x0                 },        /* LUI */
20747     { instruction         , 0                   , 0   , 32,
20748        0xfc000002, 0xe0000002, &ALUIPC           , 0,
20749        0x0                 },        /* ALUIPC */
20750 };
20751 
20752 
20753 static const Pool P_GP_LH[2] = {
20754     { instruction         , 0                   , 0   , 32,
20755        0xfc1c0001, 0x44100000, &LH_GP_           , 0,
20756        0x0                 },        /* LH[GP] */
20757     { instruction         , 0                   , 0   , 32,
20758        0xfc1c0001, 0x44100001, &LHU_GP_          , 0,
20759        0x0                 },        /* LHU[GP] */
20760 };
20761 
20762 
20763 static const Pool P_GP_SH[2] = {
20764     { instruction         , 0                   , 0   , 32,
20765        0xfc1c0001, 0x44140000, &SH_GP_           , 0,
20766        0x0                 },        /* SH[GP] */
20767     { reserved_block      , 0                   , 0   , 32,
20768        0xfc1c0001, 0x44140001, 0                      , 0,
20769        0x0                 },        /* P.GP.SH~*(1) */
20770 };
20771 
20772 
20773 static const Pool P_GP_CP1[4] = {
20774     { instruction         , 0                   , 0   , 32,
20775        0xfc1c0003, 0x44180000, &LWC1_GP_         , 0,
20776        CP1_                },        /* LWC1[GP] */
20777     { instruction         , 0                   , 0   , 32,
20778        0xfc1c0003, 0x44180001, &SWC1_GP_         , 0,
20779        CP1_                },        /* SWC1[GP] */
20780     { instruction         , 0                   , 0   , 32,
20781        0xfc1c0003, 0x44180002, &LDC1_GP_         , 0,
20782        CP1_                },        /* LDC1[GP] */
20783     { instruction         , 0                   , 0   , 32,
20784        0xfc1c0003, 0x44180003, &SDC1_GP_         , 0,
20785        CP1_                },        /* SDC1[GP] */
20786 };
20787 
20788 
20789 static const Pool P_GP_M64[4] = {
20790     { instruction         , 0                   , 0   , 32,
20791        0xfc1c0003, 0x441c0000, &LWU_GP_          , 0,
20792        MIPS64_             },        /* LWU[GP] */
20793     { reserved_block      , 0                   , 0   , 32,
20794        0xfc1c0003, 0x441c0001, 0                      , 0,
20795        0x0                 },        /* P.GP.M64~*(1) */
20796     { reserved_block      , 0                   , 0   , 32,
20797        0xfc1c0003, 0x441c0002, 0                      , 0,
20798        0x0                 },        /* P.GP.M64~*(2) */
20799     { reserved_block      , 0                   , 0   , 32,
20800        0xfc1c0003, 0x441c0003, 0                      , 0,
20801        0x0                 },        /* P.GP.M64~*(3) */
20802 };
20803 
20804 
20805 static const Pool P_GP_BH[8] = {
20806     { instruction         , 0                   , 0   , 32,
20807        0xfc1c0000, 0x44000000, &LB_GP_           , 0,
20808        0x0                 },        /* LB[GP] */
20809     { instruction         , 0                   , 0   , 32,
20810        0xfc1c0000, 0x44040000, &SB_GP_           , 0,
20811        0x0                 },        /* SB[GP] */
20812     { instruction         , 0                   , 0   , 32,
20813        0xfc1c0000, 0x44080000, &LBU_GP_          , 0,
20814        0x0                 },        /* LBU[GP] */
20815     { instruction         , 0                   , 0   , 32,
20816        0xfc1c0000, 0x440c0000, &ADDIU_GP_B_      , 0,
20817        0x0                 },        /* ADDIU[GP.B] */
20818     { pool                , P_GP_LH             , 2   , 32,
20819        0xfc1c0000, 0x44100000, 0                      , 0,
20820        0x0                 },        /* P.GP.LH */
20821     { pool                , P_GP_SH             , 2   , 32,
20822        0xfc1c0000, 0x44140000, 0                      , 0,
20823        0x0                 },        /* P.GP.SH */
20824     { pool                , P_GP_CP1            , 4   , 32,
20825        0xfc1c0000, 0x44180000, 0                      , 0,
20826        0x0                 },        /* P.GP.CP1 */
20827     { pool                , P_GP_M64            , 4   , 32,
20828        0xfc1c0000, 0x441c0000, 0                      , 0,
20829        0x0                 },        /* P.GP.M64 */
20830 };
20831 
20832 
20833 static const Pool P_LS_U12[16] = {
20834     { instruction         , 0                   , 0   , 32,
20835        0xfc00f000, 0x84000000, &LB_U12_          , 0,
20836        0x0                 },        /* LB[U12] */
20837     { instruction         , 0                   , 0   , 32,
20838        0xfc00f000, 0x84001000, &SB_U12_          , 0,
20839        0x0                 },        /* SB[U12] */
20840     { instruction         , 0                   , 0   , 32,
20841        0xfc00f000, 0x84002000, &LBU_U12_         , 0,
20842        0x0                 },        /* LBU[U12] */
20843     { instruction         , 0                   , 0   , 32,
20844        0xfc00f000, 0x84003000, &PREF_U12_        , 0,
20845        0x0                 },        /* PREF[U12] */
20846     { instruction         , 0                   , 0   , 32,
20847        0xfc00f000, 0x84004000, &LH_U12_          , 0,
20848        0x0                 },        /* LH[U12] */
20849     { instruction         , 0                   , 0   , 32,
20850        0xfc00f000, 0x84005000, &SH_U12_          , 0,
20851        0x0                 },        /* SH[U12] */
20852     { instruction         , 0                   , 0   , 32,
20853        0xfc00f000, 0x84006000, &LHU_U12_         , 0,
20854        0x0                 },        /* LHU[U12] */
20855     { instruction         , 0                   , 0   , 32,
20856        0xfc00f000, 0x84007000, &LWU_U12_         , 0,
20857        MIPS64_             },        /* LWU[U12] */
20858     { instruction         , 0                   , 0   , 32,
20859        0xfc00f000, 0x84008000, &LW_U12_          , 0,
20860        0x0                 },        /* LW[U12] */
20861     { instruction         , 0                   , 0   , 32,
20862        0xfc00f000, 0x84009000, &SW_U12_          , 0,
20863        0x0                 },        /* SW[U12] */
20864     { instruction         , 0                   , 0   , 32,
20865        0xfc00f000, 0x8400a000, &LWC1_U12_        , 0,
20866        CP1_                },        /* LWC1[U12] */
20867     { instruction         , 0                   , 0   , 32,
20868        0xfc00f000, 0x8400b000, &SWC1_U12_        , 0,
20869        CP1_                },        /* SWC1[U12] */
20870     { instruction         , 0                   , 0   , 32,
20871        0xfc00f000, 0x8400c000, &LD_U12_          , 0,
20872        MIPS64_             },        /* LD[U12] */
20873     { instruction         , 0                   , 0   , 32,
20874        0xfc00f000, 0x8400d000, &SD_U12_          , 0,
20875        MIPS64_             },        /* SD[U12] */
20876     { instruction         , 0                   , 0   , 32,
20877        0xfc00f000, 0x8400e000, &LDC1_U12_        , 0,
20878        CP1_                },        /* LDC1[U12] */
20879     { instruction         , 0                   , 0   , 32,
20880        0xfc00f000, 0x8400f000, &SDC1_U12_        , 0,
20881        CP1_                },        /* SDC1[U12] */
20882 };
20883 
20884 
20885 static const Pool P_PREF_S9_[2] = {
20886     { instruction         , 0                   , 0   , 32,
20887        0xffe07f00, 0xa7e01800, &SYNCI            , 0,
20888        0x0                 },        /* SYNCI */
20889     { instruction         , 0                   , 0   , 32,
20890        0xfc007f00, 0xa4001800, &PREF_S9_         , &PREF_S9__cond    ,
20891        0x0                 },        /* PREF[S9] */
20892 };
20893 
20894 
20895 static const Pool P_LS_S0[16] = {
20896     { instruction         , 0                   , 0   , 32,
20897        0xfc007f00, 0xa4000000, &LB_S9_           , 0,
20898        0x0                 },        /* LB[S9] */
20899     { instruction         , 0                   , 0   , 32,
20900        0xfc007f00, 0xa4000800, &SB_S9_           , 0,
20901        0x0                 },        /* SB[S9] */
20902     { instruction         , 0                   , 0   , 32,
20903        0xfc007f00, 0xa4001000, &LBU_S9_          , 0,
20904        0x0                 },        /* LBU[S9] */
20905     { pool                , P_PREF_S9_          , 2   , 32,
20906        0xfc007f00, 0xa4001800, 0                      , 0,
20907        0x0                 },        /* P.PREF[S9] */
20908     { instruction         , 0                   , 0   , 32,
20909        0xfc007f00, 0xa4002000, &LH_S9_           , 0,
20910        0x0                 },        /* LH[S9] */
20911     { instruction         , 0                   , 0   , 32,
20912        0xfc007f00, 0xa4002800, &SH_S9_           , 0,
20913        0x0                 },        /* SH[S9] */
20914     { instruction         , 0                   , 0   , 32,
20915        0xfc007f00, 0xa4003000, &LHU_S9_          , 0,
20916        0x0                 },        /* LHU[S9] */
20917     { instruction         , 0                   , 0   , 32,
20918        0xfc007f00, 0xa4003800, &LWU_S9_          , 0,
20919        MIPS64_             },        /* LWU[S9] */
20920     { instruction         , 0                   , 0   , 32,
20921        0xfc007f00, 0xa4004000, &LW_S9_           , 0,
20922        0x0                 },        /* LW[S9] */
20923     { instruction         , 0                   , 0   , 32,
20924        0xfc007f00, 0xa4004800, &SW_S9_           , 0,
20925        0x0                 },        /* SW[S9] */
20926     { instruction         , 0                   , 0   , 32,
20927        0xfc007f00, 0xa4005000, &LWC1_S9_         , 0,
20928        CP1_                },        /* LWC1[S9] */
20929     { instruction         , 0                   , 0   , 32,
20930        0xfc007f00, 0xa4005800, &SWC1_S9_         , 0,
20931        CP1_                },        /* SWC1[S9] */
20932     { instruction         , 0                   , 0   , 32,
20933        0xfc007f00, 0xa4006000, &LD_S9_           , 0,
20934        MIPS64_             },        /* LD[S9] */
20935     { instruction         , 0                   , 0   , 32,
20936        0xfc007f00, 0xa4006800, &SD_S9_           , 0,
20937        MIPS64_             },        /* SD[S9] */
20938     { instruction         , 0                   , 0   , 32,
20939        0xfc007f00, 0xa4007000, &LDC1_S9_         , 0,
20940        CP1_                },        /* LDC1[S9] */
20941     { instruction         , 0                   , 0   , 32,
20942        0xfc007f00, 0xa4007800, &SDC1_S9_         , 0,
20943        CP1_                },        /* SDC1[S9] */
20944 };
20945 
20946 
20947 static const Pool ASET_ACLR[2] = {
20948     { instruction         , 0                   , 0   , 32,
20949        0xfe007f00, 0xa4001100, &ASET             , 0,
20950        MCU_                },        /* ASET */
20951     { instruction         , 0                   , 0   , 32,
20952        0xfe007f00, 0xa6001100, &ACLR             , 0,
20953        MCU_                },        /* ACLR */
20954 };
20955 
20956 
20957 static const Pool P_LL[4] = {
20958     { instruction         , 0                   , 0   , 32,
20959        0xfc007f03, 0xa4005100, &LL               , 0,
20960        0x0                 },        /* LL */
20961     { instruction         , 0                   , 0   , 32,
20962        0xfc007f03, 0xa4005101, &LLWP             , 0,
20963        XNP_                },        /* LLWP */
20964     { reserved_block      , 0                   , 0   , 32,
20965        0xfc007f03, 0xa4005102, 0                      , 0,
20966        0x0                 },        /* P.LL~*(2) */
20967     { reserved_block      , 0                   , 0   , 32,
20968        0xfc007f03, 0xa4005103, 0                      , 0,
20969        0x0                 },        /* P.LL~*(3) */
20970 };
20971 
20972 
20973 static const Pool P_SC[4] = {
20974     { instruction         , 0                   , 0   , 32,
20975        0xfc007f03, 0xa4005900, &SC               , 0,
20976        0x0                 },        /* SC */
20977     { instruction         , 0                   , 0   , 32,
20978        0xfc007f03, 0xa4005901, &SCWP             , 0,
20979        XNP_                },        /* SCWP */
20980     { reserved_block      , 0                   , 0   , 32,
20981        0xfc007f03, 0xa4005902, 0                      , 0,
20982        0x0                 },        /* P.SC~*(2) */
20983     { reserved_block      , 0                   , 0   , 32,
20984        0xfc007f03, 0xa4005903, 0                      , 0,
20985        0x0                 },        /* P.SC~*(3) */
20986 };
20987 
20988 
20989 static const Pool P_LLD[8] = {
20990     { instruction         , 0                   , 0   , 32,
20991        0xfc007f07, 0xa4007100, &LLD              , 0,
20992        MIPS64_             },        /* LLD */
20993     { instruction         , 0                   , 0   , 32,
20994        0xfc007f07, 0xa4007101, &LLDP             , 0,
20995        MIPS64_             },        /* LLDP */
20996     { reserved_block      , 0                   , 0   , 32,
20997        0xfc007f07, 0xa4007102, 0                      , 0,
20998        0x0                 },        /* P.LLD~*(2) */
20999     { reserved_block      , 0                   , 0   , 32,
21000        0xfc007f07, 0xa4007103, 0                      , 0,
21001        0x0                 },        /* P.LLD~*(3) */
21002     { reserved_block      , 0                   , 0   , 32,
21003        0xfc007f07, 0xa4007104, 0                      , 0,
21004        0x0                 },        /* P.LLD~*(4) */
21005     { reserved_block      , 0                   , 0   , 32,
21006        0xfc007f07, 0xa4007105, 0                      , 0,
21007        0x0                 },        /* P.LLD~*(5) */
21008     { reserved_block      , 0                   , 0   , 32,
21009        0xfc007f07, 0xa4007106, 0                      , 0,
21010        0x0                 },        /* P.LLD~*(6) */
21011     { reserved_block      , 0                   , 0   , 32,
21012        0xfc007f07, 0xa4007107, 0                      , 0,
21013        0x0                 },        /* P.LLD~*(7) */
21014 };
21015 
21016 
21017 static const Pool P_SCD[8] = {
21018     { instruction         , 0                   , 0   , 32,
21019        0xfc007f07, 0xa4007900, &SCD              , 0,
21020        MIPS64_             },        /* SCD */
21021     { instruction         , 0                   , 0   , 32,
21022        0xfc007f07, 0xa4007901, &SCDP             , 0,
21023        MIPS64_             },        /* SCDP */
21024     { reserved_block      , 0                   , 0   , 32,
21025        0xfc007f07, 0xa4007902, 0                      , 0,
21026        0x0                 },        /* P.SCD~*(2) */
21027     { reserved_block      , 0                   , 0   , 32,
21028        0xfc007f07, 0xa4007903, 0                      , 0,
21029        0x0                 },        /* P.SCD~*(3) */
21030     { reserved_block      , 0                   , 0   , 32,
21031        0xfc007f07, 0xa4007904, 0                      , 0,
21032        0x0                 },        /* P.SCD~*(4) */
21033     { reserved_block      , 0                   , 0   , 32,
21034        0xfc007f07, 0xa4007905, 0                      , 0,
21035        0x0                 },        /* P.SCD~*(5) */
21036     { reserved_block      , 0                   , 0   , 32,
21037        0xfc007f07, 0xa4007906, 0                      , 0,
21038        0x0                 },        /* P.SCD~*(6) */
21039     { reserved_block      , 0                   , 0   , 32,
21040        0xfc007f07, 0xa4007907, 0                      , 0,
21041        0x0                 },        /* P.SCD~*(7) */
21042 };
21043 
21044 
21045 static const Pool P_LS_S1[16] = {
21046     { reserved_block      , 0                   , 0   , 32,
21047        0xfc007f00, 0xa4000100, 0                      , 0,
21048        0x0                 },        /* P.LS.S1~*(0) */
21049     { reserved_block      , 0                   , 0   , 32,
21050        0xfc007f00, 0xa4000900, 0                      , 0,
21051        0x0                 },        /* P.LS.S1~*(1) */
21052     { pool                , ASET_ACLR           , 2   , 32,
21053        0xfc007f00, 0xa4001100, 0                      , 0,
21054        0x0                 },        /* ASET_ACLR */
21055     { reserved_block      , 0                   , 0   , 32,
21056        0xfc007f00, 0xa4001900, 0                      , 0,
21057        0x0                 },        /* P.LS.S1~*(3) */
21058     { instruction         , 0                   , 0   , 32,
21059        0xfc007f00, 0xa4002100, &UALH             , 0,
21060        XMMS_               },        /* UALH */
21061     { instruction         , 0                   , 0   , 32,
21062        0xfc007f00, 0xa4002900, &UASH             , 0,
21063        XMMS_               },        /* UASH */
21064     { reserved_block      , 0                   , 0   , 32,
21065        0xfc007f00, 0xa4003100, 0                      , 0,
21066        0x0                 },        /* P.LS.S1~*(6) */
21067     { instruction         , 0                   , 0   , 32,
21068        0xfc007f00, 0xa4003900, &CACHE            , 0,
21069        CP0_                },        /* CACHE */
21070     { instruction         , 0                   , 0   , 32,
21071        0xfc007f00, 0xa4004100, &LWC2             , 0,
21072        CP2_                },        /* LWC2 */
21073     { instruction         , 0                   , 0   , 32,
21074        0xfc007f00, 0xa4004900, &SWC2             , 0,
21075        CP2_                },        /* SWC2 */
21076     { pool                , P_LL                , 4   , 32,
21077        0xfc007f00, 0xa4005100, 0                      , 0,
21078        0x0                 },        /* P.LL */
21079     { pool                , P_SC                , 4   , 32,
21080        0xfc007f00, 0xa4005900, 0                      , 0,
21081        0x0                 },        /* P.SC */
21082     { instruction         , 0                   , 0   , 32,
21083        0xfc007f00, 0xa4006100, &LDC2             , 0,
21084        CP2_                },        /* LDC2 */
21085     { instruction         , 0                   , 0   , 32,
21086        0xfc007f00, 0xa4006900, &SDC2             , 0,
21087        CP2_                },        /* SDC2 */
21088     { pool                , P_LLD               , 8   , 32,
21089        0xfc007f00, 0xa4007100, 0                      , 0,
21090        0x0                 },        /* P.LLD */
21091     { pool                , P_SCD               , 8   , 32,
21092        0xfc007f00, 0xa4007900, 0                      , 0,
21093        0x0                 },        /* P.SCD */
21094 };
21095 
21096 
21097 static const Pool P_PREFE[2] = {
21098     { instruction         , 0                   , 0   , 32,
21099        0xffe07f00, 0xa7e01a00, &SYNCIE           , 0,
21100        CP0_ | EVA_         },        /* SYNCIE */
21101     { instruction         , 0                   , 0   , 32,
21102        0xfc007f00, 0xa4001a00, &PREFE            , &PREFE_cond       ,
21103        CP0_ | EVA_         },        /* PREFE */
21104 };
21105 
21106 
21107 static const Pool P_LLE[4] = {
21108     { instruction         , 0                   , 0   , 32,
21109        0xfc007f03, 0xa4005200, &LLE              , 0,
21110        CP0_ | EVA_         },        /* LLE */
21111     { instruction         , 0                   , 0   , 32,
21112        0xfc007f03, 0xa4005201, &LLWPE            , 0,
21113        CP0_ | EVA_         },        /* LLWPE */
21114     { reserved_block      , 0                   , 0   , 32,
21115        0xfc007f03, 0xa4005202, 0                      , 0,
21116        0x0                 },        /* P.LLE~*(2) */
21117     { reserved_block      , 0                   , 0   , 32,
21118        0xfc007f03, 0xa4005203, 0                      , 0,
21119        0x0                 },        /* P.LLE~*(3) */
21120 };
21121 
21122 
21123 static const Pool P_SCE[4] = {
21124     { instruction         , 0                   , 0   , 32,
21125        0xfc007f03, 0xa4005a00, &SCE              , 0,
21126        CP0_ | EVA_         },        /* SCE */
21127     { instruction         , 0                   , 0   , 32,
21128        0xfc007f03, 0xa4005a01, &SCWPE            , 0,
21129        CP0_ | EVA_         },        /* SCWPE */
21130     { reserved_block      , 0                   , 0   , 32,
21131        0xfc007f03, 0xa4005a02, 0                      , 0,
21132        0x0                 },        /* P.SCE~*(2) */
21133     { reserved_block      , 0                   , 0   , 32,
21134        0xfc007f03, 0xa4005a03, 0                      , 0,
21135        0x0                 },        /* P.SCE~*(3) */
21136 };
21137 
21138 
21139 static const Pool P_LS_E0[16] = {
21140     { instruction         , 0                   , 0   , 32,
21141        0xfc007f00, 0xa4000200, &LBE              , 0,
21142        CP0_ | EVA_         },        /* LBE */
21143     { instruction         , 0                   , 0   , 32,
21144        0xfc007f00, 0xa4000a00, &SBE              , 0,
21145        CP0_ | EVA_         },        /* SBE */
21146     { instruction         , 0                   , 0   , 32,
21147        0xfc007f00, 0xa4001200, &LBUE             , 0,
21148        CP0_ | EVA_         },        /* LBUE */
21149     { pool                , P_PREFE             , 2   , 32,
21150        0xfc007f00, 0xa4001a00, 0                      , 0,
21151        0x0                 },        /* P.PREFE */
21152     { instruction         , 0                   , 0   , 32,
21153        0xfc007f00, 0xa4002200, &LHE              , 0,
21154        CP0_ | EVA_         },        /* LHE */
21155     { instruction         , 0                   , 0   , 32,
21156        0xfc007f00, 0xa4002a00, &SHE              , 0,
21157        CP0_ | EVA_         },        /* SHE */
21158     { instruction         , 0                   , 0   , 32,
21159        0xfc007f00, 0xa4003200, &LHUE             , 0,
21160        CP0_ | EVA_         },        /* LHUE */
21161     { instruction         , 0                   , 0   , 32,
21162        0xfc007f00, 0xa4003a00, &CACHEE           , 0,
21163        CP0_ | EVA_         },        /* CACHEE */
21164     { instruction         , 0                   , 0   , 32,
21165        0xfc007f00, 0xa4004200, &LWE              , 0,
21166        CP0_ | EVA_         },        /* LWE */
21167     { instruction         , 0                   , 0   , 32,
21168        0xfc007f00, 0xa4004a00, &SWE              , 0,
21169        CP0_ | EVA_         },        /* SWE */
21170     { pool                , P_LLE               , 4   , 32,
21171        0xfc007f00, 0xa4005200, 0                      , 0,
21172        0x0                 },        /* P.LLE */
21173     { pool                , P_SCE               , 4   , 32,
21174        0xfc007f00, 0xa4005a00, 0                      , 0,
21175        0x0                 },        /* P.SCE */
21176     { reserved_block      , 0                   , 0   , 32,
21177        0xfc007f00, 0xa4006200, 0                      , 0,
21178        0x0                 },        /* P.LS.E0~*(12) */
21179     { reserved_block      , 0                   , 0   , 32,
21180        0xfc007f00, 0xa4006a00, 0                      , 0,
21181        0x0                 },        /* P.LS.E0~*(13) */
21182     { reserved_block      , 0                   , 0   , 32,
21183        0xfc007f00, 0xa4007200, 0                      , 0,
21184        0x0                 },        /* P.LS.E0~*(14) */
21185     { reserved_block      , 0                   , 0   , 32,
21186        0xfc007f00, 0xa4007a00, 0                      , 0,
21187        0x0                 },        /* P.LS.E0~*(15) */
21188 };
21189 
21190 
21191 static const Pool P_LS_WM[2] = {
21192     { instruction         , 0                   , 0   , 32,
21193        0xfc000f00, 0xa4000400, &LWM              , 0,
21194        XMMS_               },        /* LWM */
21195     { instruction         , 0                   , 0   , 32,
21196        0xfc000f00, 0xa4000c00, &SWM              , 0,
21197        XMMS_               },        /* SWM */
21198 };
21199 
21200 
21201 static const Pool P_LS_UAWM[2] = {
21202     { instruction         , 0                   , 0   , 32,
21203        0xfc000f00, 0xa4000500, &UALWM            , 0,
21204        XMMS_               },        /* UALWM */
21205     { instruction         , 0                   , 0   , 32,
21206        0xfc000f00, 0xa4000d00, &UASWM            , 0,
21207        XMMS_               },        /* UASWM */
21208 };
21209 
21210 
21211 static const Pool P_LS_DM[2] = {
21212     { instruction         , 0                   , 0   , 32,
21213        0xfc000f00, 0xa4000600, &LDM              , 0,
21214        MIPS64_             },        /* LDM */
21215     { instruction         , 0                   , 0   , 32,
21216        0xfc000f00, 0xa4000e00, &SDM              , 0,
21217        MIPS64_             },        /* SDM */
21218 };
21219 
21220 
21221 static const Pool P_LS_UADM[2] = {
21222     { instruction         , 0                   , 0   , 32,
21223        0xfc000f00, 0xa4000700, &UALDM            , 0,
21224        MIPS64_             },        /* UALDM */
21225     { instruction         , 0                   , 0   , 32,
21226        0xfc000f00, 0xa4000f00, &UASDM            , 0,
21227        MIPS64_             },        /* UASDM */
21228 };
21229 
21230 
21231 static const Pool P_LS_S9[8] = {
21232     { pool                , P_LS_S0             , 16  , 32,
21233        0xfc000700, 0xa4000000, 0                      , 0,
21234        0x0                 },        /* P.LS.S0 */
21235     { pool                , P_LS_S1             , 16  , 32,
21236        0xfc000700, 0xa4000100, 0                      , 0,
21237        0x0                 },        /* P.LS.S1 */
21238     { pool                , P_LS_E0             , 16  , 32,
21239        0xfc000700, 0xa4000200, 0                      , 0,
21240        0x0                 },        /* P.LS.E0 */
21241     { reserved_block      , 0                   , 0   , 32,
21242        0xfc000700, 0xa4000300, 0                      , 0,
21243        0x0                 },        /* P.LS.S9~*(3) */
21244     { pool                , P_LS_WM             , 2   , 32,
21245        0xfc000700, 0xa4000400, 0                      , 0,
21246        0x0                 },        /* P.LS.WM */
21247     { pool                , P_LS_UAWM           , 2   , 32,
21248        0xfc000700, 0xa4000500, 0                      , 0,
21249        0x0                 },        /* P.LS.UAWM */
21250     { pool                , P_LS_DM             , 2   , 32,
21251        0xfc000700, 0xa4000600, 0                      , 0,
21252        0x0                 },        /* P.LS.DM */
21253     { pool                , P_LS_UADM           , 2   , 32,
21254        0xfc000700, 0xa4000700, 0                      , 0,
21255        0x0                 },        /* P.LS.UADM */
21256 };
21257 
21258 
21259 static const Pool P_BAL[2] = {
21260     { branch_instruction  , 0                   , 0   , 32,
21261        0xfe000000, 0x28000000, &BC_32_           , 0,
21262        0x0                 },        /* BC[32] */
21263     { call_instruction    , 0                   , 0   , 32,
21264        0xfe000000, 0x2a000000, &BALC_32_         , 0,
21265        0x0                 },        /* BALC[32] */
21266 };
21267 
21268 
21269 static const Pool P_BALRSC[2] = {
21270     { branch_instruction  , 0                   , 0   , 32,
21271        0xffe0f000, 0x48008000, &BRSC             , 0,
21272        0x0                 },        /* BRSC */
21273     { call_instruction    , 0                   , 0   , 32,
21274        0xfc00f000, 0x48008000, &BALRSC           , &BALRSC_cond      ,
21275        0x0                 },        /* BALRSC */
21276 };
21277 
21278 
21279 static const Pool P_J[16] = {
21280     { call_instruction    , 0                   , 0   , 32,
21281        0xfc00f000, 0x48000000, &JALRC_32_        , 0,
21282        0x0                 },        /* JALRC[32] */
21283     { call_instruction    , 0                   , 0   , 32,
21284        0xfc00f000, 0x48001000, &JALRC_HB         , 0,
21285        0x0                 },        /* JALRC.HB */
21286     { reserved_block      , 0                   , 0   , 32,
21287        0xfc00f000, 0x48002000, 0                      , 0,
21288        0x0                 },        /* P.J~*(2) */
21289     { reserved_block      , 0                   , 0   , 32,
21290        0xfc00f000, 0x48003000, 0                      , 0,
21291        0x0                 },        /* P.J~*(3) */
21292     { reserved_block      , 0                   , 0   , 32,
21293        0xfc00f000, 0x48004000, 0                      , 0,
21294        0x0                 },        /* P.J~*(4) */
21295     { reserved_block      , 0                   , 0   , 32,
21296        0xfc00f000, 0x48005000, 0                      , 0,
21297        0x0                 },        /* P.J~*(5) */
21298     { reserved_block      , 0                   , 0   , 32,
21299        0xfc00f000, 0x48006000, 0                      , 0,
21300        0x0                 },        /* P.J~*(6) */
21301     { reserved_block      , 0                   , 0   , 32,
21302        0xfc00f000, 0x48007000, 0                      , 0,
21303        0x0                 },        /* P.J~*(7) */
21304     { pool                , P_BALRSC            , 2   , 32,
21305        0xfc00f000, 0x48008000, 0                      , 0,
21306        0x0                 },        /* P.BALRSC */
21307     { reserved_block      , 0                   , 0   , 32,
21308        0xfc00f000, 0x48009000, 0                      , 0,
21309        0x0                 },        /* P.J~*(9) */
21310     { reserved_block      , 0                   , 0   , 32,
21311        0xfc00f000, 0x4800a000, 0                      , 0,
21312        0x0                 },        /* P.J~*(10) */
21313     { reserved_block      , 0                   , 0   , 32,
21314        0xfc00f000, 0x4800b000, 0                      , 0,
21315        0x0                 },        /* P.J~*(11) */
21316     { reserved_block      , 0                   , 0   , 32,
21317        0xfc00f000, 0x4800c000, 0                      , 0,
21318        0x0                 },        /* P.J~*(12) */
21319     { reserved_block      , 0                   , 0   , 32,
21320        0xfc00f000, 0x4800d000, 0                      , 0,
21321        0x0                 },        /* P.J~*(13) */
21322     { reserved_block      , 0                   , 0   , 32,
21323        0xfc00f000, 0x4800e000, 0                      , 0,
21324        0x0                 },        /* P.J~*(14) */
21325     { reserved_block      , 0                   , 0   , 32,
21326        0xfc00f000, 0x4800f000, 0                      , 0,
21327        0x0                 },        /* P.J~*(15) */
21328 };
21329 
21330 
21331 static const Pool P_BR3A[32] = {
21332     { branch_instruction  , 0                   , 0   , 32,
21333        0xfc1fc000, 0x88004000, &BC1EQZC          , 0,
21334        CP1_                },        /* BC1EQZC */
21335     { branch_instruction  , 0                   , 0   , 32,
21336        0xfc1fc000, 0x88014000, &BC1NEZC          , 0,
21337        CP1_                },        /* BC1NEZC */
21338     { branch_instruction  , 0                   , 0   , 32,
21339        0xfc1fc000, 0x88024000, &BC2EQZC          , 0,
21340        CP2_                },        /* BC2EQZC */
21341     { branch_instruction  , 0                   , 0   , 32,
21342        0xfc1fc000, 0x88034000, &BC2NEZC          , 0,
21343        CP2_                },        /* BC2NEZC */
21344     { branch_instruction  , 0                   , 0   , 32,
21345        0xfc1fc000, 0x88044000, &BPOSGE32C        , 0,
21346        DSP_                },        /* BPOSGE32C */
21347     { reserved_block      , 0                   , 0   , 32,
21348        0xfc1fc000, 0x88054000, 0                      , 0,
21349        0x0                 },        /* P.BR3A~*(5) */
21350     { reserved_block      , 0                   , 0   , 32,
21351        0xfc1fc000, 0x88064000, 0                      , 0,
21352        0x0                 },        /* P.BR3A~*(6) */
21353     { reserved_block      , 0                   , 0   , 32,
21354        0xfc1fc000, 0x88074000, 0                      , 0,
21355        0x0                 },        /* P.BR3A~*(7) */
21356     { reserved_block      , 0                   , 0   , 32,
21357        0xfc1fc000, 0x88084000, 0                      , 0,
21358        0x0                 },        /* P.BR3A~*(8) */
21359     { reserved_block      , 0                   , 0   , 32,
21360        0xfc1fc000, 0x88094000, 0                      , 0,
21361        0x0                 },        /* P.BR3A~*(9) */
21362     { reserved_block      , 0                   , 0   , 32,
21363        0xfc1fc000, 0x880a4000, 0                      , 0,
21364        0x0                 },        /* P.BR3A~*(10) */
21365     { reserved_block      , 0                   , 0   , 32,
21366        0xfc1fc000, 0x880b4000, 0                      , 0,
21367        0x0                 },        /* P.BR3A~*(11) */
21368     { reserved_block      , 0                   , 0   , 32,
21369        0xfc1fc000, 0x880c4000, 0                      , 0,
21370        0x0                 },        /* P.BR3A~*(12) */
21371     { reserved_block      , 0                   , 0   , 32,
21372        0xfc1fc000, 0x880d4000, 0                      , 0,
21373        0x0                 },        /* P.BR3A~*(13) */
21374     { reserved_block      , 0                   , 0   , 32,
21375        0xfc1fc000, 0x880e4000, 0                      , 0,
21376        0x0                 },        /* P.BR3A~*(14) */
21377     { reserved_block      , 0                   , 0   , 32,
21378        0xfc1fc000, 0x880f4000, 0                      , 0,
21379        0x0                 },        /* P.BR3A~*(15) */
21380     { reserved_block      , 0                   , 0   , 32,
21381        0xfc1fc000, 0x88104000, 0                      , 0,
21382        0x0                 },        /* P.BR3A~*(16) */
21383     { reserved_block      , 0                   , 0   , 32,
21384        0xfc1fc000, 0x88114000, 0                      , 0,
21385        0x0                 },        /* P.BR3A~*(17) */
21386     { reserved_block      , 0                   , 0   , 32,
21387        0xfc1fc000, 0x88124000, 0                      , 0,
21388        0x0                 },        /* P.BR3A~*(18) */
21389     { reserved_block      , 0                   , 0   , 32,
21390        0xfc1fc000, 0x88134000, 0                      , 0,
21391        0x0                 },        /* P.BR3A~*(19) */
21392     { reserved_block      , 0                   , 0   , 32,
21393        0xfc1fc000, 0x88144000, 0                      , 0,
21394        0x0                 },        /* P.BR3A~*(20) */
21395     { reserved_block      , 0                   , 0   , 32,
21396        0xfc1fc000, 0x88154000, 0                      , 0,
21397        0x0                 },        /* P.BR3A~*(21) */
21398     { reserved_block      , 0                   , 0   , 32,
21399        0xfc1fc000, 0x88164000, 0                      , 0,
21400        0x0                 },        /* P.BR3A~*(22) */
21401     { reserved_block      , 0                   , 0   , 32,
21402        0xfc1fc000, 0x88174000, 0                      , 0,
21403        0x0                 },        /* P.BR3A~*(23) */
21404     { reserved_block      , 0                   , 0   , 32,
21405        0xfc1fc000, 0x88184000, 0                      , 0,
21406        0x0                 },        /* P.BR3A~*(24) */
21407     { reserved_block      , 0                   , 0   , 32,
21408        0xfc1fc000, 0x88194000, 0                      , 0,
21409        0x0                 },        /* P.BR3A~*(25) */
21410     { reserved_block      , 0                   , 0   , 32,
21411        0xfc1fc000, 0x881a4000, 0                      , 0,
21412        0x0                 },        /* P.BR3A~*(26) */
21413     { reserved_block      , 0                   , 0   , 32,
21414        0xfc1fc000, 0x881b4000, 0                      , 0,
21415        0x0                 },        /* P.BR3A~*(27) */
21416     { reserved_block      , 0                   , 0   , 32,
21417        0xfc1fc000, 0x881c4000, 0                      , 0,
21418        0x0                 },        /* P.BR3A~*(28) */
21419     { reserved_block      , 0                   , 0   , 32,
21420        0xfc1fc000, 0x881d4000, 0                      , 0,
21421        0x0                 },        /* P.BR3A~*(29) */
21422     { reserved_block      , 0                   , 0   , 32,
21423        0xfc1fc000, 0x881e4000, 0                      , 0,
21424        0x0                 },        /* P.BR3A~*(30) */
21425     { reserved_block      , 0                   , 0   , 32,
21426        0xfc1fc000, 0x881f4000, 0                      , 0,
21427        0x0                 },        /* P.BR3A~*(31) */
21428 };
21429 
21430 
21431 static const Pool P_BR1[4] = {
21432     { branch_instruction  , 0                   , 0   , 32,
21433        0xfc00c000, 0x88000000, &BEQC_32_         , 0,
21434        0x0                 },        /* BEQC[32] */
21435     { pool                , P_BR3A              , 32  , 32,
21436        0xfc00c000, 0x88004000, 0                      , 0,
21437        0x0                 },        /* P.BR3A */
21438     { branch_instruction  , 0                   , 0   , 32,
21439        0xfc00c000, 0x88008000, &BGEC             , 0,
21440        0x0                 },        /* BGEC */
21441     { branch_instruction  , 0                   , 0   , 32,
21442        0xfc00c000, 0x8800c000, &BGEUC            , 0,
21443        0x0                 },        /* BGEUC */
21444 };
21445 
21446 
21447 static const Pool P_BR2[4] = {
21448     { branch_instruction  , 0                   , 0   , 32,
21449        0xfc00c000, 0xa8000000, &BNEC_32_         , 0,
21450        0x0                 },        /* BNEC[32] */
21451     { reserved_block      , 0                   , 0   , 32,
21452        0xfc00c000, 0xa8004000, 0                      , 0,
21453        0x0                 },        /* P.BR2~*(1) */
21454     { branch_instruction  , 0                   , 0   , 32,
21455        0xfc00c000, 0xa8008000, &BLTC             , 0,
21456        0x0                 },        /* BLTC */
21457     { branch_instruction  , 0                   , 0   , 32,
21458        0xfc00c000, 0xa800c000, &BLTUC            , 0,
21459        0x0                 },        /* BLTUC */
21460 };
21461 
21462 
21463 static const Pool P_BRI[8] = {
21464     { branch_instruction  , 0                   , 0   , 32,
21465        0xfc1c0000, 0xc8000000, &BEQIC            , 0,
21466        0x0                 },        /* BEQIC */
21467     { branch_instruction  , 0                   , 0   , 32,
21468        0xfc1c0000, 0xc8040000, &BBEQZC           , 0,
21469        XMMS_               },        /* BBEQZC */
21470     { branch_instruction  , 0                   , 0   , 32,
21471        0xfc1c0000, 0xc8080000, &BGEIC            , 0,
21472        0x0                 },        /* BGEIC */
21473     { branch_instruction  , 0                   , 0   , 32,
21474        0xfc1c0000, 0xc80c0000, &BGEIUC           , 0,
21475        0x0                 },        /* BGEIUC */
21476     { branch_instruction  , 0                   , 0   , 32,
21477        0xfc1c0000, 0xc8100000, &BNEIC            , 0,
21478        0x0                 },        /* BNEIC */
21479     { branch_instruction  , 0                   , 0   , 32,
21480        0xfc1c0000, 0xc8140000, &BBNEZC           , 0,
21481        XMMS_               },        /* BBNEZC */
21482     { branch_instruction  , 0                   , 0   , 32,
21483        0xfc1c0000, 0xc8180000, &BLTIC            , 0,
21484        0x0                 },        /* BLTIC */
21485     { branch_instruction  , 0                   , 0   , 32,
21486        0xfc1c0000, 0xc81c0000, &BLTIUC           , 0,
21487        0x0                 },        /* BLTIUC */
21488 };
21489 
21490 
21491 static const Pool P32[32] = {
21492     { pool                , P_ADDIU             , 2   , 32,
21493        0xfc000000, 0x00000000, 0                      , 0,
21494        0x0                 },        /* P.ADDIU */
21495     { pool                , P32A                , 8   , 32,
21496        0xfc000000, 0x20000000, 0                      , 0,
21497        0x0                 },        /* P32A */
21498     { pool                , P_GP_W              , 4   , 32,
21499        0xfc000000, 0x40000000, 0                      , 0,
21500        0x0                 },        /* P.GP.W */
21501     { pool                , POOL48I             , 32  , 48,
21502        0xfc0000000000ull, 0x600000000000ull, 0                      , 0,
21503        0x0                 },        /* POOL48I */
21504     { pool                , P_U12               , 16  , 32,
21505        0xfc000000, 0x80000000, 0                      , 0,
21506        0x0                 },        /* P.U12 */
21507     { pool                , POOL32F             , 8   , 32,
21508        0xfc000000, 0xa0000000, 0                      , 0,
21509        CP1_                },        /* POOL32F */
21510     { pool                , POOL32S             , 8   , 32,
21511        0xfc000000, 0xc0000000, 0                      , 0,
21512        0x0                 },        /* POOL32S */
21513     { pool                , P_LUI               , 2   , 32,
21514        0xfc000000, 0xe0000000, 0                      , 0,
21515        0x0                 },        /* P.LUI */
21516     { instruction         , 0                   , 0   , 32,
21517        0xfc000000, 0x04000000, &ADDIUPC_32_      , 0,
21518        0x0                 },        /* ADDIUPC[32] */
21519     { reserved_block      , 0                   , 0   , 32,
21520        0xfc000000, 0x24000000, 0                      , 0,
21521        0x0                 },        /* P32~*(5) */
21522     { pool                , P_GP_BH             , 8   , 32,
21523        0xfc000000, 0x44000000, 0                      , 0,
21524        0x0                 },        /* P.GP.BH */
21525     { reserved_block      , 0                   , 0   , 32,
21526        0xfc000000, 0x64000000, 0                      , 0,
21527        0x0                 },        /* P32~*(13) */
21528     { pool                , P_LS_U12            , 16  , 32,
21529        0xfc000000, 0x84000000, 0                      , 0,
21530        0x0                 },        /* P.LS.U12 */
21531     { pool                , P_LS_S9             , 8   , 32,
21532        0xfc000000, 0xa4000000, 0                      , 0,
21533        0x0                 },        /* P.LS.S9 */
21534     { reserved_block      , 0                   , 0   , 32,
21535        0xfc000000, 0xc4000000, 0                      , 0,
21536        0x0                 },        /* P32~*(25) */
21537     { reserved_block      , 0                   , 0   , 32,
21538        0xfc000000, 0xe4000000, 0                      , 0,
21539        0x0                 },        /* P32~*(29) */
21540     { call_instruction    , 0                   , 0   , 32,
21541        0xfc000000, 0x08000000, &MOVE_BALC        , 0,
21542        XMMS_               },        /* MOVE.BALC */
21543     { pool                , P_BAL               , 2   , 32,
21544        0xfc000000, 0x28000000, 0                      , 0,
21545        0x0                 },        /* P.BAL */
21546     { pool                , P_J                 , 16  , 32,
21547        0xfc000000, 0x48000000, 0                      , 0,
21548        0x0                 },        /* P.J */
21549     { reserved_block      , 0                   , 0   , 32,
21550        0xfc000000, 0x68000000, 0                      , 0,
21551        0x0                 },        /* P32~*(14) */
21552     { pool                , P_BR1               , 4   , 32,
21553        0xfc000000, 0x88000000, 0                      , 0,
21554        0x0                 },        /* P.BR1 */
21555     { pool                , P_BR2               , 4   , 32,
21556        0xfc000000, 0xa8000000, 0                      , 0,
21557        0x0                 },        /* P.BR2 */
21558     { pool                , P_BRI               , 8   , 32,
21559        0xfc000000, 0xc8000000, 0                      , 0,
21560        0x0                 },        /* P.BRI */
21561     { reserved_block      , 0                   , 0   , 32,
21562        0xfc000000, 0xe8000000, 0                      , 0,
21563        0x0                 },        /* P32~*(30) */
21564     { reserved_block      , 0                   , 0   , 32,
21565        0xfc000000, 0x0c000000, 0                      , 0,
21566        0x0                 },        /* P32~*(3) */
21567     { reserved_block      , 0                   , 0   , 32,
21568        0xfc000000, 0x2c000000, 0                      , 0,
21569        0x0                 },        /* P32~*(7) */
21570     { reserved_block      , 0                   , 0   , 32,
21571        0xfc000000, 0x4c000000, 0                      , 0,
21572        0x0                 },        /* P32~*(11) */
21573     { reserved_block      , 0                   , 0   , 32,
21574        0xfc000000, 0x6c000000, 0                      , 0,
21575        0x0                 },        /* P32~*(15) */
21576     { reserved_block      , 0                   , 0   , 32,
21577        0xfc000000, 0x8c000000, 0                      , 0,
21578        0x0                 },        /* P32~*(19) */
21579     { reserved_block      , 0                   , 0   , 32,
21580        0xfc000000, 0xac000000, 0                      , 0,
21581        0x0                 },        /* P32~*(23) */
21582     { reserved_block      , 0                   , 0   , 32,
21583        0xfc000000, 0xcc000000, 0                      , 0,
21584        0x0                 },        /* P32~*(27) */
21585     { reserved_block      , 0                   , 0   , 32,
21586        0xfc000000, 0xec000000, 0                      , 0,
21587        0x0                 },        /* P32~*(31) */
21588 };
21589 
21590 
21591 static const Pool P16_SYSCALL[2] = {
21592     { instruction         , 0                   , 0   , 16,
21593        0xfffc    , 0x1008    , &SYSCALL_16_      , 0,
21594        0x0                 },        /* SYSCALL[16] */
21595     { instruction         , 0                   , 0   , 16,
21596        0xfffc    , 0x100c    , &HYPCALL_16_      , 0,
21597        CP0_ | VZ_          },        /* HYPCALL[16] */
21598 };
21599 
21600 
21601 static const Pool P16_RI[4] = {
21602     { reserved_block      , 0                   , 0   , 16,
21603        0xfff8    , 0x1000    , 0                      , 0,
21604        0x0                 },        /* P16.RI~*(0) */
21605     { pool                , P16_SYSCALL         , 2   , 16,
21606        0xfff8    , 0x1008    , 0                      , 0,
21607        0x0                 },        /* P16.SYSCALL */
21608     { instruction         , 0                   , 0   , 16,
21609        0xfff8    , 0x1010    , &BREAK_16_        , 0,
21610        0x0                 },        /* BREAK[16] */
21611     { instruction         , 0                   , 0   , 16,
21612        0xfff8    , 0x1018    , &SDBBP_16_        , 0,
21613        EJTAG_              },        /* SDBBP[16] */
21614 };
21615 
21616 
21617 static const Pool P16_MV[2] = {
21618     { pool                , P16_RI              , 4   , 16,
21619        0xffe0    , 0x1000    , 0                      , 0,
21620        0x0                 },        /* P16.RI */
21621     { instruction         , 0                   , 0   , 16,
21622        0xfc00    , 0x1000    , &MOVE             , &MOVE_cond        ,
21623        0x0                 },        /* MOVE */
21624 };
21625 
21626 
21627 static const Pool P16_SHIFT[2] = {
21628     { instruction         , 0                   , 0   , 16,
21629        0xfc08    , 0x3000    , &SLL_16_          , 0,
21630        0x0                 },        /* SLL[16] */
21631     { instruction         , 0                   , 0   , 16,
21632        0xfc08    , 0x3008    , &SRL_16_          , 0,
21633        0x0                 },        /* SRL[16] */
21634 };
21635 
21636 
21637 static const Pool POOL16C_00[4] = {
21638     { instruction         , 0                   , 0   , 16,
21639        0xfc0f    , 0x5000    , &NOT_16_          , 0,
21640        0x0                 },        /* NOT[16] */
21641     { instruction         , 0                   , 0   , 16,
21642        0xfc0f    , 0x5004    , &XOR_16_          , 0,
21643        0x0                 },        /* XOR[16] */
21644     { instruction         , 0                   , 0   , 16,
21645        0xfc0f    , 0x5008    , &AND_16_          , 0,
21646        0x0                 },        /* AND[16] */
21647     { instruction         , 0                   , 0   , 16,
21648        0xfc0f    , 0x500c    , &OR_16_           , 0,
21649        0x0                 },        /* OR[16] */
21650 };
21651 
21652 
21653 static const Pool POOL16C_0[2] = {
21654     { pool                , POOL16C_00          , 4   , 16,
21655        0xfc03    , 0x5000    , 0                      , 0,
21656        0x0                 },        /* POOL16C_00 */
21657     { reserved_block      , 0                   , 0   , 16,
21658        0xfc03    , 0x5002    , 0                      , 0,
21659        0x0                 },        /* POOL16C_0~*(1) */
21660 };
21661 
21662 
21663 static const Pool P16C[2] = {
21664     { pool                , POOL16C_0           , 2   , 16,
21665        0xfc01    , 0x5000    , 0                      , 0,
21666        0x0                 },        /* POOL16C_0 */
21667     { instruction         , 0                   , 0   , 16,
21668        0xfc01    , 0x5001    , &LWXS_16_         , 0,
21669        0x0                 },        /* LWXS[16] */
21670 };
21671 
21672 
21673 static const Pool P16_A1[2] = {
21674     { reserved_block      , 0                   , 0   , 16,
21675        0xfc40    , 0x7000    , 0                      , 0,
21676        0x0                 },        /* P16.A1~*(0) */
21677     { instruction         , 0                   , 0   , 16,
21678        0xfc40    , 0x7040    , &ADDIU_R1_SP_     , 0,
21679        0x0                 },        /* ADDIU[R1.SP] */
21680 };
21681 
21682 
21683 static const Pool P_ADDIU_RS5_[2] = {
21684     { instruction         , 0                   , 0   , 16,
21685        0xffe8    , 0x9008    , &NOP_16_          , 0,
21686        0x0                 },        /* NOP[16] */
21687     { instruction         , 0                   , 0   , 16,
21688        0xfc08    , 0x9008    , &ADDIU_RS5_       , &ADDIU_RS5__cond  ,
21689        0x0                 },        /* ADDIU[RS5] */
21690 };
21691 
21692 
21693 static const Pool P16_A2[2] = {
21694     { instruction         , 0                   , 0   , 16,
21695        0xfc08    , 0x9000    , &ADDIU_R2_        , 0,
21696        0x0                 },        /* ADDIU[R2] */
21697     { pool                , P_ADDIU_RS5_        , 2   , 16,
21698        0xfc08    , 0x9008    , 0                      , 0,
21699        0x0                 },        /* P.ADDIU[RS5] */
21700 };
21701 
21702 
21703 static const Pool P16_ADDU[2] = {
21704     { instruction         , 0                   , 0   , 16,
21705        0xfc01    , 0xb000    , &ADDU_16_         , 0,
21706        0x0                 },        /* ADDU[16] */
21707     { instruction         , 0                   , 0   , 16,
21708        0xfc01    , 0xb001    , &SUBU_16_         , 0,
21709        0x0                 },        /* SUBU[16] */
21710 };
21711 
21712 
21713 static const Pool P16_JRC[2] = {
21714     { branch_instruction  , 0                   , 0   , 16,
21715        0xfc1f    , 0xd800    , &JRC              , 0,
21716        0x0                 },        /* JRC */
21717     { call_instruction    , 0                   , 0   , 16,
21718        0xfc1f    , 0xd810    , &JALRC_16_        , 0,
21719        0x0                 },        /* JALRC[16] */
21720 };
21721 
21722 
21723 static const Pool P16_BR1[2] = {
21724     { branch_instruction  , 0                   , 0   , 16,
21725        0xfc00    , 0xd800    , &BEQC_16_         , &BEQC_16__cond    ,
21726        XMMS_               },        /* BEQC[16] */
21727     { branch_instruction  , 0                   , 0   , 16,
21728        0xfc00    , 0xd800    , &BNEC_16_         , &BNEC_16__cond    ,
21729        XMMS_               },        /* BNEC[16] */
21730 };
21731 
21732 
21733 static const Pool P16_BR[2] = {
21734     { pool                , P16_JRC             , 2   , 16,
21735        0xfc0f    , 0xd800    , 0                      , 0,
21736        0x0                 },        /* P16.JRC */
21737     { pool                , P16_BR1             , 2   , 16,
21738        0xfc00    , 0xd800    , 0                      , &P16_BR1_cond     ,
21739        0x0                 },        /* P16.BR1 */
21740 };
21741 
21742 
21743 static const Pool P16_SR[2] = {
21744     { instruction         , 0                   , 0   , 16,
21745        0xfd00    , 0x1c00    , &SAVE_16_         , 0,
21746        0x0                 },        /* SAVE[16] */
21747     { return_instruction  , 0                   , 0   , 16,
21748        0xfd00    , 0x1d00    , &RESTORE_JRC_16_  , 0,
21749        0x0                 },        /* RESTORE.JRC[16] */
21750 };
21751 
21752 
21753 static const Pool P16_4X4[4] = {
21754     { instruction         , 0                   , 0   , 16,
21755        0xfd08    , 0x3c00    , &ADDU_4X4_        , 0,
21756        XMMS_               },        /* ADDU[4X4] */
21757     { instruction         , 0                   , 0   , 16,
21758        0xfd08    , 0x3c08    , &MUL_4X4_         , 0,
21759        XMMS_               },        /* MUL[4X4] */
21760     { reserved_block      , 0                   , 0   , 16,
21761        0xfd08    , 0x3d00    , 0                      , 0,
21762        0x0                 },        /* P16.4X4~*(2) */
21763     { reserved_block      , 0                   , 0   , 16,
21764        0xfd08    , 0x3d08    , 0                      , 0,
21765        0x0                 },        /* P16.4X4~*(3) */
21766 };
21767 
21768 
21769 static const Pool P16_LB[4] = {
21770     { instruction         , 0                   , 0   , 16,
21771        0xfc0c    , 0x5c00    , &LB_16_           , 0,
21772        0x0                 },        /* LB[16] */
21773     { instruction         , 0                   , 0   , 16,
21774        0xfc0c    , 0x5c04    , &SB_16_           , 0,
21775        0x0                 },        /* SB[16] */
21776     { instruction         , 0                   , 0   , 16,
21777        0xfc0c    , 0x5c08    , &LBU_16_          , 0,
21778        0x0                 },        /* LBU[16] */
21779     { reserved_block      , 0                   , 0   , 16,
21780        0xfc0c    , 0x5c0c    , 0                      , 0,
21781        0x0                 },        /* P16.LB~*(3) */
21782 };
21783 
21784 
21785 static const Pool P16_LH[4] = {
21786     { instruction         , 0                   , 0   , 16,
21787        0xfc09    , 0x7c00    , &LH_16_           , 0,
21788        0x0                 },        /* LH[16] */
21789     { instruction         , 0                   , 0   , 16,
21790        0xfc09    , 0x7c01    , &SH_16_           , 0,
21791        0x0                 },        /* SH[16] */
21792     { instruction         , 0                   , 0   , 16,
21793        0xfc09    , 0x7c08    , &LHU_16_          , 0,
21794        0x0                 },        /* LHU[16] */
21795     { reserved_block      , 0                   , 0   , 16,
21796        0xfc09    , 0x7c09    , 0                      , 0,
21797        0x0                 },        /* P16.LH~*(3) */
21798 };
21799 
21800 
21801 static const Pool P16[32] = {
21802     { pool                , P16_MV              , 2   , 16,
21803        0xfc00    , 0x1000    , 0                      , 0,
21804        0x0                 },        /* P16.MV */
21805     { pool                , P16_SHIFT           , 2   , 16,
21806        0xfc00    , 0x3000    , 0                      , 0,
21807        0x0                 },        /* P16.SHIFT */
21808     { pool                , P16C                , 2   , 16,
21809        0xfc00    , 0x5000    , 0                      , 0,
21810        0x0                 },        /* P16C */
21811     { pool                , P16_A1              , 2   , 16,
21812        0xfc00    , 0x7000    , 0                      , 0,
21813        0x0                 },        /* P16.A1 */
21814     { pool                , P16_A2              , 2   , 16,
21815        0xfc00    , 0x9000    , 0                      , 0,
21816        0x0                 },        /* P16.A2 */
21817     { pool                , P16_ADDU            , 2   , 16,
21818        0xfc00    , 0xb000    , 0                      , 0,
21819        0x0                 },        /* P16.ADDU */
21820     { instruction         , 0                   , 0   , 16,
21821        0xfc00    , 0xd000    , &LI_16_           , 0,
21822        0x0                 },        /* LI[16] */
21823     { instruction         , 0                   , 0   , 16,
21824        0xfc00    , 0xf000    , &ANDI_16_         , 0,
21825        0x0                 },        /* ANDI[16] */
21826     { instruction         , 0                   , 0   , 16,
21827        0xfc00    , 0x1400    , &LW_16_           , 0,
21828        0x0                 },        /* LW[16] */
21829     { instruction         , 0                   , 0   , 16,
21830        0xfc00    , 0x3400    , &LW_SP_           , 0,
21831        0x0                 },        /* LW[SP] */
21832     { instruction         , 0                   , 0   , 16,
21833        0xfc00    , 0x5400    , &LW_GP16_         , 0,
21834        0x0                 },        /* LW[GP16] */
21835     { instruction         , 0                   , 0   , 16,
21836        0xfc00    , 0x7400    , &LW_4X4_          , 0,
21837        XMMS_               },        /* LW[4X4] */
21838     { instruction         , 0                   , 0   , 16,
21839        0xfc00    , 0x9400    , &SW_16_           , 0,
21840        0x0                 },        /* SW[16] */
21841     { instruction         , 0                   , 0   , 16,
21842        0xfc00    , 0xb400    , &SW_SP_           , 0,
21843        0x0                 },        /* SW[SP] */
21844     { instruction         , 0                   , 0   , 16,
21845        0xfc00    , 0xd400    , &SW_GP16_         , 0,
21846        0x0                 },        /* SW[GP16] */
21847     { instruction         , 0                   , 0   , 16,
21848        0xfc00    , 0xf400    , &SW_4X4_          , 0,
21849        XMMS_               },        /* SW[4X4] */
21850     { branch_instruction  , 0                   , 0   , 16,
21851        0xfc00    , 0x1800    , &BC_16_           , 0,
21852        0x0                 },        /* BC[16] */
21853     { call_instruction    , 0                   , 0   , 16,
21854        0xfc00    , 0x3800    , &BALC_16_         , 0,
21855        0x0                 },        /* BALC[16] */
21856     { reserved_block      , 0                   , 0   , 16,
21857        0xfc00    , 0x5800    , 0                      , 0,
21858        0x0                 },        /* P16~*(10) */
21859     { reserved_block      , 0                   , 0   , 16,
21860        0xfc00    , 0x7800    , 0                      , 0,
21861        0x0                 },        /* P16~*(14) */
21862     { branch_instruction  , 0                   , 0   , 16,
21863        0xfc00    , 0x9800    , &BEQZC_16_        , 0,
21864        0x0                 },        /* BEQZC[16] */
21865     { branch_instruction  , 0                   , 0   , 16,
21866        0xfc00    , 0xb800    , &BNEZC_16_        , 0,
21867        0x0                 },        /* BNEZC[16] */
21868     { pool                , P16_BR              , 2   , 16,
21869        0xfc00    , 0xd800    , 0                      , 0,
21870        0x0                 },        /* P16.BR */
21871     { reserved_block      , 0                   , 0   , 16,
21872        0xfc00    , 0xf800    , 0                      , 0,
21873        0x0                 },        /* P16~*(30) */
21874     { pool                , P16_SR              , 2   , 16,
21875        0xfc00    , 0x1c00    , 0                      , 0,
21876        0x0                 },        /* P16.SR */
21877     { pool                , P16_4X4             , 4   , 16,
21878        0xfc00    , 0x3c00    , 0                      , 0,
21879        0x0                 },        /* P16.4X4 */
21880     { pool                , P16_LB              , 4   , 16,
21881        0xfc00    , 0x5c00    , 0                      , 0,
21882        0x0                 },        /* P16.LB */
21883     { pool                , P16_LH              , 4   , 16,
21884        0xfc00    , 0x7c00    , 0                      , 0,
21885        0x0                 },        /* P16.LH */
21886     { reserved_block      , 0                   , 0   , 16,
21887        0xfc00    , 0x9c00    , 0                      , 0,
21888        0x0                 },        /* P16~*(19) */
21889     { instruction         , 0                   , 0   , 16,
21890        0xfc00    , 0xbc00    , &MOVEP            , 0,
21891        XMMS_               },        /* MOVEP */
21892     { reserved_block      , 0                   , 0   , 16,
21893        0xfc00    , 0xdc00    , 0                      , 0,
21894        0x0                 },        /* P16~*(27) */
21895     { instruction         , 0                   , 0   , 16,
21896        0xfc00    , 0xfc00    , &MOVEP_REV_       , 0,
21897        XMMS_               },        /* MOVEP[REV] */
21898 };
21899 
21900 
21901 static const Pool MAJOR[2] = {
21902     { pool                , P32                 , 32  , 32,
21903        0x10000000, 0x00000000, 0                      , 0,
21904        0x0                 },        /* P32 */
21905     { pool                , P16                 , 32  , 16,
21906        0x1000    , 0x1000    , 0                      , 0,
21907        0x0                 },        /* P16 */
21908 };
21909 
21910 static bool nanomips_dis(const uint16_t *data, char **buf, Dis_info *info)
21911 {
21912     TABLE_ENTRY_TYPE type;
21913 
21914     /* Handle runtime errors. */
21915     if (unlikely(sigsetjmp(info->buf, 0) != 0)) {
21916         return false;
21917     }
21918     return Disassemble(data, buf, &type, MAJOR, ARRAY_SIZE(MAJOR), info) >= 0;
21919 }
21920 
21921 static bool read_u16(uint16_t *ret, bfd_vma memaddr,
21922                      struct disassemble_info *info)
21923 {
21924     int status = (*info->read_memory_func)(memaddr, (bfd_byte *)ret, 2, info);
21925     if (status != 0) {
21926         (*info->memory_error_func)(status, memaddr, info);
21927         return false;
21928     }
21929 
21930     if ((info->endian == BFD_ENDIAN_BIG) != HOST_BIG_ENDIAN) {
21931         bswap16s(ret);
21932     }
21933     return true;
21934 }
21935 
21936 int print_insn_nanomips(bfd_vma memaddr, struct disassemble_info *info)
21937 {
21938     int length;
21939     uint16_t words[3] = { };
21940     g_autofree char *buf = NULL;
21941 
21942     info->bytes_per_chunk = 2;
21943     info->display_endian = info->endian;
21944     info->insn_info_valid = 1;
21945     info->branch_delay_insns = 0;
21946     info->data_size = 0;
21947     info->insn_type = dis_nonbranch;
21948     info->target = 0;
21949     info->target2 = 0;
21950 
21951     Dis_info disassm_info;
21952     disassm_info.m_pc = memaddr;
21953     disassm_info.fprintf_func = info->fprintf_func;
21954     disassm_info.stream = info->stream;
21955 
21956     if (!read_u16(&words[0], memaddr, info)) {
21957         return -1;
21958     }
21959     length = 2;
21960 
21961     /* Handle 32-bit opcodes.  */
21962     if ((words[0] & 0x1000) == 0) {
21963         if (!read_u16(&words[1], memaddr + 2, info)) {
21964             return -1;
21965         }
21966         length = 4;
21967 
21968         /* Handle 48-bit opcodes.  */
21969         if ((words[0] >> 10) == 0x18) {
21970             if (!read_u16(&words[1], memaddr + 4, info)) {
21971                 return -1;
21972             }
21973             length = 6;
21974         }
21975     }
21976 
21977     for (int i = 0; i < ARRAY_SIZE(words); i++) {
21978         if (i * 2 < length) {
21979             (*info->fprintf_func)(info->stream, "%04x ", words[i]);
21980         } else {
21981             (*info->fprintf_func)(info->stream, "     ");
21982         }
21983     }
21984 
21985     if (nanomips_dis(words, &buf, &disassm_info)) {
21986         (*info->fprintf_func) (info->stream, "%s", buf);
21987     }
21988 
21989     return length;
21990 }
21991