1 /* 2 * QEMU RISC-V Disassembler 3 * 4 * Copyright (c) 2016-2017 Michael Clark <michaeljclark@mac.com> 5 * Copyright (c) 2017-2018 SiFive, Inc. 6 * 7 * This program is free software; you can redistribute it and/or modify it 8 * under the terms and conditions of the GNU General Public License, 9 * version 2 or later, as published by the Free Software Foundation. 10 * 11 * This program is distributed in the hope it will be useful, but WITHOUT 12 * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or 13 * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for 14 * more details. 15 * 16 * You should have received a copy of the GNU General Public License along with 17 * this program. If not, see <http://www.gnu.org/licenses/>. 18 */ 19 20 #include "qemu/osdep.h" 21 #include "qemu/bitops.h" 22 #include "disas/dis-asm.h" 23 #include "target/riscv/cpu_cfg.h" 24 #include "disas/riscv.h" 25 26 /* Vendor extensions */ 27 #include "disas/riscv-xthead.h" 28 #include "disas/riscv-xventana.h" 29 30 typedef enum { 31 /* 0 is reserved for rv_op_illegal. */ 32 rv_op_lui = 1, 33 rv_op_auipc = 2, 34 rv_op_jal = 3, 35 rv_op_jalr = 4, 36 rv_op_beq = 5, 37 rv_op_bne = 6, 38 rv_op_blt = 7, 39 rv_op_bge = 8, 40 rv_op_bltu = 9, 41 rv_op_bgeu = 10, 42 rv_op_lb = 11, 43 rv_op_lh = 12, 44 rv_op_lw = 13, 45 rv_op_lbu = 14, 46 rv_op_lhu = 15, 47 rv_op_sb = 16, 48 rv_op_sh = 17, 49 rv_op_sw = 18, 50 rv_op_addi = 19, 51 rv_op_slti = 20, 52 rv_op_sltiu = 21, 53 rv_op_xori = 22, 54 rv_op_ori = 23, 55 rv_op_andi = 24, 56 rv_op_slli = 25, 57 rv_op_srli = 26, 58 rv_op_srai = 27, 59 rv_op_add = 28, 60 rv_op_sub = 29, 61 rv_op_sll = 30, 62 rv_op_slt = 31, 63 rv_op_sltu = 32, 64 rv_op_xor = 33, 65 rv_op_srl = 34, 66 rv_op_sra = 35, 67 rv_op_or = 36, 68 rv_op_and = 37, 69 rv_op_fence = 38, 70 rv_op_fence_i = 39, 71 rv_op_lwu = 40, 72 rv_op_ld = 41, 73 rv_op_sd = 42, 74 rv_op_addiw = 43, 75 rv_op_slliw = 44, 76 rv_op_srliw = 45, 77 rv_op_sraiw = 46, 78 rv_op_addw = 47, 79 rv_op_subw = 48, 80 rv_op_sllw = 49, 81 rv_op_srlw = 50, 82 rv_op_sraw = 51, 83 rv_op_ldu = 52, 84 rv_op_lq = 53, 85 rv_op_sq = 54, 86 rv_op_addid = 55, 87 rv_op_sllid = 56, 88 rv_op_srlid = 57, 89 rv_op_sraid = 58, 90 rv_op_addd = 59, 91 rv_op_subd = 60, 92 rv_op_slld = 61, 93 rv_op_srld = 62, 94 rv_op_srad = 63, 95 rv_op_mul = 64, 96 rv_op_mulh = 65, 97 rv_op_mulhsu = 66, 98 rv_op_mulhu = 67, 99 rv_op_div = 68, 100 rv_op_divu = 69, 101 rv_op_rem = 70, 102 rv_op_remu = 71, 103 rv_op_mulw = 72, 104 rv_op_divw = 73, 105 rv_op_divuw = 74, 106 rv_op_remw = 75, 107 rv_op_remuw = 76, 108 rv_op_muld = 77, 109 rv_op_divd = 78, 110 rv_op_divud = 79, 111 rv_op_remd = 80, 112 rv_op_remud = 81, 113 rv_op_lr_w = 82, 114 rv_op_sc_w = 83, 115 rv_op_amoswap_w = 84, 116 rv_op_amoadd_w = 85, 117 rv_op_amoxor_w = 86, 118 rv_op_amoor_w = 87, 119 rv_op_amoand_w = 88, 120 rv_op_amomin_w = 89, 121 rv_op_amomax_w = 90, 122 rv_op_amominu_w = 91, 123 rv_op_amomaxu_w = 92, 124 rv_op_lr_d = 93, 125 rv_op_sc_d = 94, 126 rv_op_amoswap_d = 95, 127 rv_op_amoadd_d = 96, 128 rv_op_amoxor_d = 97, 129 rv_op_amoor_d = 98, 130 rv_op_amoand_d = 99, 131 rv_op_amomin_d = 100, 132 rv_op_amomax_d = 101, 133 rv_op_amominu_d = 102, 134 rv_op_amomaxu_d = 103, 135 rv_op_lr_q = 104, 136 rv_op_sc_q = 105, 137 rv_op_amoswap_q = 106, 138 rv_op_amoadd_q = 107, 139 rv_op_amoxor_q = 108, 140 rv_op_amoor_q = 109, 141 rv_op_amoand_q = 110, 142 rv_op_amomin_q = 111, 143 rv_op_amomax_q = 112, 144 rv_op_amominu_q = 113, 145 rv_op_amomaxu_q = 114, 146 rv_op_ecall = 115, 147 rv_op_ebreak = 116, 148 rv_op_uret = 117, 149 rv_op_sret = 118, 150 rv_op_hret = 119, 151 rv_op_mret = 120, 152 rv_op_dret = 121, 153 rv_op_sfence_vm = 122, 154 rv_op_sfence_vma = 123, 155 rv_op_wfi = 124, 156 rv_op_csrrw = 125, 157 rv_op_csrrs = 126, 158 rv_op_csrrc = 127, 159 rv_op_csrrwi = 128, 160 rv_op_csrrsi = 129, 161 rv_op_csrrci = 130, 162 rv_op_flw = 131, 163 rv_op_fsw = 132, 164 rv_op_fmadd_s = 133, 165 rv_op_fmsub_s = 134, 166 rv_op_fnmsub_s = 135, 167 rv_op_fnmadd_s = 136, 168 rv_op_fadd_s = 137, 169 rv_op_fsub_s = 138, 170 rv_op_fmul_s = 139, 171 rv_op_fdiv_s = 140, 172 rv_op_fsgnj_s = 141, 173 rv_op_fsgnjn_s = 142, 174 rv_op_fsgnjx_s = 143, 175 rv_op_fmin_s = 144, 176 rv_op_fmax_s = 145, 177 rv_op_fsqrt_s = 146, 178 rv_op_fle_s = 147, 179 rv_op_flt_s = 148, 180 rv_op_feq_s = 149, 181 rv_op_fcvt_w_s = 150, 182 rv_op_fcvt_wu_s = 151, 183 rv_op_fcvt_s_w = 152, 184 rv_op_fcvt_s_wu = 153, 185 rv_op_fmv_x_s = 154, 186 rv_op_fclass_s = 155, 187 rv_op_fmv_s_x = 156, 188 rv_op_fcvt_l_s = 157, 189 rv_op_fcvt_lu_s = 158, 190 rv_op_fcvt_s_l = 159, 191 rv_op_fcvt_s_lu = 160, 192 rv_op_fld = 161, 193 rv_op_fsd = 162, 194 rv_op_fmadd_d = 163, 195 rv_op_fmsub_d = 164, 196 rv_op_fnmsub_d = 165, 197 rv_op_fnmadd_d = 166, 198 rv_op_fadd_d = 167, 199 rv_op_fsub_d = 168, 200 rv_op_fmul_d = 169, 201 rv_op_fdiv_d = 170, 202 rv_op_fsgnj_d = 171, 203 rv_op_fsgnjn_d = 172, 204 rv_op_fsgnjx_d = 173, 205 rv_op_fmin_d = 174, 206 rv_op_fmax_d = 175, 207 rv_op_fcvt_s_d = 176, 208 rv_op_fcvt_d_s = 177, 209 rv_op_fsqrt_d = 178, 210 rv_op_fle_d = 179, 211 rv_op_flt_d = 180, 212 rv_op_feq_d = 181, 213 rv_op_fcvt_w_d = 182, 214 rv_op_fcvt_wu_d = 183, 215 rv_op_fcvt_d_w = 184, 216 rv_op_fcvt_d_wu = 185, 217 rv_op_fclass_d = 186, 218 rv_op_fcvt_l_d = 187, 219 rv_op_fcvt_lu_d = 188, 220 rv_op_fmv_x_d = 189, 221 rv_op_fcvt_d_l = 190, 222 rv_op_fcvt_d_lu = 191, 223 rv_op_fmv_d_x = 192, 224 rv_op_flq = 193, 225 rv_op_fsq = 194, 226 rv_op_fmadd_q = 195, 227 rv_op_fmsub_q = 196, 228 rv_op_fnmsub_q = 197, 229 rv_op_fnmadd_q = 198, 230 rv_op_fadd_q = 199, 231 rv_op_fsub_q = 200, 232 rv_op_fmul_q = 201, 233 rv_op_fdiv_q = 202, 234 rv_op_fsgnj_q = 203, 235 rv_op_fsgnjn_q = 204, 236 rv_op_fsgnjx_q = 205, 237 rv_op_fmin_q = 206, 238 rv_op_fmax_q = 207, 239 rv_op_fcvt_s_q = 208, 240 rv_op_fcvt_q_s = 209, 241 rv_op_fcvt_d_q = 210, 242 rv_op_fcvt_q_d = 211, 243 rv_op_fsqrt_q = 212, 244 rv_op_fle_q = 213, 245 rv_op_flt_q = 214, 246 rv_op_feq_q = 215, 247 rv_op_fcvt_w_q = 216, 248 rv_op_fcvt_wu_q = 217, 249 rv_op_fcvt_q_w = 218, 250 rv_op_fcvt_q_wu = 219, 251 rv_op_fclass_q = 220, 252 rv_op_fcvt_l_q = 221, 253 rv_op_fcvt_lu_q = 222, 254 rv_op_fcvt_q_l = 223, 255 rv_op_fcvt_q_lu = 224, 256 rv_op_fmv_x_q = 225, 257 rv_op_fmv_q_x = 226, 258 rv_op_c_addi4spn = 227, 259 rv_op_c_fld = 228, 260 rv_op_c_lw = 229, 261 rv_op_c_flw = 230, 262 rv_op_c_fsd = 231, 263 rv_op_c_sw = 232, 264 rv_op_c_fsw = 233, 265 rv_op_c_nop = 234, 266 rv_op_c_addi = 235, 267 rv_op_c_jal = 236, 268 rv_op_c_li = 237, 269 rv_op_c_addi16sp = 238, 270 rv_op_c_lui = 239, 271 rv_op_c_srli = 240, 272 rv_op_c_srai = 241, 273 rv_op_c_andi = 242, 274 rv_op_c_sub = 243, 275 rv_op_c_xor = 244, 276 rv_op_c_or = 245, 277 rv_op_c_and = 246, 278 rv_op_c_subw = 247, 279 rv_op_c_addw = 248, 280 rv_op_c_j = 249, 281 rv_op_c_beqz = 250, 282 rv_op_c_bnez = 251, 283 rv_op_c_slli = 252, 284 rv_op_c_fldsp = 253, 285 rv_op_c_lwsp = 254, 286 rv_op_c_flwsp = 255, 287 rv_op_c_jr = 256, 288 rv_op_c_mv = 257, 289 rv_op_c_ebreak = 258, 290 rv_op_c_jalr = 259, 291 rv_op_c_add = 260, 292 rv_op_c_fsdsp = 261, 293 rv_op_c_swsp = 262, 294 rv_op_c_fswsp = 263, 295 rv_op_c_ld = 264, 296 rv_op_c_sd = 265, 297 rv_op_c_addiw = 266, 298 rv_op_c_ldsp = 267, 299 rv_op_c_sdsp = 268, 300 rv_op_c_lq = 269, 301 rv_op_c_sq = 270, 302 rv_op_c_lqsp = 271, 303 rv_op_c_sqsp = 272, 304 rv_op_nop = 273, 305 rv_op_mv = 274, 306 rv_op_not = 275, 307 rv_op_neg = 276, 308 rv_op_negw = 277, 309 rv_op_sext_w = 278, 310 rv_op_seqz = 279, 311 rv_op_snez = 280, 312 rv_op_sltz = 281, 313 rv_op_sgtz = 282, 314 rv_op_fmv_s = 283, 315 rv_op_fabs_s = 284, 316 rv_op_fneg_s = 285, 317 rv_op_fmv_d = 286, 318 rv_op_fabs_d = 287, 319 rv_op_fneg_d = 288, 320 rv_op_fmv_q = 289, 321 rv_op_fabs_q = 290, 322 rv_op_fneg_q = 291, 323 rv_op_beqz = 292, 324 rv_op_bnez = 293, 325 rv_op_blez = 294, 326 rv_op_bgez = 295, 327 rv_op_bltz = 296, 328 rv_op_bgtz = 297, 329 rv_op_ble = 298, 330 rv_op_bleu = 299, 331 rv_op_bgt = 300, 332 rv_op_bgtu = 301, 333 rv_op_j = 302, 334 rv_op_ret = 303, 335 rv_op_jr = 304, 336 rv_op_rdcycle = 305, 337 rv_op_rdtime = 306, 338 rv_op_rdinstret = 307, 339 rv_op_rdcycleh = 308, 340 rv_op_rdtimeh = 309, 341 rv_op_rdinstreth = 310, 342 rv_op_frcsr = 311, 343 rv_op_frrm = 312, 344 rv_op_frflags = 313, 345 rv_op_fscsr = 314, 346 rv_op_fsrm = 315, 347 rv_op_fsflags = 316, 348 rv_op_fsrmi = 317, 349 rv_op_fsflagsi = 318, 350 rv_op_bseti = 319, 351 rv_op_bclri = 320, 352 rv_op_binvi = 321, 353 rv_op_bexti = 322, 354 rv_op_rori = 323, 355 rv_op_clz = 324, 356 rv_op_ctz = 325, 357 rv_op_cpop = 326, 358 rv_op_sext_h = 327, 359 rv_op_sext_b = 328, 360 rv_op_xnor = 329, 361 rv_op_orn = 330, 362 rv_op_andn = 331, 363 rv_op_rol = 332, 364 rv_op_ror = 333, 365 rv_op_sh1add = 334, 366 rv_op_sh2add = 335, 367 rv_op_sh3add = 336, 368 rv_op_sh1add_uw = 337, 369 rv_op_sh2add_uw = 338, 370 rv_op_sh3add_uw = 339, 371 rv_op_clmul = 340, 372 rv_op_clmulr = 341, 373 rv_op_clmulh = 342, 374 rv_op_min = 343, 375 rv_op_minu = 344, 376 rv_op_max = 345, 377 rv_op_maxu = 346, 378 rv_op_clzw = 347, 379 rv_op_ctzw = 348, 380 rv_op_cpopw = 349, 381 rv_op_slli_uw = 350, 382 rv_op_add_uw = 351, 383 rv_op_rolw = 352, 384 rv_op_rorw = 353, 385 rv_op_rev8 = 354, 386 rv_op_zext_h = 355, 387 rv_op_roriw = 356, 388 rv_op_orc_b = 357, 389 rv_op_bset = 358, 390 rv_op_bclr = 359, 391 rv_op_binv = 360, 392 rv_op_bext = 361, 393 rv_op_aes32esmi = 362, 394 rv_op_aes32esi = 363, 395 rv_op_aes32dsmi = 364, 396 rv_op_aes32dsi = 365, 397 rv_op_aes64ks1i = 366, 398 rv_op_aes64ks2 = 367, 399 rv_op_aes64im = 368, 400 rv_op_aes64esm = 369, 401 rv_op_aes64es = 370, 402 rv_op_aes64dsm = 371, 403 rv_op_aes64ds = 372, 404 rv_op_sha256sig0 = 373, 405 rv_op_sha256sig1 = 374, 406 rv_op_sha256sum0 = 375, 407 rv_op_sha256sum1 = 376, 408 rv_op_sha512sig0 = 377, 409 rv_op_sha512sig1 = 378, 410 rv_op_sha512sum0 = 379, 411 rv_op_sha512sum1 = 380, 412 rv_op_sha512sum0r = 381, 413 rv_op_sha512sum1r = 382, 414 rv_op_sha512sig0l = 383, 415 rv_op_sha512sig0h = 384, 416 rv_op_sha512sig1l = 385, 417 rv_op_sha512sig1h = 386, 418 rv_op_sm3p0 = 387, 419 rv_op_sm3p1 = 388, 420 rv_op_sm4ed = 389, 421 rv_op_sm4ks = 390, 422 rv_op_brev8 = 391, 423 rv_op_pack = 392, 424 rv_op_packh = 393, 425 rv_op_packw = 394, 426 rv_op_unzip = 395, 427 rv_op_zip = 396, 428 rv_op_xperm4 = 397, 429 rv_op_xperm8 = 398, 430 rv_op_vle8_v = 399, 431 rv_op_vle16_v = 400, 432 rv_op_vle32_v = 401, 433 rv_op_vle64_v = 402, 434 rv_op_vse8_v = 403, 435 rv_op_vse16_v = 404, 436 rv_op_vse32_v = 405, 437 rv_op_vse64_v = 406, 438 rv_op_vlm_v = 407, 439 rv_op_vsm_v = 408, 440 rv_op_vlse8_v = 409, 441 rv_op_vlse16_v = 410, 442 rv_op_vlse32_v = 411, 443 rv_op_vlse64_v = 412, 444 rv_op_vsse8_v = 413, 445 rv_op_vsse16_v = 414, 446 rv_op_vsse32_v = 415, 447 rv_op_vsse64_v = 416, 448 rv_op_vluxei8_v = 417, 449 rv_op_vluxei16_v = 418, 450 rv_op_vluxei32_v = 419, 451 rv_op_vluxei64_v = 420, 452 rv_op_vloxei8_v = 421, 453 rv_op_vloxei16_v = 422, 454 rv_op_vloxei32_v = 423, 455 rv_op_vloxei64_v = 424, 456 rv_op_vsuxei8_v = 425, 457 rv_op_vsuxei16_v = 426, 458 rv_op_vsuxei32_v = 427, 459 rv_op_vsuxei64_v = 428, 460 rv_op_vsoxei8_v = 429, 461 rv_op_vsoxei16_v = 430, 462 rv_op_vsoxei32_v = 431, 463 rv_op_vsoxei64_v = 432, 464 rv_op_vle8ff_v = 433, 465 rv_op_vle16ff_v = 434, 466 rv_op_vle32ff_v = 435, 467 rv_op_vle64ff_v = 436, 468 rv_op_vl1re8_v = 437, 469 rv_op_vl1re16_v = 438, 470 rv_op_vl1re32_v = 439, 471 rv_op_vl1re64_v = 440, 472 rv_op_vl2re8_v = 441, 473 rv_op_vl2re16_v = 442, 474 rv_op_vl2re32_v = 443, 475 rv_op_vl2re64_v = 444, 476 rv_op_vl4re8_v = 445, 477 rv_op_vl4re16_v = 446, 478 rv_op_vl4re32_v = 447, 479 rv_op_vl4re64_v = 448, 480 rv_op_vl8re8_v = 449, 481 rv_op_vl8re16_v = 450, 482 rv_op_vl8re32_v = 451, 483 rv_op_vl8re64_v = 452, 484 rv_op_vs1r_v = 453, 485 rv_op_vs2r_v = 454, 486 rv_op_vs4r_v = 455, 487 rv_op_vs8r_v = 456, 488 rv_op_vadd_vv = 457, 489 rv_op_vadd_vx = 458, 490 rv_op_vadd_vi = 459, 491 rv_op_vsub_vv = 460, 492 rv_op_vsub_vx = 461, 493 rv_op_vrsub_vx = 462, 494 rv_op_vrsub_vi = 463, 495 rv_op_vwaddu_vv = 464, 496 rv_op_vwaddu_vx = 465, 497 rv_op_vwadd_vv = 466, 498 rv_op_vwadd_vx = 467, 499 rv_op_vwsubu_vv = 468, 500 rv_op_vwsubu_vx = 469, 501 rv_op_vwsub_vv = 470, 502 rv_op_vwsub_vx = 471, 503 rv_op_vwaddu_wv = 472, 504 rv_op_vwaddu_wx = 473, 505 rv_op_vwadd_wv = 474, 506 rv_op_vwadd_wx = 475, 507 rv_op_vwsubu_wv = 476, 508 rv_op_vwsubu_wx = 477, 509 rv_op_vwsub_wv = 478, 510 rv_op_vwsub_wx = 479, 511 rv_op_vadc_vvm = 480, 512 rv_op_vadc_vxm = 481, 513 rv_op_vadc_vim = 482, 514 rv_op_vmadc_vvm = 483, 515 rv_op_vmadc_vxm = 484, 516 rv_op_vmadc_vim = 485, 517 rv_op_vsbc_vvm = 486, 518 rv_op_vsbc_vxm = 487, 519 rv_op_vmsbc_vvm = 488, 520 rv_op_vmsbc_vxm = 489, 521 rv_op_vand_vv = 490, 522 rv_op_vand_vx = 491, 523 rv_op_vand_vi = 492, 524 rv_op_vor_vv = 493, 525 rv_op_vor_vx = 494, 526 rv_op_vor_vi = 495, 527 rv_op_vxor_vv = 496, 528 rv_op_vxor_vx = 497, 529 rv_op_vxor_vi = 498, 530 rv_op_vsll_vv = 499, 531 rv_op_vsll_vx = 500, 532 rv_op_vsll_vi = 501, 533 rv_op_vsrl_vv = 502, 534 rv_op_vsrl_vx = 503, 535 rv_op_vsrl_vi = 504, 536 rv_op_vsra_vv = 505, 537 rv_op_vsra_vx = 506, 538 rv_op_vsra_vi = 507, 539 rv_op_vnsrl_wv = 508, 540 rv_op_vnsrl_wx = 509, 541 rv_op_vnsrl_wi = 510, 542 rv_op_vnsra_wv = 511, 543 rv_op_vnsra_wx = 512, 544 rv_op_vnsra_wi = 513, 545 rv_op_vmseq_vv = 514, 546 rv_op_vmseq_vx = 515, 547 rv_op_vmseq_vi = 516, 548 rv_op_vmsne_vv = 517, 549 rv_op_vmsne_vx = 518, 550 rv_op_vmsne_vi = 519, 551 rv_op_vmsltu_vv = 520, 552 rv_op_vmsltu_vx = 521, 553 rv_op_vmslt_vv = 522, 554 rv_op_vmslt_vx = 523, 555 rv_op_vmsleu_vv = 524, 556 rv_op_vmsleu_vx = 525, 557 rv_op_vmsleu_vi = 526, 558 rv_op_vmsle_vv = 527, 559 rv_op_vmsle_vx = 528, 560 rv_op_vmsle_vi = 529, 561 rv_op_vmsgtu_vx = 530, 562 rv_op_vmsgtu_vi = 531, 563 rv_op_vmsgt_vx = 532, 564 rv_op_vmsgt_vi = 533, 565 rv_op_vminu_vv = 534, 566 rv_op_vminu_vx = 535, 567 rv_op_vmin_vv = 536, 568 rv_op_vmin_vx = 537, 569 rv_op_vmaxu_vv = 538, 570 rv_op_vmaxu_vx = 539, 571 rv_op_vmax_vv = 540, 572 rv_op_vmax_vx = 541, 573 rv_op_vmul_vv = 542, 574 rv_op_vmul_vx = 543, 575 rv_op_vmulh_vv = 544, 576 rv_op_vmulh_vx = 545, 577 rv_op_vmulhu_vv = 546, 578 rv_op_vmulhu_vx = 547, 579 rv_op_vmulhsu_vv = 548, 580 rv_op_vmulhsu_vx = 549, 581 rv_op_vdivu_vv = 550, 582 rv_op_vdivu_vx = 551, 583 rv_op_vdiv_vv = 552, 584 rv_op_vdiv_vx = 553, 585 rv_op_vremu_vv = 554, 586 rv_op_vremu_vx = 555, 587 rv_op_vrem_vv = 556, 588 rv_op_vrem_vx = 557, 589 rv_op_vwmulu_vv = 558, 590 rv_op_vwmulu_vx = 559, 591 rv_op_vwmulsu_vv = 560, 592 rv_op_vwmulsu_vx = 561, 593 rv_op_vwmul_vv = 562, 594 rv_op_vwmul_vx = 563, 595 rv_op_vmacc_vv = 564, 596 rv_op_vmacc_vx = 565, 597 rv_op_vnmsac_vv = 566, 598 rv_op_vnmsac_vx = 567, 599 rv_op_vmadd_vv = 568, 600 rv_op_vmadd_vx = 569, 601 rv_op_vnmsub_vv = 570, 602 rv_op_vnmsub_vx = 571, 603 rv_op_vwmaccu_vv = 572, 604 rv_op_vwmaccu_vx = 573, 605 rv_op_vwmacc_vv = 574, 606 rv_op_vwmacc_vx = 575, 607 rv_op_vwmaccsu_vv = 576, 608 rv_op_vwmaccsu_vx = 577, 609 rv_op_vwmaccus_vx = 578, 610 rv_op_vmv_v_v = 579, 611 rv_op_vmv_v_x = 580, 612 rv_op_vmv_v_i = 581, 613 rv_op_vmerge_vvm = 582, 614 rv_op_vmerge_vxm = 583, 615 rv_op_vmerge_vim = 584, 616 rv_op_vsaddu_vv = 585, 617 rv_op_vsaddu_vx = 586, 618 rv_op_vsaddu_vi = 587, 619 rv_op_vsadd_vv = 588, 620 rv_op_vsadd_vx = 589, 621 rv_op_vsadd_vi = 590, 622 rv_op_vssubu_vv = 591, 623 rv_op_vssubu_vx = 592, 624 rv_op_vssub_vv = 593, 625 rv_op_vssub_vx = 594, 626 rv_op_vaadd_vv = 595, 627 rv_op_vaadd_vx = 596, 628 rv_op_vaaddu_vv = 597, 629 rv_op_vaaddu_vx = 598, 630 rv_op_vasub_vv = 599, 631 rv_op_vasub_vx = 600, 632 rv_op_vasubu_vv = 601, 633 rv_op_vasubu_vx = 602, 634 rv_op_vsmul_vv = 603, 635 rv_op_vsmul_vx = 604, 636 rv_op_vssrl_vv = 605, 637 rv_op_vssrl_vx = 606, 638 rv_op_vssrl_vi = 607, 639 rv_op_vssra_vv = 608, 640 rv_op_vssra_vx = 609, 641 rv_op_vssra_vi = 610, 642 rv_op_vnclipu_wv = 611, 643 rv_op_vnclipu_wx = 612, 644 rv_op_vnclipu_wi = 613, 645 rv_op_vnclip_wv = 614, 646 rv_op_vnclip_wx = 615, 647 rv_op_vnclip_wi = 616, 648 rv_op_vfadd_vv = 617, 649 rv_op_vfadd_vf = 618, 650 rv_op_vfsub_vv = 619, 651 rv_op_vfsub_vf = 620, 652 rv_op_vfrsub_vf = 621, 653 rv_op_vfwadd_vv = 622, 654 rv_op_vfwadd_vf = 623, 655 rv_op_vfwadd_wv = 624, 656 rv_op_vfwadd_wf = 625, 657 rv_op_vfwsub_vv = 626, 658 rv_op_vfwsub_vf = 627, 659 rv_op_vfwsub_wv = 628, 660 rv_op_vfwsub_wf = 629, 661 rv_op_vfmul_vv = 630, 662 rv_op_vfmul_vf = 631, 663 rv_op_vfdiv_vv = 632, 664 rv_op_vfdiv_vf = 633, 665 rv_op_vfrdiv_vf = 634, 666 rv_op_vfwmul_vv = 635, 667 rv_op_vfwmul_vf = 636, 668 rv_op_vfmacc_vv = 637, 669 rv_op_vfmacc_vf = 638, 670 rv_op_vfnmacc_vv = 639, 671 rv_op_vfnmacc_vf = 640, 672 rv_op_vfmsac_vv = 641, 673 rv_op_vfmsac_vf = 642, 674 rv_op_vfnmsac_vv = 643, 675 rv_op_vfnmsac_vf = 644, 676 rv_op_vfmadd_vv = 645, 677 rv_op_vfmadd_vf = 646, 678 rv_op_vfnmadd_vv = 647, 679 rv_op_vfnmadd_vf = 648, 680 rv_op_vfmsub_vv = 649, 681 rv_op_vfmsub_vf = 650, 682 rv_op_vfnmsub_vv = 651, 683 rv_op_vfnmsub_vf = 652, 684 rv_op_vfwmacc_vv = 653, 685 rv_op_vfwmacc_vf = 654, 686 rv_op_vfwnmacc_vv = 655, 687 rv_op_vfwnmacc_vf = 656, 688 rv_op_vfwmsac_vv = 657, 689 rv_op_vfwmsac_vf = 658, 690 rv_op_vfwnmsac_vv = 659, 691 rv_op_vfwnmsac_vf = 660, 692 rv_op_vfsqrt_v = 661, 693 rv_op_vfrsqrt7_v = 662, 694 rv_op_vfrec7_v = 663, 695 rv_op_vfmin_vv = 664, 696 rv_op_vfmin_vf = 665, 697 rv_op_vfmax_vv = 666, 698 rv_op_vfmax_vf = 667, 699 rv_op_vfsgnj_vv = 668, 700 rv_op_vfsgnj_vf = 669, 701 rv_op_vfsgnjn_vv = 670, 702 rv_op_vfsgnjn_vf = 671, 703 rv_op_vfsgnjx_vv = 672, 704 rv_op_vfsgnjx_vf = 673, 705 rv_op_vfslide1up_vf = 674, 706 rv_op_vfslide1down_vf = 675, 707 rv_op_vmfeq_vv = 676, 708 rv_op_vmfeq_vf = 677, 709 rv_op_vmfne_vv = 678, 710 rv_op_vmfne_vf = 679, 711 rv_op_vmflt_vv = 680, 712 rv_op_vmflt_vf = 681, 713 rv_op_vmfle_vv = 682, 714 rv_op_vmfle_vf = 683, 715 rv_op_vmfgt_vf = 684, 716 rv_op_vmfge_vf = 685, 717 rv_op_vfclass_v = 686, 718 rv_op_vfmerge_vfm = 687, 719 rv_op_vfmv_v_f = 688, 720 rv_op_vfcvt_xu_f_v = 689, 721 rv_op_vfcvt_x_f_v = 690, 722 rv_op_vfcvt_f_xu_v = 691, 723 rv_op_vfcvt_f_x_v = 692, 724 rv_op_vfcvt_rtz_xu_f_v = 693, 725 rv_op_vfcvt_rtz_x_f_v = 694, 726 rv_op_vfwcvt_xu_f_v = 695, 727 rv_op_vfwcvt_x_f_v = 696, 728 rv_op_vfwcvt_f_xu_v = 697, 729 rv_op_vfwcvt_f_x_v = 698, 730 rv_op_vfwcvt_f_f_v = 699, 731 rv_op_vfwcvt_rtz_xu_f_v = 700, 732 rv_op_vfwcvt_rtz_x_f_v = 701, 733 rv_op_vfncvt_xu_f_w = 702, 734 rv_op_vfncvt_x_f_w = 703, 735 rv_op_vfncvt_f_xu_w = 704, 736 rv_op_vfncvt_f_x_w = 705, 737 rv_op_vfncvt_f_f_w = 706, 738 rv_op_vfncvt_rod_f_f_w = 707, 739 rv_op_vfncvt_rtz_xu_f_w = 708, 740 rv_op_vfncvt_rtz_x_f_w = 709, 741 rv_op_vredsum_vs = 710, 742 rv_op_vredand_vs = 711, 743 rv_op_vredor_vs = 712, 744 rv_op_vredxor_vs = 713, 745 rv_op_vredminu_vs = 714, 746 rv_op_vredmin_vs = 715, 747 rv_op_vredmaxu_vs = 716, 748 rv_op_vredmax_vs = 717, 749 rv_op_vwredsumu_vs = 718, 750 rv_op_vwredsum_vs = 719, 751 rv_op_vfredusum_vs = 720, 752 rv_op_vfredosum_vs = 721, 753 rv_op_vfredmin_vs = 722, 754 rv_op_vfredmax_vs = 723, 755 rv_op_vfwredusum_vs = 724, 756 rv_op_vfwredosum_vs = 725, 757 rv_op_vmand_mm = 726, 758 rv_op_vmnand_mm = 727, 759 rv_op_vmandn_mm = 728, 760 rv_op_vmxor_mm = 729, 761 rv_op_vmor_mm = 730, 762 rv_op_vmnor_mm = 731, 763 rv_op_vmorn_mm = 732, 764 rv_op_vmxnor_mm = 733, 765 rv_op_vcpop_m = 734, 766 rv_op_vfirst_m = 735, 767 rv_op_vmsbf_m = 736, 768 rv_op_vmsif_m = 737, 769 rv_op_vmsof_m = 738, 770 rv_op_viota_m = 739, 771 rv_op_vid_v = 740, 772 rv_op_vmv_x_s = 741, 773 rv_op_vmv_s_x = 742, 774 rv_op_vfmv_f_s = 743, 775 rv_op_vfmv_s_f = 744, 776 rv_op_vslideup_vx = 745, 777 rv_op_vslideup_vi = 746, 778 rv_op_vslide1up_vx = 747, 779 rv_op_vslidedown_vx = 748, 780 rv_op_vslidedown_vi = 749, 781 rv_op_vslide1down_vx = 750, 782 rv_op_vrgather_vv = 751, 783 rv_op_vrgatherei16_vv = 752, 784 rv_op_vrgather_vx = 753, 785 rv_op_vrgather_vi = 754, 786 rv_op_vcompress_vm = 755, 787 rv_op_vmv1r_v = 756, 788 rv_op_vmv2r_v = 757, 789 rv_op_vmv4r_v = 758, 790 rv_op_vmv8r_v = 759, 791 rv_op_vzext_vf2 = 760, 792 rv_op_vzext_vf4 = 761, 793 rv_op_vzext_vf8 = 762, 794 rv_op_vsext_vf2 = 763, 795 rv_op_vsext_vf4 = 764, 796 rv_op_vsext_vf8 = 765, 797 rv_op_vsetvli = 766, 798 rv_op_vsetivli = 767, 799 rv_op_vsetvl = 768, 800 rv_op_c_zext_b = 769, 801 rv_op_c_sext_b = 770, 802 rv_op_c_zext_h = 771, 803 rv_op_c_sext_h = 772, 804 rv_op_c_zext_w = 773, 805 rv_op_c_not = 774, 806 rv_op_c_mul = 775, 807 rv_op_c_lbu = 776, 808 rv_op_c_lhu = 777, 809 rv_op_c_lh = 778, 810 rv_op_c_sb = 779, 811 rv_op_c_sh = 780, 812 rv_op_cm_push = 781, 813 rv_op_cm_pop = 782, 814 rv_op_cm_popret = 783, 815 rv_op_cm_popretz = 784, 816 rv_op_cm_mva01s = 785, 817 rv_op_cm_mvsa01 = 786, 818 rv_op_cm_jt = 787, 819 rv_op_cm_jalt = 788, 820 rv_op_czero_eqz = 789, 821 rv_op_czero_nez = 790, 822 rv_op_fcvt_bf16_s = 791, 823 rv_op_fcvt_s_bf16 = 792, 824 rv_op_vfncvtbf16_f_f_w = 793, 825 rv_op_vfwcvtbf16_f_f_v = 794, 826 rv_op_vfwmaccbf16_vv = 795, 827 rv_op_vfwmaccbf16_vf = 796, 828 rv_op_flh = 797, 829 rv_op_fsh = 798, 830 rv_op_fmv_h_x = 799, 831 rv_op_fmv_x_h = 800, 832 rv_op_fli_s = 801, 833 rv_op_fli_d = 802, 834 rv_op_fli_q = 803, 835 rv_op_fli_h = 804, 836 rv_op_fminm_s = 805, 837 rv_op_fmaxm_s = 806, 838 rv_op_fminm_d = 807, 839 rv_op_fmaxm_d = 808, 840 rv_op_fminm_q = 809, 841 rv_op_fmaxm_q = 810, 842 rv_op_fminm_h = 811, 843 rv_op_fmaxm_h = 812, 844 rv_op_fround_s = 813, 845 rv_op_froundnx_s = 814, 846 rv_op_fround_d = 815, 847 rv_op_froundnx_d = 816, 848 rv_op_fround_q = 817, 849 rv_op_froundnx_q = 818, 850 rv_op_fround_h = 819, 851 rv_op_froundnx_h = 820, 852 rv_op_fcvtmod_w_d = 821, 853 rv_op_fmvh_x_d = 822, 854 rv_op_fmvp_d_x = 823, 855 rv_op_fmvh_x_q = 824, 856 rv_op_fmvp_q_x = 825, 857 rv_op_fleq_s = 826, 858 rv_op_fltq_s = 827, 859 rv_op_fleq_d = 828, 860 rv_op_fltq_d = 829, 861 rv_op_fleq_q = 830, 862 rv_op_fltq_q = 831, 863 rv_op_fleq_h = 832, 864 rv_op_fltq_h = 833, 865 rv_op_vaesdf_vv = 834, 866 rv_op_vaesdf_vs = 835, 867 rv_op_vaesdm_vv = 836, 868 rv_op_vaesdm_vs = 837, 869 rv_op_vaesef_vv = 838, 870 rv_op_vaesef_vs = 839, 871 rv_op_vaesem_vv = 840, 872 rv_op_vaesem_vs = 841, 873 rv_op_vaeskf1_vi = 842, 874 rv_op_vaeskf2_vi = 843, 875 rv_op_vaesz_vs = 844, 876 rv_op_vandn_vv = 845, 877 rv_op_vandn_vx = 846, 878 rv_op_vbrev_v = 847, 879 rv_op_vbrev8_v = 848, 880 rv_op_vclmul_vv = 849, 881 rv_op_vclmul_vx = 850, 882 rv_op_vclmulh_vv = 851, 883 rv_op_vclmulh_vx = 852, 884 rv_op_vclz_v = 853, 885 rv_op_vcpop_v = 854, 886 rv_op_vctz_v = 855, 887 rv_op_vghsh_vv = 856, 888 rv_op_vgmul_vv = 857, 889 rv_op_vrev8_v = 858, 890 rv_op_vrol_vv = 859, 891 rv_op_vrol_vx = 860, 892 rv_op_vror_vv = 861, 893 rv_op_vror_vx = 862, 894 rv_op_vror_vi = 863, 895 rv_op_vsha2ch_vv = 864, 896 rv_op_vsha2cl_vv = 865, 897 rv_op_vsha2ms_vv = 866, 898 rv_op_vsm3c_vi = 867, 899 rv_op_vsm3me_vv = 868, 900 rv_op_vsm4k_vi = 869, 901 rv_op_vsm4r_vv = 870, 902 rv_op_vsm4r_vs = 871, 903 rv_op_vwsll_vv = 872, 904 rv_op_vwsll_vx = 873, 905 rv_op_vwsll_vi = 874, 906 } rv_op; 907 908 /* register names */ 909 910 static const char rv_ireg_name_sym[32][5] = { 911 "zero", "ra", "sp", "gp", "tp", "t0", "t1", "t2", 912 "s0", "s1", "a0", "a1", "a2", "a3", "a4", "a5", 913 "a6", "a7", "s2", "s3", "s4", "s5", "s6", "s7", 914 "s8", "s9", "s10", "s11", "t3", "t4", "t5", "t6", 915 }; 916 917 static const char rv_freg_name_sym[32][5] = { 918 "ft0", "ft1", "ft2", "ft3", "ft4", "ft5", "ft6", "ft7", 919 "fs0", "fs1", "fa0", "fa1", "fa2", "fa3", "fa4", "fa5", 920 "fa6", "fa7", "fs2", "fs3", "fs4", "fs5", "fs6", "fs7", 921 "fs8", "fs9", "fs10", "fs11", "ft8", "ft9", "ft10", "ft11", 922 }; 923 924 static const char rv_vreg_name_sym[32][4] = { 925 "v0", "v1", "v2", "v3", "v4", "v5", "v6", "v7", 926 "v8", "v9", "v10", "v11", "v12", "v13", "v14", "v15", 927 "v16", "v17", "v18", "v19", "v20", "v21", "v22", "v23", 928 "v24", "v25", "v26", "v27", "v28", "v29", "v30", "v31" 929 }; 930 931 /* The FLI.[HSDQ] numeric constants (0.0 for symbolic constants). 932 * The constants use the hex floating-point literal representation 933 * that is printed when using the printf %a format specifier, 934 * which matches the output that is generated by the disassembler. 935 */ 936 static const char rv_fli_name_const[32][9] = 937 { 938 "0x1p+0", "min", "0x1p-16", "0x1p-15", 939 "0x1p-8", "0x1p-7", "0x1p-4", "0x1p-3", 940 "0x1p-2", "0x1.4p-2", "0x1.8p-2", "0x1.cp-2", 941 "0x1p-1", "0x1.4p-1", "0x1.8p-1", "0x1.cp-1", 942 "0x1p+0", "0x1.4p+0", "0x1.8p+0", "0x1.cp+0", 943 "0x1p+1", "0x1.4p+1", "0x1.8p+1", "0x1p+2", 944 "0x1p+3", "0x1p+4", "0x1p+7", "0x1p+8", 945 "0x1p+15", "0x1p+16", "inf", "nan" 946 }; 947 948 /* pseudo-instruction constraints */ 949 950 static const rvc_constraint rvcc_jal[] = { rvc_rd_eq_ra, rvc_end }; 951 static const rvc_constraint rvcc_jalr[] = { rvc_rd_eq_ra, rvc_imm_eq_zero, 952 rvc_end }; 953 static const rvc_constraint rvcc_nop[] = { rvc_rd_eq_x0, rvc_rs1_eq_x0, 954 rvc_imm_eq_zero, rvc_end }; 955 static const rvc_constraint rvcc_mv[] = { rvc_imm_eq_zero, rvc_end }; 956 static const rvc_constraint rvcc_not[] = { rvc_imm_eq_n1, rvc_end }; 957 static const rvc_constraint rvcc_neg[] = { rvc_rs1_eq_x0, rvc_end }; 958 static const rvc_constraint rvcc_negw[] = { rvc_rs1_eq_x0, rvc_end }; 959 static const rvc_constraint rvcc_sext_w[] = { rvc_imm_eq_zero, rvc_end }; 960 static const rvc_constraint rvcc_seqz[] = { rvc_imm_eq_p1, rvc_end }; 961 static const rvc_constraint rvcc_snez[] = { rvc_rs1_eq_x0, rvc_end }; 962 static const rvc_constraint rvcc_sltz[] = { rvc_rs2_eq_x0, rvc_end }; 963 static const rvc_constraint rvcc_sgtz[] = { rvc_rs1_eq_x0, rvc_end }; 964 static const rvc_constraint rvcc_fmv_s[] = { rvc_rs2_eq_rs1, rvc_end }; 965 static const rvc_constraint rvcc_fabs_s[] = { rvc_rs2_eq_rs1, rvc_end }; 966 static const rvc_constraint rvcc_fneg_s[] = { rvc_rs2_eq_rs1, rvc_end }; 967 static const rvc_constraint rvcc_fmv_d[] = { rvc_rs2_eq_rs1, rvc_end }; 968 static const rvc_constraint rvcc_fabs_d[] = { rvc_rs2_eq_rs1, rvc_end }; 969 static const rvc_constraint rvcc_fneg_d[] = { rvc_rs2_eq_rs1, rvc_end }; 970 static const rvc_constraint rvcc_fmv_q[] = { rvc_rs2_eq_rs1, rvc_end }; 971 static const rvc_constraint rvcc_fabs_q[] = { rvc_rs2_eq_rs1, rvc_end }; 972 static const rvc_constraint rvcc_fneg_q[] = { rvc_rs2_eq_rs1, rvc_end }; 973 static const rvc_constraint rvcc_beqz[] = { rvc_rs2_eq_x0, rvc_end }; 974 static const rvc_constraint rvcc_bnez[] = { rvc_rs2_eq_x0, rvc_end }; 975 static const rvc_constraint rvcc_blez[] = { rvc_rs1_eq_x0, rvc_end }; 976 static const rvc_constraint rvcc_bgez[] = { rvc_rs2_eq_x0, rvc_end }; 977 static const rvc_constraint rvcc_bltz[] = { rvc_rs2_eq_x0, rvc_end }; 978 static const rvc_constraint rvcc_bgtz[] = { rvc_rs1_eq_x0, rvc_end }; 979 static const rvc_constraint rvcc_ble[] = { rvc_end }; 980 static const rvc_constraint rvcc_bleu[] = { rvc_end }; 981 static const rvc_constraint rvcc_bgt[] = { rvc_end }; 982 static const rvc_constraint rvcc_bgtu[] = { rvc_end }; 983 static const rvc_constraint rvcc_j[] = { rvc_rd_eq_x0, rvc_end }; 984 static const rvc_constraint rvcc_ret[] = { rvc_rd_eq_x0, rvc_rs1_eq_ra, 985 rvc_end }; 986 static const rvc_constraint rvcc_jr[] = { rvc_rd_eq_x0, rvc_imm_eq_zero, 987 rvc_end }; 988 static const rvc_constraint rvcc_rdcycle[] = { rvc_rs1_eq_x0, rvc_csr_eq_0xc00, 989 rvc_end }; 990 static const rvc_constraint rvcc_rdtime[] = { rvc_rs1_eq_x0, rvc_csr_eq_0xc01, 991 rvc_end }; 992 static const rvc_constraint rvcc_rdinstret[] = { rvc_rs1_eq_x0, 993 rvc_csr_eq_0xc02, rvc_end }; 994 static const rvc_constraint rvcc_rdcycleh[] = { rvc_rs1_eq_x0, 995 rvc_csr_eq_0xc80, rvc_end }; 996 static const rvc_constraint rvcc_rdtimeh[] = { rvc_rs1_eq_x0, rvc_csr_eq_0xc81, 997 rvc_end }; 998 static const rvc_constraint rvcc_rdinstreth[] = { rvc_rs1_eq_x0, 999 rvc_csr_eq_0xc82, rvc_end }; 1000 static const rvc_constraint rvcc_frcsr[] = { rvc_rs1_eq_x0, rvc_csr_eq_0x003, 1001 rvc_end }; 1002 static const rvc_constraint rvcc_frrm[] = { rvc_rs1_eq_x0, rvc_csr_eq_0x002, 1003 rvc_end }; 1004 static const rvc_constraint rvcc_frflags[] = { rvc_rs1_eq_x0, rvc_csr_eq_0x001, 1005 rvc_end }; 1006 static const rvc_constraint rvcc_fscsr[] = { rvc_csr_eq_0x003, rvc_end }; 1007 static const rvc_constraint rvcc_fsrm[] = { rvc_csr_eq_0x002, rvc_end }; 1008 static const rvc_constraint rvcc_fsflags[] = { rvc_csr_eq_0x001, rvc_end }; 1009 static const rvc_constraint rvcc_fsrmi[] = { rvc_csr_eq_0x002, rvc_end }; 1010 static const rvc_constraint rvcc_fsflagsi[] = { rvc_csr_eq_0x001, rvc_end }; 1011 1012 /* pseudo-instruction metadata */ 1013 1014 static const rv_comp_data rvcp_jal[] = { 1015 { rv_op_j, rvcc_j }, 1016 { rv_op_jal, rvcc_jal }, 1017 { rv_op_illegal, NULL } 1018 }; 1019 1020 static const rv_comp_data rvcp_jalr[] = { 1021 { rv_op_ret, rvcc_ret }, 1022 { rv_op_jr, rvcc_jr }, 1023 { rv_op_jalr, rvcc_jalr }, 1024 { rv_op_illegal, NULL } 1025 }; 1026 1027 static const rv_comp_data rvcp_beq[] = { 1028 { rv_op_beqz, rvcc_beqz }, 1029 { rv_op_illegal, NULL } 1030 }; 1031 1032 static const rv_comp_data rvcp_bne[] = { 1033 { rv_op_bnez, rvcc_bnez }, 1034 { rv_op_illegal, NULL } 1035 }; 1036 1037 static const rv_comp_data rvcp_blt[] = { 1038 { rv_op_bltz, rvcc_bltz }, 1039 { rv_op_bgtz, rvcc_bgtz }, 1040 { rv_op_bgt, rvcc_bgt }, 1041 { rv_op_illegal, NULL } 1042 }; 1043 1044 static const rv_comp_data rvcp_bge[] = { 1045 { rv_op_blez, rvcc_blez }, 1046 { rv_op_bgez, rvcc_bgez }, 1047 { rv_op_ble, rvcc_ble }, 1048 { rv_op_illegal, NULL } 1049 }; 1050 1051 static const rv_comp_data rvcp_bltu[] = { 1052 { rv_op_bgtu, rvcc_bgtu }, 1053 { rv_op_illegal, NULL } 1054 }; 1055 1056 static const rv_comp_data rvcp_bgeu[] = { 1057 { rv_op_bleu, rvcc_bleu }, 1058 { rv_op_illegal, NULL } 1059 }; 1060 1061 static const rv_comp_data rvcp_addi[] = { 1062 { rv_op_nop, rvcc_nop }, 1063 { rv_op_mv, rvcc_mv }, 1064 { rv_op_illegal, NULL } 1065 }; 1066 1067 static const rv_comp_data rvcp_sltiu[] = { 1068 { rv_op_seqz, rvcc_seqz }, 1069 { rv_op_illegal, NULL } 1070 }; 1071 1072 static const rv_comp_data rvcp_xori[] = { 1073 { rv_op_not, rvcc_not }, 1074 { rv_op_illegal, NULL } 1075 }; 1076 1077 static const rv_comp_data rvcp_sub[] = { 1078 { rv_op_neg, rvcc_neg }, 1079 { rv_op_illegal, NULL } 1080 }; 1081 1082 static const rv_comp_data rvcp_slt[] = { 1083 { rv_op_sltz, rvcc_sltz }, 1084 { rv_op_sgtz, rvcc_sgtz }, 1085 { rv_op_illegal, NULL } 1086 }; 1087 1088 static const rv_comp_data rvcp_sltu[] = { 1089 { rv_op_snez, rvcc_snez }, 1090 { rv_op_illegal, NULL } 1091 }; 1092 1093 static const rv_comp_data rvcp_addiw[] = { 1094 { rv_op_sext_w, rvcc_sext_w }, 1095 { rv_op_illegal, NULL } 1096 }; 1097 1098 static const rv_comp_data rvcp_subw[] = { 1099 { rv_op_negw, rvcc_negw }, 1100 { rv_op_illegal, NULL } 1101 }; 1102 1103 static const rv_comp_data rvcp_csrrw[] = { 1104 { rv_op_fscsr, rvcc_fscsr }, 1105 { rv_op_fsrm, rvcc_fsrm }, 1106 { rv_op_fsflags, rvcc_fsflags }, 1107 { rv_op_illegal, NULL } 1108 }; 1109 1110 1111 static const rv_comp_data rvcp_csrrs[] = { 1112 { rv_op_rdcycle, rvcc_rdcycle }, 1113 { rv_op_rdtime, rvcc_rdtime }, 1114 { rv_op_rdinstret, rvcc_rdinstret }, 1115 { rv_op_rdcycleh, rvcc_rdcycleh }, 1116 { rv_op_rdtimeh, rvcc_rdtimeh }, 1117 { rv_op_rdinstreth, rvcc_rdinstreth }, 1118 { rv_op_frcsr, rvcc_frcsr }, 1119 { rv_op_frrm, rvcc_frrm }, 1120 { rv_op_frflags, rvcc_frflags }, 1121 { rv_op_illegal, NULL } 1122 }; 1123 1124 static const rv_comp_data rvcp_csrrwi[] = { 1125 { rv_op_fsrmi, rvcc_fsrmi }, 1126 { rv_op_fsflagsi, rvcc_fsflagsi }, 1127 { rv_op_illegal, NULL } 1128 }; 1129 1130 static const rv_comp_data rvcp_fsgnj_s[] = { 1131 { rv_op_fmv_s, rvcc_fmv_s }, 1132 { rv_op_illegal, NULL } 1133 }; 1134 1135 static const rv_comp_data rvcp_fsgnjn_s[] = { 1136 { rv_op_fneg_s, rvcc_fneg_s }, 1137 { rv_op_illegal, NULL } 1138 }; 1139 1140 static const rv_comp_data rvcp_fsgnjx_s[] = { 1141 { rv_op_fabs_s, rvcc_fabs_s }, 1142 { rv_op_illegal, NULL } 1143 }; 1144 1145 static const rv_comp_data rvcp_fsgnj_d[] = { 1146 { rv_op_fmv_d, rvcc_fmv_d }, 1147 { rv_op_illegal, NULL } 1148 }; 1149 1150 static const rv_comp_data rvcp_fsgnjn_d[] = { 1151 { rv_op_fneg_d, rvcc_fneg_d }, 1152 { rv_op_illegal, NULL } 1153 }; 1154 1155 static const rv_comp_data rvcp_fsgnjx_d[] = { 1156 { rv_op_fabs_d, rvcc_fabs_d }, 1157 { rv_op_illegal, NULL } 1158 }; 1159 1160 static const rv_comp_data rvcp_fsgnj_q[] = { 1161 { rv_op_fmv_q, rvcc_fmv_q }, 1162 { rv_op_illegal, NULL } 1163 }; 1164 1165 static const rv_comp_data rvcp_fsgnjn_q[] = { 1166 { rv_op_fneg_q, rvcc_fneg_q }, 1167 { rv_op_illegal, NULL } 1168 }; 1169 1170 static const rv_comp_data rvcp_fsgnjx_q[] = { 1171 { rv_op_fabs_q, rvcc_fabs_q }, 1172 { rv_op_illegal, NULL } 1173 }; 1174 1175 /* instruction metadata */ 1176 1177 const rv_opcode_data rvi_opcode_data[] = { 1178 { "illegal", rv_codec_illegal, rv_fmt_none, NULL, 0, 0, 0 }, 1179 { "lui", rv_codec_u, rv_fmt_rd_uimm, NULL, 0, 0, 0 }, 1180 { "auipc", rv_codec_u, rv_fmt_rd_uoffset, NULL, 0, 0, 0 }, 1181 { "jal", rv_codec_uj, rv_fmt_rd_offset, rvcp_jal, 0, 0, 0 }, 1182 { "jalr", rv_codec_i, rv_fmt_rd_rs1_offset, rvcp_jalr, 0, 0, 0 }, 1183 { "beq", rv_codec_sb, rv_fmt_rs1_rs2_offset, rvcp_beq, 0, 0, 0 }, 1184 { "bne", rv_codec_sb, rv_fmt_rs1_rs2_offset, rvcp_bne, 0, 0, 0 }, 1185 { "blt", rv_codec_sb, rv_fmt_rs1_rs2_offset, rvcp_blt, 0, 0, 0 }, 1186 { "bge", rv_codec_sb, rv_fmt_rs1_rs2_offset, rvcp_bge, 0, 0, 0 }, 1187 { "bltu", rv_codec_sb, rv_fmt_rs1_rs2_offset, rvcp_bltu, 0, 0, 0 }, 1188 { "bgeu", rv_codec_sb, rv_fmt_rs1_rs2_offset, rvcp_bgeu, 0, 0, 0 }, 1189 { "lb", rv_codec_i, rv_fmt_rd_offset_rs1, NULL, 0, 0, 0 }, 1190 { "lh", rv_codec_i, rv_fmt_rd_offset_rs1, NULL, 0, 0, 0 }, 1191 { "lw", rv_codec_i, rv_fmt_rd_offset_rs1, NULL, 0, 0, 0 }, 1192 { "lbu", rv_codec_i, rv_fmt_rd_offset_rs1, NULL, 0, 0, 0 }, 1193 { "lhu", rv_codec_i, rv_fmt_rd_offset_rs1, NULL, 0, 0, 0 }, 1194 { "sb", rv_codec_s, rv_fmt_rs2_offset_rs1, NULL, 0, 0, 0 }, 1195 { "sh", rv_codec_s, rv_fmt_rs2_offset_rs1, NULL, 0, 0, 0 }, 1196 { "sw", rv_codec_s, rv_fmt_rs2_offset_rs1, NULL, 0, 0, 0 }, 1197 { "addi", rv_codec_i, rv_fmt_rd_rs1_imm, rvcp_addi, 0, 0, 0 }, 1198 { "slti", rv_codec_i, rv_fmt_rd_rs1_imm, NULL, 0, 0, 0 }, 1199 { "sltiu", rv_codec_i, rv_fmt_rd_rs1_imm, rvcp_sltiu, 0, 0, 0 }, 1200 { "xori", rv_codec_i, rv_fmt_rd_rs1_imm, rvcp_xori, 0, 0, 0 }, 1201 { "ori", rv_codec_i, rv_fmt_rd_rs1_imm, NULL, 0, 0, 0 }, 1202 { "andi", rv_codec_i, rv_fmt_rd_rs1_imm, NULL, 0, 0, 0 }, 1203 { "slli", rv_codec_i_sh7, rv_fmt_rd_rs1_imm, NULL, 0, 0, 0 }, 1204 { "srli", rv_codec_i_sh7, rv_fmt_rd_rs1_imm, NULL, 0, 0, 0 }, 1205 { "srai", rv_codec_i_sh7, rv_fmt_rd_rs1_imm, NULL, 0, 0, 0 }, 1206 { "add", rv_codec_r, rv_fmt_rd_rs1_rs2, NULL, 0, 0, 0 }, 1207 { "sub", rv_codec_r, rv_fmt_rd_rs1_rs2, rvcp_sub, 0, 0, 0 }, 1208 { "sll", rv_codec_r, rv_fmt_rd_rs1_rs2, NULL, 0, 0, 0 }, 1209 { "slt", rv_codec_r, rv_fmt_rd_rs1_rs2, rvcp_slt, 0, 0, 0 }, 1210 { "sltu", rv_codec_r, rv_fmt_rd_rs1_rs2, rvcp_sltu, 0, 0, 0 }, 1211 { "xor", rv_codec_r, rv_fmt_rd_rs1_rs2, NULL, 0, 0, 0 }, 1212 { "srl", rv_codec_r, rv_fmt_rd_rs1_rs2, NULL, 0, 0, 0 }, 1213 { "sra", rv_codec_r, rv_fmt_rd_rs1_rs2, NULL, 0, 0, 0 }, 1214 { "or", rv_codec_r, rv_fmt_rd_rs1_rs2, NULL, 0, 0, 0 }, 1215 { "and", rv_codec_r, rv_fmt_rd_rs1_rs2, NULL, 0, 0, 0 }, 1216 { "fence", rv_codec_r_f, rv_fmt_pred_succ, NULL, 0, 0, 0 }, 1217 { "fence.i", rv_codec_none, rv_fmt_none, NULL, 0, 0, 0 }, 1218 { "lwu", rv_codec_i, rv_fmt_rd_offset_rs1, NULL, 0, 0, 0 }, 1219 { "ld", rv_codec_i, rv_fmt_rd_offset_rs1, NULL, 0, 0, 0 }, 1220 { "sd", rv_codec_s, rv_fmt_rs2_offset_rs1, NULL, 0, 0, 0 }, 1221 { "addiw", rv_codec_i, rv_fmt_rd_rs1_imm, rvcp_addiw, 0, 0, 0 }, 1222 { "slliw", rv_codec_i_sh5, rv_fmt_rd_rs1_imm, NULL, 0, 0, 0 }, 1223 { "srliw", rv_codec_i_sh5, rv_fmt_rd_rs1_imm, NULL, 0, 0, 0 }, 1224 { "sraiw", rv_codec_i_sh5, rv_fmt_rd_rs1_imm, NULL, 0, 0, 0 }, 1225 { "addw", rv_codec_r, rv_fmt_rd_rs1_rs2, NULL, 0, 0, 0 }, 1226 { "subw", rv_codec_r, rv_fmt_rd_rs1_rs2, rvcp_subw, 0, 0, 0 }, 1227 { "sllw", rv_codec_r, rv_fmt_rd_rs1_rs2, NULL, 0, 0, 0 }, 1228 { "srlw", rv_codec_r, rv_fmt_rd_rs1_rs2, NULL, 0, 0, 0 }, 1229 { "sraw", rv_codec_r, rv_fmt_rd_rs1_rs2, NULL, 0, 0, 0 }, 1230 { "ldu", rv_codec_i, rv_fmt_rd_offset_rs1, NULL, 0, 0, 0 }, 1231 { "lq", rv_codec_i, rv_fmt_rd_offset_rs1, NULL, 0, 0, 0 }, 1232 { "sq", rv_codec_s, rv_fmt_rs2_offset_rs1, NULL, 0, 0, 0 }, 1233 { "addid", rv_codec_i, rv_fmt_rd_rs1_imm, NULL, 0, 0, 0 }, 1234 { "sllid", rv_codec_i_sh6, rv_fmt_rd_rs1_imm, NULL, 0, 0, 0 }, 1235 { "srlid", rv_codec_i_sh6, rv_fmt_rd_rs1_imm, NULL, 0, 0, 0 }, 1236 { "sraid", rv_codec_i_sh6, rv_fmt_rd_rs1_imm, NULL, 0, 0, 0 }, 1237 { "addd", rv_codec_r, rv_fmt_rd_rs1_rs2, NULL, 0, 0, 0 }, 1238 { "subd", rv_codec_r, rv_fmt_rd_rs1_rs2, NULL, 0, 0, 0 }, 1239 { "slld", rv_codec_r, rv_fmt_rd_rs1_rs2, NULL, 0, 0, 0 }, 1240 { "srld", rv_codec_r, rv_fmt_rd_rs1_rs2, NULL, 0, 0, 0 }, 1241 { "srad", rv_codec_r, rv_fmt_rd_rs1_rs2, NULL, 0, 0, 0 }, 1242 { "mul", rv_codec_r, rv_fmt_rd_rs1_rs2, NULL, 0, 0, 0 }, 1243 { "mulh", rv_codec_r, rv_fmt_rd_rs1_rs2, NULL, 0, 0, 0 }, 1244 { "mulhsu", rv_codec_r, rv_fmt_rd_rs1_rs2, NULL, 0, 0, 0 }, 1245 { "mulhu", rv_codec_r, rv_fmt_rd_rs1_rs2, NULL, 0, 0, 0 }, 1246 { "div", rv_codec_r, rv_fmt_rd_rs1_rs2, NULL, 0, 0, 0 }, 1247 { "divu", rv_codec_r, rv_fmt_rd_rs1_rs2, NULL, 0, 0, 0 }, 1248 { "rem", rv_codec_r, rv_fmt_rd_rs1_rs2, NULL, 0, 0, 0 }, 1249 { "remu", rv_codec_r, rv_fmt_rd_rs1_rs2, NULL, 0, 0, 0 }, 1250 { "mulw", rv_codec_r, rv_fmt_rd_rs1_rs2, NULL, 0, 0, 0 }, 1251 { "divw", rv_codec_r, rv_fmt_rd_rs1_rs2, NULL, 0, 0, 0 }, 1252 { "divuw", rv_codec_r, rv_fmt_rd_rs1_rs2, NULL, 0, 0, 0 }, 1253 { "remw", rv_codec_r, rv_fmt_rd_rs1_rs2, NULL, 0, 0, 0 }, 1254 { "remuw", rv_codec_r, rv_fmt_rd_rs1_rs2, NULL, 0, 0, 0 }, 1255 { "muld", rv_codec_r, rv_fmt_rd_rs1_rs2, NULL, 0, 0, 0 }, 1256 { "divd", rv_codec_r, rv_fmt_rd_rs1_rs2, NULL, 0, 0, 0 }, 1257 { "divud", rv_codec_r, rv_fmt_rd_rs1_rs2, NULL, 0, 0, 0 }, 1258 { "remd", rv_codec_r, rv_fmt_rd_rs1_rs2, NULL, 0, 0, 0 }, 1259 { "remud", rv_codec_r, rv_fmt_rd_rs1_rs2, NULL, 0, 0, 0 }, 1260 { "lr.w", rv_codec_r_l, rv_fmt_aqrl_rd_rs1, NULL, 0, 0, 0 }, 1261 { "sc.w", rv_codec_r_a, rv_fmt_aqrl_rd_rs2_rs1, NULL, 0, 0, 0 }, 1262 { "amoswap.w", rv_codec_r_a, rv_fmt_aqrl_rd_rs2_rs1, NULL, 0, 0, 0 }, 1263 { "amoadd.w", rv_codec_r_a, rv_fmt_aqrl_rd_rs2_rs1, NULL, 0, 0, 0 }, 1264 { "amoxor.w", rv_codec_r_a, rv_fmt_aqrl_rd_rs2_rs1, NULL, 0, 0, 0 }, 1265 { "amoor.w", rv_codec_r_a, rv_fmt_aqrl_rd_rs2_rs1, NULL, 0, 0, 0 }, 1266 { "amoand.w", rv_codec_r_a, rv_fmt_aqrl_rd_rs2_rs1, NULL, 0, 0, 0 }, 1267 { "amomin.w", rv_codec_r_a, rv_fmt_aqrl_rd_rs2_rs1, NULL, 0, 0, 0 }, 1268 { "amomax.w", rv_codec_r_a, rv_fmt_aqrl_rd_rs2_rs1, NULL, 0, 0, 0 }, 1269 { "amominu.w", rv_codec_r_a, rv_fmt_aqrl_rd_rs2_rs1, NULL, 0, 0, 0 }, 1270 { "amomaxu.w", rv_codec_r_a, rv_fmt_aqrl_rd_rs2_rs1, NULL, 0, 0, 0 }, 1271 { "lr.d", rv_codec_r_l, rv_fmt_aqrl_rd_rs1, NULL, 0, 0, 0 }, 1272 { "sc.d", rv_codec_r_a, rv_fmt_aqrl_rd_rs2_rs1, NULL, 0, 0, 0 }, 1273 { "amoswap.d", rv_codec_r_a, rv_fmt_aqrl_rd_rs2_rs1, NULL, 0, 0, 0 }, 1274 { "amoadd.d", rv_codec_r_a, rv_fmt_aqrl_rd_rs2_rs1, NULL, 0, 0, 0 }, 1275 { "amoxor.d", rv_codec_r_a, rv_fmt_aqrl_rd_rs2_rs1, NULL, 0, 0, 0 }, 1276 { "amoor.d", rv_codec_r_a, rv_fmt_aqrl_rd_rs2_rs1, NULL, 0, 0, 0 }, 1277 { "amoand.d", rv_codec_r_a, rv_fmt_aqrl_rd_rs2_rs1, NULL, 0, 0, 0 }, 1278 { "amomin.d", rv_codec_r_a, rv_fmt_aqrl_rd_rs2_rs1, NULL, 0, 0, 0 }, 1279 { "amomax.d", rv_codec_r_a, rv_fmt_aqrl_rd_rs2_rs1, NULL, 0, 0, 0 }, 1280 { "amominu.d", rv_codec_r_a, rv_fmt_aqrl_rd_rs2_rs1, NULL, 0, 0, 0 }, 1281 { "amomaxu.d", rv_codec_r_a, rv_fmt_aqrl_rd_rs2_rs1, NULL, 0, 0, 0 }, 1282 { "lr.q", rv_codec_r_l, rv_fmt_aqrl_rd_rs1, NULL, 0, 0, 0 }, 1283 { "sc.q", rv_codec_r_a, rv_fmt_aqrl_rd_rs2_rs1, NULL, 0, 0, 0 }, 1284 { "amoswap.q", rv_codec_r_a, rv_fmt_aqrl_rd_rs2_rs1, NULL, 0, 0, 0 }, 1285 { "amoadd.q", rv_codec_r_a, rv_fmt_aqrl_rd_rs2_rs1, NULL, 0, 0, 0 }, 1286 { "amoxor.q", rv_codec_r_a, rv_fmt_aqrl_rd_rs2_rs1, NULL, 0, 0, 0 }, 1287 { "amoor.q", rv_codec_r_a, rv_fmt_aqrl_rd_rs2_rs1, NULL, 0, 0, 0 }, 1288 { "amoand.q", rv_codec_r_a, rv_fmt_aqrl_rd_rs2_rs1, NULL, 0, 0, 0 }, 1289 { "amomin.q", rv_codec_r_a, rv_fmt_aqrl_rd_rs2_rs1, NULL, 0, 0, 0 }, 1290 { "amomax.q", rv_codec_r_a, rv_fmt_aqrl_rd_rs2_rs1, NULL, 0, 0, 0 }, 1291 { "amominu.q", rv_codec_r_a, rv_fmt_aqrl_rd_rs2_rs1, NULL, 0, 0, 0 }, 1292 { "amomaxu.q", rv_codec_r_a, rv_fmt_aqrl_rd_rs2_rs1, NULL, 0, 0, 0 }, 1293 { "ecall", rv_codec_none, rv_fmt_none, NULL, 0, 0, 0 }, 1294 { "ebreak", rv_codec_none, rv_fmt_none, NULL, 0, 0, 0 }, 1295 { "uret", rv_codec_none, rv_fmt_none, NULL, 0, 0, 0 }, 1296 { "sret", rv_codec_none, rv_fmt_none, NULL, 0, 0, 0 }, 1297 { "hret", rv_codec_none, rv_fmt_none, NULL, 0, 0, 0 }, 1298 { "mret", rv_codec_none, rv_fmt_none, NULL, 0, 0, 0 }, 1299 { "dret", rv_codec_none, rv_fmt_none, NULL, 0, 0, 0 }, 1300 { "sfence.vm", rv_codec_r, rv_fmt_rs1, NULL, 0, 0, 0 }, 1301 { "sfence.vma", rv_codec_r, rv_fmt_rs1_rs2, NULL, 0, 0, 0 }, 1302 { "wfi", rv_codec_none, rv_fmt_none, NULL, 0, 0, 0 }, 1303 { "csrrw", rv_codec_i_csr, rv_fmt_rd_csr_rs1, rvcp_csrrw, 0, 0, 0 }, 1304 { "csrrs", rv_codec_i_csr, rv_fmt_rd_csr_rs1, rvcp_csrrs, 0, 0, 0 }, 1305 { "csrrc", rv_codec_i_csr, rv_fmt_rd_csr_rs1, NULL, 0, 0, 0 }, 1306 { "csrrwi", rv_codec_i_csr, rv_fmt_rd_csr_zimm, rvcp_csrrwi, 0, 0, 0 }, 1307 { "csrrsi", rv_codec_i_csr, rv_fmt_rd_csr_zimm, NULL, 0, 0, 0 }, 1308 { "csrrci", rv_codec_i_csr, rv_fmt_rd_csr_zimm, NULL, 0, 0, 0 }, 1309 { "flw", rv_codec_i, rv_fmt_frd_offset_rs1, NULL, 0, 0, 0 }, 1310 { "fsw", rv_codec_s, rv_fmt_frs2_offset_rs1, NULL, 0, 0, 0 }, 1311 { "fmadd.s", rv_codec_r4_m, rv_fmt_rm_frd_frs1_frs2_frs3, NULL, 0, 0, 0 }, 1312 { "fmsub.s", rv_codec_r4_m, rv_fmt_rm_frd_frs1_frs2_frs3, NULL, 0, 0, 0 }, 1313 { "fnmsub.s", rv_codec_r4_m, rv_fmt_rm_frd_frs1_frs2_frs3, NULL, 0, 0, 0 }, 1314 { "fnmadd.s", rv_codec_r4_m, rv_fmt_rm_frd_frs1_frs2_frs3, NULL, 0, 0, 0 }, 1315 { "fadd.s", rv_codec_r_m, rv_fmt_rm_frd_frs1_frs2, NULL, 0, 0, 0 }, 1316 { "fsub.s", rv_codec_r_m, rv_fmt_rm_frd_frs1_frs2, NULL, 0, 0, 0 }, 1317 { "fmul.s", rv_codec_r_m, rv_fmt_rm_frd_frs1_frs2, NULL, 0, 0, 0 }, 1318 { "fdiv.s", rv_codec_r_m, rv_fmt_rm_frd_frs1_frs2, NULL, 0, 0, 0 }, 1319 { "fsgnj.s", rv_codec_r, rv_fmt_frd_frs1_frs2, rvcp_fsgnj_s, 0, 0, 0 }, 1320 { "fsgnjn.s", rv_codec_r, rv_fmt_frd_frs1_frs2, rvcp_fsgnjn_s, 0, 0, 0 }, 1321 { "fsgnjx.s", rv_codec_r, rv_fmt_frd_frs1_frs2, rvcp_fsgnjx_s, 0, 0, 0 }, 1322 { "fmin.s", rv_codec_r, rv_fmt_frd_frs1_frs2, NULL, 0, 0, 0 }, 1323 { "fmax.s", rv_codec_r, rv_fmt_frd_frs1_frs2, NULL, 0, 0, 0 }, 1324 { "fsqrt.s", rv_codec_r_m, rv_fmt_rm_frd_frs1, NULL, 0, 0, 0 }, 1325 { "fle.s", rv_codec_r, rv_fmt_rd_frs1_frs2, NULL, 0, 0, 0 }, 1326 { "flt.s", rv_codec_r, rv_fmt_rd_frs1_frs2, NULL, 0, 0, 0 }, 1327 { "feq.s", rv_codec_r, rv_fmt_rd_frs1_frs2, NULL, 0, 0, 0 }, 1328 { "fcvt.w.s", rv_codec_r_m, rv_fmt_rm_rd_frs1, NULL, 0, 0, 0 }, 1329 { "fcvt.wu.s", rv_codec_r_m, rv_fmt_rm_rd_frs1, NULL, 0, 0, 0 }, 1330 { "fcvt.s.w", rv_codec_r_m, rv_fmt_rm_frd_rs1, NULL, 0, 0, 0 }, 1331 { "fcvt.s.wu", rv_codec_r_m, rv_fmt_rm_frd_rs1, NULL, 0, 0, 0 }, 1332 { "fmv.x.s", rv_codec_r, rv_fmt_rd_frs1, NULL, 0, 0, 0 }, 1333 { "fclass.s", rv_codec_r, rv_fmt_rd_frs1, NULL, 0, 0, 0 }, 1334 { "fmv.s.x", rv_codec_r, rv_fmt_frd_rs1, NULL, 0, 0, 0 }, 1335 { "fcvt.l.s", rv_codec_r_m, rv_fmt_rm_rd_frs1, NULL, 0, 0, 0 }, 1336 { "fcvt.lu.s", rv_codec_r_m, rv_fmt_rm_rd_frs1, NULL, 0, 0, 0 }, 1337 { "fcvt.s.l", rv_codec_r_m, rv_fmt_rm_frd_rs1, NULL, 0, 0, 0 }, 1338 { "fcvt.s.lu", rv_codec_r_m, rv_fmt_rm_frd_rs1, NULL, 0, 0, 0 }, 1339 { "fld", rv_codec_i, rv_fmt_frd_offset_rs1, NULL, 0, 0, 0 }, 1340 { "fsd", rv_codec_s, rv_fmt_frs2_offset_rs1, NULL, 0, 0, 0 }, 1341 { "fmadd.d", rv_codec_r4_m, rv_fmt_rm_frd_frs1_frs2_frs3, NULL, 0, 0, 0 }, 1342 { "fmsub.d", rv_codec_r4_m, rv_fmt_rm_frd_frs1_frs2_frs3, NULL, 0, 0, 0 }, 1343 { "fnmsub.d", rv_codec_r4_m, rv_fmt_rm_frd_frs1_frs2_frs3, NULL, 0, 0, 0 }, 1344 { "fnmadd.d", rv_codec_r4_m, rv_fmt_rm_frd_frs1_frs2_frs3, NULL, 0, 0, 0 }, 1345 { "fadd.d", rv_codec_r_m, rv_fmt_rm_frd_frs1_frs2, NULL, 0, 0, 0 }, 1346 { "fsub.d", rv_codec_r_m, rv_fmt_rm_frd_frs1_frs2, NULL, 0, 0, 0 }, 1347 { "fmul.d", rv_codec_r_m, rv_fmt_rm_frd_frs1_frs2, NULL, 0, 0, 0 }, 1348 { "fdiv.d", rv_codec_r_m, rv_fmt_rm_frd_frs1_frs2, NULL, 0, 0, 0 }, 1349 { "fsgnj.d", rv_codec_r, rv_fmt_frd_frs1_frs2, rvcp_fsgnj_d, 0, 0, 0 }, 1350 { "fsgnjn.d", rv_codec_r, rv_fmt_frd_frs1_frs2, rvcp_fsgnjn_d, 0, 0, 0 }, 1351 { "fsgnjx.d", rv_codec_r, rv_fmt_frd_frs1_frs2, rvcp_fsgnjx_d, 0, 0, 0 }, 1352 { "fmin.d", rv_codec_r, rv_fmt_frd_frs1_frs2, NULL, 0, 0, 0 }, 1353 { "fmax.d", rv_codec_r, rv_fmt_frd_frs1_frs2, NULL, 0, 0, 0 }, 1354 { "fcvt.s.d", rv_codec_r_m, rv_fmt_rm_frd_frs1, NULL, 0, 0, 0 }, 1355 { "fcvt.d.s", rv_codec_r_m, rv_fmt_rm_frd_frs1, NULL, 0, 0, 0 }, 1356 { "fsqrt.d", rv_codec_r_m, rv_fmt_rm_frd_frs1, NULL, 0, 0, 0 }, 1357 { "fle.d", rv_codec_r, rv_fmt_rd_frs1_frs2, NULL, 0, 0, 0 }, 1358 { "flt.d", rv_codec_r, rv_fmt_rd_frs1_frs2, NULL, 0, 0, 0 }, 1359 { "feq.d", rv_codec_r, rv_fmt_rd_frs1_frs2, NULL, 0, 0, 0 }, 1360 { "fcvt.w.d", rv_codec_r_m, rv_fmt_rm_rd_frs1, NULL, 0, 0, 0 }, 1361 { "fcvt.wu.d", rv_codec_r_m, rv_fmt_rm_rd_frs1, NULL, 0, 0, 0 }, 1362 { "fcvt.d.w", rv_codec_r_m, rv_fmt_rm_frd_rs1, NULL, 0, 0, 0 }, 1363 { "fcvt.d.wu", rv_codec_r_m, rv_fmt_rm_frd_rs1, NULL, 0, 0, 0 }, 1364 { "fclass.d", rv_codec_r, rv_fmt_rd_frs1, NULL, 0, 0, 0 }, 1365 { "fcvt.l.d", rv_codec_r_m, rv_fmt_rm_rd_frs1, NULL, 0, 0, 0 }, 1366 { "fcvt.lu.d", rv_codec_r_m, rv_fmt_rm_rd_frs1, NULL, 0, 0, 0 }, 1367 { "fmv.x.d", rv_codec_r, rv_fmt_rd_frs1, NULL, 0, 0, 0 }, 1368 { "fcvt.d.l", rv_codec_r_m, rv_fmt_rm_frd_rs1, NULL, 0, 0, 0 }, 1369 { "fcvt.d.lu", rv_codec_r_m, rv_fmt_rm_frd_rs1, NULL, 0, 0, 0 }, 1370 { "fmv.d.x", rv_codec_r, rv_fmt_frd_rs1, NULL, 0, 0, 0 }, 1371 { "flq", rv_codec_i, rv_fmt_frd_offset_rs1, NULL, 0, 0, 0 }, 1372 { "fsq", rv_codec_s, rv_fmt_frs2_offset_rs1, NULL, 0, 0, 0 }, 1373 { "fmadd.q", rv_codec_r4_m, rv_fmt_rm_frd_frs1_frs2_frs3, NULL, 0, 0, 0 }, 1374 { "fmsub.q", rv_codec_r4_m, rv_fmt_rm_frd_frs1_frs2_frs3, NULL, 0, 0, 0 }, 1375 { "fnmsub.q", rv_codec_r4_m, rv_fmt_rm_frd_frs1_frs2_frs3, NULL, 0, 0, 0 }, 1376 { "fnmadd.q", rv_codec_r4_m, rv_fmt_rm_frd_frs1_frs2_frs3, NULL, 0, 0, 0 }, 1377 { "fadd.q", rv_codec_r_m, rv_fmt_rm_frd_frs1_frs2, NULL, 0, 0, 0 }, 1378 { "fsub.q", rv_codec_r_m, rv_fmt_rm_frd_frs1_frs2, NULL, 0, 0, 0 }, 1379 { "fmul.q", rv_codec_r_m, rv_fmt_rm_frd_frs1_frs2, NULL, 0, 0, 0 }, 1380 { "fdiv.q", rv_codec_r_m, rv_fmt_rm_frd_frs1_frs2, NULL, 0, 0, 0 }, 1381 { "fsgnj.q", rv_codec_r, rv_fmt_frd_frs1_frs2, rvcp_fsgnj_q, 0, 0, 0 }, 1382 { "fsgnjn.q", rv_codec_r, rv_fmt_frd_frs1_frs2, rvcp_fsgnjn_q, 0, 0, 0 }, 1383 { "fsgnjx.q", rv_codec_r, rv_fmt_frd_frs1_frs2, rvcp_fsgnjx_q, 0, 0, 0 }, 1384 { "fmin.q", rv_codec_r, rv_fmt_frd_frs1_frs2, NULL, 0, 0, 0 }, 1385 { "fmax.q", rv_codec_r, rv_fmt_frd_frs1_frs2, NULL, 0, 0, 0 }, 1386 { "fcvt.s.q", rv_codec_r_m, rv_fmt_rm_frd_frs1, NULL, 0, 0, 0 }, 1387 { "fcvt.q.s", rv_codec_r_m, rv_fmt_rm_frd_frs1, NULL, 0, 0, 0 }, 1388 { "fcvt.d.q", rv_codec_r_m, rv_fmt_rm_frd_frs1, NULL, 0, 0, 0 }, 1389 { "fcvt.q.d", rv_codec_r_m, rv_fmt_rm_frd_frs1, NULL, 0, 0, 0 }, 1390 { "fsqrt.q", rv_codec_r_m, rv_fmt_rm_frd_frs1, NULL, 0, 0, 0 }, 1391 { "fle.q", rv_codec_r, rv_fmt_rd_frs1_frs2, NULL, 0, 0, 0 }, 1392 { "flt.q", rv_codec_r, rv_fmt_rd_frs1_frs2, NULL, 0, 0, 0 }, 1393 { "feq.q", rv_codec_r, rv_fmt_rd_frs1_frs2, NULL, 0, 0, 0 }, 1394 { "fcvt.w.q", rv_codec_r_m, rv_fmt_rm_rd_frs1, NULL, 0, 0, 0 }, 1395 { "fcvt.wu.q", rv_codec_r_m, rv_fmt_rm_rd_frs1, NULL, 0, 0, 0 }, 1396 { "fcvt.q.w", rv_codec_r_m, rv_fmt_rm_frd_rs1, NULL, 0, 0, 0 }, 1397 { "fcvt.q.wu", rv_codec_r_m, rv_fmt_rm_frd_rs1, NULL, 0, 0, 0 }, 1398 { "fclass.q", rv_codec_r, rv_fmt_rd_frs1, NULL, 0, 0, 0 }, 1399 { "fcvt.l.q", rv_codec_r_m, rv_fmt_rm_rd_frs1, NULL, 0, 0, 0 }, 1400 { "fcvt.lu.q", rv_codec_r_m, rv_fmt_rm_rd_frs1, NULL, 0, 0, 0 }, 1401 { "fcvt.q.l", rv_codec_r_m, rv_fmt_rm_frd_rs1, NULL, 0, 0, 0 }, 1402 { "fcvt.q.lu", rv_codec_r_m, rv_fmt_rm_frd_rs1, NULL, 0, 0, 0 }, 1403 { "fmv.x.q", rv_codec_r, rv_fmt_rd_frs1, NULL, 0, 0, 0 }, 1404 { "fmv.q.x", rv_codec_r, rv_fmt_frd_rs1, NULL, 0, 0, 0 }, 1405 { "c.addi4spn", rv_codec_ciw_4spn, rv_fmt_rd_rs1_imm, NULL, rv_op_addi, 1406 rv_op_addi, rv_op_addi, rvcd_imm_nz }, 1407 { "c.fld", rv_codec_cl_ld, rv_fmt_frd_offset_rs1, NULL, rv_op_fld, 1408 rv_op_fld, 0 }, 1409 { "c.lw", rv_codec_cl_lw, rv_fmt_rd_offset_rs1, NULL, rv_op_lw, rv_op_lw, 1410 rv_op_lw }, 1411 { "c.flw", rv_codec_cl_lw, rv_fmt_frd_offset_rs1, NULL, rv_op_flw, 0, 0 }, 1412 { "c.fsd", rv_codec_cs_sd, rv_fmt_frs2_offset_rs1, NULL, rv_op_fsd, 1413 rv_op_fsd, 0 }, 1414 { "c.sw", rv_codec_cs_sw, rv_fmt_rs2_offset_rs1, NULL, rv_op_sw, rv_op_sw, 1415 rv_op_sw }, 1416 { "c.fsw", rv_codec_cs_sw, rv_fmt_frs2_offset_rs1, NULL, rv_op_fsw, 0, 0 }, 1417 { "c.nop", rv_codec_ci_none, rv_fmt_none, NULL, rv_op_addi, rv_op_addi, 1418 rv_op_addi }, 1419 { "c.addi", rv_codec_ci, rv_fmt_rd_rs1_imm, NULL, rv_op_addi, rv_op_addi, 1420 rv_op_addi, rvcd_imm_nz }, 1421 { "c.jal", rv_codec_cj_jal, rv_fmt_rd_offset, NULL, rv_op_jal, 0, 0 }, 1422 { "c.li", rv_codec_ci_li, rv_fmt_rd_rs1_imm, NULL, rv_op_addi, rv_op_addi, 1423 rv_op_addi }, 1424 { "c.addi16sp", rv_codec_ci_16sp, rv_fmt_rd_rs1_imm, NULL, rv_op_addi, 1425 rv_op_addi, rv_op_addi, rvcd_imm_nz }, 1426 { "c.lui", rv_codec_ci_lui, rv_fmt_rd_uimm, NULL, rv_op_lui, rv_op_lui, 1427 rv_op_lui, rvcd_imm_nz }, 1428 { "c.srli", rv_codec_cb_sh6, rv_fmt_rd_rs1_imm, NULL, rv_op_srli, 1429 rv_op_srli, rv_op_srli, rvcd_imm_nz }, 1430 { "c.srai", rv_codec_cb_sh6, rv_fmt_rd_rs1_imm, NULL, rv_op_srai, 1431 rv_op_srai, rv_op_srai, rvcd_imm_nz }, 1432 { "c.andi", rv_codec_cb_imm, rv_fmt_rd_rs1_imm, NULL, rv_op_andi, 1433 rv_op_andi, rv_op_andi }, 1434 { "c.sub", rv_codec_cs, rv_fmt_rd_rs1_rs2, NULL, rv_op_sub, rv_op_sub, 1435 rv_op_sub }, 1436 { "c.xor", rv_codec_cs, rv_fmt_rd_rs1_rs2, NULL, rv_op_xor, rv_op_xor, 1437 rv_op_xor }, 1438 { "c.or", rv_codec_cs, rv_fmt_rd_rs1_rs2, NULL, rv_op_or, rv_op_or, 1439 rv_op_or }, 1440 { "c.and", rv_codec_cs, rv_fmt_rd_rs1_rs2, NULL, rv_op_and, rv_op_and, 1441 rv_op_and }, 1442 { "c.subw", rv_codec_cs, rv_fmt_rd_rs1_rs2, NULL, rv_op_subw, rv_op_subw, 1443 rv_op_subw }, 1444 { "c.addw", rv_codec_cs, rv_fmt_rd_rs1_rs2, NULL, rv_op_addw, rv_op_addw, 1445 rv_op_addw }, 1446 { "c.j", rv_codec_cj, rv_fmt_rd_offset, NULL, rv_op_jal, rv_op_jal, 1447 rv_op_jal }, 1448 { "c.beqz", rv_codec_cb, rv_fmt_rs1_rs2_offset, NULL, rv_op_beq, rv_op_beq, 1449 rv_op_beq }, 1450 { "c.bnez", rv_codec_cb, rv_fmt_rs1_rs2_offset, NULL, rv_op_bne, rv_op_bne, 1451 rv_op_bne }, 1452 { "c.slli", rv_codec_ci_sh6, rv_fmt_rd_rs1_imm, NULL, rv_op_slli, 1453 rv_op_slli, rv_op_slli, rvcd_imm_nz }, 1454 { "c.fldsp", rv_codec_ci_ldsp, rv_fmt_frd_offset_rs1, NULL, rv_op_fld, 1455 rv_op_fld, rv_op_fld }, 1456 { "c.lwsp", rv_codec_ci_lwsp, rv_fmt_rd_offset_rs1, NULL, rv_op_lw, 1457 rv_op_lw, rv_op_lw }, 1458 { "c.flwsp", rv_codec_ci_lwsp, rv_fmt_frd_offset_rs1, NULL, rv_op_flw, 0, 1459 0 }, 1460 { "c.jr", rv_codec_cr_jr, rv_fmt_rd_rs1_offset, NULL, rv_op_jalr, 1461 rv_op_jalr, rv_op_jalr }, 1462 { "c.mv", rv_codec_cr_mv, rv_fmt_rd_rs1_rs2, NULL, rv_op_addi, rv_op_addi, 1463 rv_op_addi }, 1464 { "c.ebreak", rv_codec_ci_none, rv_fmt_none, NULL, rv_op_ebreak, 1465 rv_op_ebreak, rv_op_ebreak }, 1466 { "c.jalr", rv_codec_cr_jalr, rv_fmt_rd_rs1_offset, NULL, rv_op_jalr, 1467 rv_op_jalr, rv_op_jalr }, 1468 { "c.add", rv_codec_cr, rv_fmt_rd_rs1_rs2, NULL, rv_op_add, rv_op_add, 1469 rv_op_add }, 1470 { "c.fsdsp", rv_codec_css_sdsp, rv_fmt_frs2_offset_rs1, NULL, rv_op_fsd, 1471 rv_op_fsd, rv_op_fsd }, 1472 { "c.swsp", rv_codec_css_swsp, rv_fmt_rs2_offset_rs1, NULL, rv_op_sw, 1473 rv_op_sw, rv_op_sw }, 1474 { "c.fswsp", rv_codec_css_swsp, rv_fmt_frs2_offset_rs1, NULL, rv_op_fsw, 0, 1475 0 }, 1476 { "c.ld", rv_codec_cl_ld, rv_fmt_rd_offset_rs1, NULL, 0, rv_op_ld, 1477 rv_op_ld }, 1478 { "c.sd", rv_codec_cs_sd, rv_fmt_rs2_offset_rs1, NULL, 0, rv_op_sd, 1479 rv_op_sd }, 1480 { "c.addiw", rv_codec_ci, rv_fmt_rd_rs1_imm, NULL, 0, rv_op_addiw, 1481 rv_op_addiw }, 1482 { "c.ldsp", rv_codec_ci_ldsp, rv_fmt_rd_offset_rs1, NULL, 0, rv_op_ld, 1483 rv_op_ld }, 1484 { "c.sdsp", rv_codec_css_sdsp, rv_fmt_rs2_offset_rs1, NULL, 0, rv_op_sd, 1485 rv_op_sd }, 1486 { "c.lq", rv_codec_cl_lq, rv_fmt_rd_offset_rs1, NULL, 0, 0, rv_op_lq }, 1487 { "c.sq", rv_codec_cs_sq, rv_fmt_rs2_offset_rs1, NULL, 0, 0, rv_op_sq }, 1488 { "c.lqsp", rv_codec_ci_lqsp, rv_fmt_rd_offset_rs1, NULL, 0, 0, rv_op_lq }, 1489 { "c.sqsp", rv_codec_css_sqsp, rv_fmt_rs2_offset_rs1, NULL, 0, 0, 1490 rv_op_sq }, 1491 { "nop", rv_codec_i, rv_fmt_none, NULL, 0, 0, 0 }, 1492 { "mv", rv_codec_i, rv_fmt_rd_rs1, NULL, 0, 0, 0 }, 1493 { "not", rv_codec_i, rv_fmt_rd_rs1, NULL, 0, 0, 0 }, 1494 { "neg", rv_codec_r, rv_fmt_rd_rs2, NULL, 0, 0, 0 }, 1495 { "negw", rv_codec_r, rv_fmt_rd_rs2, NULL, 0, 0, 0 }, 1496 { "sext.w", rv_codec_i, rv_fmt_rd_rs1, NULL, 0, 0, 0 }, 1497 { "seqz", rv_codec_i, rv_fmt_rd_rs1, NULL, 0, 0, 0 }, 1498 { "snez", rv_codec_r, rv_fmt_rd_rs2, NULL, 0, 0, 0 }, 1499 { "sltz", rv_codec_r, rv_fmt_rd_rs1, NULL, 0, 0, 0 }, 1500 { "sgtz", rv_codec_r, rv_fmt_rd_rs2, NULL, 0, 0, 0 }, 1501 { "fmv.s", rv_codec_r, rv_fmt_frd_frs1, NULL, 0, 0, 0 }, 1502 { "fabs.s", rv_codec_r, rv_fmt_frd_frs1, NULL, 0, 0, 0 }, 1503 { "fneg.s", rv_codec_r, rv_fmt_frd_frs1, NULL, 0, 0, 0 }, 1504 { "fmv.d", rv_codec_r, rv_fmt_frd_frs1, NULL, 0, 0, 0 }, 1505 { "fabs.d", rv_codec_r, rv_fmt_frd_frs1, NULL, 0, 0, 0 }, 1506 { "fneg.d", rv_codec_r, rv_fmt_frd_frs1, NULL, 0, 0, 0 }, 1507 { "fmv.q", rv_codec_r, rv_fmt_frd_frs1, NULL, 0, 0, 0 }, 1508 { "fabs.q", rv_codec_r, rv_fmt_frd_frs1, NULL, 0, 0, 0 }, 1509 { "fneg.q", rv_codec_r, rv_fmt_frd_frs1, NULL, 0, 0, 0 }, 1510 { "beqz", rv_codec_sb, rv_fmt_rs1_offset, NULL, 0, 0, 0 }, 1511 { "bnez", rv_codec_sb, rv_fmt_rs1_offset, NULL, 0, 0, 0 }, 1512 { "blez", rv_codec_sb, rv_fmt_rs2_offset, NULL, 0, 0, 0 }, 1513 { "bgez", rv_codec_sb, rv_fmt_rs1_offset, NULL, 0, 0, 0 }, 1514 { "bltz", rv_codec_sb, rv_fmt_rs1_offset, NULL, 0, 0, 0 }, 1515 { "bgtz", rv_codec_sb, rv_fmt_rs2_offset, NULL, 0, 0, 0 }, 1516 { "ble", rv_codec_sb, rv_fmt_rs2_rs1_offset, NULL, 0, 0, 0 }, 1517 { "bleu", rv_codec_sb, rv_fmt_rs2_rs1_offset, NULL, 0, 0, 0 }, 1518 { "bgt", rv_codec_sb, rv_fmt_rs2_rs1_offset, NULL, 0, 0, 0 }, 1519 { "bgtu", rv_codec_sb, rv_fmt_rs2_rs1_offset, NULL, 0, 0, 0 }, 1520 { "j", rv_codec_uj, rv_fmt_offset, NULL, 0, 0, 0 }, 1521 { "ret", rv_codec_i, rv_fmt_none, NULL, 0, 0, 0 }, 1522 { "jr", rv_codec_i, rv_fmt_rs1, NULL, 0, 0, 0 }, 1523 { "rdcycle", rv_codec_i_csr, rv_fmt_rd, NULL, 0, 0, 0 }, 1524 { "rdtime", rv_codec_i_csr, rv_fmt_rd, NULL, 0, 0, 0 }, 1525 { "rdinstret", rv_codec_i_csr, rv_fmt_rd, NULL, 0, 0, 0 }, 1526 { "rdcycleh", rv_codec_i_csr, rv_fmt_rd, NULL, 0, 0, 0 }, 1527 { "rdtimeh", rv_codec_i_csr, rv_fmt_rd, NULL, 0, 0, 0 }, 1528 { "rdinstreth", rv_codec_i_csr, rv_fmt_rd, NULL, 0, 0, 0 }, 1529 { "frcsr", rv_codec_i_csr, rv_fmt_rd, NULL, 0, 0, 0 }, 1530 { "frrm", rv_codec_i_csr, rv_fmt_rd, NULL, 0, 0, 0 }, 1531 { "frflags", rv_codec_i_csr, rv_fmt_rd, NULL, 0, 0, 0 }, 1532 { "fscsr", rv_codec_i_csr, rv_fmt_rd_rs1, NULL, 0, 0, 0 }, 1533 { "fsrm", rv_codec_i_csr, rv_fmt_rd_rs1, NULL, 0, 0, 0 }, 1534 { "fsflags", rv_codec_i_csr, rv_fmt_rd_rs1, NULL, 0, 0, 0 }, 1535 { "fsrmi", rv_codec_i_csr, rv_fmt_rd_zimm, NULL, 0, 0, 0 }, 1536 { "fsflagsi", rv_codec_i_csr, rv_fmt_rd_zimm, NULL, 0, 0, 0 }, 1537 { "bseti", rv_codec_i_sh7, rv_fmt_rd_rs1_imm, NULL, 0, 0, 0 }, 1538 { "bclri", rv_codec_i_sh7, rv_fmt_rd_rs1_imm, NULL, 0, 0, 0 }, 1539 { "binvi", rv_codec_i_sh7, rv_fmt_rd_rs1_imm, NULL, 0, 0, 0 }, 1540 { "bexti", rv_codec_i_sh7, rv_fmt_rd_rs1_imm, NULL, 0, 0, 0 }, 1541 { "rori", rv_codec_i_sh7, rv_fmt_rd_rs1_imm, NULL, 0, 0, 0 }, 1542 { "clz", rv_codec_r, rv_fmt_rd_rs1, NULL, 0, 0, 0 }, 1543 { "ctz", rv_codec_r, rv_fmt_rd_rs1, NULL, 0, 0, 0 }, 1544 { "cpop", rv_codec_r, rv_fmt_rd_rs1, NULL, 0, 0, 0 }, 1545 { "sext.h", rv_codec_r, rv_fmt_rd_rs1, NULL, 0, 0, 0 }, 1546 { "sext.b", rv_codec_r, rv_fmt_rd_rs1, NULL, 0, 0, 0 }, 1547 { "xnor", rv_codec_r, rv_fmt_rd_rs1_rs2, NULL, 0, 0, 0 }, 1548 { "orn", rv_codec_r, rv_fmt_rd_rs1_rs2, NULL, 0, 0, 0 }, 1549 { "andn", rv_codec_r, rv_fmt_rd_rs1_rs2, NULL, 0, 0, 0 }, 1550 { "rol", rv_codec_r, rv_fmt_rd_rs1_rs2, NULL, 0, 0, 0 }, 1551 { "ror", rv_codec_r, rv_fmt_rd_rs1_rs2, NULL, 0, 0, 0 }, 1552 { "sh1add", rv_codec_r, rv_fmt_rd_rs1_rs2, NULL, 0, 0, 0 }, 1553 { "sh2add", rv_codec_r, rv_fmt_rd_rs1_rs2, NULL, 0, 0, 0 }, 1554 { "sh3add", rv_codec_r, rv_fmt_rd_rs1_rs2, NULL, 0, 0, 0 }, 1555 { "sh1add.uw", rv_codec_r, rv_fmt_rd_rs1_rs2, NULL, 0, 0, 0 }, 1556 { "sh2add.uw", rv_codec_r, rv_fmt_rd_rs1_rs2, NULL, 0, 0, 0 }, 1557 { "sh3add.uw", rv_codec_r, rv_fmt_rd_rs1_rs2, NULL, 0, 0, 0 }, 1558 { "clmul", rv_codec_r, rv_fmt_rd_rs1_rs2, NULL, 0, 0, 0 }, 1559 { "clmulr", rv_codec_r, rv_fmt_rd_rs1_rs2, NULL, 0, 0, 0 }, 1560 { "clmulh", rv_codec_r, rv_fmt_rd_rs1_rs2, NULL, 0, 0, 0 }, 1561 { "min", rv_codec_r, rv_fmt_rd_rs1_rs2, NULL, 0, 0, 0 }, 1562 { "minu", rv_codec_r, rv_fmt_rd_rs1_rs2, NULL, 0, 0, 0 }, 1563 { "max", rv_codec_r, rv_fmt_rd_rs1_rs2, NULL, 0, 0, 0 }, 1564 { "maxu", rv_codec_r, rv_fmt_rd_rs1_rs2, NULL, 0, 0, 0 }, 1565 { "clzw", rv_codec_r, rv_fmt_rd_rs1, NULL, 0, 0, 0 }, 1566 { "ctzw", rv_codec_r, rv_fmt_rd_rs1, NULL, 0, 0, 0 }, 1567 { "cpopw", rv_codec_r, rv_fmt_rd_rs1, NULL, 0, 0, 0 }, 1568 { "slli.uw", rv_codec_i_sh6, rv_fmt_rd_rs1_imm, NULL, 0, 0, 0 }, 1569 { "add.uw", rv_codec_r, rv_fmt_rd_rs1_rs2, NULL, 0, 0, 0 }, 1570 { "rolw", rv_codec_r, rv_fmt_rd_rs1_rs2, NULL, 0, 0, 0 }, 1571 { "rorw", rv_codec_r, rv_fmt_rd_rs1_rs2, NULL, 0, 0, 0 }, 1572 { "rev8", rv_codec_r, rv_fmt_rd_rs1, NULL, 0, 0, 0 }, 1573 { "zext.h", rv_codec_r, rv_fmt_rd_rs1, NULL, 0, 0, 0 }, 1574 { "roriw", rv_codec_i_sh5, rv_fmt_rd_rs1_imm, NULL, 0, 0, 0 }, 1575 { "orc.b", rv_codec_r, rv_fmt_rd_rs1, NULL, 0, 0, 0 }, 1576 { "bset", rv_codec_r, rv_fmt_rd_rs1_rs2, NULL, 0, 0, 0 }, 1577 { "bclr", rv_codec_r, rv_fmt_rd_rs1_rs2, NULL, 0, 0, 0 }, 1578 { "binv", rv_codec_r, rv_fmt_rd_rs1_rs2, NULL, 0, 0, 0 }, 1579 { "bext", rv_codec_r, rv_fmt_rd_rs1_rs2, NULL, 0, 0, 0 }, 1580 { "aes32esmi", rv_codec_k_bs, rv_fmt_rs1_rs2_bs, NULL, 0, 0, 0 }, 1581 { "aes32esi", rv_codec_k_bs, rv_fmt_rs1_rs2_bs, NULL, 0, 0, 0 }, 1582 { "aes32dsmi", rv_codec_k_bs, rv_fmt_rs1_rs2_bs, NULL, 0, 0, 0 }, 1583 { "aes32dsi", rv_codec_k_bs, rv_fmt_rs1_rs2_bs, NULL, 0, 0, 0 }, 1584 { "aes64ks1i", rv_codec_k_rnum, rv_fmt_rd_rs1_rnum, NULL, 0, 0, 0 }, 1585 { "aes64ks2", rv_codec_r, rv_fmt_rd_rs1_rs2, NULL, 0, 0, 0 }, 1586 { "aes64im", rv_codec_r, rv_fmt_rd_rs1, NULL, 0, 0 }, 1587 { "aes64esm", rv_codec_r, rv_fmt_rd_rs1_rs2, NULL, 0, 0, 0 }, 1588 { "aes64es", rv_codec_r, rv_fmt_rd_rs1_rs2, NULL, 0, 0, 0 }, 1589 { "aes64dsm", rv_codec_r, rv_fmt_rd_rs1_rs2, NULL, 0, 0, 0 }, 1590 { "aes64ds", rv_codec_r, rv_fmt_rd_rs1_rs2, NULL, 0, 0, 0 }, 1591 { "sha256sig0", rv_codec_r, rv_fmt_rd_rs1, NULL, 0, 0 }, 1592 { "sha256sig1", rv_codec_r, rv_fmt_rd_rs1, NULL, 0, 0 }, 1593 { "sha256sum0", rv_codec_r, rv_fmt_rd_rs1, NULL, 0, 0 }, 1594 { "sha256sum1", rv_codec_r, rv_fmt_rd_rs1, NULL, 0, 0 }, 1595 { "sha512sig0", rv_codec_r, rv_fmt_rd_rs1_rs2, NULL, 0, 0, 0 }, 1596 { "sha512sig1", rv_codec_r, rv_fmt_rd_rs1_rs2, NULL, 0, 0, 0 }, 1597 { "sha512sum0", rv_codec_r, rv_fmt_rd_rs1_rs2, NULL, 0, 0, 0 }, 1598 { "sha512sum1", rv_codec_r, rv_fmt_rd_rs1_rs2, NULL, 0, 0, 0 }, 1599 { "sha512sum0r", rv_codec_r, rv_fmt_rd_rs1_rs2, NULL, 0, 0, 0 }, 1600 { "sha512sum1r", rv_codec_r, rv_fmt_rd_rs1_rs2, NULL, 0, 0, 0 }, 1601 { "sha512sig0l", rv_codec_r, rv_fmt_rd_rs1_rs2, NULL, 0, 0, 0 }, 1602 { "sha512sig0h", rv_codec_r, rv_fmt_rd_rs1_rs2, NULL, 0, 0, 0 }, 1603 { "sha512sig1l", rv_codec_r, rv_fmt_rd_rs1_rs2, NULL, 0, 0, 0 }, 1604 { "sha512sig1h", rv_codec_r, rv_fmt_rd_rs1_rs2, NULL, 0, 0, 0 }, 1605 { "sm3p0", rv_codec_r, rv_fmt_rd_rs1, NULL, 0, 0 }, 1606 { "sm3p1", rv_codec_r, rv_fmt_rd_rs1, NULL, 0, 0 }, 1607 { "sm4ed", rv_codec_k_bs, rv_fmt_rs1_rs2_bs, NULL, 0, 0, 0 }, 1608 { "sm4ks", rv_codec_k_bs, rv_fmt_rs1_rs2_bs, NULL, 0, 0, 0 }, 1609 { "brev8", rv_codec_r, rv_fmt_rd_rs1, NULL, 0, 0, 0 }, 1610 { "pack", rv_codec_r, rv_fmt_rd_rs1_rs2, NULL, 0, 0, 0 }, 1611 { "packh", rv_codec_r, rv_fmt_rd_rs1_rs2, NULL, 0, 0, 0 }, 1612 { "packw", rv_codec_r, rv_fmt_rd_rs1_rs2, NULL, 0, 0, 0 }, 1613 { "unzip", rv_codec_r, rv_fmt_rd_rs1, NULL, 0, 0, 0 }, 1614 { "zip", rv_codec_r, rv_fmt_rd_rs1, NULL, 0, 0, 0 }, 1615 { "xperm4", rv_codec_r, rv_fmt_rd_rs1_rs2, NULL, 0, 0, 0 }, 1616 { "xperm8", rv_codec_r, rv_fmt_rd_rs1, NULL, 0, 0, 0 }, 1617 { "vle8.v", rv_codec_v_ldst, rv_fmt_ldst_vd_rs1_vm, NULL, 0, 0, 0 }, 1618 { "vle16.v", rv_codec_v_ldst, rv_fmt_ldst_vd_rs1_vm, NULL, 0, 0, 0 }, 1619 { "vle32.v", rv_codec_v_ldst, rv_fmt_ldst_vd_rs1_vm, NULL, 0, 0, 0 }, 1620 { "vle64.v", rv_codec_v_ldst, rv_fmt_ldst_vd_rs1_vm, NULL, 0, 0, 0 }, 1621 { "vse8.v", rv_codec_v_ldst, rv_fmt_ldst_vd_rs1_vm, NULL, 0, 0, 0 }, 1622 { "vse16.v", rv_codec_v_ldst, rv_fmt_ldst_vd_rs1_vm, NULL, 0, 0, 0 }, 1623 { "vse32.v", rv_codec_v_ldst, rv_fmt_ldst_vd_rs1_vm, NULL, 0, 0, 0 }, 1624 { "vse64.v", rv_codec_v_ldst, rv_fmt_ldst_vd_rs1_vm, NULL, 0, 0, 0 }, 1625 { "vlm.v", rv_codec_v_ldst, rv_fmt_ldst_vd_rs1_vm, NULL, 0, 0, 0 }, 1626 { "vsm.v", rv_codec_v_ldst, rv_fmt_ldst_vd_rs1_vm, NULL, 0, 0, 0 }, 1627 { "vlse8.v", rv_codec_v_r, rv_fmt_ldst_vd_rs1_rs2_vm, NULL, 0, 0, 0 }, 1628 { "vlse16.v", rv_codec_v_r, rv_fmt_ldst_vd_rs1_rs2_vm, NULL, 0, 0, 0 }, 1629 { "vlse32.v", rv_codec_v_r, rv_fmt_ldst_vd_rs1_rs2_vm, NULL, 0, 0, 0 }, 1630 { "vlse64.v", rv_codec_v_r, rv_fmt_ldst_vd_rs1_rs2_vm, NULL, 0, 0, 0 }, 1631 { "vsse8.v", rv_codec_v_r, rv_fmt_ldst_vd_rs1_rs2_vm, NULL, 0, 0, 0 }, 1632 { "vsse16.v", rv_codec_v_r, rv_fmt_ldst_vd_rs1_rs2_vm, NULL, 0, 0, 0 }, 1633 { "vsse32.v", rv_codec_v_r, rv_fmt_ldst_vd_rs1_rs2_vm, NULL, 0, 0, 0 }, 1634 { "vsse64.v", rv_codec_v_r, rv_fmt_ldst_vd_rs1_rs2_vm, NULL, 0, 0, 0 }, 1635 { "vluxei8.v", rv_codec_v_r, rv_fmt_ldst_vd_rs1_vs2_vm, NULL, 0, 0, 0 }, 1636 { "vluxei16.v", rv_codec_v_r, rv_fmt_ldst_vd_rs1_vs2_vm, NULL, 0, 0, 0 }, 1637 { "vluxei32.v", rv_codec_v_r, rv_fmt_ldst_vd_rs1_vs2_vm, NULL, 0, 0, 0 }, 1638 { "vluxei64.v", rv_codec_v_r, rv_fmt_ldst_vd_rs1_vs2_vm, NULL, 0, 0, 0 }, 1639 { "vloxei8.v", rv_codec_v_r, rv_fmt_ldst_vd_rs1_vs2_vm, NULL, 0, 0, 0 }, 1640 { "vloxei16.v", rv_codec_v_r, rv_fmt_ldst_vd_rs1_vs2_vm, NULL, 0, 0, 0 }, 1641 { "vloxei32.v", rv_codec_v_r, rv_fmt_ldst_vd_rs1_vs2_vm, NULL, 0, 0, 0 }, 1642 { "vloxei64.v", rv_codec_v_r, rv_fmt_ldst_vd_rs1_vs2_vm, NULL, 0, 0, 0 }, 1643 { "vsuxei8.v", rv_codec_v_r, rv_fmt_ldst_vd_rs1_vs2_vm, NULL, 0, 0, 0 }, 1644 { "vsuxei16.v", rv_codec_v_r, rv_fmt_ldst_vd_rs1_vs2_vm, NULL, 0, 0, 0 }, 1645 { "vsuxei32.v", rv_codec_v_r, rv_fmt_ldst_vd_rs1_vs2_vm, NULL, 0, 0, 0 }, 1646 { "vsuxei64.v", rv_codec_v_r, rv_fmt_ldst_vd_rs1_vs2_vm, NULL, 0, 0, 0 }, 1647 { "vsoxei8.v", rv_codec_v_r, rv_fmt_ldst_vd_rs1_vs2_vm, NULL, 0, 0, 0 }, 1648 { "vsoxei16.v", rv_codec_v_r, rv_fmt_ldst_vd_rs1_vs2_vm, NULL, 0, 0, 0 }, 1649 { "vsoxei32.v", rv_codec_v_r, rv_fmt_ldst_vd_rs1_vs2_vm, NULL, 0, 0, 0 }, 1650 { "vsoxei64.v", rv_codec_v_r, rv_fmt_ldst_vd_rs1_vs2_vm, NULL, 0, 0, 0 }, 1651 { "vle8ff.v", rv_codec_v_ldst, rv_fmt_ldst_vd_rs1_vm, NULL, 0, 0, 0 }, 1652 { "vle16ff.v", rv_codec_v_ldst, rv_fmt_ldst_vd_rs1_vm, NULL, 0, 0, 0 }, 1653 { "vle32ff.v", rv_codec_v_ldst, rv_fmt_ldst_vd_rs1_vm, NULL, 0, 0, 0 }, 1654 { "vle64ff.v", rv_codec_v_ldst, rv_fmt_ldst_vd_rs1_vm, NULL, 0, 0, 0 }, 1655 { "vl1re8.v", rv_codec_v_ldst, rv_fmt_ldst_vd_rs1_vm, NULL, 0, 0, 0 }, 1656 { "vl1re16.v", rv_codec_v_ldst, rv_fmt_ldst_vd_rs1_vm, NULL, 0, 0, 0 }, 1657 { "vl1re32.v", rv_codec_v_ldst, rv_fmt_ldst_vd_rs1_vm, NULL, 0, 0, 0 }, 1658 { "vl1re64.v", rv_codec_v_ldst, rv_fmt_ldst_vd_rs1_vm, NULL, 0, 0, 0 }, 1659 { "vl2re8.v", rv_codec_v_ldst, rv_fmt_ldst_vd_rs1_vm, NULL, 0, 0, 0 }, 1660 { "vl2re16.v", rv_codec_v_ldst, rv_fmt_ldst_vd_rs1_vm, NULL, 0, 0, 0 }, 1661 { "vl2re32.v", rv_codec_v_ldst, rv_fmt_ldst_vd_rs1_vm, NULL, 0, 0, 0 }, 1662 { "vl2re64.v", rv_codec_v_ldst, rv_fmt_ldst_vd_rs1_vm, NULL, 0, 0, 0 }, 1663 { "vl4re8.v", rv_codec_v_ldst, rv_fmt_ldst_vd_rs1_vm, NULL, 0, 0, 0 }, 1664 { "vl4re16.v", rv_codec_v_ldst, rv_fmt_ldst_vd_rs1_vm, NULL, 0, 0, 0 }, 1665 { "vl4re32.v", rv_codec_v_ldst, rv_fmt_ldst_vd_rs1_vm, NULL, 0, 0, 0 }, 1666 { "vl4re64.v", rv_codec_v_ldst, rv_fmt_ldst_vd_rs1_vm, NULL, 0, 0, 0 }, 1667 { "vl8re8.v", rv_codec_v_ldst, rv_fmt_ldst_vd_rs1_vm, NULL, 0, 0, 0 }, 1668 { "vl8re16.v", rv_codec_v_ldst, rv_fmt_ldst_vd_rs1_vm, NULL, 0, 0, 0 }, 1669 { "vl8re32.v", rv_codec_v_ldst, rv_fmt_ldst_vd_rs1_vm, NULL, 0, 0, 0 }, 1670 { "vl8re64.v", rv_codec_v_ldst, rv_fmt_ldst_vd_rs1_vm, NULL, 0, 0, 0 }, 1671 { "vs1r.v", rv_codec_v_ldst, rv_fmt_ldst_vd_rs1_vm, NULL, 0, 0, 0 }, 1672 { "vs2r.v", rv_codec_v_ldst, rv_fmt_ldst_vd_rs1_vm, NULL, 0, 0, 0 }, 1673 { "vs4r.v", rv_codec_v_ldst, rv_fmt_ldst_vd_rs1_vm, NULL, 0, 0, 0 }, 1674 { "vs8r.v", rv_codec_v_ldst, rv_fmt_ldst_vd_rs1_vm, NULL, 0, 0, 0 }, 1675 { "vadd.vv", rv_codec_v_r, rv_fmt_vd_vs2_vs1_vm, NULL, 0, 0, 0 }, 1676 { "vadd.vx", rv_codec_v_r, rv_fmt_vd_vs2_rs1_vm, NULL, 0, 0, 0 }, 1677 { "vadd.vi", rv_codec_v_i, rv_fmt_vd_vs2_imm_vm, NULL, 0, 0, 0 }, 1678 { "vsub.vv", rv_codec_v_r, rv_fmt_vd_vs2_vs1_vm, NULL, 0, 0, 0 }, 1679 { "vsub.vx", rv_codec_v_r, rv_fmt_vd_vs2_rs1_vm, NULL, 0, 0, 0 }, 1680 { "vrsub.vx", rv_codec_v_r, rv_fmt_vd_vs2_rs1_vm, NULL, 0, 0, 0 }, 1681 { "vrsub.vi", rv_codec_v_i, rv_fmt_vd_vs2_imm_vm, NULL, 0, 0, 0 }, 1682 { "vwaddu.vv", rv_codec_v_r, rv_fmt_vd_vs2_vs1_vm, NULL, 0, 0, 0 }, 1683 { "vwaddu.vx", rv_codec_v_r, rv_fmt_vd_vs2_rs1_vm, NULL, 0, 0, 0 }, 1684 { "vwadd.vv", rv_codec_v_r, rv_fmt_vd_vs2_vs1_vm, NULL, 0, 0, 0 }, 1685 { "vwadd.vx", rv_codec_v_r, rv_fmt_vd_vs2_rs1_vm, NULL, 0, 0, 0 }, 1686 { "vwsubu.vv", rv_codec_v_r, rv_fmt_vd_vs2_vs1_vm, NULL, 0, 0, 0 }, 1687 { "vwsubu.vx", rv_codec_v_r, rv_fmt_vd_vs2_rs1_vm, NULL, 0, 0, 0 }, 1688 { "vwsub.vv", rv_codec_v_r, rv_fmt_vd_vs2_vs1_vm, NULL, 0, 0, 0 }, 1689 { "vwsub.vx", rv_codec_v_r, rv_fmt_vd_vs2_rs1_vm, NULL, 0, 0, 0 }, 1690 { "vwaddu.wv", rv_codec_v_r, rv_fmt_vd_vs2_vs1_vm, NULL, 0, 0, 0 }, 1691 { "vwaddu.wx", rv_codec_v_r, rv_fmt_vd_vs2_rs1_vm, NULL, 0, 0, 0 }, 1692 { "vwadd.wv", rv_codec_v_r, rv_fmt_vd_vs2_vs1_vm, NULL, 0, 0, 0 }, 1693 { "vwadd.wx", rv_codec_v_r, rv_fmt_vd_vs2_rs1_vm, NULL, 0, 0, 0 }, 1694 { "vwsubu.wv", rv_codec_v_r, rv_fmt_vd_vs2_vs1_vm, NULL, 0, 0, 0 }, 1695 { "vwsubu.wx", rv_codec_v_r, rv_fmt_vd_vs2_rs1_vm, NULL, 0, 0, 0 }, 1696 { "vwsub.wv", rv_codec_v_r, rv_fmt_vd_vs2_vs1_vm, NULL, 0, 0, 0 }, 1697 { "vwsub.wx", rv_codec_v_r, rv_fmt_vd_vs2_rs1_vm, NULL, 0, 0, 0 }, 1698 { "vadc.vvm", rv_codec_v_r, rv_fmt_vd_vs2_vs1_vl, NULL, 0, 0, 0 }, 1699 { "vadc.vxm", rv_codec_v_r, rv_fmt_vd_vs2_rs1_vl, NULL, 0, 0, 0 }, 1700 { "vadc.vim", rv_codec_v_i, rv_fmt_vd_vs2_imm_vl, NULL, 0, 0, 0 }, 1701 { "vmadc.vvm", rv_codec_v_r, rv_fmt_vd_vs2_vs1_vl, NULL, 0, 0, 0 }, 1702 { "vmadc.vxm", rv_codec_v_r, rv_fmt_vd_vs2_rs1_vl, NULL, 0, 0, 0 }, 1703 { "vmadc.vim", rv_codec_v_i, rv_fmt_vd_vs2_imm_vl, NULL, 0, 0, 0 }, 1704 { "vsbc.vvm", rv_codec_v_r, rv_fmt_vd_vs2_vs1_vl, NULL, 0, 0, 0 }, 1705 { "vsbc.vxm", rv_codec_v_r, rv_fmt_vd_vs2_rs1_vl, NULL, 0, 0, 0 }, 1706 { "vmsbc.vvm", rv_codec_v_r, rv_fmt_vd_vs2_vs1_vl, NULL, 0, 0, 0 }, 1707 { "vmsbc.vxm", rv_codec_v_r, rv_fmt_vd_vs2_rs1_vl, NULL, 0, 0, 0 }, 1708 { "vand.vv", rv_codec_v_r, rv_fmt_vd_vs2_vs1_vm, NULL, 0, 0, 0 }, 1709 { "vand.vx", rv_codec_v_r, rv_fmt_vd_vs2_rs1_vm, NULL, 0, 0, 0 }, 1710 { "vand.vi", rv_codec_v_i, rv_fmt_vd_vs2_imm_vm, NULL, 0, 0, 0 }, 1711 { "vor.vv", rv_codec_v_r, rv_fmt_vd_vs2_vs1_vm, NULL, 0, 0, 0 }, 1712 { "vor.vx", rv_codec_v_r, rv_fmt_vd_vs2_rs1_vm, NULL, 0, 0, 0 }, 1713 { "vor.vi", rv_codec_v_i, rv_fmt_vd_vs2_imm_vm, NULL, 0, 0, 0 }, 1714 { "vxor.vv", rv_codec_v_r, rv_fmt_vd_vs2_vs1_vm, NULL, 0, 0, 0 }, 1715 { "vxor.vx", rv_codec_v_r, rv_fmt_vd_vs2_rs1_vm, NULL, 0, 0, 0 }, 1716 { "vxor.vi", rv_codec_v_i, rv_fmt_vd_vs2_imm_vm, NULL, 0, 0, 0 }, 1717 { "vsll.vv", rv_codec_v_r, rv_fmt_vd_vs2_vs1_vm, NULL, 0, 0, 0 }, 1718 { "vsll.vx", rv_codec_v_r, rv_fmt_vd_vs2_rs1_vm, NULL, 0, 0, 0 }, 1719 { "vsll.vi", rv_codec_v_i, rv_fmt_vd_vs2_uimm_vm, NULL, 0, 0, 0 }, 1720 { "vsrl.vv", rv_codec_v_r, rv_fmt_vd_vs2_vs1_vm, NULL, 0, 0, 0 }, 1721 { "vsrl.vx", rv_codec_v_r, rv_fmt_vd_vs2_rs1_vm, NULL, 0, 0, 0 }, 1722 { "vsrl.vi", rv_codec_v_i, rv_fmt_vd_vs2_uimm_vm, NULL, 0, 0, 0 }, 1723 { "vsra.vv", rv_codec_v_r, rv_fmt_vd_vs2_vs1_vm, NULL, 0, 0, 0 }, 1724 { "vsra.vx", rv_codec_v_r, rv_fmt_vd_vs2_rs1_vm, NULL, 0, 0, 0 }, 1725 { "vsra.vi", rv_codec_v_i, rv_fmt_vd_vs2_uimm_vm, NULL, 0, 0, 0 }, 1726 { "vnsrl.wv", rv_codec_v_r, rv_fmt_vd_vs2_vs1_vm, NULL, 0, 0, 0 }, 1727 { "vnsrl.wx", rv_codec_v_r, rv_fmt_vd_vs2_rs1_vm, NULL, 0, 0, 0 }, 1728 { "vnsrl.wi", rv_codec_v_i, rv_fmt_vd_vs2_uimm_vm, NULL, 0, 0, 0 }, 1729 { "vnsra.wv", rv_codec_v_r, rv_fmt_vd_vs2_vs1_vm, NULL, 0, 0, 0 }, 1730 { "vnsra.wx", rv_codec_v_r, rv_fmt_vd_vs2_rs1_vm, NULL, 0, 0, 0 }, 1731 { "vnsra.wi", rv_codec_v_i, rv_fmt_vd_vs2_uimm_vm, NULL, 0, 0, 0 }, 1732 { "vmseq.vv", rv_codec_v_r, rv_fmt_vd_vs2_vs1_vm, NULL, 0, 0, 0 }, 1733 { "vmseq.vx", rv_codec_v_r, rv_fmt_vd_vs2_rs1_vm, NULL, 0, 0, 0 }, 1734 { "vmseq.vi", rv_codec_v_i, rv_fmt_vd_vs2_imm_vm, NULL, 0, 0, 0 }, 1735 { "vmsne.vv", rv_codec_v_r, rv_fmt_vd_vs2_vs1_vm, NULL, 0, 0, 0 }, 1736 { "vmsne.vx", rv_codec_v_r, rv_fmt_vd_vs2_rs1_vm, NULL, 0, 0, 0 }, 1737 { "vmsne.vi", rv_codec_v_i, rv_fmt_vd_vs2_imm_vm, NULL, 0, 0, 0 }, 1738 { "vmsltu.vv", rv_codec_v_r, rv_fmt_vd_vs2_vs1_vm, NULL, 0, 0, 0 }, 1739 { "vmsltu.vx", rv_codec_v_r, rv_fmt_vd_vs2_rs1_vm, NULL, 0, 0, 0 }, 1740 { "vmslt.vv", rv_codec_v_r, rv_fmt_vd_vs2_vs1_vm, NULL, 0, 0, 0 }, 1741 { "vmslt.vx", rv_codec_v_r, rv_fmt_vd_vs2_rs1_vm, NULL, 0, 0, 0 }, 1742 { "vmsleu.vv", rv_codec_v_r, rv_fmt_vd_vs2_vs1_vm, NULL, 0, 0, 0 }, 1743 { "vmsleu.vx", rv_codec_v_r, rv_fmt_vd_vs2_rs1_vm, NULL, 0, 0, 0 }, 1744 { "vmsleu.vi", rv_codec_v_i, rv_fmt_vd_vs2_imm_vm, NULL, 0, 0, 0 }, 1745 { "vmsle.vv", rv_codec_v_r, rv_fmt_vd_vs2_vs1_vm, NULL, 0, 0, 0 }, 1746 { "vmsle.vx", rv_codec_v_r, rv_fmt_vd_vs2_rs1_vm, NULL, 0, 0, 0 }, 1747 { "vmsle.vi", rv_codec_v_i, rv_fmt_vd_vs2_imm_vm, NULL, 0, 0, 0 }, 1748 { "vmsgtu.vx", rv_codec_v_r, rv_fmt_vd_vs2_rs1_vm, NULL, 0, 0, 0 }, 1749 { "vmsgtu.vi", rv_codec_v_i, rv_fmt_vd_vs2_imm_vm, NULL, 0, 0, 0 }, 1750 { "vmsgt.vx", rv_codec_v_r, rv_fmt_vd_vs2_rs1_vm, NULL, 0, 0, 0 }, 1751 { "vmsgt.vi", rv_codec_v_i, rv_fmt_vd_vs2_imm_vm, NULL, 0, 0, 0 }, 1752 { "vminu.vv", rv_codec_v_r, rv_fmt_vd_vs2_vs1_vm, NULL, 0, 0, 0 }, 1753 { "vminu.vx", rv_codec_v_r, rv_fmt_vd_vs2_rs1_vm, NULL, 0, 0, 0 }, 1754 { "vmin.vv", rv_codec_v_r, rv_fmt_vd_vs2_vs1_vm, NULL, 0, 0, 0 }, 1755 { "vmin.vx", rv_codec_v_r, rv_fmt_vd_vs2_rs1_vm, NULL, 0, 0, 0 }, 1756 { "vmaxu.vv", rv_codec_v_r, rv_fmt_vd_vs2_vs1_vm, NULL, 0, 0, 0 }, 1757 { "vmaxu.vx", rv_codec_v_r, rv_fmt_vd_vs2_rs1_vm, NULL, 0, 0, 0 }, 1758 { "vmax.vv", rv_codec_v_r, rv_fmt_vd_vs2_vs1_vm, NULL, 0, 0, 0 }, 1759 { "vmax.vx", rv_codec_v_r, rv_fmt_vd_vs2_rs1_vm, NULL, 0, 0, 0 }, 1760 { "vmul.vv", rv_codec_v_r, rv_fmt_vd_vs2_vs1_vm, NULL, 0, 0, 0 }, 1761 { "vmul.vx", rv_codec_v_r, rv_fmt_vd_vs2_rs1_vm, NULL, 0, 0, 0 }, 1762 { "vmulh.vv", rv_codec_v_r, rv_fmt_vd_vs2_vs1_vm, NULL, 0, 0, 0 }, 1763 { "vmulh.vx", rv_codec_v_r, rv_fmt_vd_vs2_rs1_vm, NULL, 0, 0, 0 }, 1764 { "vmulhu.vv", rv_codec_v_r, rv_fmt_vd_vs2_vs1_vm, NULL, 0, 0, 0 }, 1765 { "vmulhu.vx", rv_codec_v_r, rv_fmt_vd_vs2_rs1_vm, NULL, 0, 0, 0 }, 1766 { "vmulhsu.vv", rv_codec_v_r, rv_fmt_vd_vs2_vs1_vm, NULL, 0, 0, 0 }, 1767 { "vmulhsu.vx", rv_codec_v_r, rv_fmt_vd_vs2_rs1_vm, NULL, 0, 0, 0 }, 1768 { "vdivu.vv", rv_codec_v_r, rv_fmt_vd_vs2_vs1_vm, NULL, 0, 0, 0 }, 1769 { "vdivu.vx", rv_codec_v_r, rv_fmt_vd_vs2_rs1_vm, NULL, 0, 0, 0 }, 1770 { "vdiv.vv", rv_codec_v_r, rv_fmt_vd_vs2_vs1_vm, NULL, 0, 0, 0 }, 1771 { "vdiv.vx", rv_codec_v_r, rv_fmt_vd_vs2_rs1_vm, NULL, 0, 0, 0 }, 1772 { "vremu.vv", rv_codec_v_r, rv_fmt_vd_vs2_vs1_vm, NULL, 0, 0, 0 }, 1773 { "vremu.vx", rv_codec_v_r, rv_fmt_vd_vs2_rs1_vm, NULL, 0, 0, 0 }, 1774 { "vrem.vv", rv_codec_v_r, rv_fmt_vd_vs2_vs1_vm, NULL, 0, 0, 0 }, 1775 { "vrem.vx", rv_codec_v_r, rv_fmt_vd_vs2_rs1_vm, NULL, 0, 0, 0 }, 1776 { "vwmulu.vv", rv_codec_v_r, rv_fmt_vd_vs2_vs1_vm, NULL, 0, 0, 0 }, 1777 { "vwmulu.vx", rv_codec_v_r, rv_fmt_vd_vs2_rs1_vm, NULL, 0, 0, 0 }, 1778 { "vwmulsu.vv", rv_codec_v_r, rv_fmt_vd_vs2_vs1_vm, NULL, 0, 0, 0 }, 1779 { "vwmulsu.vx", rv_codec_v_r, rv_fmt_vd_vs2_rs1_vm, NULL, 0, 0, 0 }, 1780 { "vwmul.vv", rv_codec_v_r, rv_fmt_vd_vs2_vs1_vm, NULL, 0, 0, 0 }, 1781 { "vwmul.vx", rv_codec_v_r, rv_fmt_vd_vs2_rs1_vm, NULL, 0, 0, 0 }, 1782 { "vmacc.vv", rv_codec_v_r, rv_fmt_vd_vs1_vs2_vm, NULL, 0, 0, 0 }, 1783 { "vmacc.vx", rv_codec_v_r, rv_fmt_vd_rs1_vs2_vm, NULL, 0, 0, 0 }, 1784 { "vnmsac.vv", rv_codec_v_r, rv_fmt_vd_vs1_vs2_vm, NULL, 0, 0, 0 }, 1785 { "vnmsac.vx", rv_codec_v_r, rv_fmt_vd_rs1_vs2_vm, NULL, 0, 0, 0 }, 1786 { "vmadd.vv", rv_codec_v_r, rv_fmt_vd_vs1_vs2_vm, NULL, 0, 0, 0 }, 1787 { "vmadd.vx", rv_codec_v_r, rv_fmt_vd_rs1_vs2_vm, NULL, 0, 0, 0 }, 1788 { "vnmsub.vv", rv_codec_v_r, rv_fmt_vd_vs1_vs2_vm, NULL, 0, 0, 0 }, 1789 { "vnmsub.vx", rv_codec_v_r, rv_fmt_vd_rs1_vs2_vm, NULL, 0, 0, 0 }, 1790 { "vwmaccu.vv", rv_codec_v_r, rv_fmt_vd_vs1_vs2_vm, NULL, 0, 0, 0 }, 1791 { "vwmaccu.vx", rv_codec_v_r, rv_fmt_vd_rs1_vs2_vm, NULL, 0, 0, 0 }, 1792 { "vwmacc.vv", rv_codec_v_r, rv_fmt_vd_vs1_vs2_vm, NULL, 0, 0, 0 }, 1793 { "vwmacc.vx", rv_codec_v_r, rv_fmt_vd_rs1_vs2_vm, NULL, 0, 0, 0 }, 1794 { "vwmaccsu.vv", rv_codec_v_r, rv_fmt_vd_vs1_vs2_vm, NULL, 0, 0, 0 }, 1795 { "vwmaccsu.vx", rv_codec_v_r, rv_fmt_vd_rs1_vs2_vm, NULL, 0, 0, 0 }, 1796 { "vwmaccus.vx", rv_codec_v_r, rv_fmt_vd_rs1_vs2_vm, NULL, 0, 0, 0 }, 1797 { "vmv.v.v", rv_codec_v_r, rv_fmt_vd_vs1, NULL, 0, 0, 0 }, 1798 { "vmv.v.x", rv_codec_v_r, rv_fmt_vd_rs1, NULL, 0, 0, 0 }, 1799 { "vmv.v.i", rv_codec_v_i, rv_fmt_vd_imm, NULL, 0, 0, 0 }, 1800 { "vmerge.vvm", rv_codec_v_r, rv_fmt_vd_vs2_vs1_vl, NULL, 0, 0, 0 }, 1801 { "vmerge.vxm", rv_codec_v_r, rv_fmt_vd_vs2_rs1_vl, NULL, 0, 0, 0 }, 1802 { "vmerge.vim", rv_codec_v_i, rv_fmt_vd_vs2_imm_vl, NULL, 0, 0, 0 }, 1803 { "vsaddu.vv", rv_codec_v_r, rv_fmt_vd_vs2_vs1_vm, NULL, 0, 0, 0 }, 1804 { "vsaddu.vx", rv_codec_v_r, rv_fmt_vd_vs2_rs1_vm, NULL, 0, 0, 0 }, 1805 { "vsaddu.vi", rv_codec_v_i, rv_fmt_vd_vs2_imm_vm, NULL, 0, 0, 0 }, 1806 { "vsadd.vv", rv_codec_v_r, rv_fmt_vd_vs2_vs1_vm, NULL, 0, 0, 0 }, 1807 { "vsadd.vx", rv_codec_v_r, rv_fmt_vd_vs2_rs1_vm, NULL, 0, 0, 0 }, 1808 { "vsadd.vi", rv_codec_v_i, rv_fmt_vd_vs2_imm_vm, NULL, 0, 0, 0 }, 1809 { "vssubu.vv", rv_codec_v_r, rv_fmt_vd_vs2_vs1_vm, NULL, 0, 0, 0 }, 1810 { "vssubu.vx", rv_codec_v_r, rv_fmt_vd_vs2_rs1_vm, NULL, 0, 0, 0 }, 1811 { "vssub.vv", rv_codec_v_r, rv_fmt_vd_vs2_vs1_vm, NULL, 0, 0, 0 }, 1812 { "vssub.vx", rv_codec_v_r, rv_fmt_vd_vs2_rs1_vm, NULL, 0, 0, 0 }, 1813 { "vaadd.vv", rv_codec_v_r, rv_fmt_vd_vs2_vs1_vm, NULL, 0, 0, 0 }, 1814 { "vaadd.vx", rv_codec_v_r, rv_fmt_vd_vs2_rs1_vm, NULL, 0, 0, 0 }, 1815 { "vaaddu.vv", rv_codec_v_r, rv_fmt_vd_vs2_vs1_vm, NULL, 0, 0, 0 }, 1816 { "vaaddu.vx", rv_codec_v_r, rv_fmt_vd_vs2_rs1_vm, NULL, 0, 0, 0 }, 1817 { "vasub.vv", rv_codec_v_r, rv_fmt_vd_vs2_vs1_vm, NULL, 0, 0, 0 }, 1818 { "vasub.vx", rv_codec_v_r, rv_fmt_vd_vs2_rs1_vm, NULL, 0, 0, 0 }, 1819 { "vasubu.vv", rv_codec_v_r, rv_fmt_vd_vs2_vs1_vm, NULL, 0, 0, 0 }, 1820 { "vasubu.vx", rv_codec_v_r, rv_fmt_vd_vs2_rs1_vm, NULL, 0, 0, 0 }, 1821 { "vsmul.vv", rv_codec_v_r, rv_fmt_vd_vs2_vs1_vm, NULL, 0, 0, 0 }, 1822 { "vsmul.vx", rv_codec_v_r, rv_fmt_vd_vs2_rs1_vm, NULL, 0, 0, 0 }, 1823 { "vssrl.vv", rv_codec_v_r, rv_fmt_vd_vs2_vs1_vm, NULL, 0, 0, 0 }, 1824 { "vssrl.vx", rv_codec_v_r, rv_fmt_vd_vs2_rs1_vm, NULL, 0, 0, 0 }, 1825 { "vssrl.vi", rv_codec_v_i, rv_fmt_vd_vs2_uimm_vm, NULL, 0, 0, 0 }, 1826 { "vssra.vv", rv_codec_v_r, rv_fmt_vd_vs2_vs1_vm, NULL, 0, 0, 0 }, 1827 { "vssra.vx", rv_codec_v_r, rv_fmt_vd_vs2_rs1_vm, NULL, 0, 0, 0 }, 1828 { "vssra.vi", rv_codec_v_i, rv_fmt_vd_vs2_uimm_vm, NULL, 0, 0, 0 }, 1829 { "vnclipu.wv", rv_codec_v_r, rv_fmt_vd_vs2_vs1_vm, NULL, 0, 0, 0 }, 1830 { "vnclipu.wx", rv_codec_v_r, rv_fmt_vd_vs2_rs1_vm, NULL, 0, 0, 0 }, 1831 { "vnclipu.wi", rv_codec_v_i, rv_fmt_vd_vs2_uimm_vm, NULL, 0, 0, 0 }, 1832 { "vnclip.wv", rv_codec_v_r, rv_fmt_vd_vs2_vs1_vm, NULL, 0, 0, 0 }, 1833 { "vnclip.wx", rv_codec_v_r, rv_fmt_vd_vs2_rs1_vm, NULL, 0, 0, 0 }, 1834 { "vnclip.wi", rv_codec_v_i, rv_fmt_vd_vs2_uimm_vm, NULL, 0, 0, 0 }, 1835 { "vfadd.vv", rv_codec_v_r, rv_fmt_vd_vs2_vs1_vm, NULL, 0, 0, 0 }, 1836 { "vfadd.vf", rv_codec_v_r, rv_fmt_vd_vs2_fs1_vm, NULL, 0, 0, 0 }, 1837 { "vfsub.vv", rv_codec_v_r, rv_fmt_vd_vs2_vs1_vm, NULL, 0, 0, 0 }, 1838 { "vfsub.vf", rv_codec_v_r, rv_fmt_vd_vs2_fs1_vm, NULL, 0, 0, 0 }, 1839 { "vfrsub.vf", rv_codec_v_r, rv_fmt_vd_vs2_fs1_vm, NULL, 0, 0, 0 }, 1840 { "vfwadd.vv", rv_codec_v_r, rv_fmt_vd_vs2_vs1_vm, NULL, 0, 0, 0 }, 1841 { "vfwadd.vf", rv_codec_v_r, rv_fmt_vd_vs2_fs1_vm, NULL, 0, 0, 0 }, 1842 { "vfwadd.wv", rv_codec_v_r, rv_fmt_vd_vs2_vs1_vm, NULL, 0, 0, 0 }, 1843 { "vfwadd.wf", rv_codec_v_r, rv_fmt_vd_vs2_fs1_vm, NULL, 0, 0, 0 }, 1844 { "vfwsub.vv", rv_codec_v_r, rv_fmt_vd_vs2_vs1_vm, NULL, 0, 0, 0 }, 1845 { "vfwsub.vf", rv_codec_v_r, rv_fmt_vd_vs2_fs1_vm, NULL, 0, 0, 0 }, 1846 { "vfwsub.wv", rv_codec_v_r, rv_fmt_vd_vs2_vs1_vm, NULL, 0, 0, 0 }, 1847 { "vfwsub.wf", rv_codec_v_r, rv_fmt_vd_vs2_fs1_vm, NULL, 0, 0, 0 }, 1848 { "vfmul.vv", rv_codec_v_r, rv_fmt_vd_vs2_vs1_vm, NULL, 0, 0, 0 }, 1849 { "vfmul.vf", rv_codec_v_r, rv_fmt_vd_vs2_fs1_vm, NULL, 0, 0, 0 }, 1850 { "vfdiv.vv", rv_codec_v_r, rv_fmt_vd_vs2_vs1_vm, NULL, 0, 0, 0 }, 1851 { "vfdiv.vf", rv_codec_v_r, rv_fmt_vd_vs2_fs1_vm, NULL, 0, 0, 0 }, 1852 { "vfrdiv.vf", rv_codec_v_r, rv_fmt_vd_vs2_fs1_vm, NULL, 0, 0, 0 }, 1853 { "vfwmul.vv", rv_codec_v_r, rv_fmt_vd_vs2_vs1_vm, NULL, 0, 0, 0 }, 1854 { "vfwmul.vf", rv_codec_v_r, rv_fmt_vd_vs2_fs1_vm, NULL, 0, 0, 0 }, 1855 { "vfmacc.vv", rv_codec_v_r, rv_fmt_vd_vs1_vs2_vm, NULL, 0, 0, 0 }, 1856 { "vfmacc.vf", rv_codec_v_r, rv_fmt_vd_fs1_vs2_vm, NULL, 0, 0, 0 }, 1857 { "vfnmacc.vv", rv_codec_v_r, rv_fmt_vd_vs1_vs2_vm, NULL, 0, 0, 0 }, 1858 { "vfnmacc.vf", rv_codec_v_r, rv_fmt_vd_fs1_vs2_vm, NULL, 0, 0, 0 }, 1859 { "vfmsac.vv", rv_codec_v_r, rv_fmt_vd_vs1_vs2_vm, NULL, 0, 0, 0 }, 1860 { "vfmsac.vf", rv_codec_v_r, rv_fmt_vd_fs1_vs2_vm, NULL, 0, 0, 0 }, 1861 { "vfnmsac.vv", rv_codec_v_r, rv_fmt_vd_vs1_vs2_vm, NULL, 0, 0, 0 }, 1862 { "vfnmsac.vf", rv_codec_v_r, rv_fmt_vd_fs1_vs2_vm, NULL, 0, 0, 0 }, 1863 { "vfmadd.vv", rv_codec_v_r, rv_fmt_vd_vs1_vs2_vm, NULL, 0, 0, 0 }, 1864 { "vfmadd.vf", rv_codec_v_r, rv_fmt_vd_fs1_vs2_vm, NULL, 0, 0, 0 }, 1865 { "vfnmadd.vv", rv_codec_v_r, rv_fmt_vd_vs1_vs2_vm, NULL, 0, 0, 0 }, 1866 { "vfnmadd.vf", rv_codec_v_r, rv_fmt_vd_fs1_vs2_vm, NULL, 0, 0, 0 }, 1867 { "vfmsub.vv", rv_codec_v_r, rv_fmt_vd_vs1_vs2_vm, NULL, 0, 0, 0 }, 1868 { "vfmsub.vf", rv_codec_v_r, rv_fmt_vd_fs1_vs2_vm, NULL, 0, 0, 0 }, 1869 { "vfnmsub.vv", rv_codec_v_r, rv_fmt_vd_vs1_vs2_vm, NULL, 0, 0, 0 }, 1870 { "vfnmsub.vf", rv_codec_v_r, rv_fmt_vd_fs1_vs2_vm, NULL, 0, 0, 0 }, 1871 { "vfwmacc.vv", rv_codec_v_r, rv_fmt_vd_vs1_vs2_vm, NULL, 0, 0, 0 }, 1872 { "vfwmacc.vf", rv_codec_v_r, rv_fmt_vd_fs1_vs2_vm, NULL, 0, 0, 0 }, 1873 { "vfwnmacc.vv", rv_codec_v_r, rv_fmt_vd_vs1_vs2_vm, NULL, 0, 0, 0 }, 1874 { "vfwnmacc.vf", rv_codec_v_r, rv_fmt_vd_fs1_vs2_vm, NULL, 0, 0, 0 }, 1875 { "vfwmsac.vv", rv_codec_v_r, rv_fmt_vd_vs1_vs2_vm, NULL, 0, 0, 0 }, 1876 { "vfwmsac.vf", rv_codec_v_r, rv_fmt_vd_fs1_vs2_vm, NULL, 0, 0, 0 }, 1877 { "vfwnmsac.vv", rv_codec_v_r, rv_fmt_vd_vs1_vs2_vm, NULL, 0, 0, 0 }, 1878 { "vfwnmsac.vf", rv_codec_v_r, rv_fmt_vd_fs1_vs2_vm, NULL, 0, 0, 0 }, 1879 { "vfsqrt.v", rv_codec_v_r, rv_fmt_vd_vs2, NULL, 0, 0, 0 }, 1880 { "vfrsqrt7.v", rv_codec_v_r, rv_fmt_vd_vs2, NULL, 0, 0, 0 }, 1881 { "vfrec7.v", rv_codec_v_r, rv_fmt_vd_vs2, NULL, 0, 0, 0 }, 1882 { "vfmin.vv", rv_codec_v_r, rv_fmt_vd_vs2_vs1_vm, NULL, 0, 0, 0 }, 1883 { "vfmin.vf", rv_codec_v_r, rv_fmt_vd_vs2_fs1_vm, NULL, 0, 0, 0 }, 1884 { "vfmax.vv", rv_codec_v_r, rv_fmt_vd_vs2_vs1_vm, NULL, 0, 0, 0 }, 1885 { "vfmax.vf", rv_codec_v_r, rv_fmt_vd_vs2_fs1_vm, NULL, 0, 0, 0 }, 1886 { "vfsgnj.vv", rv_codec_v_r, rv_fmt_vd_vs2_vs1_vm, NULL, 0, 0, 0 }, 1887 { "vfsgnj.vf", rv_codec_v_r, rv_fmt_vd_vs2_fs1_vm, NULL, 0, 0, 0 }, 1888 { "vfsgnjn.vv", rv_codec_v_r, rv_fmt_vd_vs2_vs1_vm, NULL, 0, 0, 0 }, 1889 { "vfsgnjn.vf", rv_codec_v_r, rv_fmt_vd_vs2_fs1_vm, NULL, 0, 0, 0 }, 1890 { "vfsgnjx.vv", rv_codec_v_r, rv_fmt_vd_vs2_vs1_vm, NULL, 0, 0, 0 }, 1891 { "vfsgnjx.vf", rv_codec_v_r, rv_fmt_vd_vs2_fs1_vm, NULL, 0, 0, 0 }, 1892 { "vfslide1up.vf", rv_codec_v_r, rv_fmt_vd_vs2_fs1_vm, NULL, 0, 0, 0 }, 1893 { "vfslide1down.vf", rv_codec_v_r, rv_fmt_vd_vs2_fs1_vm, NULL, 0, 0, 0 }, 1894 { "vmfeq.vv", rv_codec_v_r, rv_fmt_vd_vs2_vs1_vm, NULL, 0, 0, 0 }, 1895 { "vmfeq.vf", rv_codec_v_r, rv_fmt_vd_vs2_fs1_vm, NULL, 0, 0, 0 }, 1896 { "vmfne.vv", rv_codec_v_r, rv_fmt_vd_vs2_vs1_vm, NULL, 0, 0, 0 }, 1897 { "vmfne.vf", rv_codec_v_r, rv_fmt_vd_vs2_fs1_vm, NULL, 0, 0, 0 }, 1898 { "vmflt.vv", rv_codec_v_r, rv_fmt_vd_vs2_vs1_vm, NULL, 0, 0, 0 }, 1899 { "vmflt.vf", rv_codec_v_r, rv_fmt_vd_vs2_fs1_vm, NULL, 0, 0, 0 }, 1900 { "vmfle.vv", rv_codec_v_r, rv_fmt_vd_vs2_vs1_vm, NULL, 0, 0, 0 }, 1901 { "vmfle.vf", rv_codec_v_r, rv_fmt_vd_vs2_fs1_vm, NULL, 0, 0, 0 }, 1902 { "vmfgt.vf", rv_codec_v_r, rv_fmt_vd_vs2_fs1_vm, NULL, 0, 0, 0 }, 1903 { "vmfge.vf", rv_codec_v_r, rv_fmt_vd_vs2_fs1_vm, NULL, 0, 0, 0 }, 1904 { "vfclass.v", rv_codec_v_r, rv_fmt_vd_vs2_vm, NULL, 0, 0, 0 }, 1905 { "vfmerge.vfm", rv_codec_v_r, rv_fmt_vd_vs2_fs1_vl, NULL, 0, 0, 0 }, 1906 { "vfmv.v.f", rv_codec_v_r, rv_fmt_vd_fs1, NULL, 0, 0, 0 }, 1907 { "vfcvt.xu.f.v", rv_codec_v_r, rv_fmt_vd_vs2_vm, NULL, 0, 0, 0 }, 1908 { "vfcvt.x.f.v", rv_codec_v_r, rv_fmt_vd_vs2_vm, NULL, 0, 0, 0 }, 1909 { "vfcvt.f.xu.v", rv_codec_v_r, rv_fmt_vd_vs2_vm, NULL, 0, 0, 0 }, 1910 { "vfcvt.f.x.v", rv_codec_v_r, rv_fmt_vd_vs2_vm, NULL, 0, 0, 0 }, 1911 { "vfcvt.rtz.xu.f.v", rv_codec_v_r, rv_fmt_vd_vs2_vm, NULL, 0, 0, 0 }, 1912 { "vfcvt.rtz.x.f.v", rv_codec_v_r, rv_fmt_vd_vs2_vm, NULL, 0, 0, 0 }, 1913 { "vfwcvt.xu.f.v", rv_codec_v_r, rv_fmt_vd_vs2_vm, NULL, 0, 0, 0 }, 1914 { "vfwcvt.x.f.v", rv_codec_v_r, rv_fmt_vd_vs2_vm, NULL, 0, 0, 0 }, 1915 { "vfwcvt.f.xu.v", rv_codec_v_r, rv_fmt_vd_vs2_vm, NULL, 0, 0, 0 }, 1916 { "vfwcvt.f.x.v", rv_codec_v_r, rv_fmt_vd_vs2_vm, NULL, 0, 0, 0 }, 1917 { "vfwcvt.f.f.v", rv_codec_v_r, rv_fmt_vd_vs2_vm, NULL, 0, 0, 0 }, 1918 { "vfwcvt.rtz.xu.f.v", rv_codec_v_r, rv_fmt_vd_vs2_vm, NULL, 0, 0, 0 }, 1919 { "vfwcvt.rtz.x.f.v", rv_codec_v_r, rv_fmt_vd_vs2_vm, NULL, 0, 0, 0 }, 1920 { "vfncvt.xu.f.w", rv_codec_v_r, rv_fmt_vd_vs2_vm, NULL, 0, 0, 0 }, 1921 { "vfncvt.x.f.w", rv_codec_v_r, rv_fmt_vd_vs2_vm, NULL, 0, 0, 0 }, 1922 { "vfncvt.f.xu.w", rv_codec_v_r, rv_fmt_vd_vs2_vm, NULL, 0, 0, 0 }, 1923 { "vfncvt.f.x.w", rv_codec_v_r, rv_fmt_vd_vs2_vm, NULL, 0, 0, 0 }, 1924 { "vfncvt.f.f.w", rv_codec_v_r, rv_fmt_vd_vs2_vm, NULL, 0, 0, 0 }, 1925 { "vfncvt.rod.f.f.w", rv_codec_v_r, rv_fmt_vd_vs2_vm, NULL, 0, 0, 0 }, 1926 { "vfncvt.rtz.xu.f.w", rv_codec_v_r, rv_fmt_vd_vs2_vm, NULL, 0, 0, 0 }, 1927 { "vfncvt.rtz.x.f.w", rv_codec_v_r, rv_fmt_vd_vs2_vm, NULL, 0, 0, 0 }, 1928 { "vredsum.vs", rv_codec_v_r, rv_fmt_vd_vs2_vs1_vm, NULL, 0, 0, 0 }, 1929 { "vredand.vs", rv_codec_v_r, rv_fmt_vd_vs2_vs1_vm, NULL, 0, 0, 0 }, 1930 { "vredor.vs", rv_codec_v_r, rv_fmt_vd_vs2_vs1_vm, NULL, 0, 0, 0 }, 1931 { "vredxor.vs", rv_codec_v_r, rv_fmt_vd_vs2_vs1_vm, NULL, 0, 0, 0 }, 1932 { "vredminu.vs", rv_codec_v_r, rv_fmt_vd_vs2_vs1_vm, NULL, 0, 0, 0 }, 1933 { "vredmin.vs", rv_codec_v_r, rv_fmt_vd_vs2_vs1_vm, NULL, 0, 0, 0 }, 1934 { "vredmaxu.vs", rv_codec_v_r, rv_fmt_vd_vs2_vs1_vm, NULL, 0, 0, 0 }, 1935 { "vredmax.vs", rv_codec_v_r, rv_fmt_vd_vs2_vs1_vm, NULL, 0, 0, 0 }, 1936 { "vwredsumu.vs", rv_codec_v_r, rv_fmt_vd_vs2_vs1_vm, NULL, 0, 0, 0 }, 1937 { "vwredsum.vs", rv_codec_v_r, rv_fmt_vd_vs2_vs1_vm, NULL, 0, 0, 0 }, 1938 { "vfredusum.vs", rv_codec_v_r, rv_fmt_vd_vs2_vs1_vm, NULL, 0, 0, 0 }, 1939 { "vfredosum.vs", rv_codec_v_r, rv_fmt_vd_vs2_vs1_vm, NULL, 0, 0, 0 }, 1940 { "vfredmin.vs", rv_codec_v_r, rv_fmt_vd_vs2_vs1_vm, NULL, 0, 0, 0 }, 1941 { "vfredmax.vs", rv_codec_v_r, rv_fmt_vd_vs2_vs1_vm, NULL, 0, 0, 0 }, 1942 { "vfwredusum.vs", rv_codec_v_r, rv_fmt_vd_vs2_vs1_vm, NULL, 0, 0, 0 }, 1943 { "vfwredosum.vs", rv_codec_v_r, rv_fmt_vd_vs2_vs1_vm, NULL, 0, 0, 0 }, 1944 { "vmand.mm", rv_codec_v_r, rv_fmt_vd_vs2_vs1_vm, NULL, 0, 0, 0 }, 1945 { "vmnand.mm", rv_codec_v_r, rv_fmt_vd_vs2_vs1_vm, NULL, 0, 0, 0 }, 1946 { "vmandn.mm", rv_codec_v_r, rv_fmt_vd_vs2_vs1_vm, NULL, 0, 0, 0 }, 1947 { "vmxor.mm", rv_codec_v_r, rv_fmt_vd_vs2_vs1_vm, NULL, 0, 0, 0 }, 1948 { "vmor.mm", rv_codec_v_r, rv_fmt_vd_vs2_vs1_vm, NULL, 0, 0, 0 }, 1949 { "vmnor.mm", rv_codec_v_r, rv_fmt_vd_vs2_vs1_vm, NULL, 0, 0, 0 }, 1950 { "vmorn.mm", rv_codec_v_r, rv_fmt_vd_vs2_vs1_vm, NULL, 0, 0, 0 }, 1951 { "vmxnor.mm", rv_codec_v_r, rv_fmt_vd_vs2_vs1_vm, NULL, 0, 0, 0 }, 1952 { "vcpop.m", rv_codec_v_r, rv_fmt_rd_vs2_vm, NULL, 0, 0, 0 }, 1953 { "vfirst.m", rv_codec_v_r, rv_fmt_rd_vs2_vm, NULL, 0, 0, 0 }, 1954 { "vmsbf.m", rv_codec_v_r, rv_fmt_vd_vs2_vm, NULL, 0, 0, 0 }, 1955 { "vmsif.m", rv_codec_v_r, rv_fmt_vd_vs2_vm, NULL, 0, 0, 0 }, 1956 { "vmsof.m", rv_codec_v_r, rv_fmt_vd_vs2_vm, NULL, 0, 0, 0 }, 1957 { "viota.m", rv_codec_v_r, rv_fmt_vd_vs2_vm, NULL, 0, 0, 0 }, 1958 { "vid.v", rv_codec_v_r, rv_fmt_vd_vm, NULL, 0, 0, 0 }, 1959 { "vmv.x.s", rv_codec_v_r, rv_fmt_rd_vs2, NULL, 0, 0, 0 }, 1960 { "vmv.s.x", rv_codec_v_r, rv_fmt_vd_rs1, NULL, 0, 0, 0 }, 1961 { "vfmv.f.s", rv_codec_v_r, rv_fmt_fd_vs2, NULL, 0, 0, 0 }, 1962 { "vfmv.s.f", rv_codec_v_r, rv_fmt_vd_fs1, NULL, 0, 0, 0 }, 1963 { "vslideup.vx", rv_codec_v_r, rv_fmt_vd_vs2_rs1_vm, NULL, 0, 0, 0 }, 1964 { "vslideup.vi", rv_codec_v_i, rv_fmt_vd_vs2_uimm_vm, NULL, 0, 0, 0 }, 1965 { "vslide1up.vx", rv_codec_v_r, rv_fmt_vd_vs2_rs1_vm, NULL, 0, 0, 0 }, 1966 { "vslidedown.vx", rv_codec_v_r, rv_fmt_vd_vs2_rs1_vm, NULL, 0, 0, 0 }, 1967 { "vslidedown.vi", rv_codec_v_i, rv_fmt_vd_vs2_uimm_vm, NULL, 0, 0, 0 }, 1968 { "vslide1down.vx", rv_codec_v_r, rv_fmt_vd_vs2_rs1_vm, NULL, 0, 0, 0 }, 1969 { "vrgather.vv", rv_codec_v_r, rv_fmt_vd_vs2_vs1_vm, NULL, 0, 0, 0 }, 1970 { "vrgatherei16.vv", rv_codec_v_r, rv_fmt_vd_vs2_vs1_vm, NULL, 0, 0, 0 }, 1971 { "vrgather.vx", rv_codec_v_r, rv_fmt_vd_vs2_rs1_vm, NULL, 0, 0, 0 }, 1972 { "vrgather.vi", rv_codec_v_i, rv_fmt_vd_vs2_uimm_vm, NULL, 0, 0, 0 }, 1973 { "vcompress.vm", rv_codec_v_r, rv_fmt_vd_vs2_vs1, NULL, 0, 0, 0 }, 1974 { "vmv1r.v", rv_codec_v_r, rv_fmt_vd_vs2, NULL, 0, 0, 0 }, 1975 { "vmv2r.v", rv_codec_v_r, rv_fmt_vd_vs2, NULL, 0, 0, 0 }, 1976 { "vmv4r.v", rv_codec_v_r, rv_fmt_vd_vs2, NULL, 0, 0, 0 }, 1977 { "vmv8r.v", rv_codec_v_r, rv_fmt_vd_vs2, NULL, 0, 0, 0 }, 1978 { "vzext.vf2", rv_codec_v_r, rv_fmt_vd_vs2_vm, NULL, 0, 0, 0 }, 1979 { "vzext.vf4", rv_codec_v_r, rv_fmt_vd_vs2_vm, NULL, 0, 0, 0 }, 1980 { "vzext.vf8", rv_codec_v_r, rv_fmt_vd_vs2_vm, NULL, 0, 0, 0 }, 1981 { "vsext.vf2", rv_codec_v_r, rv_fmt_vd_vs2_vm, NULL, 0, 0, 0 }, 1982 { "vsext.vf4", rv_codec_v_r, rv_fmt_vd_vs2_vm, NULL, 0, 0, 0 }, 1983 { "vsext.vf8", rv_codec_v_r, rv_fmt_vd_vs2_vm, NULL, 0, 0, 0 }, 1984 { "vsetvli", rv_codec_vsetvli, rv_fmt_vsetvli, NULL, 0, 0, 0 }, 1985 { "vsetivli", rv_codec_vsetivli, rv_fmt_vsetivli, NULL, 0, 0, 0 }, 1986 { "vsetvl", rv_codec_r, rv_fmt_rd_rs1_rs2, NULL, 0, 0, 0 }, 1987 { "c.zext.b", rv_codec_zcb_ext, rv_fmt_rd, NULL, 0 }, 1988 { "c.sext.b", rv_codec_zcb_ext, rv_fmt_rd, NULL, 0 }, 1989 { "c.zext.h", rv_codec_zcb_ext, rv_fmt_rd, NULL, 0 }, 1990 { "c.sext.h", rv_codec_zcb_ext, rv_fmt_rd, NULL, 0 }, 1991 { "c.zext.w", rv_codec_zcb_ext, rv_fmt_rd, NULL, 0 }, 1992 { "c.not", rv_codec_zcb_ext, rv_fmt_rd, NULL, 0 }, 1993 { "c.mul", rv_codec_zcb_mul, rv_fmt_rd_rs2, NULL, 0, 0 }, 1994 { "c.lbu", rv_codec_zcb_lb, rv_fmt_rs1_rs2_zce_ldst, NULL, 0, 0, 0 }, 1995 { "c.lhu", rv_codec_zcb_lh, rv_fmt_rs1_rs2_zce_ldst, NULL, 0, 0, 0 }, 1996 { "c.lh", rv_codec_zcb_lh, rv_fmt_rs1_rs2_zce_ldst, NULL, 0, 0, 0 }, 1997 { "c.sb", rv_codec_zcb_lb, rv_fmt_rs1_rs2_zce_ldst, NULL, 0, 0, 0 }, 1998 { "c.sh", rv_codec_zcb_lh, rv_fmt_rs1_rs2_zce_ldst, NULL, 0, 0, 0 }, 1999 { "cm.push", rv_codec_zcmp_cm_pushpop, rv_fmt_push_rlist, NULL, 0, 0 }, 2000 { "cm.pop", rv_codec_zcmp_cm_pushpop, rv_fmt_pop_rlist, NULL, 0, 0 }, 2001 { "cm.popret", rv_codec_zcmp_cm_pushpop, rv_fmt_pop_rlist, NULL, 0, 0, 0 }, 2002 { "cm.popretz", rv_codec_zcmp_cm_pushpop, rv_fmt_pop_rlist, NULL, 0, 0 }, 2003 { "cm.mva01s", rv_codec_zcmp_cm_mv, rv_fmt_rd_rs2, NULL, 0, 0, 0 }, 2004 { "cm.mvsa01", rv_codec_zcmp_cm_mv, rv_fmt_rd_rs2, NULL, 0, 0, 0 }, 2005 { "cm.jt", rv_codec_zcmt_jt, rv_fmt_zcmt_index, NULL, 0 }, 2006 { "cm.jalt", rv_codec_zcmt_jt, rv_fmt_zcmt_index, NULL, 0 }, 2007 { "czero.eqz", rv_codec_r, rv_fmt_rd_rs1_rs2, NULL, 0, 0, 0 }, 2008 { "czero.nez", rv_codec_r, rv_fmt_rd_rs1_rs2, NULL, 0, 0, 0 }, 2009 { "fcvt.bf16.s", rv_codec_r_m, rv_fmt_rm_frd_frs1, NULL, 0, 0, 0 }, 2010 { "fcvt.s.bf16", rv_codec_r_m, rv_fmt_rm_frd_frs1, NULL, 0, 0, 0 }, 2011 { "vfncvtbf16.f.f.w", rv_codec_v_r, rv_fmt_vd_vs2_vm, NULL, 0, 0, 0 }, 2012 { "vfwcvtbf16.f.f.v", rv_codec_v_r, rv_fmt_vd_vs2_vm, NULL, 0, 0, 0 }, 2013 { "vfwmaccbf16.vv", rv_codec_v_r, rv_fmt_vd_vs1_vs2_vm, NULL, 0, 0, 0 }, 2014 { "vfwmaccbf16.vf", rv_codec_v_r, rv_fmt_vd_fs1_vs2_vm, NULL, 0, 0, 0 }, 2015 { "flh", rv_codec_i, rv_fmt_frd_offset_rs1, NULL, 0, 0, 0 }, 2016 { "fsh", rv_codec_s, rv_fmt_frs2_offset_rs1, NULL, 0, 0, 0 }, 2017 { "fmv.h.x", rv_codec_r, rv_fmt_frd_rs1, NULL, 0, 0, 0 }, 2018 { "fmv.x.h", rv_codec_r, rv_fmt_rd_frs1, NULL, 0, 0, 0 }, 2019 { "fli.s", rv_codec_fli, rv_fmt_fli, NULL, 0, 0, 0 }, 2020 { "fli.d", rv_codec_fli, rv_fmt_fli, NULL, 0, 0, 0 }, 2021 { "fli.q", rv_codec_fli, rv_fmt_fli, NULL, 0, 0, 0 }, 2022 { "fli.h", rv_codec_fli, rv_fmt_fli, NULL, 0, 0, 0 }, 2023 { "fminm.s", rv_codec_r, rv_fmt_frd_frs1_frs2, NULL, 0, 0, 0 }, 2024 { "fmaxm.s", rv_codec_r, rv_fmt_frd_frs1_frs2, NULL, 0, 0, 0 }, 2025 { "fminm.d", rv_codec_r, rv_fmt_frd_frs1_frs2, NULL, 0, 0, 0 }, 2026 { "fmaxm.d", rv_codec_r, rv_fmt_frd_frs1_frs2, NULL, 0, 0, 0 }, 2027 { "fminm.q", rv_codec_r, rv_fmt_frd_frs1_frs2, NULL, 0, 0, 0 }, 2028 { "fmaxm.q", rv_codec_r, rv_fmt_frd_frs1_frs2, NULL, 0, 0, 0 }, 2029 { "fminm.h", rv_codec_r, rv_fmt_frd_frs1_frs2, NULL, 0, 0, 0 }, 2030 { "fmaxm.h", rv_codec_r, rv_fmt_frd_frs1_frs2, NULL, 0, 0, 0 }, 2031 { "fround.s", rv_codec_r_m, rv_fmt_rm_frd_frs1, NULL, 0, 0, 0 }, 2032 { "froundnx.s", rv_codec_r_m, rv_fmt_rm_frd_frs1, NULL, 0, 0, 0 }, 2033 { "fround.d", rv_codec_r_m, rv_fmt_rm_frd_frs1, NULL, 0, 0, 0 }, 2034 { "froundnx.d", rv_codec_r_m, rv_fmt_rm_frd_frs1, NULL, 0, 0, 0 }, 2035 { "fround.q", rv_codec_r_m, rv_fmt_rm_frd_frs1, NULL, 0, 0, 0 }, 2036 { "froundnx.q", rv_codec_r_m, rv_fmt_rm_frd_frs1, NULL, 0, 0, 0 }, 2037 { "fround.h", rv_codec_r_m, rv_fmt_rm_frd_frs1, NULL, 0, 0, 0 }, 2038 { "froundnx.h", rv_codec_r_m, rv_fmt_rm_frd_frs1, NULL, 0, 0, 0 }, 2039 { "fcvtmod.w.d", rv_codec_r_m, rv_fmt_rm_rd_frs1, NULL, 0, 0, 0 }, 2040 { "fmvh.x.d", rv_codec_r, rv_fmt_rd_frs1, NULL, 0, 0, 0 }, 2041 { "fmvp.d.x", rv_codec_r, rv_fmt_frd_rs1_rs2, NULL, 0, 0, 0 }, 2042 { "fmvh.x.q", rv_codec_r, rv_fmt_rd_frs1, NULL, 0, 0, 0 }, 2043 { "fmvp.q.x", rv_codec_r, rv_fmt_frd_rs1_rs2, NULL, 0, 0, 0 }, 2044 { "fleq.s", rv_codec_r, rv_fmt_rd_frs1_frs2, NULL, 0, 0, 0 }, 2045 { "fltq.s", rv_codec_r, rv_fmt_rd_frs1_frs2, NULL, 0, 0, 0 }, 2046 { "fleq.d", rv_codec_r, rv_fmt_rd_frs1_frs2, NULL, 0, 0, 0 }, 2047 { "fltq.d", rv_codec_r, rv_fmt_rd_frs1_frs2, NULL, 0, 0, 0 }, 2048 { "fleq.q", rv_codec_r, rv_fmt_rd_frs1_frs2, NULL, 0, 0, 0 }, 2049 { "fltq.q", rv_codec_r, rv_fmt_rd_frs1_frs2, NULL, 0, 0, 0 }, 2050 { "fleq.h", rv_codec_r, rv_fmt_rd_frs1_frs2, NULL, 0, 0, 0 }, 2051 { "fltq.h", rv_codec_r, rv_fmt_rd_frs1_frs2, NULL, 0, 0, 0 }, 2052 { "vaesdf.vv", rv_codec_v_r, rv_fmt_vd_vs2, NULL, 0, 0, 0 }, 2053 { "vaesdf.vs", rv_codec_v_r, rv_fmt_vd_vs2, NULL, 0, 0, 0 }, 2054 { "vaesdm.vv", rv_codec_v_r, rv_fmt_vd_vs2, NULL, 0, 0, 0 }, 2055 { "vaesdm.vs", rv_codec_v_r, rv_fmt_vd_vs2, NULL, 0, 0, 0 }, 2056 { "vaesef.vv", rv_codec_v_r, rv_fmt_vd_vs2, NULL, 0, 0, 0 }, 2057 { "vaesef.vs", rv_codec_v_r, rv_fmt_vd_vs2, NULL, 0, 0, 0 }, 2058 { "vaesem.vv", rv_codec_v_r, rv_fmt_vd_vs2, NULL, 0, 0, 0 }, 2059 { "vaesem.vs", rv_codec_v_r, rv_fmt_vd_vs2, NULL, 0, 0, 0 }, 2060 { "vaeskf1.vi", rv_codec_v_i, rv_fmt_vd_vs2_uimm, NULL, 0, 0, 0 }, 2061 { "vaeskf2.vi", rv_codec_v_i, rv_fmt_vd_vs2_uimm, NULL, 0, 0, 0 }, 2062 { "vaesz.vs", rv_codec_v_r, rv_fmt_vd_vs2, NULL, 0, 0, 0 }, 2063 { "vandn.vv", rv_codec_v_r, rv_fmt_vd_vs2_vs1_vm, NULL, 0, 0, 0 }, 2064 { "vandn.vx", rv_codec_v_r, rv_fmt_vd_vs2_rs1_vm, NULL, 0, 0, 0 }, 2065 { "vbrev.v", rv_codec_v_r, rv_fmt_vd_vs2_vm, NULL, 0, 0, 0 }, 2066 { "vbrev8.v", rv_codec_v_r, rv_fmt_vd_vs2_vm, NULL, 0, 0, 0 }, 2067 { "vclmul.vv", rv_codec_v_r, rv_fmt_vd_vs2_vs1_vm, NULL, 0, 0, 0 }, 2068 { "vclmul.vx", rv_codec_v_r, rv_fmt_vd_vs2_rs1_vm, NULL, 0, 0, 0 }, 2069 { "vclmulh.vv", rv_codec_v_r, rv_fmt_vd_vs2_vs1_vm, NULL, 0, 0, 0 }, 2070 { "vclmulh.vx", rv_codec_v_r, rv_fmt_vd_vs2_rs1_vm, NULL, 0, 0, 0 }, 2071 { "vclz.v", rv_codec_v_r, rv_fmt_vd_vs2_vm, NULL, 0, 0, 0 }, 2072 { "vcpop.v", rv_codec_v_r, rv_fmt_vd_vs2_vm, NULL, 0, 0, 0 }, 2073 { "vctz.v", rv_codec_v_r, rv_fmt_vd_vs2_vm, NULL, 0, 0, 0 }, 2074 { "vghsh.vv", rv_codec_v_r, rv_fmt_vd_vs2_vs1, NULL, 0, 0, 0 }, 2075 { "vgmul.vv", rv_codec_v_r, rv_fmt_vd_vs2, NULL, 0, 0, 0 }, 2076 { "vrev8.v", rv_codec_v_r, rv_fmt_vd_vs2_vm, NULL, 0, 0, 0 }, 2077 { "vrol.vv", rv_codec_v_r, rv_fmt_vd_vs2_vs1_vm, NULL, 0, 0, 0 }, 2078 { "vrol.vx", rv_codec_v_r, rv_fmt_vd_vs2_rs1_vm, NULL, 0, 0, 0 }, 2079 { "vror.vv", rv_codec_v_r, rv_fmt_vd_vs2_vs1_vm, NULL, 0, 0, 0 }, 2080 { "vror.vx", rv_codec_v_r, rv_fmt_vd_vs2_rs1_vm, NULL, 0, 0, 0 }, 2081 { "vror.vi", rv_codec_vror_vi, rv_fmt_vd_vs2_uimm_vm, NULL, 0, 0, 0 }, 2082 { "vsha2ch.vv", rv_codec_v_r, rv_fmt_vd_vs2_vs1, NULL, 0, 0, 0 }, 2083 { "vsha2cl.vv", rv_codec_v_r, rv_fmt_vd_vs2_vs1, NULL, 0, 0, 0 }, 2084 { "vsha2ms.vv", rv_codec_v_r, rv_fmt_vd_vs2_vs1, NULL, 0, 0, 0 }, 2085 { "vsm3c.vi", rv_codec_v_i, rv_fmt_vd_vs2_uimm, NULL, 0, 0, 0 }, 2086 { "vsm3me.vv", rv_codec_v_r, rv_fmt_vd_vs2_vs1, NULL, 0, 0, 0 }, 2087 { "vsm4k.vi", rv_codec_v_i, rv_fmt_vd_vs2_uimm, NULL, 0, 0, 0 }, 2088 { "vsm4r.vv", rv_codec_v_r, rv_fmt_vd_vs2, NULL, 0, 0, 0 }, 2089 { "vsm4r.vs", rv_codec_v_r, rv_fmt_vd_vs2, NULL, 0, 0, 0 }, 2090 { "vwsll.vv", rv_codec_v_r, rv_fmt_vd_vs2_vs1_vm, NULL, 0, 0, 0 }, 2091 { "vwsll.vx", rv_codec_v_r, rv_fmt_vd_vs2_rs1_vm, NULL, 0, 0, 0 }, 2092 { "vwsll.vi", rv_codec_v_i, rv_fmt_vd_vs2_uimm_vm, NULL, 0, 0, 0 }, 2093 }; 2094 2095 /* CSR names */ 2096 2097 static const char *csr_name(int csrno) 2098 { 2099 switch (csrno) { 2100 case 0x0000: return "ustatus"; 2101 case 0x0001: return "fflags"; 2102 case 0x0002: return "frm"; 2103 case 0x0003: return "fcsr"; 2104 case 0x0004: return "uie"; 2105 case 0x0005: return "utvec"; 2106 case 0x0008: return "vstart"; 2107 case 0x0009: return "vxsat"; 2108 case 0x000a: return "vxrm"; 2109 case 0x000f: return "vcsr"; 2110 case 0x0015: return "seed"; 2111 case 0x0017: return "jvt"; 2112 case 0x0040: return "uscratch"; 2113 case 0x0041: return "uepc"; 2114 case 0x0042: return "ucause"; 2115 case 0x0043: return "utval"; 2116 case 0x0044: return "uip"; 2117 case 0x0100: return "sstatus"; 2118 case 0x0104: return "sie"; 2119 case 0x0105: return "stvec"; 2120 case 0x0106: return "scounteren"; 2121 case 0x0140: return "sscratch"; 2122 case 0x0141: return "sepc"; 2123 case 0x0142: return "scause"; 2124 case 0x0143: return "stval"; 2125 case 0x0144: return "sip"; 2126 case 0x0180: return "satp"; 2127 case 0x0200: return "hstatus"; 2128 case 0x0202: return "hedeleg"; 2129 case 0x0203: return "hideleg"; 2130 case 0x0204: return "hie"; 2131 case 0x0205: return "htvec"; 2132 case 0x0240: return "hscratch"; 2133 case 0x0241: return "hepc"; 2134 case 0x0242: return "hcause"; 2135 case 0x0243: return "hbadaddr"; 2136 case 0x0244: return "hip"; 2137 case 0x0300: return "mstatus"; 2138 case 0x0301: return "misa"; 2139 case 0x0302: return "medeleg"; 2140 case 0x0303: return "mideleg"; 2141 case 0x0304: return "mie"; 2142 case 0x0305: return "mtvec"; 2143 case 0x0306: return "mcounteren"; 2144 case 0x0320: return "mucounteren"; 2145 case 0x0321: return "mscounteren"; 2146 case 0x0322: return "mhcounteren"; 2147 case 0x0323: return "mhpmevent3"; 2148 case 0x0324: return "mhpmevent4"; 2149 case 0x0325: return "mhpmevent5"; 2150 case 0x0326: return "mhpmevent6"; 2151 case 0x0327: return "mhpmevent7"; 2152 case 0x0328: return "mhpmevent8"; 2153 case 0x0329: return "mhpmevent9"; 2154 case 0x032a: return "mhpmevent10"; 2155 case 0x032b: return "mhpmevent11"; 2156 case 0x032c: return "mhpmevent12"; 2157 case 0x032d: return "mhpmevent13"; 2158 case 0x032e: return "mhpmevent14"; 2159 case 0x032f: return "mhpmevent15"; 2160 case 0x0330: return "mhpmevent16"; 2161 case 0x0331: return "mhpmevent17"; 2162 case 0x0332: return "mhpmevent18"; 2163 case 0x0333: return "mhpmevent19"; 2164 case 0x0334: return "mhpmevent20"; 2165 case 0x0335: return "mhpmevent21"; 2166 case 0x0336: return "mhpmevent22"; 2167 case 0x0337: return "mhpmevent23"; 2168 case 0x0338: return "mhpmevent24"; 2169 case 0x0339: return "mhpmevent25"; 2170 case 0x033a: return "mhpmevent26"; 2171 case 0x033b: return "mhpmevent27"; 2172 case 0x033c: return "mhpmevent28"; 2173 case 0x033d: return "mhpmevent29"; 2174 case 0x033e: return "mhpmevent30"; 2175 case 0x033f: return "mhpmevent31"; 2176 case 0x0340: return "mscratch"; 2177 case 0x0341: return "mepc"; 2178 case 0x0342: return "mcause"; 2179 case 0x0343: return "mtval"; 2180 case 0x0344: return "mip"; 2181 case 0x0380: return "mbase"; 2182 case 0x0381: return "mbound"; 2183 case 0x0382: return "mibase"; 2184 case 0x0383: return "mibound"; 2185 case 0x0384: return "mdbase"; 2186 case 0x0385: return "mdbound"; 2187 case 0x03a0: return "pmpcfg3"; 2188 case 0x03b0: return "pmpaddr0"; 2189 case 0x03b1: return "pmpaddr1"; 2190 case 0x03b2: return "pmpaddr2"; 2191 case 0x03b3: return "pmpaddr3"; 2192 case 0x03b4: return "pmpaddr4"; 2193 case 0x03b5: return "pmpaddr5"; 2194 case 0x03b6: return "pmpaddr6"; 2195 case 0x03b7: return "pmpaddr7"; 2196 case 0x03b8: return "pmpaddr8"; 2197 case 0x03b9: return "pmpaddr9"; 2198 case 0x03ba: return "pmpaddr10"; 2199 case 0x03bb: return "pmpaddr11"; 2200 case 0x03bc: return "pmpaddr12"; 2201 case 0x03bd: return "pmpaddr13"; 2202 case 0x03be: return "pmpaddr14"; 2203 case 0x03bf: return "pmpaddr15"; 2204 case 0x0780: return "mtohost"; 2205 case 0x0781: return "mfromhost"; 2206 case 0x0782: return "mreset"; 2207 case 0x0783: return "mipi"; 2208 case 0x0784: return "miobase"; 2209 case 0x07a0: return "tselect"; 2210 case 0x07a1: return "tdata1"; 2211 case 0x07a2: return "tdata2"; 2212 case 0x07a3: return "tdata3"; 2213 case 0x07b0: return "dcsr"; 2214 case 0x07b1: return "dpc"; 2215 case 0x07b2: return "dscratch"; 2216 case 0x0b00: return "mcycle"; 2217 case 0x0b01: return "mtime"; 2218 case 0x0b02: return "minstret"; 2219 case 0x0b03: return "mhpmcounter3"; 2220 case 0x0b04: return "mhpmcounter4"; 2221 case 0x0b05: return "mhpmcounter5"; 2222 case 0x0b06: return "mhpmcounter6"; 2223 case 0x0b07: return "mhpmcounter7"; 2224 case 0x0b08: return "mhpmcounter8"; 2225 case 0x0b09: return "mhpmcounter9"; 2226 case 0x0b0a: return "mhpmcounter10"; 2227 case 0x0b0b: return "mhpmcounter11"; 2228 case 0x0b0c: return "mhpmcounter12"; 2229 case 0x0b0d: return "mhpmcounter13"; 2230 case 0x0b0e: return "mhpmcounter14"; 2231 case 0x0b0f: return "mhpmcounter15"; 2232 case 0x0b10: return "mhpmcounter16"; 2233 case 0x0b11: return "mhpmcounter17"; 2234 case 0x0b12: return "mhpmcounter18"; 2235 case 0x0b13: return "mhpmcounter19"; 2236 case 0x0b14: return "mhpmcounter20"; 2237 case 0x0b15: return "mhpmcounter21"; 2238 case 0x0b16: return "mhpmcounter22"; 2239 case 0x0b17: return "mhpmcounter23"; 2240 case 0x0b18: return "mhpmcounter24"; 2241 case 0x0b19: return "mhpmcounter25"; 2242 case 0x0b1a: return "mhpmcounter26"; 2243 case 0x0b1b: return "mhpmcounter27"; 2244 case 0x0b1c: return "mhpmcounter28"; 2245 case 0x0b1d: return "mhpmcounter29"; 2246 case 0x0b1e: return "mhpmcounter30"; 2247 case 0x0b1f: return "mhpmcounter31"; 2248 case 0x0b80: return "mcycleh"; 2249 case 0x0b81: return "mtimeh"; 2250 case 0x0b82: return "minstreth"; 2251 case 0x0b83: return "mhpmcounter3h"; 2252 case 0x0b84: return "mhpmcounter4h"; 2253 case 0x0b85: return "mhpmcounter5h"; 2254 case 0x0b86: return "mhpmcounter6h"; 2255 case 0x0b87: return "mhpmcounter7h"; 2256 case 0x0b88: return "mhpmcounter8h"; 2257 case 0x0b89: return "mhpmcounter9h"; 2258 case 0x0b8a: return "mhpmcounter10h"; 2259 case 0x0b8b: return "mhpmcounter11h"; 2260 case 0x0b8c: return "mhpmcounter12h"; 2261 case 0x0b8d: return "mhpmcounter13h"; 2262 case 0x0b8e: return "mhpmcounter14h"; 2263 case 0x0b8f: return "mhpmcounter15h"; 2264 case 0x0b90: return "mhpmcounter16h"; 2265 case 0x0b91: return "mhpmcounter17h"; 2266 case 0x0b92: return "mhpmcounter18h"; 2267 case 0x0b93: return "mhpmcounter19h"; 2268 case 0x0b94: return "mhpmcounter20h"; 2269 case 0x0b95: return "mhpmcounter21h"; 2270 case 0x0b96: return "mhpmcounter22h"; 2271 case 0x0b97: return "mhpmcounter23h"; 2272 case 0x0b98: return "mhpmcounter24h"; 2273 case 0x0b99: return "mhpmcounter25h"; 2274 case 0x0b9a: return "mhpmcounter26h"; 2275 case 0x0b9b: return "mhpmcounter27h"; 2276 case 0x0b9c: return "mhpmcounter28h"; 2277 case 0x0b9d: return "mhpmcounter29h"; 2278 case 0x0b9e: return "mhpmcounter30h"; 2279 case 0x0b9f: return "mhpmcounter31h"; 2280 case 0x0c00: return "cycle"; 2281 case 0x0c01: return "time"; 2282 case 0x0c02: return "instret"; 2283 case 0x0c20: return "vl"; 2284 case 0x0c21: return "vtype"; 2285 case 0x0c22: return "vlenb"; 2286 case 0x0c80: return "cycleh"; 2287 case 0x0c81: return "timeh"; 2288 case 0x0c82: return "instreth"; 2289 case 0x0d00: return "scycle"; 2290 case 0x0d01: return "stime"; 2291 case 0x0d02: return "sinstret"; 2292 case 0x0d80: return "scycleh"; 2293 case 0x0d81: return "stimeh"; 2294 case 0x0d82: return "sinstreth"; 2295 case 0x0e00: return "hcycle"; 2296 case 0x0e01: return "htime"; 2297 case 0x0e02: return "hinstret"; 2298 case 0x0e80: return "hcycleh"; 2299 case 0x0e81: return "htimeh"; 2300 case 0x0e82: return "hinstreth"; 2301 case 0x0f11: return "mvendorid"; 2302 case 0x0f12: return "marchid"; 2303 case 0x0f13: return "mimpid"; 2304 case 0x0f14: return "mhartid"; 2305 default: return NULL; 2306 } 2307 } 2308 2309 /* decode opcode */ 2310 2311 static void decode_inst_opcode(rv_decode *dec, rv_isa isa) 2312 { 2313 rv_inst inst = dec->inst; 2314 rv_opcode op = rv_op_illegal; 2315 switch ((inst >> 0) & 0b11) { 2316 case 0: 2317 switch ((inst >> 13) & 0b111) { 2318 case 0: op = rv_op_c_addi4spn; break; 2319 case 1: 2320 if (isa == rv128) { 2321 op = rv_op_c_lq; 2322 } else { 2323 op = rv_op_c_fld; 2324 } 2325 break; 2326 case 2: op = rv_op_c_lw; break; 2327 case 3: 2328 if (isa == rv32) { 2329 op = rv_op_c_flw; 2330 } else { 2331 op = rv_op_c_ld; 2332 } 2333 break; 2334 case 4: 2335 switch ((inst >> 10) & 0b111) { 2336 case 0: op = rv_op_c_lbu; break; 2337 case 1: 2338 if (((inst >> 6) & 1) == 0) { 2339 op = rv_op_c_lhu; 2340 } else { 2341 op = rv_op_c_lh; 2342 } 2343 break; 2344 case 2: op = rv_op_c_sb; break; 2345 case 3: 2346 if (((inst >> 6) & 1) == 0) { 2347 op = rv_op_c_sh; 2348 } 2349 break; 2350 } 2351 break; 2352 case 5: 2353 if (isa == rv128) { 2354 op = rv_op_c_sq; 2355 } else { 2356 op = rv_op_c_fsd; 2357 } 2358 break; 2359 case 6: op = rv_op_c_sw; break; 2360 case 7: 2361 if (isa == rv32) { 2362 op = rv_op_c_fsw; 2363 } else { 2364 op = rv_op_c_sd; 2365 } 2366 break; 2367 } 2368 break; 2369 case 1: 2370 switch ((inst >> 13) & 0b111) { 2371 case 0: 2372 switch ((inst >> 2) & 0b11111111111) { 2373 case 0: op = rv_op_c_nop; break; 2374 default: op = rv_op_c_addi; break; 2375 } 2376 break; 2377 case 1: 2378 if (isa == rv32) { 2379 op = rv_op_c_jal; 2380 } else { 2381 op = rv_op_c_addiw; 2382 } 2383 break; 2384 case 2: op = rv_op_c_li; break; 2385 case 3: 2386 switch ((inst >> 7) & 0b11111) { 2387 case 2: op = rv_op_c_addi16sp; break; 2388 default: op = rv_op_c_lui; break; 2389 } 2390 break; 2391 case 4: 2392 switch ((inst >> 10) & 0b11) { 2393 case 0: 2394 op = rv_op_c_srli; 2395 break; 2396 case 1: 2397 op = rv_op_c_srai; 2398 break; 2399 case 2: op = rv_op_c_andi; break; 2400 case 3: 2401 switch (((inst >> 10) & 0b100) | ((inst >> 5) & 0b011)) { 2402 case 0: op = rv_op_c_sub; break; 2403 case 1: op = rv_op_c_xor; break; 2404 case 2: op = rv_op_c_or; break; 2405 case 3: op = rv_op_c_and; break; 2406 case 4: op = rv_op_c_subw; break; 2407 case 5: op = rv_op_c_addw; break; 2408 case 6: op = rv_op_c_mul; break; 2409 case 7: 2410 switch ((inst >> 2) & 0b111) { 2411 case 0: op = rv_op_c_zext_b; break; 2412 case 1: op = rv_op_c_sext_b; break; 2413 case 2: op = rv_op_c_zext_h; break; 2414 case 3: op = rv_op_c_sext_h; break; 2415 case 4: op = rv_op_c_zext_w; break; 2416 case 5: op = rv_op_c_not; break; 2417 } 2418 break; 2419 } 2420 break; 2421 } 2422 break; 2423 case 5: op = rv_op_c_j; break; 2424 case 6: op = rv_op_c_beqz; break; 2425 case 7: op = rv_op_c_bnez; break; 2426 } 2427 break; 2428 case 2: 2429 switch ((inst >> 13) & 0b111) { 2430 case 0: 2431 op = rv_op_c_slli; 2432 break; 2433 case 1: 2434 if (isa == rv128) { 2435 op = rv_op_c_lqsp; 2436 } else { 2437 op = rv_op_c_fldsp; 2438 } 2439 break; 2440 case 2: op = rv_op_c_lwsp; break; 2441 case 3: 2442 if (isa == rv32) { 2443 op = rv_op_c_flwsp; 2444 } else { 2445 op = rv_op_c_ldsp; 2446 } 2447 break; 2448 case 4: 2449 switch ((inst >> 12) & 0b1) { 2450 case 0: 2451 switch ((inst >> 2) & 0b11111) { 2452 case 0: op = rv_op_c_jr; break; 2453 default: op = rv_op_c_mv; break; 2454 } 2455 break; 2456 case 1: 2457 switch ((inst >> 2) & 0b11111) { 2458 case 0: 2459 switch ((inst >> 7) & 0b11111) { 2460 case 0: op = rv_op_c_ebreak; break; 2461 default: op = rv_op_c_jalr; break; 2462 } 2463 break; 2464 default: op = rv_op_c_add; break; 2465 } 2466 break; 2467 } 2468 break; 2469 case 5: 2470 if (isa == rv128) { 2471 op = rv_op_c_sqsp; 2472 } else { 2473 op = rv_op_c_fsdsp; 2474 if (dec->cfg->ext_zcmp && ((inst >> 12) & 0b01)) { 2475 switch ((inst >> 8) & 0b01111) { 2476 case 8: 2477 if (((inst >> 4) & 0b01111) >= 4) { 2478 op = rv_op_cm_push; 2479 } 2480 break; 2481 case 10: 2482 if (((inst >> 4) & 0b01111) >= 4) { 2483 op = rv_op_cm_pop; 2484 } 2485 break; 2486 case 12: 2487 if (((inst >> 4) & 0b01111) >= 4) { 2488 op = rv_op_cm_popretz; 2489 } 2490 break; 2491 case 14: 2492 if (((inst >> 4) & 0b01111) >= 4) { 2493 op = rv_op_cm_popret; 2494 } 2495 break; 2496 } 2497 } else { 2498 switch ((inst >> 10) & 0b011) { 2499 case 0: 2500 if (!dec->cfg->ext_zcmt) { 2501 break; 2502 } 2503 if (((inst >> 2) & 0xFF) >= 32) { 2504 op = rv_op_cm_jalt; 2505 } else { 2506 op = rv_op_cm_jt; 2507 } 2508 break; 2509 case 3: 2510 if (!dec->cfg->ext_zcmp) { 2511 break; 2512 } 2513 switch ((inst >> 5) & 0b011) { 2514 case 1: op = rv_op_cm_mvsa01; break; 2515 case 3: op = rv_op_cm_mva01s; break; 2516 } 2517 break; 2518 } 2519 } 2520 } 2521 break; 2522 case 6: op = rv_op_c_swsp; break; 2523 case 7: 2524 if (isa == rv32) { 2525 op = rv_op_c_fswsp; 2526 } else { 2527 op = rv_op_c_sdsp; 2528 } 2529 break; 2530 } 2531 break; 2532 case 3: 2533 switch ((inst >> 2) & 0b11111) { 2534 case 0: 2535 switch ((inst >> 12) & 0b111) { 2536 case 0: op = rv_op_lb; break; 2537 case 1: op = rv_op_lh; break; 2538 case 2: op = rv_op_lw; break; 2539 case 3: op = rv_op_ld; break; 2540 case 4: op = rv_op_lbu; break; 2541 case 5: op = rv_op_lhu; break; 2542 case 6: op = rv_op_lwu; break; 2543 case 7: op = rv_op_ldu; break; 2544 } 2545 break; 2546 case 1: 2547 switch ((inst >> 12) & 0b111) { 2548 case 0: 2549 switch ((inst >> 20) & 0b111111111111) { 2550 case 40: op = rv_op_vl1re8_v; break; 2551 case 552: op = rv_op_vl2re8_v; break; 2552 case 1576: op = rv_op_vl4re8_v; break; 2553 case 3624: op = rv_op_vl8re8_v; break; 2554 } 2555 switch ((inst >> 26) & 0b111) { 2556 case 0: 2557 switch ((inst >> 20) & 0b11111) { 2558 case 0: op = rv_op_vle8_v; break; 2559 case 11: op = rv_op_vlm_v; break; 2560 case 16: op = rv_op_vle8ff_v; break; 2561 } 2562 break; 2563 case 1: op = rv_op_vluxei8_v; break; 2564 case 2: op = rv_op_vlse8_v; break; 2565 case 3: op = rv_op_vloxei8_v; break; 2566 } 2567 break; 2568 case 1: op = rv_op_flh; break; 2569 case 2: op = rv_op_flw; break; 2570 case 3: op = rv_op_fld; break; 2571 case 4: op = rv_op_flq; break; 2572 case 5: 2573 switch ((inst >> 20) & 0b111111111111) { 2574 case 40: op = rv_op_vl1re16_v; break; 2575 case 552: op = rv_op_vl2re16_v; break; 2576 case 1576: op = rv_op_vl4re16_v; break; 2577 case 3624: op = rv_op_vl8re16_v; break; 2578 } 2579 switch ((inst >> 26) & 0b111) { 2580 case 0: 2581 switch ((inst >> 20) & 0b11111) { 2582 case 0: op = rv_op_vle16_v; break; 2583 case 16: op = rv_op_vle16ff_v; break; 2584 } 2585 break; 2586 case 1: op = rv_op_vluxei16_v; break; 2587 case 2: op = rv_op_vlse16_v; break; 2588 case 3: op = rv_op_vloxei16_v; break; 2589 } 2590 break; 2591 case 6: 2592 switch ((inst >> 20) & 0b111111111111) { 2593 case 40: op = rv_op_vl1re32_v; break; 2594 case 552: op = rv_op_vl2re32_v; break; 2595 case 1576: op = rv_op_vl4re32_v; break; 2596 case 3624: op = rv_op_vl8re32_v; break; 2597 } 2598 switch ((inst >> 26) & 0b111) { 2599 case 0: 2600 switch ((inst >> 20) & 0b11111) { 2601 case 0: op = rv_op_vle32_v; break; 2602 case 16: op = rv_op_vle32ff_v; break; 2603 } 2604 break; 2605 case 1: op = rv_op_vluxei32_v; break; 2606 case 2: op = rv_op_vlse32_v; break; 2607 case 3: op = rv_op_vloxei32_v; break; 2608 } 2609 break; 2610 case 7: 2611 switch ((inst >> 20) & 0b111111111111) { 2612 case 40: op = rv_op_vl1re64_v; break; 2613 case 552: op = rv_op_vl2re64_v; break; 2614 case 1576: op = rv_op_vl4re64_v; break; 2615 case 3624: op = rv_op_vl8re64_v; break; 2616 } 2617 switch ((inst >> 26) & 0b111) { 2618 case 0: 2619 switch ((inst >> 20) & 0b11111) { 2620 case 0: op = rv_op_vle64_v; break; 2621 case 16: op = rv_op_vle64ff_v; break; 2622 } 2623 break; 2624 case 1: op = rv_op_vluxei64_v; break; 2625 case 2: op = rv_op_vlse64_v; break; 2626 case 3: op = rv_op_vloxei64_v; break; 2627 } 2628 break; 2629 } 2630 break; 2631 case 3: 2632 switch ((inst >> 12) & 0b111) { 2633 case 0: op = rv_op_fence; break; 2634 case 1: op = rv_op_fence_i; break; 2635 case 2: op = rv_op_lq; break; 2636 } 2637 break; 2638 case 4: 2639 switch ((inst >> 12) & 0b111) { 2640 case 0: op = rv_op_addi; break; 2641 case 1: 2642 switch ((inst >> 27) & 0b11111) { 2643 case 0b00000: op = rv_op_slli; break; 2644 case 0b00001: 2645 switch ((inst >> 20) & 0b1111111) { 2646 case 0b0001111: op = rv_op_zip; break; 2647 } 2648 break; 2649 case 0b00010: 2650 switch ((inst >> 20) & 0b1111111) { 2651 case 0b0000000: op = rv_op_sha256sum0; break; 2652 case 0b0000001: op = rv_op_sha256sum1; break; 2653 case 0b0000010: op = rv_op_sha256sig0; break; 2654 case 0b0000011: op = rv_op_sha256sig1; break; 2655 case 0b0000100: op = rv_op_sha512sum0; break; 2656 case 0b0000101: op = rv_op_sha512sum1; break; 2657 case 0b0000110: op = rv_op_sha512sig0; break; 2658 case 0b0000111: op = rv_op_sha512sig1; break; 2659 case 0b0001000: op = rv_op_sm3p0; break; 2660 case 0b0001001: op = rv_op_sm3p1; break; 2661 } 2662 break; 2663 case 0b00101: op = rv_op_bseti; break; 2664 case 0b00110: 2665 switch ((inst >> 20) & 0b1111111) { 2666 case 0b0000000: op = rv_op_aes64im; break; 2667 default: 2668 if (((inst >> 24) & 0b0111) == 0b001) { 2669 op = rv_op_aes64ks1i; 2670 } 2671 break; 2672 } 2673 break; 2674 case 0b01001: op = rv_op_bclri; break; 2675 case 0b01101: op = rv_op_binvi; break; 2676 case 0b01100: 2677 switch ((inst >> 20) & 0b1111111) { 2678 case 0b0000000: op = rv_op_clz; break; 2679 case 0b0000001: op = rv_op_ctz; break; 2680 case 0b0000010: op = rv_op_cpop; break; 2681 /* 0b0000011 */ 2682 case 0b0000100: op = rv_op_sext_b; break; 2683 case 0b0000101: op = rv_op_sext_h; break; 2684 } 2685 break; 2686 } 2687 break; 2688 case 2: op = rv_op_slti; break; 2689 case 3: op = rv_op_sltiu; break; 2690 case 4: op = rv_op_xori; break; 2691 case 5: 2692 switch ((inst >> 27) & 0b11111) { 2693 case 0b00000: op = rv_op_srli; break; 2694 case 0b00001: 2695 switch ((inst >> 20) & 0b1111111) { 2696 case 0b0001111: op = rv_op_unzip; break; 2697 } 2698 break; 2699 case 0b00101: op = rv_op_orc_b; break; 2700 case 0b01000: op = rv_op_srai; break; 2701 case 0b01001: op = rv_op_bexti; break; 2702 case 0b01100: op = rv_op_rori; break; 2703 case 0b01101: 2704 switch ((inst >> 20) & 0b1111111) { 2705 case 0b0011000: op = rv_op_rev8; break; 2706 case 0b0111000: op = rv_op_rev8; break; 2707 case 0b0000111: op = rv_op_brev8; break; 2708 } 2709 break; 2710 } 2711 break; 2712 case 6: op = rv_op_ori; break; 2713 case 7: op = rv_op_andi; break; 2714 } 2715 break; 2716 case 5: op = rv_op_auipc; break; 2717 case 6: 2718 switch ((inst >> 12) & 0b111) { 2719 case 0: op = rv_op_addiw; break; 2720 case 1: 2721 switch ((inst >> 26) & 0b111111) { 2722 case 0: op = rv_op_slliw; break; 2723 case 2: op = rv_op_slli_uw; break; 2724 case 24: 2725 switch ((inst >> 20) & 0b11111) { 2726 case 0b00000: op = rv_op_clzw; break; 2727 case 0b00001: op = rv_op_ctzw; break; 2728 case 0b00010: op = rv_op_cpopw; break; 2729 } 2730 break; 2731 } 2732 break; 2733 case 5: 2734 switch ((inst >> 25) & 0b1111111) { 2735 case 0: op = rv_op_srliw; break; 2736 case 32: op = rv_op_sraiw; break; 2737 case 48: op = rv_op_roriw; break; 2738 } 2739 break; 2740 } 2741 break; 2742 case 8: 2743 switch ((inst >> 12) & 0b111) { 2744 case 0: op = rv_op_sb; break; 2745 case 1: op = rv_op_sh; break; 2746 case 2: op = rv_op_sw; break; 2747 case 3: op = rv_op_sd; break; 2748 case 4: op = rv_op_sq; break; 2749 } 2750 break; 2751 case 9: 2752 switch ((inst >> 12) & 0b111) { 2753 case 0: 2754 switch ((inst >> 20) & 0b111111111111) { 2755 case 40: op = rv_op_vs1r_v; break; 2756 case 552: op = rv_op_vs2r_v; break; 2757 case 1576: op = rv_op_vs4r_v; break; 2758 case 3624: op = rv_op_vs8r_v; break; 2759 } 2760 switch ((inst >> 26) & 0b111) { 2761 case 0: 2762 switch ((inst >> 20) & 0b11111) { 2763 case 0: op = rv_op_vse8_v; break; 2764 case 11: op = rv_op_vsm_v; break; 2765 } 2766 break; 2767 case 1: op = rv_op_vsuxei8_v; break; 2768 case 2: op = rv_op_vsse8_v; break; 2769 case 3: op = rv_op_vsoxei8_v; break; 2770 } 2771 break; 2772 case 1: op = rv_op_fsh; break; 2773 case 2: op = rv_op_fsw; break; 2774 case 3: op = rv_op_fsd; break; 2775 case 4: op = rv_op_fsq; break; 2776 case 5: 2777 switch ((inst >> 26) & 0b111) { 2778 case 0: 2779 switch ((inst >> 20) & 0b11111) { 2780 case 0: op = rv_op_vse16_v; break; 2781 } 2782 break; 2783 case 1: op = rv_op_vsuxei16_v; break; 2784 case 2: op = rv_op_vsse16_v; break; 2785 case 3: op = rv_op_vsoxei16_v; break; 2786 } 2787 break; 2788 case 6: 2789 switch ((inst >> 26) & 0b111) { 2790 case 0: 2791 switch ((inst >> 20) & 0b11111) { 2792 case 0: op = rv_op_vse32_v; break; 2793 } 2794 break; 2795 case 1: op = rv_op_vsuxei32_v; break; 2796 case 2: op = rv_op_vsse32_v; break; 2797 case 3: op = rv_op_vsoxei32_v; break; 2798 } 2799 break; 2800 case 7: 2801 switch ((inst >> 26) & 0b111) { 2802 case 0: 2803 switch ((inst >> 20) & 0b11111) { 2804 case 0: op = rv_op_vse64_v; break; 2805 } 2806 break; 2807 case 1: op = rv_op_vsuxei64_v; break; 2808 case 2: op = rv_op_vsse64_v; break; 2809 case 3: op = rv_op_vsoxei64_v; break; 2810 } 2811 break; 2812 } 2813 break; 2814 case 11: 2815 switch (((inst >> 24) & 0b11111000) | 2816 ((inst >> 12) & 0b00000111)) { 2817 case 2: op = rv_op_amoadd_w; break; 2818 case 3: op = rv_op_amoadd_d; break; 2819 case 4: op = rv_op_amoadd_q; break; 2820 case 10: op = rv_op_amoswap_w; break; 2821 case 11: op = rv_op_amoswap_d; break; 2822 case 12: op = rv_op_amoswap_q; break; 2823 case 18: 2824 switch ((inst >> 20) & 0b11111) { 2825 case 0: op = rv_op_lr_w; break; 2826 } 2827 break; 2828 case 19: 2829 switch ((inst >> 20) & 0b11111) { 2830 case 0: op = rv_op_lr_d; break; 2831 } 2832 break; 2833 case 20: 2834 switch ((inst >> 20) & 0b11111) { 2835 case 0: op = rv_op_lr_q; break; 2836 } 2837 break; 2838 case 26: op = rv_op_sc_w; break; 2839 case 27: op = rv_op_sc_d; break; 2840 case 28: op = rv_op_sc_q; break; 2841 case 34: op = rv_op_amoxor_w; break; 2842 case 35: op = rv_op_amoxor_d; break; 2843 case 36: op = rv_op_amoxor_q; break; 2844 case 66: op = rv_op_amoor_w; break; 2845 case 67: op = rv_op_amoor_d; break; 2846 case 68: op = rv_op_amoor_q; break; 2847 case 98: op = rv_op_amoand_w; break; 2848 case 99: op = rv_op_amoand_d; break; 2849 case 100: op = rv_op_amoand_q; break; 2850 case 130: op = rv_op_amomin_w; break; 2851 case 131: op = rv_op_amomin_d; break; 2852 case 132: op = rv_op_amomin_q; break; 2853 case 162: op = rv_op_amomax_w; break; 2854 case 163: op = rv_op_amomax_d; break; 2855 case 164: op = rv_op_amomax_q; break; 2856 case 194: op = rv_op_amominu_w; break; 2857 case 195: op = rv_op_amominu_d; break; 2858 case 196: op = rv_op_amominu_q; break; 2859 case 226: op = rv_op_amomaxu_w; break; 2860 case 227: op = rv_op_amomaxu_d; break; 2861 case 228: op = rv_op_amomaxu_q; break; 2862 } 2863 break; 2864 case 12: 2865 switch (((inst >> 22) & 0b1111111000) | 2866 ((inst >> 12) & 0b0000000111)) { 2867 case 0: op = rv_op_add; break; 2868 case 1: op = rv_op_sll; break; 2869 case 2: op = rv_op_slt; break; 2870 case 3: op = rv_op_sltu; break; 2871 case 4: op = rv_op_xor; break; 2872 case 5: op = rv_op_srl; break; 2873 case 6: op = rv_op_or; break; 2874 case 7: op = rv_op_and; break; 2875 case 8: op = rv_op_mul; break; 2876 case 9: op = rv_op_mulh; break; 2877 case 10: op = rv_op_mulhsu; break; 2878 case 11: op = rv_op_mulhu; break; 2879 case 12: op = rv_op_div; break; 2880 case 13: op = rv_op_divu; break; 2881 case 14: op = rv_op_rem; break; 2882 case 15: op = rv_op_remu; break; 2883 case 36: 2884 switch ((inst >> 20) & 0b11111) { 2885 case 0: op = rv_op_zext_h; break; 2886 default: op = rv_op_pack; break; 2887 } 2888 break; 2889 case 39: op = rv_op_packh; break; 2890 2891 case 41: op = rv_op_clmul; break; 2892 case 42: op = rv_op_clmulr; break; 2893 case 43: op = rv_op_clmulh; break; 2894 case 44: op = rv_op_min; break; 2895 case 45: op = rv_op_minu; break; 2896 case 46: op = rv_op_max; break; 2897 case 47: op = rv_op_maxu; break; 2898 case 075: op = rv_op_czero_eqz; break; 2899 case 077: op = rv_op_czero_nez; break; 2900 case 130: op = rv_op_sh1add; break; 2901 case 132: op = rv_op_sh2add; break; 2902 case 134: op = rv_op_sh3add; break; 2903 case 161: op = rv_op_bset; break; 2904 case 162: op = rv_op_xperm4; break; 2905 case 164: op = rv_op_xperm8; break; 2906 case 200: op = rv_op_aes64es; break; 2907 case 216: op = rv_op_aes64esm; break; 2908 case 232: op = rv_op_aes64ds; break; 2909 case 248: op = rv_op_aes64dsm; break; 2910 case 256: op = rv_op_sub; break; 2911 case 260: op = rv_op_xnor; break; 2912 case 261: op = rv_op_sra; break; 2913 case 262: op = rv_op_orn; break; 2914 case 263: op = rv_op_andn; break; 2915 case 289: op = rv_op_bclr; break; 2916 case 293: op = rv_op_bext; break; 2917 case 320: op = rv_op_sha512sum0r; break; 2918 case 328: op = rv_op_sha512sum1r; break; 2919 case 336: op = rv_op_sha512sig0l; break; 2920 case 344: op = rv_op_sha512sig1l; break; 2921 case 368: op = rv_op_sha512sig0h; break; 2922 case 376: op = rv_op_sha512sig1h; break; 2923 case 385: op = rv_op_rol; break; 2924 case 389: op = rv_op_ror; break; 2925 case 417: op = rv_op_binv; break; 2926 case 504: op = rv_op_aes64ks2; break; 2927 } 2928 switch ((inst >> 25) & 0b0011111) { 2929 case 17: op = rv_op_aes32esi; break; 2930 case 19: op = rv_op_aes32esmi; break; 2931 case 21: op = rv_op_aes32dsi; break; 2932 case 23: op = rv_op_aes32dsmi; break; 2933 case 24: op = rv_op_sm4ed; break; 2934 case 26: op = rv_op_sm4ks; break; 2935 } 2936 break; 2937 case 13: op = rv_op_lui; break; 2938 case 14: 2939 switch (((inst >> 22) & 0b1111111000) | 2940 ((inst >> 12) & 0b0000000111)) { 2941 case 0: op = rv_op_addw; break; 2942 case 1: op = rv_op_sllw; break; 2943 case 5: op = rv_op_srlw; break; 2944 case 8: op = rv_op_mulw; break; 2945 case 12: op = rv_op_divw; break; 2946 case 13: op = rv_op_divuw; break; 2947 case 14: op = rv_op_remw; break; 2948 case 15: op = rv_op_remuw; break; 2949 case 32: op = rv_op_add_uw; break; 2950 case 36: 2951 switch ((inst >> 20) & 0b11111) { 2952 case 0: op = rv_op_zext_h; break; 2953 default: op = rv_op_packw; break; 2954 } 2955 break; 2956 case 130: op = rv_op_sh1add_uw; break; 2957 case 132: op = rv_op_sh2add_uw; break; 2958 case 134: op = rv_op_sh3add_uw; break; 2959 case 256: op = rv_op_subw; break; 2960 case 261: op = rv_op_sraw; break; 2961 case 385: op = rv_op_rolw; break; 2962 case 389: op = rv_op_rorw; break; 2963 } 2964 break; 2965 case 16: 2966 switch ((inst >> 25) & 0b11) { 2967 case 0: op = rv_op_fmadd_s; break; 2968 case 1: op = rv_op_fmadd_d; break; 2969 case 3: op = rv_op_fmadd_q; break; 2970 } 2971 break; 2972 case 17: 2973 switch ((inst >> 25) & 0b11) { 2974 case 0: op = rv_op_fmsub_s; break; 2975 case 1: op = rv_op_fmsub_d; break; 2976 case 3: op = rv_op_fmsub_q; break; 2977 } 2978 break; 2979 case 18: 2980 switch ((inst >> 25) & 0b11) { 2981 case 0: op = rv_op_fnmsub_s; break; 2982 case 1: op = rv_op_fnmsub_d; break; 2983 case 3: op = rv_op_fnmsub_q; break; 2984 } 2985 break; 2986 case 19: 2987 switch ((inst >> 25) & 0b11) { 2988 case 0: op = rv_op_fnmadd_s; break; 2989 case 1: op = rv_op_fnmadd_d; break; 2990 case 3: op = rv_op_fnmadd_q; break; 2991 } 2992 break; 2993 case 20: 2994 switch ((inst >> 25) & 0b1111111) { 2995 case 0: op = rv_op_fadd_s; break; 2996 case 1: op = rv_op_fadd_d; break; 2997 case 3: op = rv_op_fadd_q; break; 2998 case 4: op = rv_op_fsub_s; break; 2999 case 5: op = rv_op_fsub_d; break; 3000 case 7: op = rv_op_fsub_q; break; 3001 case 8: op = rv_op_fmul_s; break; 3002 case 9: op = rv_op_fmul_d; break; 3003 case 11: op = rv_op_fmul_q; break; 3004 case 12: op = rv_op_fdiv_s; break; 3005 case 13: op = rv_op_fdiv_d; break; 3006 case 15: op = rv_op_fdiv_q; break; 3007 case 16: 3008 switch ((inst >> 12) & 0b111) { 3009 case 0: op = rv_op_fsgnj_s; break; 3010 case 1: op = rv_op_fsgnjn_s; break; 3011 case 2: op = rv_op_fsgnjx_s; break; 3012 } 3013 break; 3014 case 17: 3015 switch ((inst >> 12) & 0b111) { 3016 case 0: op = rv_op_fsgnj_d; break; 3017 case 1: op = rv_op_fsgnjn_d; break; 3018 case 2: op = rv_op_fsgnjx_d; break; 3019 } 3020 break; 3021 case 19: 3022 switch ((inst >> 12) & 0b111) { 3023 case 0: op = rv_op_fsgnj_q; break; 3024 case 1: op = rv_op_fsgnjn_q; break; 3025 case 2: op = rv_op_fsgnjx_q; break; 3026 } 3027 break; 3028 case 20: 3029 switch ((inst >> 12) & 0b111) { 3030 case 0: op = rv_op_fmin_s; break; 3031 case 1: op = rv_op_fmax_s; break; 3032 case 2: op = rv_op_fminm_s; break; 3033 case 3: op = rv_op_fmaxm_s; break; 3034 } 3035 break; 3036 case 21: 3037 switch ((inst >> 12) & 0b111) { 3038 case 0: op = rv_op_fmin_d; break; 3039 case 1: op = rv_op_fmax_d; break; 3040 case 2: op = rv_op_fminm_d; break; 3041 case 3: op = rv_op_fmaxm_d; break; 3042 } 3043 break; 3044 case 22: 3045 switch (((inst >> 12) & 0b111)) { 3046 case 2: op = rv_op_fminm_h; break; 3047 case 3: op = rv_op_fmaxm_h; break; 3048 } 3049 break; 3050 case 23: 3051 switch ((inst >> 12) & 0b111) { 3052 case 0: op = rv_op_fmin_q; break; 3053 case 1: op = rv_op_fmax_q; break; 3054 case 2: op = rv_op_fminm_q; break; 3055 case 3: op = rv_op_fmaxm_q; break; 3056 } 3057 break; 3058 case 32: 3059 switch ((inst >> 20) & 0b11111) { 3060 case 1: op = rv_op_fcvt_s_d; break; 3061 case 3: op = rv_op_fcvt_s_q; break; 3062 case 4: op = rv_op_fround_s; break; 3063 case 5: op = rv_op_froundnx_s; break; 3064 case 6: op = rv_op_fcvt_s_bf16; break; 3065 } 3066 break; 3067 case 33: 3068 switch ((inst >> 20) & 0b11111) { 3069 case 0: op = rv_op_fcvt_d_s; break; 3070 case 3: op = rv_op_fcvt_d_q; break; 3071 case 4: op = rv_op_fround_d; break; 3072 case 5: op = rv_op_froundnx_d; break; 3073 } 3074 break; 3075 case 34: 3076 switch (((inst >> 20) & 0b11111)) { 3077 case 4: op = rv_op_fround_h; break; 3078 case 5: op = rv_op_froundnx_h; break; 3079 case 8: op = rv_op_fcvt_bf16_s; break; 3080 } 3081 break; 3082 case 35: 3083 switch ((inst >> 20) & 0b11111) { 3084 case 0: op = rv_op_fcvt_q_s; break; 3085 case 1: op = rv_op_fcvt_q_d; break; 3086 case 4: op = rv_op_fround_q; break; 3087 case 5: op = rv_op_froundnx_q; break; 3088 } 3089 break; 3090 case 44: 3091 switch ((inst >> 20) & 0b11111) { 3092 case 0: op = rv_op_fsqrt_s; break; 3093 } 3094 break; 3095 case 45: 3096 switch ((inst >> 20) & 0b11111) { 3097 case 0: op = rv_op_fsqrt_d; break; 3098 } 3099 break; 3100 case 47: 3101 switch ((inst >> 20) & 0b11111) { 3102 case 0: op = rv_op_fsqrt_q; break; 3103 } 3104 break; 3105 case 80: 3106 switch ((inst >> 12) & 0b111) { 3107 case 0: op = rv_op_fle_s; break; 3108 case 1: op = rv_op_flt_s; break; 3109 case 2: op = rv_op_feq_s; break; 3110 case 4: op = rv_op_fleq_s; break; 3111 case 5: op = rv_op_fltq_s; break; 3112 } 3113 break; 3114 case 81: 3115 switch ((inst >> 12) & 0b111) { 3116 case 0: op = rv_op_fle_d; break; 3117 case 1: op = rv_op_flt_d; break; 3118 case 2: op = rv_op_feq_d; break; 3119 case 4: op = rv_op_fleq_d; break; 3120 case 5: op = rv_op_fltq_d; break; 3121 } 3122 break; 3123 case 82: 3124 switch (((inst >> 12) & 0b111)) { 3125 case 4: op = rv_op_fleq_h; break; 3126 case 5: op = rv_op_fltq_h; break; 3127 } 3128 break; 3129 case 83: 3130 switch ((inst >> 12) & 0b111) { 3131 case 0: op = rv_op_fle_q; break; 3132 case 1: op = rv_op_flt_q; break; 3133 case 2: op = rv_op_feq_q; break; 3134 case 4: op = rv_op_fleq_q; break; 3135 case 5: op = rv_op_fltq_q; break; 3136 } 3137 break; 3138 case 89: 3139 switch (((inst >> 12) & 0b111)) { 3140 case 0: op = rv_op_fmvp_d_x; break; 3141 } 3142 break; 3143 case 91: 3144 switch (((inst >> 12) & 0b111)) { 3145 case 0: op = rv_op_fmvp_q_x; break; 3146 } 3147 break; 3148 case 96: 3149 switch ((inst >> 20) & 0b11111) { 3150 case 0: op = rv_op_fcvt_w_s; break; 3151 case 1: op = rv_op_fcvt_wu_s; break; 3152 case 2: op = rv_op_fcvt_l_s; break; 3153 case 3: op = rv_op_fcvt_lu_s; break; 3154 } 3155 break; 3156 case 97: 3157 switch ((inst >> 20) & 0b11111) { 3158 case 0: op = rv_op_fcvt_w_d; break; 3159 case 1: op = rv_op_fcvt_wu_d; break; 3160 case 2: op = rv_op_fcvt_l_d; break; 3161 case 3: op = rv_op_fcvt_lu_d; break; 3162 case 8: op = rv_op_fcvtmod_w_d; break; 3163 } 3164 break; 3165 case 99: 3166 switch ((inst >> 20) & 0b11111) { 3167 case 0: op = rv_op_fcvt_w_q; break; 3168 case 1: op = rv_op_fcvt_wu_q; break; 3169 case 2: op = rv_op_fcvt_l_q; break; 3170 case 3: op = rv_op_fcvt_lu_q; break; 3171 } 3172 break; 3173 case 104: 3174 switch ((inst >> 20) & 0b11111) { 3175 case 0: op = rv_op_fcvt_s_w; break; 3176 case 1: op = rv_op_fcvt_s_wu; break; 3177 case 2: op = rv_op_fcvt_s_l; break; 3178 case 3: op = rv_op_fcvt_s_lu; break; 3179 } 3180 break; 3181 case 105: 3182 switch ((inst >> 20) & 0b11111) { 3183 case 0: op = rv_op_fcvt_d_w; break; 3184 case 1: op = rv_op_fcvt_d_wu; break; 3185 case 2: op = rv_op_fcvt_d_l; break; 3186 case 3: op = rv_op_fcvt_d_lu; break; 3187 } 3188 break; 3189 case 107: 3190 switch ((inst >> 20) & 0b11111) { 3191 case 0: op = rv_op_fcvt_q_w; break; 3192 case 1: op = rv_op_fcvt_q_wu; break; 3193 case 2: op = rv_op_fcvt_q_l; break; 3194 case 3: op = rv_op_fcvt_q_lu; break; 3195 } 3196 break; 3197 case 112: 3198 switch (((inst >> 17) & 0b11111000) | 3199 ((inst >> 12) & 0b00000111)) { 3200 case 0: op = rv_op_fmv_x_s; break; 3201 case 1: op = rv_op_fclass_s; break; 3202 } 3203 break; 3204 case 113: 3205 switch (((inst >> 17) & 0b11111000) | 3206 ((inst >> 12) & 0b00000111)) { 3207 case 0: op = rv_op_fmv_x_d; break; 3208 case 1: op = rv_op_fclass_d; break; 3209 case 8: op = rv_op_fmvh_x_d; break; 3210 } 3211 break; 3212 case 114: 3213 switch (((inst >> 17) & 0b11111000) | 3214 ((inst >> 12) & 0b00000111)) { 3215 case 0: op = rv_op_fmv_x_h; break; 3216 } 3217 break; 3218 case 115: 3219 switch (((inst >> 17) & 0b11111000) | 3220 ((inst >> 12) & 0b00000111)) { 3221 case 0: op = rv_op_fmv_x_q; break; 3222 case 1: op = rv_op_fclass_q; break; 3223 case 8: op = rv_op_fmvh_x_q; break; 3224 } 3225 break; 3226 case 120: 3227 switch (((inst >> 17) & 0b11111000) | 3228 ((inst >> 12) & 0b00000111)) { 3229 case 0: op = rv_op_fmv_s_x; break; 3230 case 8: op = rv_op_fli_s; break; 3231 } 3232 break; 3233 case 121: 3234 switch (((inst >> 17) & 0b11111000) | 3235 ((inst >> 12) & 0b00000111)) { 3236 case 0: op = rv_op_fmv_d_x; break; 3237 case 8: op = rv_op_fli_d; break; 3238 } 3239 break; 3240 case 122: 3241 switch (((inst >> 17) & 0b11111000) | 3242 ((inst >> 12) & 0b00000111)) { 3243 case 0: op = rv_op_fmv_h_x; break; 3244 case 8: op = rv_op_fli_h; break; 3245 } 3246 break; 3247 case 123: 3248 switch (((inst >> 17) & 0b11111000) | 3249 ((inst >> 12) & 0b00000111)) { 3250 case 0: op = rv_op_fmv_q_x; break; 3251 case 8: op = rv_op_fli_q; break; 3252 } 3253 break; 3254 } 3255 break; 3256 case 21: 3257 switch ((inst >> 12) & 0b111) { 3258 case 0: 3259 switch ((inst >> 26) & 0b111111) { 3260 case 0: op = rv_op_vadd_vv; break; 3261 case 1: op = rv_op_vandn_vv; break; 3262 case 2: op = rv_op_vsub_vv; break; 3263 case 4: op = rv_op_vminu_vv; break; 3264 case 5: op = rv_op_vmin_vv; break; 3265 case 6: op = rv_op_vmaxu_vv; break; 3266 case 7: op = rv_op_vmax_vv; break; 3267 case 9: op = rv_op_vand_vv; break; 3268 case 10: op = rv_op_vor_vv; break; 3269 case 11: op = rv_op_vxor_vv; break; 3270 case 12: op = rv_op_vrgather_vv; break; 3271 case 14: op = rv_op_vrgatherei16_vv; break; 3272 case 16: 3273 if (((inst >> 25) & 1) == 0) { 3274 op = rv_op_vadc_vvm; 3275 } 3276 break; 3277 case 17: op = rv_op_vmadc_vvm; break; 3278 case 18: 3279 if (((inst >> 25) & 1) == 0) { 3280 op = rv_op_vsbc_vvm; 3281 } 3282 break; 3283 case 19: op = rv_op_vmsbc_vvm; break; 3284 case 20: op = rv_op_vror_vv; break; 3285 case 21: op = rv_op_vrol_vv; break; 3286 case 23: 3287 if (((inst >> 20) & 0b111111) == 32) 3288 op = rv_op_vmv_v_v; 3289 else if (((inst >> 25) & 1) == 0) 3290 op = rv_op_vmerge_vvm; 3291 break; 3292 case 24: op = rv_op_vmseq_vv; break; 3293 case 25: op = rv_op_vmsne_vv; break; 3294 case 26: op = rv_op_vmsltu_vv; break; 3295 case 27: op = rv_op_vmslt_vv; break; 3296 case 28: op = rv_op_vmsleu_vv; break; 3297 case 29: op = rv_op_vmsle_vv; break; 3298 case 32: op = rv_op_vsaddu_vv; break; 3299 case 33: op = rv_op_vsadd_vv; break; 3300 case 34: op = rv_op_vssubu_vv; break; 3301 case 35: op = rv_op_vssub_vv; break; 3302 case 37: op = rv_op_vsll_vv; break; 3303 case 39: op = rv_op_vsmul_vv; break; 3304 case 40: op = rv_op_vsrl_vv; break; 3305 case 41: op = rv_op_vsra_vv; break; 3306 case 42: op = rv_op_vssrl_vv; break; 3307 case 43: op = rv_op_vssra_vv; break; 3308 case 44: op = rv_op_vnsrl_wv; break; 3309 case 45: op = rv_op_vnsra_wv; break; 3310 case 46: op = rv_op_vnclipu_wv; break; 3311 case 47: op = rv_op_vnclip_wv; break; 3312 case 48: op = rv_op_vwredsumu_vs; break; 3313 case 49: op = rv_op_vwredsum_vs; break; 3314 case 53: op = rv_op_vwsll_vv; break; 3315 } 3316 break; 3317 case 1: 3318 switch ((inst >> 26) & 0b111111) { 3319 case 0: op = rv_op_vfadd_vv; break; 3320 case 1: op = rv_op_vfredusum_vs; break; 3321 case 2: op = rv_op_vfsub_vv; break; 3322 case 3: op = rv_op_vfredosum_vs; break; 3323 case 4: op = rv_op_vfmin_vv; break; 3324 case 5: op = rv_op_vfredmin_vs; break; 3325 case 6: op = rv_op_vfmax_vv; break; 3326 case 7: op = rv_op_vfredmax_vs; break; 3327 case 8: op = rv_op_vfsgnj_vv; break; 3328 case 9: op = rv_op_vfsgnjn_vv; break; 3329 case 10: op = rv_op_vfsgnjx_vv; break; 3330 case 16: 3331 switch ((inst >> 15) & 0b11111) { 3332 case 0: if ((inst >> 25) & 1) op = rv_op_vfmv_f_s; break; 3333 } 3334 break; 3335 case 18: 3336 switch ((inst >> 15) & 0b11111) { 3337 case 0: op = rv_op_vfcvt_xu_f_v; break; 3338 case 1: op = rv_op_vfcvt_x_f_v; break; 3339 case 2: op = rv_op_vfcvt_f_xu_v; break; 3340 case 3: op = rv_op_vfcvt_f_x_v; break; 3341 case 6: op = rv_op_vfcvt_rtz_xu_f_v; break; 3342 case 7: op = rv_op_vfcvt_rtz_x_f_v; break; 3343 case 8: op = rv_op_vfwcvt_xu_f_v; break; 3344 case 9: op = rv_op_vfwcvt_x_f_v; break; 3345 case 10: op = rv_op_vfwcvt_f_xu_v; break; 3346 case 11: op = rv_op_vfwcvt_f_x_v; break; 3347 case 12: op = rv_op_vfwcvt_f_f_v; break; 3348 case 13: op = rv_op_vfwcvtbf16_f_f_v; break; 3349 case 14: op = rv_op_vfwcvt_rtz_xu_f_v; break; 3350 case 15: op = rv_op_vfwcvt_rtz_x_f_v; break; 3351 case 16: op = rv_op_vfncvt_xu_f_w; break; 3352 case 17: op = rv_op_vfncvt_x_f_w; break; 3353 case 18: op = rv_op_vfncvt_f_xu_w; break; 3354 case 19: op = rv_op_vfncvt_f_x_w; break; 3355 case 20: op = rv_op_vfncvt_f_f_w; break; 3356 case 21: op = rv_op_vfncvt_rod_f_f_w; break; 3357 case 22: op = rv_op_vfncvt_rtz_xu_f_w; break; 3358 case 23: op = rv_op_vfncvt_rtz_x_f_w; break; 3359 case 29: op = rv_op_vfncvtbf16_f_f_w; break; 3360 } 3361 break; 3362 case 19: 3363 switch ((inst >> 15) & 0b11111) { 3364 case 0: op = rv_op_vfsqrt_v; break; 3365 case 4: op = rv_op_vfrsqrt7_v; break; 3366 case 5: op = rv_op_vfrec7_v; break; 3367 case 16: op = rv_op_vfclass_v; break; 3368 } 3369 break; 3370 case 24: op = rv_op_vmfeq_vv; break; 3371 case 25: op = rv_op_vmfle_vv; break; 3372 case 27: op = rv_op_vmflt_vv; break; 3373 case 28: op = rv_op_vmfne_vv; break; 3374 case 32: op = rv_op_vfdiv_vv; break; 3375 case 36: op = rv_op_vfmul_vv; break; 3376 case 40: op = rv_op_vfmadd_vv; break; 3377 case 41: op = rv_op_vfnmadd_vv; break; 3378 case 42: op = rv_op_vfmsub_vv; break; 3379 case 43: op = rv_op_vfnmsub_vv; break; 3380 case 44: op = rv_op_vfmacc_vv; break; 3381 case 45: op = rv_op_vfnmacc_vv; break; 3382 case 46: op = rv_op_vfmsac_vv; break; 3383 case 47: op = rv_op_vfnmsac_vv; break; 3384 case 48: op = rv_op_vfwadd_vv; break; 3385 case 49: op = rv_op_vfwredusum_vs; break; 3386 case 50: op = rv_op_vfwsub_vv; break; 3387 case 51: op = rv_op_vfwredosum_vs; break; 3388 case 52: op = rv_op_vfwadd_wv; break; 3389 case 54: op = rv_op_vfwsub_wv; break; 3390 case 56: op = rv_op_vfwmul_vv; break; 3391 case 59: op = rv_op_vfwmaccbf16_vv; break; 3392 case 60: op = rv_op_vfwmacc_vv; break; 3393 case 61: op = rv_op_vfwnmacc_vv; break; 3394 case 62: op = rv_op_vfwmsac_vv; break; 3395 case 63: op = rv_op_vfwnmsac_vv; break; 3396 } 3397 break; 3398 case 2: 3399 switch ((inst >> 26) & 0b111111) { 3400 case 0: op = rv_op_vredsum_vs; break; 3401 case 1: op = rv_op_vredand_vs; break; 3402 case 2: op = rv_op_vredor_vs; break; 3403 case 3: op = rv_op_vredxor_vs; break; 3404 case 4: op = rv_op_vredminu_vs; break; 3405 case 5: op = rv_op_vredmin_vs; break; 3406 case 6: op = rv_op_vredmaxu_vs; break; 3407 case 7: op = rv_op_vredmax_vs; break; 3408 case 8: op = rv_op_vaaddu_vv; break; 3409 case 9: op = rv_op_vaadd_vv; break; 3410 case 10: op = rv_op_vasubu_vv; break; 3411 case 11: op = rv_op_vasub_vv; break; 3412 case 12: op = rv_op_vclmul_vv; break; 3413 case 13: op = rv_op_vclmulh_vv; break; 3414 case 16: 3415 switch ((inst >> 15) & 0b11111) { 3416 case 0: if ((inst >> 25) & 1) op = rv_op_vmv_x_s; break; 3417 case 16: op = rv_op_vcpop_m; break; 3418 case 17: op = rv_op_vfirst_m; break; 3419 } 3420 break; 3421 case 18: 3422 switch ((inst >> 15) & 0b11111) { 3423 case 2: op = rv_op_vzext_vf8; break; 3424 case 3: op = rv_op_vsext_vf8; break; 3425 case 4: op = rv_op_vzext_vf4; break; 3426 case 5: op = rv_op_vsext_vf4; break; 3427 case 6: op = rv_op_vzext_vf2; break; 3428 case 7: op = rv_op_vsext_vf2; break; 3429 case 8: op = rv_op_vbrev8_v; break; 3430 case 9: op = rv_op_vrev8_v; break; 3431 case 10: op = rv_op_vbrev_v; break; 3432 case 12: op = rv_op_vclz_v; break; 3433 case 13: op = rv_op_vctz_v; break; 3434 case 14: op = rv_op_vcpop_v; break; 3435 } 3436 break; 3437 case 20: 3438 switch ((inst >> 15) & 0b11111) { 3439 case 1: op = rv_op_vmsbf_m; break; 3440 case 2: op = rv_op_vmsof_m; break; 3441 case 3: op = rv_op_vmsif_m; break; 3442 case 16: op = rv_op_viota_m; break; 3443 case 17: 3444 if (((inst >> 20) & 0b11111) == 0) { 3445 op = rv_op_vid_v; 3446 } 3447 break; 3448 } 3449 break; 3450 case 23: if ((inst >> 25) & 1) op = rv_op_vcompress_vm; break; 3451 case 24: if ((inst >> 25) & 1) op = rv_op_vmandn_mm; break; 3452 case 25: if ((inst >> 25) & 1) op = rv_op_vmand_mm; break; 3453 case 26: if ((inst >> 25) & 1) op = rv_op_vmor_mm; break; 3454 case 27: if ((inst >> 25) & 1) op = rv_op_vmxor_mm; break; 3455 case 28: if ((inst >> 25) & 1) op = rv_op_vmorn_mm; break; 3456 case 29: if ((inst >> 25) & 1) op = rv_op_vmnand_mm; break; 3457 case 30: if ((inst >> 25) & 1) op = rv_op_vmnor_mm; break; 3458 case 31: if ((inst >> 25) & 1) op = rv_op_vmxnor_mm; break; 3459 case 32: op = rv_op_vdivu_vv; break; 3460 case 33: op = rv_op_vdiv_vv; break; 3461 case 34: op = rv_op_vremu_vv; break; 3462 case 35: op = rv_op_vrem_vv; break; 3463 case 36: op = rv_op_vmulhu_vv; break; 3464 case 37: op = rv_op_vmul_vv; break; 3465 case 38: op = rv_op_vmulhsu_vv; break; 3466 case 39: op = rv_op_vmulh_vv; break; 3467 case 41: op = rv_op_vmadd_vv; break; 3468 case 43: op = rv_op_vnmsub_vv; break; 3469 case 45: op = rv_op_vmacc_vv; break; 3470 case 47: op = rv_op_vnmsac_vv; break; 3471 case 48: op = rv_op_vwaddu_vv; break; 3472 case 49: op = rv_op_vwadd_vv; break; 3473 case 50: op = rv_op_vwsubu_vv; break; 3474 case 51: op = rv_op_vwsub_vv; break; 3475 case 52: op = rv_op_vwaddu_wv; break; 3476 case 53: op = rv_op_vwadd_wv; break; 3477 case 54: op = rv_op_vwsubu_wv; break; 3478 case 55: op = rv_op_vwsub_wv; break; 3479 case 56: op = rv_op_vwmulu_vv; break; 3480 case 58: op = rv_op_vwmulsu_vv; break; 3481 case 59: op = rv_op_vwmul_vv; break; 3482 case 60: op = rv_op_vwmaccu_vv; break; 3483 case 61: op = rv_op_vwmacc_vv; break; 3484 case 63: op = rv_op_vwmaccsu_vv; break; 3485 } 3486 break; 3487 case 3: 3488 switch ((inst >> 26) & 0b111111) { 3489 case 0: op = rv_op_vadd_vi; break; 3490 case 3: op = rv_op_vrsub_vi; break; 3491 case 9: op = rv_op_vand_vi; break; 3492 case 10: op = rv_op_vor_vi; break; 3493 case 11: op = rv_op_vxor_vi; break; 3494 case 12: op = rv_op_vrgather_vi; break; 3495 case 14: op = rv_op_vslideup_vi; break; 3496 case 15: op = rv_op_vslidedown_vi; break; 3497 case 16: 3498 if (((inst >> 25) & 1) == 0) { 3499 op = rv_op_vadc_vim; 3500 } 3501 break; 3502 case 17: op = rv_op_vmadc_vim; break; 3503 case 20: case 21: op = rv_op_vror_vi; break; 3504 case 23: 3505 if (((inst >> 20) & 0b111111) == 32) 3506 op = rv_op_vmv_v_i; 3507 else if (((inst >> 25) & 1) == 0) 3508 op = rv_op_vmerge_vim; 3509 break; 3510 case 24: op = rv_op_vmseq_vi; break; 3511 case 25: op = rv_op_vmsne_vi; break; 3512 case 28: op = rv_op_vmsleu_vi; break; 3513 case 29: op = rv_op_vmsle_vi; break; 3514 case 30: op = rv_op_vmsgtu_vi; break; 3515 case 31: op = rv_op_vmsgt_vi; break; 3516 case 32: op = rv_op_vsaddu_vi; break; 3517 case 33: op = rv_op_vsadd_vi; break; 3518 case 37: op = rv_op_vsll_vi; break; 3519 case 39: 3520 switch ((inst >> 15) & 0b11111) { 3521 case 0: op = rv_op_vmv1r_v; break; 3522 case 1: op = rv_op_vmv2r_v; break; 3523 case 3: op = rv_op_vmv4r_v; break; 3524 case 7: op = rv_op_vmv8r_v; break; 3525 } 3526 break; 3527 case 40: op = rv_op_vsrl_vi; break; 3528 case 41: op = rv_op_vsra_vi; break; 3529 case 42: op = rv_op_vssrl_vi; break; 3530 case 43: op = rv_op_vssra_vi; break; 3531 case 44: op = rv_op_vnsrl_wi; break; 3532 case 45: op = rv_op_vnsra_wi; break; 3533 case 46: op = rv_op_vnclipu_wi; break; 3534 case 47: op = rv_op_vnclip_wi; break; 3535 case 53: op = rv_op_vwsll_vi; break; 3536 } 3537 break; 3538 case 4: 3539 switch ((inst >> 26) & 0b111111) { 3540 case 0: op = rv_op_vadd_vx; break; 3541 case 1: op = rv_op_vandn_vx; break; 3542 case 2: op = rv_op_vsub_vx; break; 3543 case 3: op = rv_op_vrsub_vx; break; 3544 case 4: op = rv_op_vminu_vx; break; 3545 case 5: op = rv_op_vmin_vx; break; 3546 case 6: op = rv_op_vmaxu_vx; break; 3547 case 7: op = rv_op_vmax_vx; break; 3548 case 9: op = rv_op_vand_vx; break; 3549 case 10: op = rv_op_vor_vx; break; 3550 case 11: op = rv_op_vxor_vx; break; 3551 case 12: op = rv_op_vrgather_vx; break; 3552 case 14: op = rv_op_vslideup_vx; break; 3553 case 15: op = rv_op_vslidedown_vx; break; 3554 case 16: 3555 if (((inst >> 25) & 1) == 0) { 3556 op = rv_op_vadc_vxm; 3557 } 3558 break; 3559 case 17: op = rv_op_vmadc_vxm; break; 3560 case 18: 3561 if (((inst >> 25) & 1) == 0) { 3562 op = rv_op_vsbc_vxm; 3563 } 3564 break; 3565 case 19: op = rv_op_vmsbc_vxm; break; 3566 case 20: op = rv_op_vror_vx; break; 3567 case 21: op = rv_op_vrol_vx; break; 3568 case 23: 3569 if (((inst >> 20) & 0b111111) == 32) 3570 op = rv_op_vmv_v_x; 3571 else if (((inst >> 25) & 1) == 0) 3572 op = rv_op_vmerge_vxm; 3573 break; 3574 case 24: op = rv_op_vmseq_vx; break; 3575 case 25: op = rv_op_vmsne_vx; break; 3576 case 26: op = rv_op_vmsltu_vx; break; 3577 case 27: op = rv_op_vmslt_vx; break; 3578 case 28: op = rv_op_vmsleu_vx; break; 3579 case 29: op = rv_op_vmsle_vx; break; 3580 case 30: op = rv_op_vmsgtu_vx; break; 3581 case 31: op = rv_op_vmsgt_vx; break; 3582 case 32: op = rv_op_vsaddu_vx; break; 3583 case 33: op = rv_op_vsadd_vx; break; 3584 case 34: op = rv_op_vssubu_vx; break; 3585 case 35: op = rv_op_vssub_vx; break; 3586 case 37: op = rv_op_vsll_vx; break; 3587 case 39: op = rv_op_vsmul_vx; break; 3588 case 40: op = rv_op_vsrl_vx; break; 3589 case 41: op = rv_op_vsra_vx; break; 3590 case 42: op = rv_op_vssrl_vx; break; 3591 case 43: op = rv_op_vssra_vx; break; 3592 case 44: op = rv_op_vnsrl_wx; break; 3593 case 45: op = rv_op_vnsra_wx; break; 3594 case 46: op = rv_op_vnclipu_wx; break; 3595 case 47: op = rv_op_vnclip_wx; break; 3596 case 53: op = rv_op_vwsll_vx; break; 3597 } 3598 break; 3599 case 5: 3600 switch ((inst >> 26) & 0b111111) { 3601 case 0: op = rv_op_vfadd_vf; break; 3602 case 2: op = rv_op_vfsub_vf; break; 3603 case 4: op = rv_op_vfmin_vf; break; 3604 case 6: op = rv_op_vfmax_vf; break; 3605 case 8: op = rv_op_vfsgnj_vf; break; 3606 case 9: op = rv_op_vfsgnjn_vf; break; 3607 case 10: op = rv_op_vfsgnjx_vf; break; 3608 case 14: op = rv_op_vfslide1up_vf; break; 3609 case 15: op = rv_op_vfslide1down_vf; break; 3610 case 16: 3611 switch ((inst >> 20) & 0b11111) { 3612 case 0: if ((inst >> 25) & 1) op = rv_op_vfmv_s_f; break; 3613 } 3614 break; 3615 case 23: 3616 if (((inst >> 25) & 1) == 0) 3617 op = rv_op_vfmerge_vfm; 3618 else if (((inst >> 20) & 0b111111) == 32) 3619 op = rv_op_vfmv_v_f; 3620 break; 3621 case 24: op = rv_op_vmfeq_vf; break; 3622 case 25: op = rv_op_vmfle_vf; break; 3623 case 27: op = rv_op_vmflt_vf; break; 3624 case 28: op = rv_op_vmfne_vf; break; 3625 case 29: op = rv_op_vmfgt_vf; break; 3626 case 31: op = rv_op_vmfge_vf; break; 3627 case 32: op = rv_op_vfdiv_vf; break; 3628 case 33: op = rv_op_vfrdiv_vf; break; 3629 case 36: op = rv_op_vfmul_vf; break; 3630 case 39: op = rv_op_vfrsub_vf; break; 3631 case 40: op = rv_op_vfmadd_vf; break; 3632 case 41: op = rv_op_vfnmadd_vf; break; 3633 case 42: op = rv_op_vfmsub_vf; break; 3634 case 43: op = rv_op_vfnmsub_vf; break; 3635 case 44: op = rv_op_vfmacc_vf; break; 3636 case 45: op = rv_op_vfnmacc_vf; break; 3637 case 46: op = rv_op_vfmsac_vf; break; 3638 case 47: op = rv_op_vfnmsac_vf; break; 3639 case 48: op = rv_op_vfwadd_vf; break; 3640 case 50: op = rv_op_vfwsub_vf; break; 3641 case 52: op = rv_op_vfwadd_wf; break; 3642 case 54: op = rv_op_vfwsub_wf; break; 3643 case 56: op = rv_op_vfwmul_vf; break; 3644 case 59: op = rv_op_vfwmaccbf16_vf; break; 3645 case 60: op = rv_op_vfwmacc_vf; break; 3646 case 61: op = rv_op_vfwnmacc_vf; break; 3647 case 62: op = rv_op_vfwmsac_vf; break; 3648 case 63: op = rv_op_vfwnmsac_vf; break; 3649 } 3650 break; 3651 case 6: 3652 switch ((inst >> 26) & 0b111111) { 3653 case 8: op = rv_op_vaaddu_vx; break; 3654 case 9: op = rv_op_vaadd_vx; break; 3655 case 10: op = rv_op_vasubu_vx; break; 3656 case 11: op = rv_op_vasub_vx; break; 3657 case 12: op = rv_op_vclmul_vx; break; 3658 case 13: op = rv_op_vclmulh_vx; break; 3659 case 14: op = rv_op_vslide1up_vx; break; 3660 case 15: op = rv_op_vslide1down_vx; break; 3661 case 16: 3662 switch ((inst >> 20) & 0b11111) { 3663 case 0: if ((inst >> 25) & 1) op = rv_op_vmv_s_x; break; 3664 } 3665 break; 3666 case 32: op = rv_op_vdivu_vx; break; 3667 case 33: op = rv_op_vdiv_vx; break; 3668 case 34: op = rv_op_vremu_vx; break; 3669 case 35: op = rv_op_vrem_vx; break; 3670 case 36: op = rv_op_vmulhu_vx; break; 3671 case 37: op = rv_op_vmul_vx; break; 3672 case 38: op = rv_op_vmulhsu_vx; break; 3673 case 39: op = rv_op_vmulh_vx; break; 3674 case 41: op = rv_op_vmadd_vx; break; 3675 case 43: op = rv_op_vnmsub_vx; break; 3676 case 45: op = rv_op_vmacc_vx; break; 3677 case 47: op = rv_op_vnmsac_vx; break; 3678 case 48: op = rv_op_vwaddu_vx; break; 3679 case 49: op = rv_op_vwadd_vx; break; 3680 case 50: op = rv_op_vwsubu_vx; break; 3681 case 51: op = rv_op_vwsub_vx; break; 3682 case 52: op = rv_op_vwaddu_wx; break; 3683 case 53: op = rv_op_vwadd_wx; break; 3684 case 54: op = rv_op_vwsubu_wx; break; 3685 case 55: op = rv_op_vwsub_wx; break; 3686 case 56: op = rv_op_vwmulu_vx; break; 3687 case 58: op = rv_op_vwmulsu_vx; break; 3688 case 59: op = rv_op_vwmul_vx; break; 3689 case 60: op = rv_op_vwmaccu_vx; break; 3690 case 61: op = rv_op_vwmacc_vx; break; 3691 case 62: op = rv_op_vwmaccus_vx; break; 3692 case 63: op = rv_op_vwmaccsu_vx; break; 3693 } 3694 break; 3695 case 7: 3696 if (((inst >> 31) & 1) == 0) { 3697 op = rv_op_vsetvli; 3698 } else if ((inst >> 30) & 1) { 3699 op = rv_op_vsetivli; 3700 } else if (((inst >> 25) & 0b11111) == 0) { 3701 op = rv_op_vsetvl; 3702 } 3703 break; 3704 } 3705 break; 3706 case 22: 3707 switch ((inst >> 12) & 0b111) { 3708 case 0: op = rv_op_addid; break; 3709 case 1: 3710 switch ((inst >> 26) & 0b111111) { 3711 case 0: op = rv_op_sllid; break; 3712 } 3713 break; 3714 case 5: 3715 switch ((inst >> 26) & 0b111111) { 3716 case 0: op = rv_op_srlid; break; 3717 case 16: op = rv_op_sraid; break; 3718 } 3719 break; 3720 } 3721 break; 3722 case 24: 3723 switch ((inst >> 12) & 0b111) { 3724 case 0: op = rv_op_beq; break; 3725 case 1: op = rv_op_bne; break; 3726 case 4: op = rv_op_blt; break; 3727 case 5: op = rv_op_bge; break; 3728 case 6: op = rv_op_bltu; break; 3729 case 7: op = rv_op_bgeu; break; 3730 } 3731 break; 3732 case 25: 3733 switch ((inst >> 12) & 0b111) { 3734 case 0: op = rv_op_jalr; break; 3735 } 3736 break; 3737 case 27: op = rv_op_jal; break; 3738 case 28: 3739 switch ((inst >> 12) & 0b111) { 3740 case 0: 3741 switch (((inst >> 20) & 0b111111100000) | 3742 ((inst >> 7) & 0b000000011111)) { 3743 case 0: 3744 switch ((inst >> 15) & 0b1111111111) { 3745 case 0: op = rv_op_ecall; break; 3746 case 32: op = rv_op_ebreak; break; 3747 case 64: op = rv_op_uret; break; 3748 } 3749 break; 3750 case 256: 3751 switch ((inst >> 20) & 0b11111) { 3752 case 2: 3753 switch ((inst >> 15) & 0b11111) { 3754 case 0: op = rv_op_sret; break; 3755 } 3756 break; 3757 case 4: op = rv_op_sfence_vm; break; 3758 case 5: 3759 switch ((inst >> 15) & 0b11111) { 3760 case 0: op = rv_op_wfi; break; 3761 } 3762 break; 3763 } 3764 break; 3765 case 288: op = rv_op_sfence_vma; break; 3766 case 512: 3767 switch ((inst >> 15) & 0b1111111111) { 3768 case 64: op = rv_op_hret; break; 3769 } 3770 break; 3771 case 768: 3772 switch ((inst >> 15) & 0b1111111111) { 3773 case 64: op = rv_op_mret; break; 3774 } 3775 break; 3776 case 1952: 3777 switch ((inst >> 15) & 0b1111111111) { 3778 case 576: op = rv_op_dret; break; 3779 } 3780 break; 3781 } 3782 break; 3783 case 1: op = rv_op_csrrw; break; 3784 case 2: op = rv_op_csrrs; break; 3785 case 3: op = rv_op_csrrc; break; 3786 case 5: op = rv_op_csrrwi; break; 3787 case 6: op = rv_op_csrrsi; break; 3788 case 7: op = rv_op_csrrci; break; 3789 } 3790 break; 3791 case 29: 3792 if (((inst >> 25) & 1) == 1 && ((inst >> 12) & 0b111) == 2) { 3793 switch ((inst >> 26) & 0b111111) { 3794 case 32: op = rv_op_vsm3me_vv; break; 3795 case 33: op = rv_op_vsm4k_vi; break; 3796 case 34: op = rv_op_vaeskf1_vi; break; 3797 case 40: 3798 switch ((inst >> 15) & 0b11111) { 3799 case 0: op = rv_op_vaesdm_vv; break; 3800 case 1: op = rv_op_vaesdf_vv; break; 3801 case 2: op = rv_op_vaesem_vv; break; 3802 case 3: op = rv_op_vaesef_vv; break; 3803 case 16: op = rv_op_vsm4r_vv; break; 3804 case 17: op = rv_op_vgmul_vv; break; 3805 } 3806 break; 3807 case 41: 3808 switch ((inst >> 15) & 0b11111) { 3809 case 0: op = rv_op_vaesdm_vs; break; 3810 case 1: op = rv_op_vaesdf_vs; break; 3811 case 2: op = rv_op_vaesem_vs; break; 3812 case 3: op = rv_op_vaesef_vs; break; 3813 case 7: op = rv_op_vaesz_vs; break; 3814 case 16: op = rv_op_vsm4r_vs; break; 3815 } 3816 break; 3817 case 42: op = rv_op_vaeskf2_vi; break; 3818 case 43: op = rv_op_vsm3c_vi; break; 3819 case 44: op = rv_op_vghsh_vv; break; 3820 case 45: op = rv_op_vsha2ms_vv; break; 3821 case 46: op = rv_op_vsha2ch_vv; break; 3822 case 47: op = rv_op_vsha2cl_vv; break; 3823 } 3824 } 3825 break; 3826 case 30: 3827 switch (((inst >> 22) & 0b1111111000) | 3828 ((inst >> 12) & 0b0000000111)) { 3829 case 0: op = rv_op_addd; break; 3830 case 1: op = rv_op_slld; break; 3831 case 5: op = rv_op_srld; break; 3832 case 8: op = rv_op_muld; break; 3833 case 12: op = rv_op_divd; break; 3834 case 13: op = rv_op_divud; break; 3835 case 14: op = rv_op_remd; break; 3836 case 15: op = rv_op_remud; break; 3837 case 256: op = rv_op_subd; break; 3838 case 261: op = rv_op_srad; break; 3839 } 3840 break; 3841 } 3842 break; 3843 } 3844 dec->op = op; 3845 } 3846 3847 /* operand extractors */ 3848 3849 static uint32_t operand_rd(rv_inst inst) 3850 { 3851 return (inst << 52) >> 59; 3852 } 3853 3854 static uint32_t operand_rs1(rv_inst inst) 3855 { 3856 return (inst << 44) >> 59; 3857 } 3858 3859 static uint32_t operand_rs2(rv_inst inst) 3860 { 3861 return (inst << 39) >> 59; 3862 } 3863 3864 static uint32_t operand_rs3(rv_inst inst) 3865 { 3866 return (inst << 32) >> 59; 3867 } 3868 3869 static uint32_t operand_aq(rv_inst inst) 3870 { 3871 return (inst << 37) >> 63; 3872 } 3873 3874 static uint32_t operand_rl(rv_inst inst) 3875 { 3876 return (inst << 38) >> 63; 3877 } 3878 3879 static uint32_t operand_pred(rv_inst inst) 3880 { 3881 return (inst << 36) >> 60; 3882 } 3883 3884 static uint32_t operand_succ(rv_inst inst) 3885 { 3886 return (inst << 40) >> 60; 3887 } 3888 3889 static uint32_t operand_rm(rv_inst inst) 3890 { 3891 return (inst << 49) >> 61; 3892 } 3893 3894 static uint32_t operand_shamt5(rv_inst inst) 3895 { 3896 return (inst << 39) >> 59; 3897 } 3898 3899 static uint32_t operand_shamt6(rv_inst inst) 3900 { 3901 return (inst << 38) >> 58; 3902 } 3903 3904 static uint32_t operand_shamt7(rv_inst inst) 3905 { 3906 return (inst << 37) >> 57; 3907 } 3908 3909 static uint32_t operand_crdq(rv_inst inst) 3910 { 3911 return (inst << 59) >> 61; 3912 } 3913 3914 static uint32_t operand_crs1q(rv_inst inst) 3915 { 3916 return (inst << 54) >> 61; 3917 } 3918 3919 static uint32_t operand_crs1rdq(rv_inst inst) 3920 { 3921 return (inst << 54) >> 61; 3922 } 3923 3924 static uint32_t operand_crs2q(rv_inst inst) 3925 { 3926 return (inst << 59) >> 61; 3927 } 3928 3929 static uint32_t calculate_xreg(uint32_t sreg) 3930 { 3931 return sreg < 2 ? sreg + 8 : sreg + 16; 3932 } 3933 3934 static uint32_t operand_sreg1(rv_inst inst) 3935 { 3936 return calculate_xreg((inst << 54) >> 61); 3937 } 3938 3939 static uint32_t operand_sreg2(rv_inst inst) 3940 { 3941 return calculate_xreg((inst << 59) >> 61); 3942 } 3943 3944 static uint32_t operand_crd(rv_inst inst) 3945 { 3946 return (inst << 52) >> 59; 3947 } 3948 3949 static uint32_t operand_crs1(rv_inst inst) 3950 { 3951 return (inst << 52) >> 59; 3952 } 3953 3954 static uint32_t operand_crs1rd(rv_inst inst) 3955 { 3956 return (inst << 52) >> 59; 3957 } 3958 3959 static uint32_t operand_crs2(rv_inst inst) 3960 { 3961 return (inst << 57) >> 59; 3962 } 3963 3964 static uint32_t operand_cimmsh5(rv_inst inst) 3965 { 3966 return (inst << 57) >> 59; 3967 } 3968 3969 static uint32_t operand_csr12(rv_inst inst) 3970 { 3971 return (inst << 32) >> 52; 3972 } 3973 3974 static int32_t operand_imm12(rv_inst inst) 3975 { 3976 return ((int64_t)inst << 32) >> 52; 3977 } 3978 3979 static int32_t operand_imm20(rv_inst inst) 3980 { 3981 return (((int64_t)inst << 32) >> 44) << 12; 3982 } 3983 3984 static int32_t operand_jimm20(rv_inst inst) 3985 { 3986 return (((int64_t)inst << 32) >> 63) << 20 | 3987 ((inst << 33) >> 54) << 1 | 3988 ((inst << 43) >> 63) << 11 | 3989 ((inst << 44) >> 56) << 12; 3990 } 3991 3992 static int32_t operand_simm12(rv_inst inst) 3993 { 3994 return (((int64_t)inst << 32) >> 57) << 5 | 3995 (inst << 52) >> 59; 3996 } 3997 3998 static int32_t operand_sbimm12(rv_inst inst) 3999 { 4000 return (((int64_t)inst << 32) >> 63) << 12 | 4001 ((inst << 33) >> 58) << 5 | 4002 ((inst << 52) >> 60) << 1 | 4003 ((inst << 56) >> 63) << 11; 4004 } 4005 4006 static uint32_t operand_cimmshl6(rv_inst inst, rv_isa isa) 4007 { 4008 int imm = ((inst << 51) >> 63) << 5 | 4009 (inst << 57) >> 59; 4010 if (isa == rv128) { 4011 imm = imm ? imm : 64; 4012 } 4013 return imm; 4014 } 4015 4016 static uint32_t operand_cimmshr6(rv_inst inst, rv_isa isa) 4017 { 4018 int imm = ((inst << 51) >> 63) << 5 | 4019 (inst << 57) >> 59; 4020 if (isa == rv128) { 4021 imm = imm | (imm & 32) << 1; 4022 imm = imm ? imm : 64; 4023 } 4024 return imm; 4025 } 4026 4027 static int32_t operand_cimmi(rv_inst inst) 4028 { 4029 return (((int64_t)inst << 51) >> 63) << 5 | 4030 (inst << 57) >> 59; 4031 } 4032 4033 static int32_t operand_cimmui(rv_inst inst) 4034 { 4035 return (((int64_t)inst << 51) >> 63) << 17 | 4036 ((inst << 57) >> 59) << 12; 4037 } 4038 4039 static uint32_t operand_cimmlwsp(rv_inst inst) 4040 { 4041 return ((inst << 51) >> 63) << 5 | 4042 ((inst << 57) >> 61) << 2 | 4043 ((inst << 60) >> 62) << 6; 4044 } 4045 4046 static uint32_t operand_cimmldsp(rv_inst inst) 4047 { 4048 return ((inst << 51) >> 63) << 5 | 4049 ((inst << 57) >> 62) << 3 | 4050 ((inst << 59) >> 61) << 6; 4051 } 4052 4053 static uint32_t operand_cimmlqsp(rv_inst inst) 4054 { 4055 return ((inst << 51) >> 63) << 5 | 4056 ((inst << 57) >> 63) << 4 | 4057 ((inst << 58) >> 60) << 6; 4058 } 4059 4060 static int32_t operand_cimm16sp(rv_inst inst) 4061 { 4062 return (((int64_t)inst << 51) >> 63) << 9 | 4063 ((inst << 57) >> 63) << 4 | 4064 ((inst << 58) >> 63) << 6 | 4065 ((inst << 59) >> 62) << 7 | 4066 ((inst << 61) >> 63) << 5; 4067 } 4068 4069 static int32_t operand_cimmj(rv_inst inst) 4070 { 4071 return (((int64_t)inst << 51) >> 63) << 11 | 4072 ((inst << 52) >> 63) << 4 | 4073 ((inst << 53) >> 62) << 8 | 4074 ((inst << 55) >> 63) << 10 | 4075 ((inst << 56) >> 63) << 6 | 4076 ((inst << 57) >> 63) << 7 | 4077 ((inst << 58) >> 61) << 1 | 4078 ((inst << 61) >> 63) << 5; 4079 } 4080 4081 static int32_t operand_cimmb(rv_inst inst) 4082 { 4083 return (((int64_t)inst << 51) >> 63) << 8 | 4084 ((inst << 52) >> 62) << 3 | 4085 ((inst << 57) >> 62) << 6 | 4086 ((inst << 59) >> 62) << 1 | 4087 ((inst << 61) >> 63) << 5; 4088 } 4089 4090 static uint32_t operand_cimmswsp(rv_inst inst) 4091 { 4092 return ((inst << 51) >> 60) << 2 | 4093 ((inst << 55) >> 62) << 6; 4094 } 4095 4096 static uint32_t operand_cimmsdsp(rv_inst inst) 4097 { 4098 return ((inst << 51) >> 61) << 3 | 4099 ((inst << 54) >> 61) << 6; 4100 } 4101 4102 static uint32_t operand_cimmsqsp(rv_inst inst) 4103 { 4104 return ((inst << 51) >> 62) << 4 | 4105 ((inst << 53) >> 60) << 6; 4106 } 4107 4108 static uint32_t operand_cimm4spn(rv_inst inst) 4109 { 4110 return ((inst << 51) >> 62) << 4 | 4111 ((inst << 53) >> 60) << 6 | 4112 ((inst << 57) >> 63) << 2 | 4113 ((inst << 58) >> 63) << 3; 4114 } 4115 4116 static uint32_t operand_cimmw(rv_inst inst) 4117 { 4118 return ((inst << 51) >> 61) << 3 | 4119 ((inst << 57) >> 63) << 2 | 4120 ((inst << 58) >> 63) << 6; 4121 } 4122 4123 static uint32_t operand_cimmd(rv_inst inst) 4124 { 4125 return ((inst << 51) >> 61) << 3 | 4126 ((inst << 57) >> 62) << 6; 4127 } 4128 4129 static uint32_t operand_cimmq(rv_inst inst) 4130 { 4131 return ((inst << 51) >> 62) << 4 | 4132 ((inst << 53) >> 63) << 8 | 4133 ((inst << 57) >> 62) << 6; 4134 } 4135 4136 static uint32_t operand_vimm(rv_inst inst) 4137 { 4138 return (int64_t)(inst << 44) >> 59; 4139 } 4140 4141 static uint32_t operand_vzimm11(rv_inst inst) 4142 { 4143 return (inst << 33) >> 53; 4144 } 4145 4146 static uint32_t operand_vzimm10(rv_inst inst) 4147 { 4148 return (inst << 34) >> 54; 4149 } 4150 4151 static uint32_t operand_vzimm6(rv_inst inst) 4152 { 4153 return ((inst << 37) >> 63) << 5 | 4154 ((inst << 44) >> 59); 4155 } 4156 4157 static uint32_t operand_bs(rv_inst inst) 4158 { 4159 return (inst << 32) >> 62; 4160 } 4161 4162 static uint32_t operand_rnum(rv_inst inst) 4163 { 4164 return (inst << 40) >> 60; 4165 } 4166 4167 static uint32_t operand_vm(rv_inst inst) 4168 { 4169 return (inst << 38) >> 63; 4170 } 4171 4172 static uint32_t operand_uimm_c_lb(rv_inst inst) 4173 { 4174 return (((inst << 58) >> 63) << 1) | 4175 ((inst << 57) >> 63); 4176 } 4177 4178 static uint32_t operand_uimm_c_lh(rv_inst inst) 4179 { 4180 return (((inst << 58) >> 63) << 1); 4181 } 4182 4183 static uint32_t operand_zcmp_spimm(rv_inst inst) 4184 { 4185 return ((inst << 60) >> 62) << 4; 4186 } 4187 4188 static uint32_t operand_zcmp_rlist(rv_inst inst) 4189 { 4190 return ((inst << 56) >> 60); 4191 } 4192 4193 static uint32_t operand_imm6(rv_inst inst) 4194 { 4195 return (inst << 38) >> 60; 4196 } 4197 4198 static uint32_t operand_imm2(rv_inst inst) 4199 { 4200 return (inst << 37) >> 62; 4201 } 4202 4203 static uint32_t operand_immh(rv_inst inst) 4204 { 4205 return (inst << 32) >> 58; 4206 } 4207 4208 static uint32_t operand_imml(rv_inst inst) 4209 { 4210 return (inst << 38) >> 58; 4211 } 4212 4213 static uint32_t calculate_stack_adj(rv_isa isa, uint32_t rlist, uint32_t spimm) 4214 { 4215 int xlen_bytes_log2 = isa == rv64 ? 3 : 2; 4216 int regs = rlist == 15 ? 13 : rlist - 3; 4217 uint32_t stack_adj_base = ROUND_UP(regs << xlen_bytes_log2, 16); 4218 return stack_adj_base + spimm; 4219 } 4220 4221 static uint32_t operand_zcmp_stack_adj(rv_inst inst, rv_isa isa) 4222 { 4223 return calculate_stack_adj(isa, operand_zcmp_rlist(inst), 4224 operand_zcmp_spimm(inst)); 4225 } 4226 4227 static uint32_t operand_tbl_index(rv_inst inst) 4228 { 4229 return ((inst << 54) >> 56); 4230 } 4231 4232 /* decode operands */ 4233 4234 static void decode_inst_operands(rv_decode *dec, rv_isa isa) 4235 { 4236 const rv_opcode_data *opcode_data = dec->opcode_data; 4237 rv_inst inst = dec->inst; 4238 dec->codec = opcode_data[dec->op].codec; 4239 switch (dec->codec) { 4240 case rv_codec_none: 4241 dec->rd = dec->rs1 = dec->rs2 = rv_ireg_zero; 4242 dec->imm = 0; 4243 break; 4244 case rv_codec_u: 4245 dec->rd = operand_rd(inst); 4246 dec->rs1 = dec->rs2 = rv_ireg_zero; 4247 dec->imm = operand_imm20(inst); 4248 break; 4249 case rv_codec_uj: 4250 dec->rd = operand_rd(inst); 4251 dec->rs1 = dec->rs2 = rv_ireg_zero; 4252 dec->imm = operand_jimm20(inst); 4253 break; 4254 case rv_codec_i: 4255 dec->rd = operand_rd(inst); 4256 dec->rs1 = operand_rs1(inst); 4257 dec->rs2 = rv_ireg_zero; 4258 dec->imm = operand_imm12(inst); 4259 break; 4260 case rv_codec_i_sh5: 4261 dec->rd = operand_rd(inst); 4262 dec->rs1 = operand_rs1(inst); 4263 dec->rs2 = rv_ireg_zero; 4264 dec->imm = operand_shamt5(inst); 4265 break; 4266 case rv_codec_i_sh6: 4267 dec->rd = operand_rd(inst); 4268 dec->rs1 = operand_rs1(inst); 4269 dec->rs2 = rv_ireg_zero; 4270 dec->imm = operand_shamt6(inst); 4271 break; 4272 case rv_codec_i_sh7: 4273 dec->rd = operand_rd(inst); 4274 dec->rs1 = operand_rs1(inst); 4275 dec->rs2 = rv_ireg_zero; 4276 dec->imm = operand_shamt7(inst); 4277 break; 4278 case rv_codec_i_csr: 4279 dec->rd = operand_rd(inst); 4280 dec->rs1 = operand_rs1(inst); 4281 dec->rs2 = rv_ireg_zero; 4282 dec->imm = operand_csr12(inst); 4283 break; 4284 case rv_codec_s: 4285 dec->rd = rv_ireg_zero; 4286 dec->rs1 = operand_rs1(inst); 4287 dec->rs2 = operand_rs2(inst); 4288 dec->imm = operand_simm12(inst); 4289 break; 4290 case rv_codec_sb: 4291 dec->rd = rv_ireg_zero; 4292 dec->rs1 = operand_rs1(inst); 4293 dec->rs2 = operand_rs2(inst); 4294 dec->imm = operand_sbimm12(inst); 4295 break; 4296 case rv_codec_r: 4297 dec->rd = operand_rd(inst); 4298 dec->rs1 = operand_rs1(inst); 4299 dec->rs2 = operand_rs2(inst); 4300 dec->imm = 0; 4301 break; 4302 case rv_codec_r_m: 4303 dec->rd = operand_rd(inst); 4304 dec->rs1 = operand_rs1(inst); 4305 dec->rs2 = operand_rs2(inst); 4306 dec->imm = 0; 4307 dec->rm = operand_rm(inst); 4308 break; 4309 case rv_codec_r4_m: 4310 dec->rd = operand_rd(inst); 4311 dec->rs1 = operand_rs1(inst); 4312 dec->rs2 = operand_rs2(inst); 4313 dec->rs3 = operand_rs3(inst); 4314 dec->imm = 0; 4315 dec->rm = operand_rm(inst); 4316 break; 4317 case rv_codec_r_a: 4318 dec->rd = operand_rd(inst); 4319 dec->rs1 = operand_rs1(inst); 4320 dec->rs2 = operand_rs2(inst); 4321 dec->imm = 0; 4322 dec->aq = operand_aq(inst); 4323 dec->rl = operand_rl(inst); 4324 break; 4325 case rv_codec_r_l: 4326 dec->rd = operand_rd(inst); 4327 dec->rs1 = operand_rs1(inst); 4328 dec->rs2 = rv_ireg_zero; 4329 dec->imm = 0; 4330 dec->aq = operand_aq(inst); 4331 dec->rl = operand_rl(inst); 4332 break; 4333 case rv_codec_r_f: 4334 dec->rd = dec->rs1 = dec->rs2 = rv_ireg_zero; 4335 dec->pred = operand_pred(inst); 4336 dec->succ = operand_succ(inst); 4337 dec->imm = 0; 4338 break; 4339 case rv_codec_cb: 4340 dec->rd = rv_ireg_zero; 4341 dec->rs1 = operand_crs1q(inst) + 8; 4342 dec->rs2 = rv_ireg_zero; 4343 dec->imm = operand_cimmb(inst); 4344 break; 4345 case rv_codec_cb_imm: 4346 dec->rd = dec->rs1 = operand_crs1rdq(inst) + 8; 4347 dec->rs2 = rv_ireg_zero; 4348 dec->imm = operand_cimmi(inst); 4349 break; 4350 case rv_codec_cb_sh5: 4351 dec->rd = dec->rs1 = operand_crs1rdq(inst) + 8; 4352 dec->rs2 = rv_ireg_zero; 4353 dec->imm = operand_cimmsh5(inst); 4354 break; 4355 case rv_codec_cb_sh6: 4356 dec->rd = dec->rs1 = operand_crs1rdq(inst) + 8; 4357 dec->rs2 = rv_ireg_zero; 4358 dec->imm = operand_cimmshr6(inst, isa); 4359 break; 4360 case rv_codec_ci: 4361 dec->rd = dec->rs1 = operand_crs1rd(inst); 4362 dec->rs2 = rv_ireg_zero; 4363 dec->imm = operand_cimmi(inst); 4364 break; 4365 case rv_codec_ci_sh5: 4366 dec->rd = dec->rs1 = operand_crs1rd(inst); 4367 dec->rs2 = rv_ireg_zero; 4368 dec->imm = operand_cimmsh5(inst); 4369 break; 4370 case rv_codec_ci_sh6: 4371 dec->rd = dec->rs1 = operand_crs1rd(inst); 4372 dec->rs2 = rv_ireg_zero; 4373 dec->imm = operand_cimmshl6(inst, isa); 4374 break; 4375 case rv_codec_ci_16sp: 4376 dec->rd = rv_ireg_sp; 4377 dec->rs1 = rv_ireg_sp; 4378 dec->rs2 = rv_ireg_zero; 4379 dec->imm = operand_cimm16sp(inst); 4380 break; 4381 case rv_codec_ci_lwsp: 4382 dec->rd = operand_crd(inst); 4383 dec->rs1 = rv_ireg_sp; 4384 dec->rs2 = rv_ireg_zero; 4385 dec->imm = operand_cimmlwsp(inst); 4386 break; 4387 case rv_codec_ci_ldsp: 4388 dec->rd = operand_crd(inst); 4389 dec->rs1 = rv_ireg_sp; 4390 dec->rs2 = rv_ireg_zero; 4391 dec->imm = operand_cimmldsp(inst); 4392 break; 4393 case rv_codec_ci_lqsp: 4394 dec->rd = operand_crd(inst); 4395 dec->rs1 = rv_ireg_sp; 4396 dec->rs2 = rv_ireg_zero; 4397 dec->imm = operand_cimmlqsp(inst); 4398 break; 4399 case rv_codec_ci_li: 4400 dec->rd = operand_crd(inst); 4401 dec->rs1 = rv_ireg_zero; 4402 dec->rs2 = rv_ireg_zero; 4403 dec->imm = operand_cimmi(inst); 4404 break; 4405 case rv_codec_ci_lui: 4406 dec->rd = operand_crd(inst); 4407 dec->rs1 = rv_ireg_zero; 4408 dec->rs2 = rv_ireg_zero; 4409 dec->imm = operand_cimmui(inst); 4410 break; 4411 case rv_codec_ci_none: 4412 dec->rd = dec->rs1 = dec->rs2 = rv_ireg_zero; 4413 dec->imm = 0; 4414 break; 4415 case rv_codec_ciw_4spn: 4416 dec->rd = operand_crdq(inst) + 8; 4417 dec->rs1 = rv_ireg_sp; 4418 dec->rs2 = rv_ireg_zero; 4419 dec->imm = operand_cimm4spn(inst); 4420 break; 4421 case rv_codec_cj: 4422 dec->rd = dec->rs1 = dec->rs2 = rv_ireg_zero; 4423 dec->imm = operand_cimmj(inst); 4424 break; 4425 case rv_codec_cj_jal: 4426 dec->rd = rv_ireg_ra; 4427 dec->rs1 = dec->rs2 = rv_ireg_zero; 4428 dec->imm = operand_cimmj(inst); 4429 break; 4430 case rv_codec_cl_lw: 4431 dec->rd = operand_crdq(inst) + 8; 4432 dec->rs1 = operand_crs1q(inst) + 8; 4433 dec->rs2 = rv_ireg_zero; 4434 dec->imm = operand_cimmw(inst); 4435 break; 4436 case rv_codec_cl_ld: 4437 dec->rd = operand_crdq(inst) + 8; 4438 dec->rs1 = operand_crs1q(inst) + 8; 4439 dec->rs2 = rv_ireg_zero; 4440 dec->imm = operand_cimmd(inst); 4441 break; 4442 case rv_codec_cl_lq: 4443 dec->rd = operand_crdq(inst) + 8; 4444 dec->rs1 = operand_crs1q(inst) + 8; 4445 dec->rs2 = rv_ireg_zero; 4446 dec->imm = operand_cimmq(inst); 4447 break; 4448 case rv_codec_cr: 4449 dec->rd = dec->rs1 = operand_crs1rd(inst); 4450 dec->rs2 = operand_crs2(inst); 4451 dec->imm = 0; 4452 break; 4453 case rv_codec_cr_mv: 4454 dec->rd = operand_crd(inst); 4455 dec->rs1 = operand_crs2(inst); 4456 dec->rs2 = rv_ireg_zero; 4457 dec->imm = 0; 4458 break; 4459 case rv_codec_cr_jalr: 4460 dec->rd = rv_ireg_ra; 4461 dec->rs1 = operand_crs1(inst); 4462 dec->rs2 = rv_ireg_zero; 4463 dec->imm = 0; 4464 break; 4465 case rv_codec_cr_jr: 4466 dec->rd = rv_ireg_zero; 4467 dec->rs1 = operand_crs1(inst); 4468 dec->rs2 = rv_ireg_zero; 4469 dec->imm = 0; 4470 break; 4471 case rv_codec_cs: 4472 dec->rd = dec->rs1 = operand_crs1rdq(inst) + 8; 4473 dec->rs2 = operand_crs2q(inst) + 8; 4474 dec->imm = 0; 4475 break; 4476 case rv_codec_cs_sw: 4477 dec->rd = rv_ireg_zero; 4478 dec->rs1 = operand_crs1q(inst) + 8; 4479 dec->rs2 = operand_crs2q(inst) + 8; 4480 dec->imm = operand_cimmw(inst); 4481 break; 4482 case rv_codec_cs_sd: 4483 dec->rd = rv_ireg_zero; 4484 dec->rs1 = operand_crs1q(inst) + 8; 4485 dec->rs2 = operand_crs2q(inst) + 8; 4486 dec->imm = operand_cimmd(inst); 4487 break; 4488 case rv_codec_cs_sq: 4489 dec->rd = rv_ireg_zero; 4490 dec->rs1 = operand_crs1q(inst) + 8; 4491 dec->rs2 = operand_crs2q(inst) + 8; 4492 dec->imm = operand_cimmq(inst); 4493 break; 4494 case rv_codec_css_swsp: 4495 dec->rd = rv_ireg_zero; 4496 dec->rs1 = rv_ireg_sp; 4497 dec->rs2 = operand_crs2(inst); 4498 dec->imm = operand_cimmswsp(inst); 4499 break; 4500 case rv_codec_css_sdsp: 4501 dec->rd = rv_ireg_zero; 4502 dec->rs1 = rv_ireg_sp; 4503 dec->rs2 = operand_crs2(inst); 4504 dec->imm = operand_cimmsdsp(inst); 4505 break; 4506 case rv_codec_css_sqsp: 4507 dec->rd = rv_ireg_zero; 4508 dec->rs1 = rv_ireg_sp; 4509 dec->rs2 = operand_crs2(inst); 4510 dec->imm = operand_cimmsqsp(inst); 4511 break; 4512 case rv_codec_k_bs: 4513 dec->rs1 = operand_rs1(inst); 4514 dec->rs2 = operand_rs2(inst); 4515 dec->bs = operand_bs(inst); 4516 break; 4517 case rv_codec_k_rnum: 4518 dec->rd = operand_rd(inst); 4519 dec->rs1 = operand_rs1(inst); 4520 dec->rnum = operand_rnum(inst); 4521 break; 4522 case rv_codec_v_r: 4523 dec->rd = operand_rd(inst); 4524 dec->rs1 = operand_rs1(inst); 4525 dec->rs2 = operand_rs2(inst); 4526 dec->vm = operand_vm(inst); 4527 break; 4528 case rv_codec_v_ldst: 4529 dec->rd = operand_rd(inst); 4530 dec->rs1 = operand_rs1(inst); 4531 dec->vm = operand_vm(inst); 4532 break; 4533 case rv_codec_v_i: 4534 dec->rd = operand_rd(inst); 4535 dec->rs2 = operand_rs2(inst); 4536 dec->imm = operand_vimm(inst); 4537 dec->vm = operand_vm(inst); 4538 break; 4539 case rv_codec_vror_vi: 4540 dec->rd = operand_rd(inst); 4541 dec->rs2 = operand_rs2(inst); 4542 dec->imm = operand_vzimm6(inst); 4543 dec->vm = operand_vm(inst); 4544 break; 4545 case rv_codec_vsetvli: 4546 dec->rd = operand_rd(inst); 4547 dec->rs1 = operand_rs1(inst); 4548 dec->vzimm = operand_vzimm11(inst); 4549 break; 4550 case rv_codec_vsetivli: 4551 dec->rd = operand_rd(inst); 4552 dec->imm = operand_vimm(inst); 4553 dec->vzimm = operand_vzimm10(inst); 4554 break; 4555 case rv_codec_zcb_lb: 4556 dec->rs1 = operand_crs1q(inst) + 8; 4557 dec->rs2 = operand_crs2q(inst) + 8; 4558 dec->imm = operand_uimm_c_lb(inst); 4559 break; 4560 case rv_codec_zcb_lh: 4561 dec->rs1 = operand_crs1q(inst) + 8; 4562 dec->rs2 = operand_crs2q(inst) + 8; 4563 dec->imm = operand_uimm_c_lh(inst); 4564 break; 4565 case rv_codec_zcb_ext: 4566 dec->rd = operand_crs1q(inst) + 8; 4567 break; 4568 case rv_codec_zcb_mul: 4569 dec->rd = operand_crs1rdq(inst) + 8; 4570 dec->rs2 = operand_crs2q(inst) + 8; 4571 break; 4572 case rv_codec_zcmp_cm_pushpop: 4573 dec->imm = operand_zcmp_stack_adj(inst, isa); 4574 dec->rlist = operand_zcmp_rlist(inst); 4575 break; 4576 case rv_codec_zcmp_cm_mv: 4577 dec->rd = operand_sreg1(inst); 4578 dec->rs2 = operand_sreg2(inst); 4579 break; 4580 case rv_codec_zcmt_jt: 4581 dec->imm = operand_tbl_index(inst); 4582 break; 4583 case rv_codec_fli: 4584 dec->rd = operand_rd(inst); 4585 dec->imm = operand_rs1(inst); 4586 break; 4587 case rv_codec_r2_imm5: 4588 dec->rd = operand_rd(inst); 4589 dec->rs1 = operand_rs1(inst); 4590 dec->imm = operand_rs2(inst); 4591 break; 4592 case rv_codec_r2: 4593 dec->rd = operand_rd(inst); 4594 dec->rs1 = operand_rs1(inst); 4595 break; 4596 case rv_codec_r2_imm6: 4597 dec->rd = operand_rd(inst); 4598 dec->rs1 = operand_rs1(inst); 4599 dec->imm = operand_imm6(inst); 4600 break; 4601 case rv_codec_r_imm2: 4602 dec->rd = operand_rd(inst); 4603 dec->rs1 = operand_rs1(inst); 4604 dec->rs2 = operand_rs2(inst); 4605 dec->imm = operand_imm2(inst); 4606 break; 4607 case rv_codec_r2_immhl: 4608 dec->rd = operand_rd(inst); 4609 dec->rs1 = operand_rs1(inst); 4610 dec->imm = operand_immh(inst); 4611 dec->imm1 = operand_imml(inst); 4612 break; 4613 case rv_codec_r2_imm2_imm5: 4614 dec->rd = operand_rd(inst); 4615 dec->rs1 = operand_rs1(inst); 4616 dec->imm = sextract32(operand_rs2(inst), 0, 5); 4617 dec->imm1 = operand_imm2(inst); 4618 break; 4619 }; 4620 } 4621 4622 /* check constraint */ 4623 4624 static bool check_constraints(rv_decode *dec, const rvc_constraint *c) 4625 { 4626 int32_t imm = dec->imm; 4627 uint8_t rd = dec->rd, rs1 = dec->rs1, rs2 = dec->rs2; 4628 while (*c != rvc_end) { 4629 switch (*c) { 4630 case rvc_rd_eq_ra: 4631 if (!(rd == 1)) { 4632 return false; 4633 } 4634 break; 4635 case rvc_rd_eq_x0: 4636 if (!(rd == 0)) { 4637 return false; 4638 } 4639 break; 4640 case rvc_rs1_eq_x0: 4641 if (!(rs1 == 0)) { 4642 return false; 4643 } 4644 break; 4645 case rvc_rs2_eq_x0: 4646 if (!(rs2 == 0)) { 4647 return false; 4648 } 4649 break; 4650 case rvc_rs2_eq_rs1: 4651 if (!(rs2 == rs1)) { 4652 return false; 4653 } 4654 break; 4655 case rvc_rs1_eq_ra: 4656 if (!(rs1 == 1)) { 4657 return false; 4658 } 4659 break; 4660 case rvc_imm_eq_zero: 4661 if (!(imm == 0)) { 4662 return false; 4663 } 4664 break; 4665 case rvc_imm_eq_n1: 4666 if (!(imm == -1)) { 4667 return false; 4668 } 4669 break; 4670 case rvc_imm_eq_p1: 4671 if (!(imm == 1)) { 4672 return false; 4673 } 4674 break; 4675 case rvc_csr_eq_0x001: 4676 if (!(imm == 0x001)) { 4677 return false; 4678 } 4679 break; 4680 case rvc_csr_eq_0x002: 4681 if (!(imm == 0x002)) { 4682 return false; 4683 } 4684 break; 4685 case rvc_csr_eq_0x003: 4686 if (!(imm == 0x003)) { 4687 return false; 4688 } 4689 break; 4690 case rvc_csr_eq_0xc00: 4691 if (!(imm == 0xc00)) { 4692 return false; 4693 } 4694 break; 4695 case rvc_csr_eq_0xc01: 4696 if (!(imm == 0xc01)) { 4697 return false; 4698 } 4699 break; 4700 case rvc_csr_eq_0xc02: 4701 if (!(imm == 0xc02)) { 4702 return false; 4703 } 4704 break; 4705 case rvc_csr_eq_0xc80: 4706 if (!(imm == 0xc80)) { 4707 return false; 4708 } 4709 break; 4710 case rvc_csr_eq_0xc81: 4711 if (!(imm == 0xc81)) { 4712 return false; 4713 } 4714 break; 4715 case rvc_csr_eq_0xc82: 4716 if (!(imm == 0xc82)) { 4717 return false; 4718 } 4719 break; 4720 default: break; 4721 } 4722 c++; 4723 } 4724 return true; 4725 } 4726 4727 /* instruction length */ 4728 4729 static size_t inst_length(rv_inst inst) 4730 { 4731 /* NOTE: supports maximum instruction size of 64-bits */ 4732 4733 /* 4734 * instruction length coding 4735 * 4736 * aa - 16 bit aa != 11 4737 * bbb11 - 32 bit bbb != 111 4738 * 011111 - 48 bit 4739 * 0111111 - 64 bit 4740 */ 4741 4742 return (inst & 0b11) != 0b11 ? 2 4743 : (inst & 0b11100) != 0b11100 ? 4 4744 : (inst & 0b111111) == 0b011111 ? 6 4745 : (inst & 0b1111111) == 0b0111111 ? 8 4746 : 0; 4747 } 4748 4749 /* format instruction */ 4750 4751 static void append(char *s1, const char *s2, size_t n) 4752 { 4753 size_t l1 = strlen(s1); 4754 if (n - l1 - 1 > 0) { 4755 strncat(s1, s2, n - l1); 4756 } 4757 } 4758 4759 static void format_inst(char *buf, size_t buflen, size_t tab, rv_decode *dec) 4760 { 4761 const rv_opcode_data *opcode_data = dec->opcode_data; 4762 char tmp[64]; 4763 const char *fmt; 4764 4765 fmt = opcode_data[dec->op].format; 4766 while (*fmt) { 4767 switch (*fmt) { 4768 case 'O': 4769 append(buf, opcode_data[dec->op].name, buflen); 4770 break; 4771 case '(': 4772 append(buf, "(", buflen); 4773 break; 4774 case ',': 4775 append(buf, ",", buflen); 4776 break; 4777 case ')': 4778 append(buf, ")", buflen); 4779 break; 4780 case '-': 4781 append(buf, "-", buflen); 4782 break; 4783 case 'b': 4784 snprintf(tmp, sizeof(tmp), "%d", dec->bs); 4785 append(buf, tmp, buflen); 4786 break; 4787 case 'n': 4788 snprintf(tmp, sizeof(tmp), "%d", dec->rnum); 4789 append(buf, tmp, buflen); 4790 break; 4791 case '0': 4792 append(buf, rv_ireg_name_sym[dec->rd], buflen); 4793 break; 4794 case '1': 4795 append(buf, rv_ireg_name_sym[dec->rs1], buflen); 4796 break; 4797 case '2': 4798 append(buf, rv_ireg_name_sym[dec->rs2], buflen); 4799 break; 4800 case '3': 4801 append(buf, dec->cfg->ext_zfinx ? rv_ireg_name_sym[dec->rd] : 4802 rv_freg_name_sym[dec->rd], 4803 buflen); 4804 break; 4805 case '4': 4806 append(buf, dec->cfg->ext_zfinx ? rv_ireg_name_sym[dec->rs1] : 4807 rv_freg_name_sym[dec->rs1], 4808 buflen); 4809 break; 4810 case '5': 4811 append(buf, dec->cfg->ext_zfinx ? rv_ireg_name_sym[dec->rs2] : 4812 rv_freg_name_sym[dec->rs2], 4813 buflen); 4814 break; 4815 case '6': 4816 append(buf, dec->cfg->ext_zfinx ? rv_ireg_name_sym[dec->rs3] : 4817 rv_freg_name_sym[dec->rs3], 4818 buflen); 4819 break; 4820 case '7': 4821 snprintf(tmp, sizeof(tmp), "%d", dec->rs1); 4822 append(buf, tmp, buflen); 4823 break; 4824 case 'i': 4825 snprintf(tmp, sizeof(tmp), "%d", dec->imm); 4826 append(buf, tmp, buflen); 4827 break; 4828 case 'u': 4829 snprintf(tmp, sizeof(tmp), "%u", ((uint32_t)dec->imm & 0b111111)); 4830 append(buf, tmp, buflen); 4831 break; 4832 case 'j': 4833 snprintf(tmp, sizeof(tmp), "%d", dec->imm1); 4834 append(buf, tmp, buflen); 4835 break; 4836 case 'o': 4837 snprintf(tmp, sizeof(tmp), "%d", dec->imm); 4838 append(buf, tmp, buflen); 4839 while (strlen(buf) < tab * 2) { 4840 append(buf, " ", buflen); 4841 } 4842 snprintf(tmp, sizeof(tmp), "# 0x%" PRIx64, 4843 dec->pc + dec->imm); 4844 append(buf, tmp, buflen); 4845 break; 4846 case 'U': 4847 fmt++; 4848 snprintf(tmp, sizeof(tmp), "%d", dec->imm >> 12); 4849 append(buf, tmp, buflen); 4850 if (*fmt == 'o') { 4851 while (strlen(buf) < tab * 2) { 4852 append(buf, " ", buflen); 4853 } 4854 snprintf(tmp, sizeof(tmp), "# 0x%" PRIx64, 4855 dec->pc + dec->imm); 4856 append(buf, tmp, buflen); 4857 } 4858 break; 4859 case 'c': { 4860 const char *name = csr_name(dec->imm & 0xfff); 4861 if (name) { 4862 append(buf, name, buflen); 4863 } else { 4864 snprintf(tmp, sizeof(tmp), "0x%03x", dec->imm & 0xfff); 4865 append(buf, tmp, buflen); 4866 } 4867 break; 4868 } 4869 case 'r': 4870 switch (dec->rm) { 4871 case rv_rm_rne: 4872 append(buf, "rne", buflen); 4873 break; 4874 case rv_rm_rtz: 4875 append(buf, "rtz", buflen); 4876 break; 4877 case rv_rm_rdn: 4878 append(buf, "rdn", buflen); 4879 break; 4880 case rv_rm_rup: 4881 append(buf, "rup", buflen); 4882 break; 4883 case rv_rm_rmm: 4884 append(buf, "rmm", buflen); 4885 break; 4886 case rv_rm_dyn: 4887 append(buf, "dyn", buflen); 4888 break; 4889 default: 4890 append(buf, "inv", buflen); 4891 break; 4892 } 4893 break; 4894 case 'p': 4895 if (dec->pred & rv_fence_i) { 4896 append(buf, "i", buflen); 4897 } 4898 if (dec->pred & rv_fence_o) { 4899 append(buf, "o", buflen); 4900 } 4901 if (dec->pred & rv_fence_r) { 4902 append(buf, "r", buflen); 4903 } 4904 if (dec->pred & rv_fence_w) { 4905 append(buf, "w", buflen); 4906 } 4907 break; 4908 case 's': 4909 if (dec->succ & rv_fence_i) { 4910 append(buf, "i", buflen); 4911 } 4912 if (dec->succ & rv_fence_o) { 4913 append(buf, "o", buflen); 4914 } 4915 if (dec->succ & rv_fence_r) { 4916 append(buf, "r", buflen); 4917 } 4918 if (dec->succ & rv_fence_w) { 4919 append(buf, "w", buflen); 4920 } 4921 break; 4922 case '\t': 4923 while (strlen(buf) < tab) { 4924 append(buf, " ", buflen); 4925 } 4926 break; 4927 case 'A': 4928 if (dec->aq) { 4929 append(buf, ".aq", buflen); 4930 } 4931 break; 4932 case 'R': 4933 if (dec->rl) { 4934 append(buf, ".rl", buflen); 4935 } 4936 break; 4937 case 'l': 4938 append(buf, ",v0", buflen); 4939 break; 4940 case 'm': 4941 if (dec->vm == 0) { 4942 append(buf, ",v0.t", buflen); 4943 } 4944 break; 4945 case 'D': 4946 append(buf, rv_vreg_name_sym[dec->rd], buflen); 4947 break; 4948 case 'E': 4949 append(buf, rv_vreg_name_sym[dec->rs1], buflen); 4950 break; 4951 case 'F': 4952 append(buf, rv_vreg_name_sym[dec->rs2], buflen); 4953 break; 4954 case 'G': 4955 append(buf, rv_vreg_name_sym[dec->rs3], buflen); 4956 break; 4957 case 'v': { 4958 char nbuf[32] = {0}; 4959 const int sew = 1 << (((dec->vzimm >> 3) & 0b111) + 3); 4960 sprintf(nbuf, "%d", sew); 4961 const int lmul = dec->vzimm & 0b11; 4962 const int flmul = (dec->vzimm >> 2) & 1; 4963 const char *vta = (dec->vzimm >> 6) & 1 ? "ta" : "tu"; 4964 const char *vma = (dec->vzimm >> 7) & 1 ? "ma" : "mu"; 4965 append(buf, "e", buflen); 4966 append(buf, nbuf, buflen); 4967 append(buf, ",m", buflen); 4968 if (flmul) { 4969 switch (lmul) { 4970 case 3: 4971 sprintf(nbuf, "f2"); 4972 break; 4973 case 2: 4974 sprintf(nbuf, "f4"); 4975 break; 4976 case 1: 4977 sprintf(nbuf, "f8"); 4978 break; 4979 } 4980 append(buf, nbuf, buflen); 4981 } else { 4982 sprintf(nbuf, "%d", 1 << lmul); 4983 append(buf, nbuf, buflen); 4984 } 4985 append(buf, ",", buflen); 4986 append(buf, vta, buflen); 4987 append(buf, ",", buflen); 4988 append(buf, vma, buflen); 4989 break; 4990 } 4991 case 'x': { 4992 switch (dec->rlist) { 4993 case 4: 4994 snprintf(tmp, sizeof(tmp), "{ra}"); 4995 break; 4996 case 5: 4997 snprintf(tmp, sizeof(tmp), "{ra, s0}"); 4998 break; 4999 case 15: 5000 snprintf(tmp, sizeof(tmp), "{ra, s0-s11}"); 5001 break; 5002 default: 5003 snprintf(tmp, sizeof(tmp), "{ra, s0-s%d}", dec->rlist - 5); 5004 break; 5005 } 5006 append(buf, tmp, buflen); 5007 break; 5008 } 5009 case 'h': 5010 append(buf, rv_fli_name_const[dec->imm], buflen); 5011 break; 5012 default: 5013 break; 5014 } 5015 fmt++; 5016 } 5017 } 5018 5019 /* lift instruction to pseudo-instruction */ 5020 5021 static void decode_inst_lift_pseudo(rv_decode *dec) 5022 { 5023 const rv_opcode_data *opcode_data = dec->opcode_data; 5024 const rv_comp_data *comp_data = opcode_data[dec->op].pseudo; 5025 if (!comp_data) { 5026 return; 5027 } 5028 while (comp_data->constraints) { 5029 if (check_constraints(dec, comp_data->constraints)) { 5030 dec->op = comp_data->op; 5031 dec->codec = opcode_data[dec->op].codec; 5032 return; 5033 } 5034 comp_data++; 5035 } 5036 } 5037 5038 /* decompress instruction */ 5039 5040 static void decode_inst_decompress_rv32(rv_decode *dec) 5041 { 5042 const rv_opcode_data *opcode_data = dec->opcode_data; 5043 int decomp_op = opcode_data[dec->op].decomp_rv32; 5044 if (decomp_op != rv_op_illegal) { 5045 if ((opcode_data[dec->op].decomp_data & rvcd_imm_nz) 5046 && dec->imm == 0) { 5047 dec->op = rv_op_illegal; 5048 } else { 5049 dec->op = decomp_op; 5050 dec->codec = opcode_data[decomp_op].codec; 5051 } 5052 } 5053 } 5054 5055 static void decode_inst_decompress_rv64(rv_decode *dec) 5056 { 5057 const rv_opcode_data *opcode_data = dec->opcode_data; 5058 int decomp_op = opcode_data[dec->op].decomp_rv64; 5059 if (decomp_op != rv_op_illegal) { 5060 if ((opcode_data[dec->op].decomp_data & rvcd_imm_nz) 5061 && dec->imm == 0) { 5062 dec->op = rv_op_illegal; 5063 } else { 5064 dec->op = decomp_op; 5065 dec->codec = opcode_data[decomp_op].codec; 5066 } 5067 } 5068 } 5069 5070 static void decode_inst_decompress_rv128(rv_decode *dec) 5071 { 5072 const rv_opcode_data *opcode_data = dec->opcode_data; 5073 int decomp_op = opcode_data[dec->op].decomp_rv128; 5074 if (decomp_op != rv_op_illegal) { 5075 if ((opcode_data[dec->op].decomp_data & rvcd_imm_nz) 5076 && dec->imm == 0) { 5077 dec->op = rv_op_illegal; 5078 } else { 5079 dec->op = decomp_op; 5080 dec->codec = opcode_data[decomp_op].codec; 5081 } 5082 } 5083 } 5084 5085 static void decode_inst_decompress(rv_decode *dec, rv_isa isa) 5086 { 5087 switch (isa) { 5088 case rv32: 5089 decode_inst_decompress_rv32(dec); 5090 break; 5091 case rv64: 5092 decode_inst_decompress_rv64(dec); 5093 break; 5094 case rv128: 5095 decode_inst_decompress_rv128(dec); 5096 break; 5097 } 5098 } 5099 5100 /* disassemble instruction */ 5101 5102 static void 5103 disasm_inst(char *buf, size_t buflen, rv_isa isa, uint64_t pc, rv_inst inst, 5104 RISCVCPUConfig *cfg) 5105 { 5106 rv_decode dec = { 0 }; 5107 dec.pc = pc; 5108 dec.inst = inst; 5109 dec.cfg = cfg; 5110 5111 static const struct { 5112 bool (*guard_func)(const RISCVCPUConfig *); 5113 const rv_opcode_data *opcode_data; 5114 void (*decode_func)(rv_decode *, rv_isa); 5115 } decoders[] = { 5116 { always_true_p, rvi_opcode_data, decode_inst_opcode }, 5117 { has_xtheadba_p, xthead_opcode_data, decode_xtheadba }, 5118 { has_xtheadbb_p, xthead_opcode_data, decode_xtheadbb }, 5119 { has_xtheadbs_p, xthead_opcode_data, decode_xtheadbs }, 5120 { has_xtheadcmo_p, xthead_opcode_data, decode_xtheadcmo }, 5121 { has_xtheadcondmov_p, xthead_opcode_data, decode_xtheadcondmov }, 5122 { has_xtheadfmemidx_p, xthead_opcode_data, decode_xtheadfmemidx }, 5123 { has_xtheadfmv_p, xthead_opcode_data, decode_xtheadfmv }, 5124 { has_xtheadmac_p, xthead_opcode_data, decode_xtheadmac }, 5125 { has_xtheadmemidx_p, xthead_opcode_data, decode_xtheadmemidx }, 5126 { has_xtheadmempair_p, xthead_opcode_data, decode_xtheadmempair }, 5127 { has_xtheadsync_p, xthead_opcode_data, decode_xtheadsync }, 5128 { has_XVentanaCondOps_p, ventana_opcode_data, decode_xventanacondops }, 5129 }; 5130 5131 for (size_t i = 0; i < ARRAY_SIZE(decoders); i++) { 5132 bool (*guard_func)(const RISCVCPUConfig *) = decoders[i].guard_func; 5133 const rv_opcode_data *opcode_data = decoders[i].opcode_data; 5134 void (*decode_func)(rv_decode *, rv_isa) = decoders[i].decode_func; 5135 5136 if (guard_func(cfg)) { 5137 dec.opcode_data = opcode_data; 5138 decode_func(&dec, isa); 5139 if (dec.op != rv_op_illegal) 5140 break; 5141 } 5142 } 5143 5144 if (dec.op == rv_op_illegal) { 5145 dec.opcode_data = rvi_opcode_data; 5146 } 5147 5148 decode_inst_operands(&dec, isa); 5149 decode_inst_decompress(&dec, isa); 5150 decode_inst_lift_pseudo(&dec); 5151 format_inst(buf, buflen, 24, &dec); 5152 } 5153 5154 #define INST_FMT_2 "%04" PRIx64 " " 5155 #define INST_FMT_4 "%08" PRIx64 " " 5156 #define INST_FMT_6 "%012" PRIx64 " " 5157 #define INST_FMT_8 "%016" PRIx64 " " 5158 5159 static int 5160 print_insn_riscv(bfd_vma memaddr, struct disassemble_info *info, rv_isa isa) 5161 { 5162 char buf[128] = { 0 }; 5163 bfd_byte packet[2]; 5164 rv_inst inst = 0; 5165 size_t len = 2; 5166 bfd_vma n; 5167 int status; 5168 5169 /* Instructions are made of 2-byte packets in little-endian order */ 5170 for (n = 0; n < len; n += 2) { 5171 status = (*info->read_memory_func)(memaddr + n, packet, 2, info); 5172 if (status != 0) { 5173 /* Don't fail just because we fell off the end. */ 5174 if (n > 0) { 5175 break; 5176 } 5177 (*info->memory_error_func)(status, memaddr, info); 5178 return status; 5179 } 5180 inst |= ((rv_inst) bfd_getl16(packet)) << (8 * n); 5181 if (n == 0) { 5182 len = inst_length(inst); 5183 } 5184 } 5185 5186 switch (len) { 5187 case 2: 5188 (*info->fprintf_func)(info->stream, INST_FMT_2, inst); 5189 break; 5190 case 4: 5191 (*info->fprintf_func)(info->stream, INST_FMT_4, inst); 5192 break; 5193 case 6: 5194 (*info->fprintf_func)(info->stream, INST_FMT_6, inst); 5195 break; 5196 default: 5197 (*info->fprintf_func)(info->stream, INST_FMT_8, inst); 5198 break; 5199 } 5200 5201 disasm_inst(buf, sizeof(buf), isa, memaddr, inst, 5202 (RISCVCPUConfig *)info->target_info); 5203 (*info->fprintf_func)(info->stream, "%s", buf); 5204 5205 return len; 5206 } 5207 5208 int print_insn_riscv32(bfd_vma memaddr, struct disassemble_info *info) 5209 { 5210 return print_insn_riscv(memaddr, info, rv32); 5211 } 5212 5213 int print_insn_riscv64(bfd_vma memaddr, struct disassemble_info *info) 5214 { 5215 return print_insn_riscv(memaddr, info, rv64); 5216 } 5217 5218 int print_insn_riscv128(bfd_vma memaddr, struct disassemble_info *info) 5219 { 5220 return print_insn_riscv(memaddr, info, rv128); 5221 } 5222