1*444fa225SPeter MaydellQEMU<->ACPI BIOS CPU hotplug interface 2*444fa225SPeter Maydell====================================== 3*444fa225SPeter Maydell 4*444fa225SPeter MaydellQEMU supports CPU hotplug via ACPI. This document 5*444fa225SPeter Maydelldescribes the interface between QEMU and the ACPI BIOS. 6*444fa225SPeter Maydell 7*444fa225SPeter MaydellACPI BIOS GPE.2 handler is dedicated for notifying OS about CPU hot-add 8*444fa225SPeter Maydelland hot-remove events. 9*444fa225SPeter Maydell 10*444fa225SPeter Maydell 11*444fa225SPeter MaydellLegacy ACPI CPU hotplug interface registers 12*444fa225SPeter Maydell------------------------------------------- 13*444fa225SPeter Maydell 14*444fa225SPeter MaydellCPU present bitmap for: 15*444fa225SPeter Maydell 16*444fa225SPeter Maydell- ICH9-LPC (IO port 0x0cd8-0xcf7, 1-byte access) 17*444fa225SPeter Maydell- PIIX-PM (IO port 0xaf00-0xaf1f, 1-byte access) 18*444fa225SPeter Maydell- One bit per CPU. Bit position reflects corresponding CPU APIC ID. Read-only. 19*444fa225SPeter Maydell- The first DWORD in bitmap is used in write mode to switch from legacy 20*444fa225SPeter Maydell to modern CPU hotplug interface, write 0 into it to do switch. 21*444fa225SPeter Maydell 22*444fa225SPeter MaydellQEMU sets corresponding CPU bit on hot-add event and issues SCI 23*444fa225SPeter Maydellwith GPE.2 event set. CPU present map is read by ACPI BIOS GPE.2 handler 24*444fa225SPeter Maydellto notify OS about CPU hot-add events. CPU hot-remove isn't supported. 25*444fa225SPeter Maydell 26*444fa225SPeter Maydell 27*444fa225SPeter MaydellModern ACPI CPU hotplug interface registers 28*444fa225SPeter Maydell------------------------------------------- 29*444fa225SPeter Maydell 30*444fa225SPeter MaydellRegister block base address: 31*444fa225SPeter Maydell 32*444fa225SPeter Maydell- ICH9-LPC IO port 0x0cd8 33*444fa225SPeter Maydell- PIIX-PM IO port 0xaf00 34*444fa225SPeter Maydell 35*444fa225SPeter MaydellRegister block size: 36*444fa225SPeter Maydell 37*444fa225SPeter Maydell- ACPI_CPU_HOTPLUG_REG_LEN = 12 38*444fa225SPeter Maydell 39*444fa225SPeter MaydellAll accesses to registers described below, imply little-endian byte order. 40*444fa225SPeter Maydell 41*444fa225SPeter MaydellReserved registers behavior: 42*444fa225SPeter Maydell 43*444fa225SPeter Maydell- write accesses are ignored 44*444fa225SPeter Maydell- read accesses return all bits set to 0. 45*444fa225SPeter Maydell 46*444fa225SPeter MaydellThe last stored value in 'CPU selector' must refer to a possible CPU, otherwise 47*444fa225SPeter Maydell 48*444fa225SPeter Maydell- reads from any register return 0 49*444fa225SPeter Maydell- writes to any other register are ignored until valid value is stored into it 50*444fa225SPeter Maydell 51*444fa225SPeter MaydellOn QEMU start, 'CPU selector' is initialized to a valid value, on reset it 52*444fa225SPeter Maydellkeeps the current value. 53*444fa225SPeter Maydell 54*444fa225SPeter MaydellRead access behavior 55*444fa225SPeter Maydell^^^^^^^^^^^^^^^^^^^^ 56*444fa225SPeter Maydell 57*444fa225SPeter Maydelloffset [0x0-0x3] 58*444fa225SPeter Maydell Command data 2: (DWORD access) 59*444fa225SPeter Maydell 60*444fa225SPeter Maydell If value last stored in 'Command field' is: 61*444fa225SPeter Maydell 62*444fa225SPeter Maydell 0: 63*444fa225SPeter Maydell reads as 0x0 64*444fa225SPeter Maydell 3: 65*444fa225SPeter Maydell upper 32 bits of architecture specific CPU ID value 66*444fa225SPeter Maydell other values: 67*444fa225SPeter Maydell reserved 68*444fa225SPeter Maydell 69*444fa225SPeter Maydelloffset [0x4] 70*444fa225SPeter Maydell CPU device status fields: (1 byte access) 71*444fa225SPeter Maydell 72*444fa225SPeter Maydell bits: 73*444fa225SPeter Maydell 74*444fa225SPeter Maydell 0: 75*444fa225SPeter Maydell Device is enabled and may be used by guest 76*444fa225SPeter Maydell 1: 77*444fa225SPeter Maydell Device insert event, used to distinguish device for which 78*444fa225SPeter Maydell no device check event to OSPM was issued. 79*444fa225SPeter Maydell It's valid only when bit 0 is set. 80*444fa225SPeter Maydell 2: 81*444fa225SPeter Maydell Device remove event, used to distinguish device for which 82*444fa225SPeter Maydell no device eject request to OSPM was issued. Firmware must 83*444fa225SPeter Maydell ignore this bit. 84*444fa225SPeter Maydell 3: 85*444fa225SPeter Maydell reserved and should be ignored by OSPM 86*444fa225SPeter Maydell 4: 87*444fa225SPeter Maydell if set to 1, OSPM requests firmware to perform device eject. 88*444fa225SPeter Maydell 5-7: 89*444fa225SPeter Maydell reserved and should be ignored by OSPM 90*444fa225SPeter Maydell 91*444fa225SPeter Maydelloffset [0x5-0x7] 92*444fa225SPeter Maydell reserved 93*444fa225SPeter Maydell 94*444fa225SPeter Maydelloffset [0x8] 95*444fa225SPeter Maydell Command data: (DWORD access) 96*444fa225SPeter Maydell 97*444fa225SPeter Maydell If value last stored in 'Command field' is one of: 98*444fa225SPeter Maydell 99*444fa225SPeter Maydell 0: 100*444fa225SPeter Maydell contains 'CPU selector' value of a CPU with pending event[s] 101*444fa225SPeter Maydell 3: 102*444fa225SPeter Maydell lower 32 bits of architecture specific CPU ID value 103*444fa225SPeter Maydell (in x86 case: APIC ID) 104*444fa225SPeter Maydell otherwise: 105*444fa225SPeter Maydell contains 0 106*444fa225SPeter Maydell 107*444fa225SPeter MaydellWrite access behavior 108*444fa225SPeter Maydell^^^^^^^^^^^^^^^^^^^^^ 109*444fa225SPeter Maydell 110*444fa225SPeter Maydelloffset [0x0-0x3] 111*444fa225SPeter Maydell CPU selector: (DWORD access) 112*444fa225SPeter Maydell 113*444fa225SPeter Maydell Selects active CPU device. All following accesses to other 114*444fa225SPeter Maydell registers will read/store data from/to selected CPU. 115*444fa225SPeter Maydell Valid values: [0 .. max_cpus) 116*444fa225SPeter Maydell 117*444fa225SPeter Maydelloffset [0x4] 118*444fa225SPeter Maydell CPU device control fields: (1 byte access) 119*444fa225SPeter Maydell 120*444fa225SPeter Maydell bits: 121*444fa225SPeter Maydell 122*444fa225SPeter Maydell 0: 123*444fa225SPeter Maydell reserved, OSPM must clear it before writing to register. 124*444fa225SPeter Maydell 1: 125*444fa225SPeter Maydell if set to 1 clears device insert event, set by OSPM 126*444fa225SPeter Maydell after it has emitted device check event for the 127*444fa225SPeter Maydell selected CPU device 128*444fa225SPeter Maydell 2: 129*444fa225SPeter Maydell if set to 1 clears device remove event, set by OSPM 130*444fa225SPeter Maydell after it has emitted device eject request for the 131*444fa225SPeter Maydell selected CPU device. 132*444fa225SPeter Maydell 3: 133*444fa225SPeter Maydell if set to 1 initiates device eject, set by OSPM when it 134*444fa225SPeter Maydell triggers CPU device removal and calls _EJ0 method or by firmware 135*444fa225SPeter Maydell when bit #4 is set. In case bit #4 were set, it's cleared as 136*444fa225SPeter Maydell part of device eject. 137*444fa225SPeter Maydell 4: 138*444fa225SPeter Maydell if set to 1, OSPM hands over device eject to firmware. 139*444fa225SPeter Maydell Firmware shall issue device eject request as described above 140*444fa225SPeter Maydell (bit #3) and OSPM should not touch device eject bit (#3) in case 141*444fa225SPeter Maydell it's asked firmware to perform CPU device eject. 142*444fa225SPeter Maydell 5-7: 143*444fa225SPeter Maydell reserved, OSPM must clear them before writing to register 144*444fa225SPeter Maydell 145*444fa225SPeter Maydelloffset[0x5] 146*444fa225SPeter Maydell Command field: (1 byte access) 147*444fa225SPeter Maydell 148*444fa225SPeter Maydell value: 149*444fa225SPeter Maydell 150*444fa225SPeter Maydell 0: 151*444fa225SPeter Maydell selects a CPU device with inserting/removing events and 152*444fa225SPeter Maydell following reads from 'Command data' register return 153*444fa225SPeter Maydell selected CPU ('CPU selector' value). 154*444fa225SPeter Maydell If no CPU with events found, the current 'CPU selector' doesn't 155*444fa225SPeter Maydell change and corresponding insert/remove event flags are not modified. 156*444fa225SPeter Maydell 157*444fa225SPeter Maydell 1: 158*444fa225SPeter Maydell following writes to 'Command data' register set OST event 159*444fa225SPeter Maydell register in QEMU 160*444fa225SPeter Maydell 2: 161*444fa225SPeter Maydell following writes to 'Command data' register set OST status 162*444fa225SPeter Maydell register in QEMU 163*444fa225SPeter Maydell 3: 164*444fa225SPeter Maydell following reads from 'Command data' and 'Command data 2' return 165*444fa225SPeter Maydell architecture specific CPU ID value for currently selected CPU. 166*444fa225SPeter Maydell other values: 167*444fa225SPeter Maydell reserved 168*444fa225SPeter Maydell 169*444fa225SPeter Maydelloffset [0x6-0x7] 170*444fa225SPeter Maydell reserved 171*444fa225SPeter Maydell 172*444fa225SPeter Maydelloffset [0x8] 173*444fa225SPeter Maydell Command data: (DWORD access) 174*444fa225SPeter Maydell 175*444fa225SPeter Maydell If last stored 'Command field' value is: 176*444fa225SPeter Maydell 177*444fa225SPeter Maydell 1: 178*444fa225SPeter Maydell stores value into OST event register 179*444fa225SPeter Maydell 2: 180*444fa225SPeter Maydell stores value into OST status register, triggers 181*444fa225SPeter Maydell ACPI_DEVICE_OST QMP event from QEMU to external applications 182*444fa225SPeter Maydell with current values of OST event and status registers. 183*444fa225SPeter Maydell other values: 184*444fa225SPeter Maydell reserved 185*444fa225SPeter Maydell 186*444fa225SPeter MaydellTypical usecases 187*444fa225SPeter Maydell---------------- 188*444fa225SPeter Maydell 189*444fa225SPeter Maydell(x86) Detecting and enabling modern CPU hotplug interface 190*444fa225SPeter Maydell^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^ 191*444fa225SPeter Maydell 192*444fa225SPeter MaydellQEMU starts with legacy CPU hotplug interface enabled. Detecting and 193*444fa225SPeter Maydellswitching to modern interface is based on the 2 legacy CPU hotplug features: 194*444fa225SPeter Maydell 195*444fa225SPeter Maydell#. Writes into CPU bitmap are ignored. 196*444fa225SPeter Maydell#. CPU bitmap always has bit #0 set, corresponding to boot CPU. 197*444fa225SPeter Maydell 198*444fa225SPeter MaydellUse following steps to detect and enable modern CPU hotplug interface: 199*444fa225SPeter Maydell 200*444fa225SPeter Maydell#. Store 0x0 to the 'CPU selector' register, attempting to switch to modern mode 201*444fa225SPeter Maydell#. Store 0x0 to the 'CPU selector' register, to ensure valid selector value 202*444fa225SPeter Maydell#. Store 0x0 to the 'Command field' register 203*444fa225SPeter Maydell#. Read the 'Command data 2' register. 204*444fa225SPeter Maydell If read value is 0x0, the modern interface is enabled. 205*444fa225SPeter Maydell Otherwise legacy or no CPU hotplug interface available 206*444fa225SPeter Maydell 207*444fa225SPeter MaydellGet a cpu with pending event 208*444fa225SPeter Maydell^^^^^^^^^^^^^^^^^^^^^^^^^^^^ 209*444fa225SPeter Maydell 210*444fa225SPeter Maydell#. Store 0x0 to the 'CPU selector' register. 211*444fa225SPeter Maydell#. Store 0x0 to the 'Command field' register. 212*444fa225SPeter Maydell#. Read the 'CPU device status fields' register. 213*444fa225SPeter Maydell#. If both bit #1 and bit #2 are clear in the value read, there is no CPU 214*444fa225SPeter Maydell with a pending event and selected CPU remains unchanged. 215*444fa225SPeter Maydell#. Otherwise, read the 'Command data' register. The value read is the 216*444fa225SPeter Maydell selector of the CPU with the pending event (which is already selected). 217*444fa225SPeter Maydell 218*444fa225SPeter MaydellEnumerate CPUs present/non present CPUs 219*444fa225SPeter Maydell^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^ 220*444fa225SPeter Maydell 221*444fa225SPeter Maydell#. Set the present CPU count to 0. 222*444fa225SPeter Maydell#. Set the iterator to 0. 223*444fa225SPeter Maydell#. Store 0x0 to the 'CPU selector' register, to ensure that it's in 224*444fa225SPeter Maydell a valid state and that access to other registers won't be ignored. 225*444fa225SPeter Maydell#. Store 0x0 to the 'Command field' register to make 'Command data' 226*444fa225SPeter Maydell register return 'CPU selector' value of selected CPU 227*444fa225SPeter Maydell#. Read the 'CPU device status fields' register. 228*444fa225SPeter Maydell#. If bit #0 is set, increment the present CPU count. 229*444fa225SPeter Maydell#. Increment the iterator. 230*444fa225SPeter Maydell#. Store the iterator to the 'CPU selector' register. 231*444fa225SPeter Maydell#. Read the 'Command data' register. 232*444fa225SPeter Maydell#. If the value read is not zero, goto 05. 233*444fa225SPeter Maydell#. Otherwise store 0x0 to the 'CPU selector' register, to put it 234*444fa225SPeter Maydell into a valid state and exit. 235*444fa225SPeter Maydell The iterator at this point equals "max_cpus". 236