1A-profile CPU architecture support 2================================== 3 4QEMU's TCG emulation includes support for the Armv5, Armv6, Armv7 and 5Armv8 versions of the A-profile architecture. It also has support for 6the following architecture extensions: 7 8- FEAT_AA32BF16 (AArch32 BFloat16 instructions) 9- FEAT_AA32HPD (AArch32 hierarchical permission disables) 10- FEAT_AA32I8MM (AArch32 Int8 matrix multiplication instructions) 11- FEAT_AES (AESD and AESE instructions) 12- FEAT_BBM at level 2 (Translation table break-before-make levels) 13- FEAT_BF16 (AArch64 BFloat16 instructions) 14- FEAT_BTI (Branch Target Identification) 15- FEAT_CSV2 (Cache speculation variant 2) 16- FEAT_CSV2_1p1 (Cache speculation variant 2, version 1.1) 17- FEAT_CSV2_1p2 (Cache speculation variant 2, version 1.2) 18- FEAT_CSV2_2 (Cache speculation variant 2, version 2) 19- FEAT_CSV3 (Cache speculation variant 3) 20- FEAT_DGH (Data gathering hint) 21- FEAT_DIT (Data Independent Timing instructions) 22- FEAT_DPB (DC CVAP instruction) 23- FEAT_Debugv8p2 (Debug changes for v8.2) 24- FEAT_Debugv8p4 (Debug changes for v8.4) 25- FEAT_DotProd (Advanced SIMD dot product instructions) 26- FEAT_DoubleFault (Double Fault Extension) 27- FEAT_ETS (Enhanced Translation Synchronization) 28- FEAT_FCMA (Floating-point complex number instructions) 29- FEAT_FHM (Floating-point half-precision multiplication instructions) 30- FEAT_FP16 (Half-precision floating-point data processing) 31- FEAT_FRINTTS (Floating-point to integer instructions) 32- FEAT_FlagM (Flag manipulation instructions v2) 33- FEAT_FlagM2 (Enhancements to flag manipulation instructions) 34- FEAT_HCX (Support for the HCRX_EL2 register) 35- FEAT_HPDS (Hierarchical permission disables) 36- FEAT_I8MM (AArch64 Int8 matrix multiplication instructions) 37- FEAT_IDST (ID space trap handling) 38- FEAT_IESB (Implicit error synchronization event) 39- FEAT_JSCVT (JavaScript conversion instructions) 40- FEAT_LOR (Limited ordering regions) 41- FEAT_LPA (Large Physical Address space) 42- FEAT_LPA2 (Large Physical and virtual Address space v2) 43- FEAT_LRCPC (Load-acquire RCpc instructions) 44- FEAT_LRCPC2 (Load-acquire RCpc instructions v2) 45- FEAT_LSE (Large System Extensions) 46- FEAT_LVA (Large Virtual Address space) 47- FEAT_MTE (Memory Tagging Extension) 48- FEAT_MTE2 (Memory Tagging Extension) 49- FEAT_MTE3 (MTE Asymmetric Fault Handling) 50- FEAT_PAN (Privileged access never) 51- FEAT_PAN2 (AT S1E1R and AT S1E1W instruction variants affected by PSTATE.PAN) 52- FEAT_PAuth (Pointer authentication) 53- FEAT_PMULL (PMULL, PMULL2 instructions) 54- FEAT_PMUv3p1 (PMU Extensions v3.1) 55- FEAT_PMUv3p4 (PMU Extensions v3.4) 56- FEAT_PMUv3p5 (PMU Extensions v3.5) 57- FEAT_RAS (Reliability, availability, and serviceability) 58- FEAT_RASv1p1 (RAS Extension v1.1) 59- FEAT_RDM (Advanced SIMD rounding double multiply accumulate instructions) 60- FEAT_RNG (Random number generator) 61- FEAT_S2FWB (Stage 2 forced Write-Back) 62- FEAT_SB (Speculation Barrier) 63- FEAT_SEL2 (Secure EL2) 64- FEAT_SHA1 (SHA1 instructions) 65- FEAT_SHA256 (SHA256 instructions) 66- FEAT_SHA3 (Advanced SIMD SHA3 instructions) 67- FEAT_SHA512 (Advanced SIMD SHA512 instructions) 68- FEAT_SM3 (Advanced SIMD SM3 instructions) 69- FEAT_SM4 (Advanced SIMD SM4 instructions) 70- FEAT_SME (Scalable Matrix Extension) 71- FEAT_SME_FA64 (Full A64 instruction set in Streaming SVE mode) 72- FEAT_SME_F64F64 (Double-precision floating-point outer product instructions) 73- FEAT_SME_I16I64 (16-bit to 64-bit integer widening outer product instructions) 74- FEAT_SPECRES (Speculation restriction instructions) 75- FEAT_SSBS (Speculative Store Bypass Safe) 76- FEAT_TLBIOS (TLB invalidate instructions in Outer Shareable domain) 77- FEAT_TLBIRANGE (TLB invalidate range instructions) 78- FEAT_TTCNP (Translation table Common not private translations) 79- FEAT_TTL (Translation Table Level) 80- FEAT_TTST (Small translation tables) 81- FEAT_UAO (Unprivileged Access Override control) 82- FEAT_VHE (Virtualization Host Extensions) 83- FEAT_VMID16 (16-bit VMID) 84- FEAT_XNX (Translation table stage 2 Unprivileged Execute-never) 85- SVE (The Scalable Vector Extension) 86- SVE2 (The Scalable Vector Extension v2) 87 88For information on the specifics of these extensions, please refer 89to the `Armv8-A Arm Architecture Reference Manual 90<https://developer.arm.com/documentation/ddi0487/latest>`_. 91 92When a specific named CPU is being emulated, only those features which 93are present in hardware for that CPU are emulated. (If a feature is 94not in the list above then it is not supported, even if the real 95hardware should have it.) The ``max`` CPU enables all features. 96 97R-profile CPU architecture support 98================================== 99 100QEMU's TCG emulation support for R-profile CPUs is currently limited. 101We emulate only the Cortex-R5 and Cortex-R5F CPUs. 102 103M-profile CPU architecture support 104================================== 105 106QEMU's TCG emulation includes support for Armv6-M, Armv7-M, Armv8-M, and 107Armv8.1-M versions of the M-profile architucture. It also has support 108for the following architecture extensions: 109 110- FP (Floating-point Extension) 111- FPCXT (FPCXT access instructions) 112- HP (Half-precision floating-point instructions) 113- LOB (Low Overhead loops and Branch future) 114- M (Main Extension) 115- MPU (Memory Protection Unit Extension) 116- PXN (Privileged Execute Never) 117- RAS (Reliability, Serviceability and Availability): "minimum RAS Extension" only 118- S (Security Extension) 119- ST (System Timer Extension) 120 121For information on the specifics of these extensions, please refer 122to the `Armv8-M Arm Architecture Reference Manual 123<https://developer.arm.com/documentation/ddi0553/latest>`_. 124 125When a specific named CPU is being emulated, only those features which 126are present in hardware for that CPU are emulated. (If a feature is 127not in the list above then it is not supported, even if the real 128hardware should have it.) There is no equivalent of the ``max`` CPU for 129M-profile. 130