1*f780e63fSPeter MaydellArm MPS2 and MPS3 boards (``mps2-an385``, ``mps2-an386``, ``mps2-an500``, ``mps2-an505``, ``mps2-an511``, ``mps2-an521``, ``mps3-an524``, ``mps3-an536``, ``mps3-an547``) 2*f780e63fSPeter Maydell========================================================================================================================================================================= 3ba7912a5SPeter Maydell 4*f780e63fSPeter MaydellThese board models use Arm M-profile or R-profile CPUs. 5ba7912a5SPeter Maydell 6ced8bb04SPeter MaydellThe Arm MPS2, MPS2+ and MPS3 dev boards are FPGA based (the 2+ has a 7ced8bb04SPeter Maydellbigger FPGA but is otherwise the same as the 2; the 3 has a bigger 8ced8bb04SPeter MaydellFPGA again, can handle 4GB of RAM and has a USB controller and QSPI flash). 9ced8bb04SPeter Maydell 10ced8bb04SPeter MaydellSince the CPU itself and most of the devices are in the FPGA, the 11ced8bb04SPeter Maydelldetails of the board as seen by the guest depend significantly on the 12ced8bb04SPeter MaydellFPGA image. 13ba7912a5SPeter Maydell 14ba7912a5SPeter MaydellQEMU models the following FPGA images: 15ba7912a5SPeter Maydell 16*f780e63fSPeter MaydellFPGA images using M-profile CPUs: 17*f780e63fSPeter Maydell 18ba7912a5SPeter Maydell``mps2-an385`` 1999dfb04aSPeter Maydell Cortex-M3 as documented in Arm Application Note AN385 20897d2726SPeter Maydell``mps2-an386`` 2199dfb04aSPeter Maydell Cortex-M4 as documented in Arm Application Note AN386 226d4811c4SPeter Maydell``mps2-an500`` 2399dfb04aSPeter Maydell Cortex-M7 as documented in Arm Application Note AN500 24ba7912a5SPeter Maydell``mps2-an505`` 2599dfb04aSPeter Maydell Cortex-M33 as documented in Arm Application Note AN505 2699dfb04aSPeter Maydell``mps2-an511`` 2799dfb04aSPeter Maydell Cortex-M3 'DesignStart' as documented in Arm Application Note AN511 28ba7912a5SPeter Maydell``mps2-an521`` 2999dfb04aSPeter Maydell Dual Cortex-M33 as documented in Arm Application Note AN521 30ced8bb04SPeter Maydell``mps3-an524`` 31ced8bb04SPeter Maydell Dual Cortex-M33 on an MPS3, as documented in Arm Application Note AN524 32dd750743SPeter Maydell``mps3-an547`` 33dd750743SPeter Maydell Cortex-M55 on an MPS3, as documented in Arm Application Note AN547 34ba7912a5SPeter Maydell 35*f780e63fSPeter MaydellFPGA images using R-profile CPUs: 36*f780e63fSPeter Maydell 37*f780e63fSPeter Maydell``mps3-an536`` 38*f780e63fSPeter Maydell Dual Cortex-R52 on an MPS3, as documented in Arm Application Note AN536 39*f780e63fSPeter Maydell 40ba7912a5SPeter MaydellDifferences between QEMU and real hardware: 41ba7912a5SPeter Maydell 42897d2726SPeter Maydell- AN385/AN386 remapping of low 16K of memory to either ZBT SSRAM1 or to 43ba7912a5SPeter Maydell block RAM is unimplemented (QEMU always maps this to ZBT SSRAM1, as 44ba7912a5SPeter Maydell if zbt_boot_ctrl is always zero) 45ced8bb04SPeter Maydell- AN524 remapping of low memory to either BRAM or to QSPI flash is 46ced8bb04SPeter Maydell unimplemented (QEMU always maps this to BRAM, ignoring the 47ced8bb04SPeter Maydell SCC CFG_REG0 memory-remap bit) 48ba7912a5SPeter Maydell- QEMU provides a LAN9118 ethernet rather than LAN9220; the only guest 49ba7912a5SPeter Maydell visible difference is that the LAN9118 doesn't support checksum 50ba7912a5SPeter Maydell offloading 51ced8bb04SPeter Maydell- QEMU does not model the QSPI flash in MPS3 boards as real QSPI 52ced8bb04SPeter Maydell flash, but only as simple ROM, so attempting to rewrite the flash 53ced8bb04SPeter Maydell from the guest will fail 54ced8bb04SPeter Maydell- QEMU does not model the USB controller in MPS3 boards 55*f780e63fSPeter Maydell- AN536 does not support runtime control of CPU reset and halt via 56*f780e63fSPeter Maydell the SCC CFG_REG0 register. 57*f780e63fSPeter Maydell- AN536 does not support enabling or disabling the flash and ATCM 58*f780e63fSPeter Maydell interfaces via the SCC CFG_REG1 register. 59*f780e63fSPeter Maydell- AN536 does not support setting of the initial vector table 60*f780e63fSPeter Maydell base address via the SCC CFG_REG6 and CFG_REG7 register config, 61*f780e63fSPeter Maydell and does not provide a mechanism for specifying these values at 62*f780e63fSPeter Maydell startup, so all guest images must be built to start from TCM 63*f780e63fSPeter Maydell (i.e. to expect the interrupt vector base at 0 from reset). 64*f780e63fSPeter Maydell- AN536 defaults to only creating a single CPU; this is the equivalent 65*f780e63fSPeter Maydell of the way the real FPGA image usually runs with the second Cortex-R52 66*f780e63fSPeter Maydell held in halt via the initial SCC CFG_REG0 register setting. You can 67*f780e63fSPeter Maydell create the second CPU with ``-smp 2``; both CPUs will then start 68*f780e63fSPeter Maydell execution immediately on startup. 69*f780e63fSPeter Maydell 70*f780e63fSPeter MaydellNote that for the AN536 the first UART is accessible only by 71*f780e63fSPeter MaydellCPU0, and the second UART is accessible only by CPU1. The 72*f780e63fSPeter Maydellfirst UART accessible shared between both CPUs is the third 73*f780e63fSPeter MaydellUART. Guest software might therefore be built to use either 74*f780e63fSPeter Maydellthe first UART or the third UART; if you don't see any output 75*f780e63fSPeter Maydellfrom the UART you are looking at, try one of the others. 76*f780e63fSPeter Maydell(Even if the AN536 machine is started with a single CPU and so 77*f780e63fSPeter Maydellno "CPU1-only UART", the UART numbering remains the same, 78*f780e63fSPeter Maydellwith the third UART being the first of the shared ones.) 79f1dfab0dSPeter Maydell 80f1dfab0dSPeter MaydellMachine-specific options 81f1dfab0dSPeter Maydell"""""""""""""""""""""""" 82f1dfab0dSPeter Maydell 83f1dfab0dSPeter MaydellThe following machine-specific options are supported: 84f1dfab0dSPeter Maydell 85f1dfab0dSPeter Maydellremap 86f1dfab0dSPeter Maydell Supported for ``mps3-an524`` only. 87f1dfab0dSPeter Maydell Set ``BRAM``/``QSPI`` to select the initial memory mapping. The 88f1dfab0dSPeter Maydell default is ``BRAM``. 89