xref: /qemu/docs/system/target-xtensa.rst (revision 44d79a6b)
1*324b2298SPaolo Bonzini.. _Xtensa-System-emulator:
2*324b2298SPaolo Bonzini
3*324b2298SPaolo BonziniXtensa System emulator
4*324b2298SPaolo Bonzini----------------------
5*324b2298SPaolo Bonzini
6*324b2298SPaolo BonziniTwo executables cover simulation of both Xtensa endian options,
7*324b2298SPaolo Bonzini``qemu-system-xtensa`` and ``qemu-system-xtensaeb``. Two different
8*324b2298SPaolo Bonzinimachine types are emulated:
9*324b2298SPaolo Bonzini
10*324b2298SPaolo Bonzini-  Xtensa emulator pseudo board \"sim\"
11*324b2298SPaolo Bonzini
12*324b2298SPaolo Bonzini-  Avnet LX60/LX110/LX200 board
13*324b2298SPaolo Bonzini
14*324b2298SPaolo BonziniThe sim pseudo board emulation provides an environment similar to one
15*324b2298SPaolo Bonziniprovided by the proprietary Tensilica ISS. It supports:
16*324b2298SPaolo Bonzini
17*324b2298SPaolo Bonzini-  A range of Xtensa CPUs, default is the DC232B
18*324b2298SPaolo Bonzini
19*324b2298SPaolo Bonzini-  Console and filesystem access via semihosting calls
20*324b2298SPaolo Bonzini
21*324b2298SPaolo BonziniThe Avnet LX60/LX110/LX200 emulation supports:
22*324b2298SPaolo Bonzini
23*324b2298SPaolo Bonzini-  A range of Xtensa CPUs, default is the DC232B
24*324b2298SPaolo Bonzini
25*324b2298SPaolo Bonzini-  16550 UART
26*324b2298SPaolo Bonzini
27*324b2298SPaolo Bonzini-  OpenCores 10/100 Mbps Ethernet MAC
28