1 /* 2 * SPDX-License-Identifier: GPL-2.0-or-later 3 * Compare-and-swap for 128-bit atomic operations, AArch64 version. 4 * 5 * Copyright (C) 2018, 2023 Linaro, Ltd. 6 * 7 * See docs/devel/atomics.rst for discussion about the guarantees each 8 * atomic primitive is meant to provide. 9 */ 10 11 #ifndef AARCH64_ATOMIC128_CAS_H 12 #define AARCH64_ATOMIC128_CAS_H 13 14 /* Through gcc 10, aarch64 has no support for 128-bit atomics. */ 15 #if defined(CONFIG_ATOMIC128) || defined(CONFIG_CMPXCHG128) 16 #include "host/include/generic/host/atomic128-cas.h" 17 #else 18 static inline Int128 atomic16_cmpxchg(Int128 *ptr, Int128 cmp, Int128 new) 19 { 20 uint64_t cmpl = int128_getlo(cmp), cmph = int128_gethi(cmp); 21 uint64_t newl = int128_getlo(new), newh = int128_gethi(new); 22 uint64_t oldl, oldh; 23 uint32_t tmp; 24 25 asm("0: ldaxp %[oldl], %[oldh], %[mem]\n\t" 26 "cmp %[oldl], %[cmpl]\n\t" 27 "ccmp %[oldh], %[cmph], #0, eq\n\t" 28 "b.ne 1f\n\t" 29 "stlxp %w[tmp], %[newl], %[newh], %[mem]\n\t" 30 "cbnz %w[tmp], 0b\n" 31 "1:" 32 : [mem] "+m"(*ptr), [tmp] "=&r"(tmp), 33 [oldl] "=&r"(oldl), [oldh] "=&r"(oldh) 34 : [cmpl] "r"(cmpl), [cmph] "r"(cmph), 35 [newl] "r"(newl), [newh] "r"(newh) 36 : "memory", "cc"); 37 38 return int128_make128(oldl, oldh); 39 } 40 41 # define CONFIG_CMPXCHG128 1 42 # define HAVE_CMPXCHG128 1 43 #endif 44 45 #endif /* AARCH64_ATOMIC128_CAS_H */ 46