1 /* 2 * ACPI implementation 3 * 4 * Copyright (c) 2006 Fabrice Bellard 5 * 6 * This library is free software; you can redistribute it and/or 7 * modify it under the terms of the GNU Lesser General Public 8 * License version 2 as published by the Free Software Foundation. 9 * 10 * This library is distributed in the hope that it will be useful, 11 * but WITHOUT ANY WARRANTY; without even the implied warranty of 12 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU 13 * Lesser General Public License for more details. 14 * 15 * You should have received a copy of the GNU Lesser General Public 16 * License along with this library; if not, see <http://www.gnu.org/licenses/> 17 * 18 * Contributions after 2012-01-13 are licensed under the terms of the 19 * GNU GPL, version 2 or (at your option) any later version. 20 */ 21 #include "qemu/osdep.h" 22 #include "hw/hw.h" 23 #include "hw/i386/pc.h" 24 #include "hw/isa/apm.h" 25 #include "hw/i2c/pm_smbus.h" 26 #include "hw/pci/pci.h" 27 #include "hw/acpi/acpi.h" 28 #include "sysemu/sysemu.h" 29 #include "qapi/error.h" 30 #include "qemu/range.h" 31 #include "hw/nvram/fw_cfg.h" 32 #include "exec/address-spaces.h" 33 #include "hw/acpi/piix4.h" 34 #include "hw/acpi/pcihp.h" 35 #include "hw/acpi/cpu_hotplug.h" 36 #include "hw/acpi/cpu.h" 37 #include "hw/hotplug.h" 38 #include "hw/mem/pc-dimm.h" 39 #include "hw/acpi/memory_hotplug.h" 40 #include "hw/acpi/acpi_dev_interface.h" 41 #include "hw/xen/xen.h" 42 #include "qom/cpu.h" 43 44 //#define DEBUG 45 46 #ifdef DEBUG 47 # define PIIX4_DPRINTF(format, ...) printf(format, ## __VA_ARGS__) 48 #else 49 # define PIIX4_DPRINTF(format, ...) do { } while (0) 50 #endif 51 52 #define GPE_BASE 0xafe0 53 #define GPE_LEN 4 54 55 struct pci_status { 56 uint32_t up; /* deprecated, maintained for migration compatibility */ 57 uint32_t down; 58 }; 59 60 typedef struct PIIX4PMState { 61 /*< private >*/ 62 PCIDevice parent_obj; 63 /*< public >*/ 64 65 MemoryRegion io; 66 uint32_t io_base; 67 68 MemoryRegion io_gpe; 69 ACPIREGS ar; 70 71 APMState apm; 72 73 PMSMBus smb; 74 uint32_t smb_io_base; 75 76 qemu_irq irq; 77 qemu_irq smi_irq; 78 int smm_enabled; 79 Notifier machine_ready; 80 Notifier powerdown_notifier; 81 82 AcpiPciHpState acpi_pci_hotplug; 83 bool use_acpi_pci_hotplug; 84 85 uint8_t disable_s3; 86 uint8_t disable_s4; 87 uint8_t s4_val; 88 89 bool cpu_hotplug_legacy; 90 AcpiCpuHotplug gpe_cpu; 91 CPUHotplugState cpuhp_state; 92 93 MemHotplugState acpi_memory_hotplug; 94 } PIIX4PMState; 95 96 #define TYPE_PIIX4_PM "PIIX4_PM" 97 98 #define PIIX4_PM(obj) \ 99 OBJECT_CHECK(PIIX4PMState, (obj), TYPE_PIIX4_PM) 100 101 static void piix4_acpi_system_hot_add_init(MemoryRegion *parent, 102 PCIBus *bus, PIIX4PMState *s); 103 104 #define ACPI_ENABLE 0xf1 105 #define ACPI_DISABLE 0xf0 106 107 static void pm_tmr_timer(ACPIREGS *ar) 108 { 109 PIIX4PMState *s = container_of(ar, PIIX4PMState, ar); 110 acpi_update_sci(&s->ar, s->irq); 111 } 112 113 static void apm_ctrl_changed(uint32_t val, void *arg) 114 { 115 PIIX4PMState *s = arg; 116 PCIDevice *d = PCI_DEVICE(s); 117 118 /* ACPI specs 3.0, 4.7.2.5 */ 119 acpi_pm1_cnt_update(&s->ar, val == ACPI_ENABLE, val == ACPI_DISABLE); 120 if (val == ACPI_ENABLE || val == ACPI_DISABLE) { 121 return; 122 } 123 124 if (d->config[0x5b] & (1 << 1)) { 125 if (s->smi_irq) { 126 qemu_irq_raise(s->smi_irq); 127 } 128 } 129 } 130 131 static void pm_io_space_update(PIIX4PMState *s) 132 { 133 PCIDevice *d = PCI_DEVICE(s); 134 135 s->io_base = le32_to_cpu(*(uint32_t *)(d->config + 0x40)); 136 s->io_base &= 0xffc0; 137 138 memory_region_transaction_begin(); 139 memory_region_set_enabled(&s->io, d->config[0x80] & 1); 140 memory_region_set_address(&s->io, s->io_base); 141 memory_region_transaction_commit(); 142 } 143 144 static void smbus_io_space_update(PIIX4PMState *s) 145 { 146 PCIDevice *d = PCI_DEVICE(s); 147 148 s->smb_io_base = le32_to_cpu(*(uint32_t *)(d->config + 0x90)); 149 s->smb_io_base &= 0xffc0; 150 151 memory_region_transaction_begin(); 152 memory_region_set_enabled(&s->smb.io, d->config[0xd2] & 1); 153 memory_region_set_address(&s->smb.io, s->smb_io_base); 154 memory_region_transaction_commit(); 155 } 156 157 static void pm_write_config(PCIDevice *d, 158 uint32_t address, uint32_t val, int len) 159 { 160 pci_default_write_config(d, address, val, len); 161 if (range_covers_byte(address, len, 0x80) || 162 ranges_overlap(address, len, 0x40, 4)) { 163 pm_io_space_update((PIIX4PMState *)d); 164 } 165 if (range_covers_byte(address, len, 0xd2) || 166 ranges_overlap(address, len, 0x90, 4)) { 167 smbus_io_space_update((PIIX4PMState *)d); 168 } 169 } 170 171 static int vmstate_acpi_post_load(void *opaque, int version_id) 172 { 173 PIIX4PMState *s = opaque; 174 175 pm_io_space_update(s); 176 return 0; 177 } 178 179 #define VMSTATE_GPE_ARRAY(_field, _state) \ 180 { \ 181 .name = (stringify(_field)), \ 182 .version_id = 0, \ 183 .info = &vmstate_info_uint16, \ 184 .size = sizeof(uint16_t), \ 185 .flags = VMS_SINGLE | VMS_POINTER, \ 186 .offset = vmstate_offset_pointer(_state, _field, uint8_t), \ 187 } 188 189 static const VMStateDescription vmstate_gpe = { 190 .name = "gpe", 191 .version_id = 1, 192 .minimum_version_id = 1, 193 .fields = (VMStateField[]) { 194 VMSTATE_GPE_ARRAY(sts, ACPIGPE), 195 VMSTATE_GPE_ARRAY(en, ACPIGPE), 196 VMSTATE_END_OF_LIST() 197 } 198 }; 199 200 static const VMStateDescription vmstate_pci_status = { 201 .name = "pci_status", 202 .version_id = 1, 203 .minimum_version_id = 1, 204 .fields = (VMStateField[]) { 205 VMSTATE_UINT32(up, struct AcpiPciHpPciStatus), 206 VMSTATE_UINT32(down, struct AcpiPciHpPciStatus), 207 VMSTATE_END_OF_LIST() 208 } 209 }; 210 211 static int acpi_load_old(QEMUFile *f, void *opaque, int version_id) 212 { 213 PIIX4PMState *s = opaque; 214 int ret, i; 215 uint16_t temp; 216 217 ret = pci_device_load(PCI_DEVICE(s), f); 218 if (ret < 0) { 219 return ret; 220 } 221 qemu_get_be16s(f, &s->ar.pm1.evt.sts); 222 qemu_get_be16s(f, &s->ar.pm1.evt.en); 223 qemu_get_be16s(f, &s->ar.pm1.cnt.cnt); 224 225 ret = vmstate_load_state(f, &vmstate_apm, &s->apm, 1); 226 if (ret) { 227 return ret; 228 } 229 230 timer_get(f, s->ar.tmr.timer); 231 qemu_get_sbe64s(f, &s->ar.tmr.overflow_time); 232 233 qemu_get_be16s(f, (uint16_t *)s->ar.gpe.sts); 234 for (i = 0; i < 3; i++) { 235 qemu_get_be16s(f, &temp); 236 } 237 238 qemu_get_be16s(f, (uint16_t *)s->ar.gpe.en); 239 for (i = 0; i < 3; i++) { 240 qemu_get_be16s(f, &temp); 241 } 242 243 ret = vmstate_load_state(f, &vmstate_pci_status, 244 &s->acpi_pci_hotplug.acpi_pcihp_pci_status[ACPI_PCIHP_BSEL_DEFAULT], 1); 245 return ret; 246 } 247 248 static bool vmstate_test_use_acpi_pci_hotplug(void *opaque, int version_id) 249 { 250 PIIX4PMState *s = opaque; 251 return s->use_acpi_pci_hotplug; 252 } 253 254 static bool vmstate_test_no_use_acpi_pci_hotplug(void *opaque, int version_id) 255 { 256 PIIX4PMState *s = opaque; 257 return !s->use_acpi_pci_hotplug; 258 } 259 260 static bool vmstate_test_use_memhp(void *opaque) 261 { 262 PIIX4PMState *s = opaque; 263 return s->acpi_memory_hotplug.is_enabled; 264 } 265 266 static const VMStateDescription vmstate_memhp_state = { 267 .name = "piix4_pm/memhp", 268 .version_id = 1, 269 .minimum_version_id = 1, 270 .minimum_version_id_old = 1, 271 .needed = vmstate_test_use_memhp, 272 .fields = (VMStateField[]) { 273 VMSTATE_MEMORY_HOTPLUG(acpi_memory_hotplug, PIIX4PMState), 274 VMSTATE_END_OF_LIST() 275 } 276 }; 277 278 static bool vmstate_test_use_cpuhp(void *opaque) 279 { 280 PIIX4PMState *s = opaque; 281 return !s->cpu_hotplug_legacy; 282 } 283 284 static int vmstate_cpuhp_pre_load(void *opaque) 285 { 286 Object *obj = OBJECT(opaque); 287 object_property_set_bool(obj, false, "cpu-hotplug-legacy", &error_abort); 288 return 0; 289 } 290 291 static const VMStateDescription vmstate_cpuhp_state = { 292 .name = "piix4_pm/cpuhp", 293 .version_id = 1, 294 .minimum_version_id = 1, 295 .minimum_version_id_old = 1, 296 .needed = vmstate_test_use_cpuhp, 297 .pre_load = vmstate_cpuhp_pre_load, 298 .fields = (VMStateField[]) { 299 VMSTATE_CPU_HOTPLUG(cpuhp_state, PIIX4PMState), 300 VMSTATE_END_OF_LIST() 301 } 302 }; 303 304 /* qemu-kvm 1.2 uses version 3 but advertised as 2 305 * To support incoming qemu-kvm 1.2 migration, change version_id 306 * and minimum_version_id to 2 below (which breaks migration from 307 * qemu 1.2). 308 * 309 */ 310 static const VMStateDescription vmstate_acpi = { 311 .name = "piix4_pm", 312 .version_id = 3, 313 .minimum_version_id = 3, 314 .minimum_version_id_old = 1, 315 .load_state_old = acpi_load_old, 316 .post_load = vmstate_acpi_post_load, 317 .fields = (VMStateField[]) { 318 VMSTATE_PCI_DEVICE(parent_obj, PIIX4PMState), 319 VMSTATE_UINT16(ar.pm1.evt.sts, PIIX4PMState), 320 VMSTATE_UINT16(ar.pm1.evt.en, PIIX4PMState), 321 VMSTATE_UINT16(ar.pm1.cnt.cnt, PIIX4PMState), 322 VMSTATE_STRUCT(apm, PIIX4PMState, 0, vmstate_apm, APMState), 323 VMSTATE_TIMER_PTR(ar.tmr.timer, PIIX4PMState), 324 VMSTATE_INT64(ar.tmr.overflow_time, PIIX4PMState), 325 VMSTATE_STRUCT(ar.gpe, PIIX4PMState, 2, vmstate_gpe, ACPIGPE), 326 VMSTATE_STRUCT_TEST( 327 acpi_pci_hotplug.acpi_pcihp_pci_status[ACPI_PCIHP_BSEL_DEFAULT], 328 PIIX4PMState, 329 vmstate_test_no_use_acpi_pci_hotplug, 330 2, vmstate_pci_status, 331 struct AcpiPciHpPciStatus), 332 VMSTATE_PCI_HOTPLUG(acpi_pci_hotplug, PIIX4PMState, 333 vmstate_test_use_acpi_pci_hotplug), 334 VMSTATE_END_OF_LIST() 335 }, 336 .subsections = (const VMStateDescription*[]) { 337 &vmstate_memhp_state, 338 &vmstate_cpuhp_state, 339 NULL 340 } 341 }; 342 343 static void piix4_reset(void *opaque) 344 { 345 PIIX4PMState *s = opaque; 346 PCIDevice *d = PCI_DEVICE(s); 347 uint8_t *pci_conf = d->config; 348 349 pci_conf[0x58] = 0; 350 pci_conf[0x59] = 0; 351 pci_conf[0x5a] = 0; 352 pci_conf[0x5b] = 0; 353 354 pci_conf[0x40] = 0x01; /* PM io base read only bit */ 355 pci_conf[0x80] = 0; 356 357 if (!s->smm_enabled) { 358 /* Mark SMM as already inited (until KVM supports SMM). */ 359 pci_conf[0x5B] = 0x02; 360 } 361 pm_io_space_update(s); 362 acpi_pcihp_reset(&s->acpi_pci_hotplug); 363 } 364 365 static void piix4_pm_powerdown_req(Notifier *n, void *opaque) 366 { 367 PIIX4PMState *s = container_of(n, PIIX4PMState, powerdown_notifier); 368 369 assert(s != NULL); 370 acpi_pm1_evt_power_down(&s->ar); 371 } 372 373 static void piix4_device_plug_cb(HotplugHandler *hotplug_dev, 374 DeviceState *dev, Error **errp) 375 { 376 PIIX4PMState *s = PIIX4_PM(hotplug_dev); 377 378 if (s->acpi_memory_hotplug.is_enabled && 379 object_dynamic_cast(OBJECT(dev), TYPE_PC_DIMM)) { 380 if (object_dynamic_cast(OBJECT(dev), TYPE_NVDIMM)) { 381 nvdimm_acpi_plug_cb(hotplug_dev, dev); 382 } else { 383 acpi_memory_plug_cb(hotplug_dev, &s->acpi_memory_hotplug, 384 dev, errp); 385 } 386 } else if (object_dynamic_cast(OBJECT(dev), TYPE_PCI_DEVICE)) { 387 acpi_pcihp_device_plug_cb(hotplug_dev, &s->acpi_pci_hotplug, dev, errp); 388 } else if (object_dynamic_cast(OBJECT(dev), TYPE_CPU)) { 389 if (s->cpu_hotplug_legacy) { 390 legacy_acpi_cpu_plug_cb(hotplug_dev, &s->gpe_cpu, dev, errp); 391 } else { 392 acpi_cpu_plug_cb(hotplug_dev, &s->cpuhp_state, dev, errp); 393 } 394 } else { 395 error_setg(errp, "acpi: device plug request for not supported device" 396 " type: %s", object_get_typename(OBJECT(dev))); 397 } 398 } 399 400 static void piix4_device_unplug_request_cb(HotplugHandler *hotplug_dev, 401 DeviceState *dev, Error **errp) 402 { 403 PIIX4PMState *s = PIIX4_PM(hotplug_dev); 404 405 if (s->acpi_memory_hotplug.is_enabled && 406 object_dynamic_cast(OBJECT(dev), TYPE_PC_DIMM)) { 407 acpi_memory_unplug_request_cb(hotplug_dev, &s->acpi_memory_hotplug, 408 dev, errp); 409 } else if (object_dynamic_cast(OBJECT(dev), TYPE_PCI_DEVICE)) { 410 acpi_pcihp_device_unplug_cb(hotplug_dev, &s->acpi_pci_hotplug, dev, 411 errp); 412 } else if (object_dynamic_cast(OBJECT(dev), TYPE_CPU) && 413 !s->cpu_hotplug_legacy) { 414 acpi_cpu_unplug_request_cb(hotplug_dev, &s->cpuhp_state, dev, errp); 415 } else { 416 error_setg(errp, "acpi: device unplug request for not supported device" 417 " type: %s", object_get_typename(OBJECT(dev))); 418 } 419 } 420 421 static void piix4_device_unplug_cb(HotplugHandler *hotplug_dev, 422 DeviceState *dev, Error **errp) 423 { 424 PIIX4PMState *s = PIIX4_PM(hotplug_dev); 425 426 if (s->acpi_memory_hotplug.is_enabled && 427 object_dynamic_cast(OBJECT(dev), TYPE_PC_DIMM)) { 428 acpi_memory_unplug_cb(&s->acpi_memory_hotplug, dev, errp); 429 } else if (object_dynamic_cast(OBJECT(dev), TYPE_CPU) && 430 !s->cpu_hotplug_legacy) { 431 acpi_cpu_unplug_cb(&s->cpuhp_state, dev, errp); 432 } else { 433 error_setg(errp, "acpi: device unplug for not supported device" 434 " type: %s", object_get_typename(OBJECT(dev))); 435 } 436 } 437 438 static void piix4_update_bus_hotplug(PCIBus *pci_bus, void *opaque) 439 { 440 PIIX4PMState *s = opaque; 441 442 /* pci_bus cannot outlive PIIX4PMState, because /machine keeps it alive 443 * and it's not hot-unpluggable */ 444 qbus_set_hotplug_handler(BUS(pci_bus), DEVICE(s), &error_abort); 445 } 446 447 static void piix4_pm_machine_ready(Notifier *n, void *opaque) 448 { 449 PIIX4PMState *s = container_of(n, PIIX4PMState, machine_ready); 450 PCIDevice *d = PCI_DEVICE(s); 451 MemoryRegion *io_as = pci_address_space_io(d); 452 uint8_t *pci_conf; 453 454 pci_conf = d->config; 455 pci_conf[0x5f] = 0x10 | 456 (memory_region_present(io_as, 0x378) ? 0x80 : 0); 457 pci_conf[0x63] = 0x60; 458 pci_conf[0x67] = (memory_region_present(io_as, 0x3f8) ? 0x08 : 0) | 459 (memory_region_present(io_as, 0x2f8) ? 0x90 : 0); 460 461 if (s->use_acpi_pci_hotplug) { 462 pci_for_each_bus(pci_get_bus(d), piix4_update_bus_hotplug, s); 463 } else { 464 piix4_update_bus_hotplug(pci_get_bus(d), s); 465 } 466 } 467 468 static void piix4_pm_add_propeties(PIIX4PMState *s) 469 { 470 static const uint8_t acpi_enable_cmd = ACPI_ENABLE; 471 static const uint8_t acpi_disable_cmd = ACPI_DISABLE; 472 static const uint32_t gpe0_blk = GPE_BASE; 473 static const uint32_t gpe0_blk_len = GPE_LEN; 474 static const uint16_t sci_int = 9; 475 476 object_property_add_uint8_ptr(OBJECT(s), ACPI_PM_PROP_ACPI_ENABLE_CMD, 477 &acpi_enable_cmd, NULL); 478 object_property_add_uint8_ptr(OBJECT(s), ACPI_PM_PROP_ACPI_DISABLE_CMD, 479 &acpi_disable_cmd, NULL); 480 object_property_add_uint32_ptr(OBJECT(s), ACPI_PM_PROP_GPE0_BLK, 481 &gpe0_blk, NULL); 482 object_property_add_uint32_ptr(OBJECT(s), ACPI_PM_PROP_GPE0_BLK_LEN, 483 &gpe0_blk_len, NULL); 484 object_property_add_uint16_ptr(OBJECT(s), ACPI_PM_PROP_SCI_INT, 485 &sci_int, NULL); 486 object_property_add_uint32_ptr(OBJECT(s), ACPI_PM_PROP_PM_IO_BASE, 487 &s->io_base, NULL); 488 } 489 490 static void piix4_pm_realize(PCIDevice *dev, Error **errp) 491 { 492 PIIX4PMState *s = PIIX4_PM(dev); 493 uint8_t *pci_conf; 494 495 pci_conf = dev->config; 496 pci_conf[0x06] = 0x80; 497 pci_conf[0x07] = 0x02; 498 pci_conf[0x09] = 0x00; 499 pci_conf[0x3d] = 0x01; // interrupt pin 1 500 501 /* APM */ 502 apm_init(dev, &s->apm, apm_ctrl_changed, s); 503 504 if (!s->smm_enabled) { 505 /* Mark SMM as already inited to prevent SMM from running. KVM does not 506 * support SMM mode. */ 507 pci_conf[0x5B] = 0x02; 508 } 509 510 /* XXX: which specification is used ? The i82731AB has different 511 mappings */ 512 pci_conf[0x90] = s->smb_io_base | 1; 513 pci_conf[0x91] = s->smb_io_base >> 8; 514 pci_conf[0xd2] = 0x09; 515 pm_smbus_init(DEVICE(dev), &s->smb); 516 memory_region_set_enabled(&s->smb.io, pci_conf[0xd2] & 1); 517 memory_region_add_subregion(pci_address_space_io(dev), 518 s->smb_io_base, &s->smb.io); 519 520 memory_region_init(&s->io, OBJECT(s), "piix4-pm", 64); 521 memory_region_set_enabled(&s->io, false); 522 memory_region_add_subregion(pci_address_space_io(dev), 523 0, &s->io); 524 525 acpi_pm_tmr_init(&s->ar, pm_tmr_timer, &s->io); 526 acpi_pm1_evt_init(&s->ar, pm_tmr_timer, &s->io); 527 acpi_pm1_cnt_init(&s->ar, &s->io, s->disable_s3, s->disable_s4, s->s4_val); 528 acpi_gpe_init(&s->ar, GPE_LEN); 529 530 s->powerdown_notifier.notify = piix4_pm_powerdown_req; 531 qemu_register_powerdown_notifier(&s->powerdown_notifier); 532 533 s->machine_ready.notify = piix4_pm_machine_ready; 534 qemu_add_machine_init_done_notifier(&s->machine_ready); 535 qemu_register_reset(piix4_reset, s); 536 537 piix4_acpi_system_hot_add_init(pci_address_space_io(dev), 538 pci_get_bus(dev), s); 539 540 piix4_pm_add_propeties(s); 541 } 542 543 Object *piix4_pm_find(void) 544 { 545 bool ambig; 546 Object *o = object_resolve_path_type("", TYPE_PIIX4_PM, &ambig); 547 548 if (ambig || !o) { 549 return NULL; 550 } 551 return o; 552 } 553 554 I2CBus *piix4_pm_init(PCIBus *bus, int devfn, uint32_t smb_io_base, 555 qemu_irq sci_irq, qemu_irq smi_irq, 556 int smm_enabled, DeviceState **piix4_pm) 557 { 558 DeviceState *dev; 559 PIIX4PMState *s; 560 561 dev = DEVICE(pci_create(bus, devfn, TYPE_PIIX4_PM)); 562 qdev_prop_set_uint32(dev, "smb_io_base", smb_io_base); 563 if (piix4_pm) { 564 *piix4_pm = dev; 565 } 566 567 s = PIIX4_PM(dev); 568 s->irq = sci_irq; 569 s->smi_irq = smi_irq; 570 s->smm_enabled = smm_enabled; 571 if (xen_enabled()) { 572 s->use_acpi_pci_hotplug = false; 573 } 574 575 qdev_init_nofail(dev); 576 577 return s->smb.smbus; 578 } 579 580 static uint64_t gpe_readb(void *opaque, hwaddr addr, unsigned width) 581 { 582 PIIX4PMState *s = opaque; 583 uint32_t val = acpi_gpe_ioport_readb(&s->ar, addr); 584 585 PIIX4_DPRINTF("gpe read %" HWADDR_PRIx " == %" PRIu32 "\n", addr, val); 586 return val; 587 } 588 589 static void gpe_writeb(void *opaque, hwaddr addr, uint64_t val, 590 unsigned width) 591 { 592 PIIX4PMState *s = opaque; 593 594 acpi_gpe_ioport_writeb(&s->ar, addr, val); 595 acpi_update_sci(&s->ar, s->irq); 596 597 PIIX4_DPRINTF("gpe write %" HWADDR_PRIx " <== %" PRIu64 "\n", addr, val); 598 } 599 600 static const MemoryRegionOps piix4_gpe_ops = { 601 .read = gpe_readb, 602 .write = gpe_writeb, 603 .valid.min_access_size = 1, 604 .valid.max_access_size = 4, 605 .impl.min_access_size = 1, 606 .impl.max_access_size = 1, 607 .endianness = DEVICE_LITTLE_ENDIAN, 608 }; 609 610 611 static bool piix4_get_cpu_hotplug_legacy(Object *obj, Error **errp) 612 { 613 PIIX4PMState *s = PIIX4_PM(obj); 614 615 return s->cpu_hotplug_legacy; 616 } 617 618 static void piix4_set_cpu_hotplug_legacy(Object *obj, bool value, Error **errp) 619 { 620 PIIX4PMState *s = PIIX4_PM(obj); 621 622 assert(!value); 623 if (s->cpu_hotplug_legacy && value == false) { 624 acpi_switch_to_modern_cphp(&s->gpe_cpu, &s->cpuhp_state, 625 PIIX4_CPU_HOTPLUG_IO_BASE); 626 } 627 s->cpu_hotplug_legacy = value; 628 } 629 630 static void piix4_acpi_system_hot_add_init(MemoryRegion *parent, 631 PCIBus *bus, PIIX4PMState *s) 632 { 633 memory_region_init_io(&s->io_gpe, OBJECT(s), &piix4_gpe_ops, s, 634 "acpi-gpe0", GPE_LEN); 635 memory_region_add_subregion(parent, GPE_BASE, &s->io_gpe); 636 637 acpi_pcihp_init(OBJECT(s), &s->acpi_pci_hotplug, bus, parent, 638 s->use_acpi_pci_hotplug); 639 640 s->cpu_hotplug_legacy = true; 641 object_property_add_bool(OBJECT(s), "cpu-hotplug-legacy", 642 piix4_get_cpu_hotplug_legacy, 643 piix4_set_cpu_hotplug_legacy, 644 NULL); 645 legacy_acpi_cpu_hotplug_init(parent, OBJECT(s), &s->gpe_cpu, 646 PIIX4_CPU_HOTPLUG_IO_BASE); 647 648 if (s->acpi_memory_hotplug.is_enabled) { 649 acpi_memory_hotplug_init(parent, OBJECT(s), &s->acpi_memory_hotplug, 650 ACPI_MEMORY_HOTPLUG_BASE); 651 } 652 } 653 654 static void piix4_ospm_status(AcpiDeviceIf *adev, ACPIOSTInfoList ***list) 655 { 656 PIIX4PMState *s = PIIX4_PM(adev); 657 658 acpi_memory_ospm_status(&s->acpi_memory_hotplug, list); 659 if (!s->cpu_hotplug_legacy) { 660 acpi_cpu_ospm_status(&s->cpuhp_state, list); 661 } 662 } 663 664 static void piix4_send_gpe(AcpiDeviceIf *adev, AcpiEventStatusBits ev) 665 { 666 PIIX4PMState *s = PIIX4_PM(adev); 667 668 acpi_send_gpe_event(&s->ar, s->irq, ev); 669 } 670 671 static Property piix4_pm_properties[] = { 672 DEFINE_PROP_UINT32("smb_io_base", PIIX4PMState, smb_io_base, 0), 673 DEFINE_PROP_UINT8(ACPI_PM_PROP_S3_DISABLED, PIIX4PMState, disable_s3, 0), 674 DEFINE_PROP_UINT8(ACPI_PM_PROP_S4_DISABLED, PIIX4PMState, disable_s4, 0), 675 DEFINE_PROP_UINT8(ACPI_PM_PROP_S4_VAL, PIIX4PMState, s4_val, 2), 676 DEFINE_PROP_BOOL("acpi-pci-hotplug-with-bridge-support", PIIX4PMState, 677 use_acpi_pci_hotplug, true), 678 DEFINE_PROP_BOOL("memory-hotplug-support", PIIX4PMState, 679 acpi_memory_hotplug.is_enabled, true), 680 DEFINE_PROP_END_OF_LIST(), 681 }; 682 683 static void piix4_pm_class_init(ObjectClass *klass, void *data) 684 { 685 DeviceClass *dc = DEVICE_CLASS(klass); 686 PCIDeviceClass *k = PCI_DEVICE_CLASS(klass); 687 HotplugHandlerClass *hc = HOTPLUG_HANDLER_CLASS(klass); 688 AcpiDeviceIfClass *adevc = ACPI_DEVICE_IF_CLASS(klass); 689 690 k->realize = piix4_pm_realize; 691 k->config_write = pm_write_config; 692 k->vendor_id = PCI_VENDOR_ID_INTEL; 693 k->device_id = PCI_DEVICE_ID_INTEL_82371AB_3; 694 k->revision = 0x03; 695 k->class_id = PCI_CLASS_BRIDGE_OTHER; 696 dc->desc = "PM"; 697 dc->vmsd = &vmstate_acpi; 698 dc->props = piix4_pm_properties; 699 /* 700 * Reason: part of PIIX4 southbridge, needs to be wired up, 701 * e.g. by mips_malta_init() 702 */ 703 dc->user_creatable = false; 704 dc->hotpluggable = false; 705 hc->plug = piix4_device_plug_cb; 706 hc->unplug_request = piix4_device_unplug_request_cb; 707 hc->unplug = piix4_device_unplug_cb; 708 adevc->ospm_status = piix4_ospm_status; 709 adevc->send_event = piix4_send_gpe; 710 adevc->madt_cpu = pc_madt_cpu_entry; 711 } 712 713 static const TypeInfo piix4_pm_info = { 714 .name = TYPE_PIIX4_PM, 715 .parent = TYPE_PCI_DEVICE, 716 .instance_size = sizeof(PIIX4PMState), 717 .class_init = piix4_pm_class_init, 718 .interfaces = (InterfaceInfo[]) { 719 { TYPE_HOTPLUG_HANDLER }, 720 { TYPE_ACPI_DEVICE_IF }, 721 { INTERFACE_CONVENTIONAL_PCI_DEVICE }, 722 { } 723 } 724 }; 725 726 static void piix4_pm_register_types(void) 727 { 728 type_register_static(&piix4_pm_info); 729 } 730 731 type_init(piix4_pm_register_types) 732