1 /* 2 * ACPI implementation 3 * 4 * Copyright (c) 2006 Fabrice Bellard 5 * 6 * This library is free software; you can redistribute it and/or 7 * modify it under the terms of the GNU Lesser General Public 8 * License version 2 as published by the Free Software Foundation. 9 * 10 * This library is distributed in the hope that it will be useful, 11 * but WITHOUT ANY WARRANTY; without even the implied warranty of 12 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU 13 * Lesser General Public License for more details. 14 * 15 * You should have received a copy of the GNU Lesser General Public 16 * License along with this library; if not, see <http://www.gnu.org/licenses/> 17 * 18 * Contributions after 2012-01-13 are licensed under the terms of the 19 * GNU GPL, version 2 or (at your option) any later version. 20 */ 21 #include "qemu/osdep.h" 22 #include "hw/hw.h" 23 #include "hw/i386/pc.h" 24 #include "hw/isa/apm.h" 25 #include "hw/i2c/pm_smbus.h" 26 #include "hw/pci/pci.h" 27 #include "hw/acpi/acpi.h" 28 #include "sysemu/sysemu.h" 29 #include "qapi/error.h" 30 #include "qemu/range.h" 31 #include "exec/ioport.h" 32 #include "hw/nvram/fw_cfg.h" 33 #include "exec/address-spaces.h" 34 #include "hw/acpi/piix4.h" 35 #include "hw/acpi/pcihp.h" 36 #include "hw/acpi/cpu_hotplug.h" 37 #include "hw/acpi/cpu.h" 38 #include "hw/hotplug.h" 39 #include "hw/mem/pc-dimm.h" 40 #include "hw/acpi/memory_hotplug.h" 41 #include "hw/acpi/acpi_dev_interface.h" 42 #include "hw/xen/xen.h" 43 #include "qom/cpu.h" 44 45 //#define DEBUG 46 47 #ifdef DEBUG 48 # define PIIX4_DPRINTF(format, ...) printf(format, ## __VA_ARGS__) 49 #else 50 # define PIIX4_DPRINTF(format, ...) do { } while (0) 51 #endif 52 53 #define GPE_BASE 0xafe0 54 #define GPE_LEN 4 55 56 struct pci_status { 57 uint32_t up; /* deprecated, maintained for migration compatibility */ 58 uint32_t down; 59 }; 60 61 typedef struct PIIX4PMState { 62 /*< private >*/ 63 PCIDevice parent_obj; 64 /*< public >*/ 65 66 MemoryRegion io; 67 uint32_t io_base; 68 69 MemoryRegion io_gpe; 70 ACPIREGS ar; 71 72 APMState apm; 73 74 PMSMBus smb; 75 uint32_t smb_io_base; 76 77 qemu_irq irq; 78 qemu_irq smi_irq; 79 int smm_enabled; 80 Notifier machine_ready; 81 Notifier powerdown_notifier; 82 83 AcpiPciHpState acpi_pci_hotplug; 84 bool use_acpi_pci_hotplug; 85 86 uint8_t disable_s3; 87 uint8_t disable_s4; 88 uint8_t s4_val; 89 90 bool cpu_hotplug_legacy; 91 AcpiCpuHotplug gpe_cpu; 92 CPUHotplugState cpuhp_state; 93 94 MemHotplugState acpi_memory_hotplug; 95 } PIIX4PMState; 96 97 #define TYPE_PIIX4_PM "PIIX4_PM" 98 99 #define PIIX4_PM(obj) \ 100 OBJECT_CHECK(PIIX4PMState, (obj), TYPE_PIIX4_PM) 101 102 static void piix4_acpi_system_hot_add_init(MemoryRegion *parent, 103 PCIBus *bus, PIIX4PMState *s); 104 105 #define ACPI_ENABLE 0xf1 106 #define ACPI_DISABLE 0xf0 107 108 static void pm_tmr_timer(ACPIREGS *ar) 109 { 110 PIIX4PMState *s = container_of(ar, PIIX4PMState, ar); 111 acpi_update_sci(&s->ar, s->irq); 112 } 113 114 static void apm_ctrl_changed(uint32_t val, void *arg) 115 { 116 PIIX4PMState *s = arg; 117 PCIDevice *d = PCI_DEVICE(s); 118 119 /* ACPI specs 3.0, 4.7.2.5 */ 120 acpi_pm1_cnt_update(&s->ar, val == ACPI_ENABLE, val == ACPI_DISABLE); 121 if (val == ACPI_ENABLE || val == ACPI_DISABLE) { 122 return; 123 } 124 125 if (d->config[0x5b] & (1 << 1)) { 126 if (s->smi_irq) { 127 qemu_irq_raise(s->smi_irq); 128 } 129 } 130 } 131 132 static void pm_io_space_update(PIIX4PMState *s) 133 { 134 PCIDevice *d = PCI_DEVICE(s); 135 136 s->io_base = le32_to_cpu(*(uint32_t *)(d->config + 0x40)); 137 s->io_base &= 0xffc0; 138 139 memory_region_transaction_begin(); 140 memory_region_set_enabled(&s->io, d->config[0x80] & 1); 141 memory_region_set_address(&s->io, s->io_base); 142 memory_region_transaction_commit(); 143 } 144 145 static void smbus_io_space_update(PIIX4PMState *s) 146 { 147 PCIDevice *d = PCI_DEVICE(s); 148 149 s->smb_io_base = le32_to_cpu(*(uint32_t *)(d->config + 0x90)); 150 s->smb_io_base &= 0xffc0; 151 152 memory_region_transaction_begin(); 153 memory_region_set_enabled(&s->smb.io, d->config[0xd2] & 1); 154 memory_region_set_address(&s->smb.io, s->smb_io_base); 155 memory_region_transaction_commit(); 156 } 157 158 static void pm_write_config(PCIDevice *d, 159 uint32_t address, uint32_t val, int len) 160 { 161 pci_default_write_config(d, address, val, len); 162 if (range_covers_byte(address, len, 0x80) || 163 ranges_overlap(address, len, 0x40, 4)) { 164 pm_io_space_update((PIIX4PMState *)d); 165 } 166 if (range_covers_byte(address, len, 0xd2) || 167 ranges_overlap(address, len, 0x90, 4)) { 168 smbus_io_space_update((PIIX4PMState *)d); 169 } 170 } 171 172 static int vmstate_acpi_post_load(void *opaque, int version_id) 173 { 174 PIIX4PMState *s = opaque; 175 176 pm_io_space_update(s); 177 return 0; 178 } 179 180 #define VMSTATE_GPE_ARRAY(_field, _state) \ 181 { \ 182 .name = (stringify(_field)), \ 183 .version_id = 0, \ 184 .info = &vmstate_info_uint16, \ 185 .size = sizeof(uint16_t), \ 186 .flags = VMS_SINGLE | VMS_POINTER, \ 187 .offset = vmstate_offset_pointer(_state, _field, uint8_t), \ 188 } 189 190 static const VMStateDescription vmstate_gpe = { 191 .name = "gpe", 192 .version_id = 1, 193 .minimum_version_id = 1, 194 .fields = (VMStateField[]) { 195 VMSTATE_GPE_ARRAY(sts, ACPIGPE), 196 VMSTATE_GPE_ARRAY(en, ACPIGPE), 197 VMSTATE_END_OF_LIST() 198 } 199 }; 200 201 static const VMStateDescription vmstate_pci_status = { 202 .name = "pci_status", 203 .version_id = 1, 204 .minimum_version_id = 1, 205 .fields = (VMStateField[]) { 206 VMSTATE_UINT32(up, struct AcpiPciHpPciStatus), 207 VMSTATE_UINT32(down, struct AcpiPciHpPciStatus), 208 VMSTATE_END_OF_LIST() 209 } 210 }; 211 212 static int acpi_load_old(QEMUFile *f, void *opaque, int version_id) 213 { 214 PIIX4PMState *s = opaque; 215 int ret, i; 216 uint16_t temp; 217 218 ret = pci_device_load(PCI_DEVICE(s), f); 219 if (ret < 0) { 220 return ret; 221 } 222 qemu_get_be16s(f, &s->ar.pm1.evt.sts); 223 qemu_get_be16s(f, &s->ar.pm1.evt.en); 224 qemu_get_be16s(f, &s->ar.pm1.cnt.cnt); 225 226 ret = vmstate_load_state(f, &vmstate_apm, &s->apm, 1); 227 if (ret) { 228 return ret; 229 } 230 231 timer_get(f, s->ar.tmr.timer); 232 qemu_get_sbe64s(f, &s->ar.tmr.overflow_time); 233 234 qemu_get_be16s(f, (uint16_t *)s->ar.gpe.sts); 235 for (i = 0; i < 3; i++) { 236 qemu_get_be16s(f, &temp); 237 } 238 239 qemu_get_be16s(f, (uint16_t *)s->ar.gpe.en); 240 for (i = 0; i < 3; i++) { 241 qemu_get_be16s(f, &temp); 242 } 243 244 ret = vmstate_load_state(f, &vmstate_pci_status, 245 &s->acpi_pci_hotplug.acpi_pcihp_pci_status[ACPI_PCIHP_BSEL_DEFAULT], 1); 246 return ret; 247 } 248 249 static bool vmstate_test_use_acpi_pci_hotplug(void *opaque, int version_id) 250 { 251 PIIX4PMState *s = opaque; 252 return s->use_acpi_pci_hotplug; 253 } 254 255 static bool vmstate_test_no_use_acpi_pci_hotplug(void *opaque, int version_id) 256 { 257 PIIX4PMState *s = opaque; 258 return !s->use_acpi_pci_hotplug; 259 } 260 261 static bool vmstate_test_use_memhp(void *opaque) 262 { 263 PIIX4PMState *s = opaque; 264 return s->acpi_memory_hotplug.is_enabled; 265 } 266 267 static const VMStateDescription vmstate_memhp_state = { 268 .name = "piix4_pm/memhp", 269 .version_id = 1, 270 .minimum_version_id = 1, 271 .minimum_version_id_old = 1, 272 .needed = vmstate_test_use_memhp, 273 .fields = (VMStateField[]) { 274 VMSTATE_MEMORY_HOTPLUG(acpi_memory_hotplug, PIIX4PMState), 275 VMSTATE_END_OF_LIST() 276 } 277 }; 278 279 static bool vmstate_test_use_cpuhp(void *opaque) 280 { 281 PIIX4PMState *s = opaque; 282 return !s->cpu_hotplug_legacy; 283 } 284 285 static int vmstate_cpuhp_pre_load(void *opaque) 286 { 287 Object *obj = OBJECT(opaque); 288 object_property_set_bool(obj, false, "cpu-hotplug-legacy", &error_abort); 289 return 0; 290 } 291 292 static const VMStateDescription vmstate_cpuhp_state = { 293 .name = "piix4_pm/cpuhp", 294 .version_id = 1, 295 .minimum_version_id = 1, 296 .minimum_version_id_old = 1, 297 .needed = vmstate_test_use_cpuhp, 298 .pre_load = vmstate_cpuhp_pre_load, 299 .fields = (VMStateField[]) { 300 VMSTATE_CPU_HOTPLUG(cpuhp_state, PIIX4PMState), 301 VMSTATE_END_OF_LIST() 302 } 303 }; 304 305 /* qemu-kvm 1.2 uses version 3 but advertised as 2 306 * To support incoming qemu-kvm 1.2 migration, change version_id 307 * and minimum_version_id to 2 below (which breaks migration from 308 * qemu 1.2). 309 * 310 */ 311 static const VMStateDescription vmstate_acpi = { 312 .name = "piix4_pm", 313 .version_id = 3, 314 .minimum_version_id = 3, 315 .minimum_version_id_old = 1, 316 .load_state_old = acpi_load_old, 317 .post_load = vmstate_acpi_post_load, 318 .fields = (VMStateField[]) { 319 VMSTATE_PCI_DEVICE(parent_obj, PIIX4PMState), 320 VMSTATE_UINT16(ar.pm1.evt.sts, PIIX4PMState), 321 VMSTATE_UINT16(ar.pm1.evt.en, PIIX4PMState), 322 VMSTATE_UINT16(ar.pm1.cnt.cnt, PIIX4PMState), 323 VMSTATE_STRUCT(apm, PIIX4PMState, 0, vmstate_apm, APMState), 324 VMSTATE_TIMER_PTR(ar.tmr.timer, PIIX4PMState), 325 VMSTATE_INT64(ar.tmr.overflow_time, PIIX4PMState), 326 VMSTATE_STRUCT(ar.gpe, PIIX4PMState, 2, vmstate_gpe, ACPIGPE), 327 VMSTATE_STRUCT_TEST( 328 acpi_pci_hotplug.acpi_pcihp_pci_status[ACPI_PCIHP_BSEL_DEFAULT], 329 PIIX4PMState, 330 vmstate_test_no_use_acpi_pci_hotplug, 331 2, vmstate_pci_status, 332 struct AcpiPciHpPciStatus), 333 VMSTATE_PCI_HOTPLUG(acpi_pci_hotplug, PIIX4PMState, 334 vmstate_test_use_acpi_pci_hotplug), 335 VMSTATE_END_OF_LIST() 336 }, 337 .subsections = (const VMStateDescription*[]) { 338 &vmstate_memhp_state, 339 &vmstate_cpuhp_state, 340 NULL 341 } 342 }; 343 344 static void piix4_reset(void *opaque) 345 { 346 PIIX4PMState *s = opaque; 347 PCIDevice *d = PCI_DEVICE(s); 348 uint8_t *pci_conf = d->config; 349 350 pci_conf[0x58] = 0; 351 pci_conf[0x59] = 0; 352 pci_conf[0x5a] = 0; 353 pci_conf[0x5b] = 0; 354 355 pci_conf[0x40] = 0x01; /* PM io base read only bit */ 356 pci_conf[0x80] = 0; 357 358 if (!s->smm_enabled) { 359 /* Mark SMM as already inited (until KVM supports SMM). */ 360 pci_conf[0x5B] = 0x02; 361 } 362 pm_io_space_update(s); 363 acpi_pcihp_reset(&s->acpi_pci_hotplug); 364 } 365 366 static void piix4_pm_powerdown_req(Notifier *n, void *opaque) 367 { 368 PIIX4PMState *s = container_of(n, PIIX4PMState, powerdown_notifier); 369 370 assert(s != NULL); 371 acpi_pm1_evt_power_down(&s->ar); 372 } 373 374 static void piix4_device_plug_cb(HotplugHandler *hotplug_dev, 375 DeviceState *dev, Error **errp) 376 { 377 PIIX4PMState *s = PIIX4_PM(hotplug_dev); 378 379 if (s->acpi_memory_hotplug.is_enabled && 380 object_dynamic_cast(OBJECT(dev), TYPE_PC_DIMM)) { 381 acpi_memory_plug_cb(hotplug_dev, &s->acpi_memory_hotplug, dev, errp); 382 } else if (object_dynamic_cast(OBJECT(dev), TYPE_PCI_DEVICE)) { 383 acpi_pcihp_device_plug_cb(hotplug_dev, &s->acpi_pci_hotplug, dev, errp); 384 } else if (object_dynamic_cast(OBJECT(dev), TYPE_CPU)) { 385 if (s->cpu_hotplug_legacy) { 386 legacy_acpi_cpu_plug_cb(hotplug_dev, &s->gpe_cpu, dev, errp); 387 } else { 388 acpi_cpu_plug_cb(hotplug_dev, &s->cpuhp_state, dev, errp); 389 } 390 } else { 391 error_setg(errp, "acpi: device plug request for not supported device" 392 " type: %s", object_get_typename(OBJECT(dev))); 393 } 394 } 395 396 static void piix4_device_unplug_request_cb(HotplugHandler *hotplug_dev, 397 DeviceState *dev, Error **errp) 398 { 399 PIIX4PMState *s = PIIX4_PM(hotplug_dev); 400 401 if (s->acpi_memory_hotplug.is_enabled && 402 object_dynamic_cast(OBJECT(dev), TYPE_PC_DIMM)) { 403 acpi_memory_unplug_request_cb(hotplug_dev, &s->acpi_memory_hotplug, 404 dev, errp); 405 } else if (object_dynamic_cast(OBJECT(dev), TYPE_PCI_DEVICE)) { 406 acpi_pcihp_device_unplug_cb(hotplug_dev, &s->acpi_pci_hotplug, dev, 407 errp); 408 } else if (object_dynamic_cast(OBJECT(dev), TYPE_CPU) && 409 !s->cpu_hotplug_legacy) { 410 acpi_cpu_unplug_request_cb(hotplug_dev, &s->cpuhp_state, dev, errp); 411 } else { 412 error_setg(errp, "acpi: device unplug request for not supported device" 413 " type: %s", object_get_typename(OBJECT(dev))); 414 } 415 } 416 417 static void piix4_device_unplug_cb(HotplugHandler *hotplug_dev, 418 DeviceState *dev, Error **errp) 419 { 420 PIIX4PMState *s = PIIX4_PM(hotplug_dev); 421 422 if (s->acpi_memory_hotplug.is_enabled && 423 object_dynamic_cast(OBJECT(dev), TYPE_PC_DIMM)) { 424 acpi_memory_unplug_cb(&s->acpi_memory_hotplug, dev, errp); 425 } else if (object_dynamic_cast(OBJECT(dev), TYPE_CPU) && 426 !s->cpu_hotplug_legacy) { 427 acpi_cpu_unplug_cb(&s->cpuhp_state, dev, errp); 428 } else { 429 error_setg(errp, "acpi: device unplug for not supported device" 430 " type: %s", object_get_typename(OBJECT(dev))); 431 } 432 } 433 434 static void piix4_update_bus_hotplug(PCIBus *pci_bus, void *opaque) 435 { 436 PIIX4PMState *s = opaque; 437 438 qbus_set_hotplug_handler(BUS(pci_bus), DEVICE(s), &error_abort); 439 } 440 441 static void piix4_pm_machine_ready(Notifier *n, void *opaque) 442 { 443 PIIX4PMState *s = container_of(n, PIIX4PMState, machine_ready); 444 PCIDevice *d = PCI_DEVICE(s); 445 MemoryRegion *io_as = pci_address_space_io(d); 446 uint8_t *pci_conf; 447 448 pci_conf = d->config; 449 pci_conf[0x5f] = 0x10 | 450 (memory_region_present(io_as, 0x378) ? 0x80 : 0); 451 pci_conf[0x63] = 0x60; 452 pci_conf[0x67] = (memory_region_present(io_as, 0x3f8) ? 0x08 : 0) | 453 (memory_region_present(io_as, 0x2f8) ? 0x90 : 0); 454 455 if (s->use_acpi_pci_hotplug) { 456 pci_for_each_bus(d->bus, piix4_update_bus_hotplug, s); 457 } else { 458 piix4_update_bus_hotplug(d->bus, s); 459 } 460 } 461 462 static void piix4_pm_add_propeties(PIIX4PMState *s) 463 { 464 static const uint8_t acpi_enable_cmd = ACPI_ENABLE; 465 static const uint8_t acpi_disable_cmd = ACPI_DISABLE; 466 static const uint32_t gpe0_blk = GPE_BASE; 467 static const uint32_t gpe0_blk_len = GPE_LEN; 468 static const uint16_t sci_int = 9; 469 470 object_property_add_uint8_ptr(OBJECT(s), ACPI_PM_PROP_ACPI_ENABLE_CMD, 471 &acpi_enable_cmd, NULL); 472 object_property_add_uint8_ptr(OBJECT(s), ACPI_PM_PROP_ACPI_DISABLE_CMD, 473 &acpi_disable_cmd, NULL); 474 object_property_add_uint32_ptr(OBJECT(s), ACPI_PM_PROP_GPE0_BLK, 475 &gpe0_blk, NULL); 476 object_property_add_uint32_ptr(OBJECT(s), ACPI_PM_PROP_GPE0_BLK_LEN, 477 &gpe0_blk_len, NULL); 478 object_property_add_uint16_ptr(OBJECT(s), ACPI_PM_PROP_SCI_INT, 479 &sci_int, NULL); 480 object_property_add_uint32_ptr(OBJECT(s), ACPI_PM_PROP_PM_IO_BASE, 481 &s->io_base, NULL); 482 } 483 484 static void piix4_pm_realize(PCIDevice *dev, Error **errp) 485 { 486 PIIX4PMState *s = PIIX4_PM(dev); 487 uint8_t *pci_conf; 488 489 pci_conf = dev->config; 490 pci_conf[0x06] = 0x80; 491 pci_conf[0x07] = 0x02; 492 pci_conf[0x09] = 0x00; 493 pci_conf[0x3d] = 0x01; // interrupt pin 1 494 495 /* APM */ 496 apm_init(dev, &s->apm, apm_ctrl_changed, s); 497 498 if (!s->smm_enabled) { 499 /* Mark SMM as already inited to prevent SMM from running. KVM does not 500 * support SMM mode. */ 501 pci_conf[0x5B] = 0x02; 502 } 503 504 /* XXX: which specification is used ? The i82731AB has different 505 mappings */ 506 pci_conf[0x90] = s->smb_io_base | 1; 507 pci_conf[0x91] = s->smb_io_base >> 8; 508 pci_conf[0xd2] = 0x09; 509 pm_smbus_init(DEVICE(dev), &s->smb); 510 memory_region_set_enabled(&s->smb.io, pci_conf[0xd2] & 1); 511 memory_region_add_subregion(pci_address_space_io(dev), 512 s->smb_io_base, &s->smb.io); 513 514 memory_region_init(&s->io, OBJECT(s), "piix4-pm", 64); 515 memory_region_set_enabled(&s->io, false); 516 memory_region_add_subregion(pci_address_space_io(dev), 517 0, &s->io); 518 519 acpi_pm_tmr_init(&s->ar, pm_tmr_timer, &s->io); 520 acpi_pm1_evt_init(&s->ar, pm_tmr_timer, &s->io); 521 acpi_pm1_cnt_init(&s->ar, &s->io, s->disable_s3, s->disable_s4, s->s4_val); 522 acpi_gpe_init(&s->ar, GPE_LEN); 523 524 s->powerdown_notifier.notify = piix4_pm_powerdown_req; 525 qemu_register_powerdown_notifier(&s->powerdown_notifier); 526 527 s->machine_ready.notify = piix4_pm_machine_ready; 528 qemu_add_machine_init_done_notifier(&s->machine_ready); 529 qemu_register_reset(piix4_reset, s); 530 531 piix4_acpi_system_hot_add_init(pci_address_space_io(dev), dev->bus, s); 532 533 piix4_pm_add_propeties(s); 534 } 535 536 Object *piix4_pm_find(void) 537 { 538 bool ambig; 539 Object *o = object_resolve_path_type("", TYPE_PIIX4_PM, &ambig); 540 541 if (ambig || !o) { 542 return NULL; 543 } 544 return o; 545 } 546 547 I2CBus *piix4_pm_init(PCIBus *bus, int devfn, uint32_t smb_io_base, 548 qemu_irq sci_irq, qemu_irq smi_irq, 549 int smm_enabled, DeviceState **piix4_pm) 550 { 551 DeviceState *dev; 552 PIIX4PMState *s; 553 554 dev = DEVICE(pci_create(bus, devfn, TYPE_PIIX4_PM)); 555 qdev_prop_set_uint32(dev, "smb_io_base", smb_io_base); 556 if (piix4_pm) { 557 *piix4_pm = dev; 558 } 559 560 s = PIIX4_PM(dev); 561 s->irq = sci_irq; 562 s->smi_irq = smi_irq; 563 s->smm_enabled = smm_enabled; 564 if (xen_enabled()) { 565 s->use_acpi_pci_hotplug = false; 566 } 567 568 qdev_init_nofail(dev); 569 570 return s->smb.smbus; 571 } 572 573 static uint64_t gpe_readb(void *opaque, hwaddr addr, unsigned width) 574 { 575 PIIX4PMState *s = opaque; 576 uint32_t val = acpi_gpe_ioport_readb(&s->ar, addr); 577 578 PIIX4_DPRINTF("gpe read %" HWADDR_PRIx " == %" PRIu32 "\n", addr, val); 579 return val; 580 } 581 582 static void gpe_writeb(void *opaque, hwaddr addr, uint64_t val, 583 unsigned width) 584 { 585 PIIX4PMState *s = opaque; 586 587 acpi_gpe_ioport_writeb(&s->ar, addr, val); 588 acpi_update_sci(&s->ar, s->irq); 589 590 PIIX4_DPRINTF("gpe write %" HWADDR_PRIx " <== %" PRIu64 "\n", addr, val); 591 } 592 593 static const MemoryRegionOps piix4_gpe_ops = { 594 .read = gpe_readb, 595 .write = gpe_writeb, 596 .valid.min_access_size = 1, 597 .valid.max_access_size = 4, 598 .impl.min_access_size = 1, 599 .impl.max_access_size = 1, 600 .endianness = DEVICE_LITTLE_ENDIAN, 601 }; 602 603 604 static bool piix4_get_cpu_hotplug_legacy(Object *obj, Error **errp) 605 { 606 PIIX4PMState *s = PIIX4_PM(obj); 607 608 return s->cpu_hotplug_legacy; 609 } 610 611 static void piix4_set_cpu_hotplug_legacy(Object *obj, bool value, Error **errp) 612 { 613 PIIX4PMState *s = PIIX4_PM(obj); 614 615 assert(!value); 616 if (s->cpu_hotplug_legacy && value == false) { 617 acpi_switch_to_modern_cphp(&s->gpe_cpu, &s->cpuhp_state, 618 PIIX4_CPU_HOTPLUG_IO_BASE); 619 } 620 s->cpu_hotplug_legacy = value; 621 } 622 623 static void piix4_acpi_system_hot_add_init(MemoryRegion *parent, 624 PCIBus *bus, PIIX4PMState *s) 625 { 626 memory_region_init_io(&s->io_gpe, OBJECT(s), &piix4_gpe_ops, s, 627 "acpi-gpe0", GPE_LEN); 628 memory_region_add_subregion(parent, GPE_BASE, &s->io_gpe); 629 630 acpi_pcihp_init(OBJECT(s), &s->acpi_pci_hotplug, bus, parent, 631 s->use_acpi_pci_hotplug); 632 633 s->cpu_hotplug_legacy = true; 634 object_property_add_bool(OBJECT(s), "cpu-hotplug-legacy", 635 piix4_get_cpu_hotplug_legacy, 636 piix4_set_cpu_hotplug_legacy, 637 NULL); 638 legacy_acpi_cpu_hotplug_init(parent, OBJECT(s), &s->gpe_cpu, 639 PIIX4_CPU_HOTPLUG_IO_BASE); 640 641 if (s->acpi_memory_hotplug.is_enabled) { 642 acpi_memory_hotplug_init(parent, OBJECT(s), &s->acpi_memory_hotplug); 643 } 644 } 645 646 static void piix4_ospm_status(AcpiDeviceIf *adev, ACPIOSTInfoList ***list) 647 { 648 PIIX4PMState *s = PIIX4_PM(adev); 649 650 acpi_memory_ospm_status(&s->acpi_memory_hotplug, list); 651 if (!s->cpu_hotplug_legacy) { 652 acpi_cpu_ospm_status(&s->cpuhp_state, list); 653 } 654 } 655 656 static void piix4_send_gpe(AcpiDeviceIf *adev, AcpiEventStatusBits ev) 657 { 658 PIIX4PMState *s = PIIX4_PM(adev); 659 660 acpi_send_gpe_event(&s->ar, s->irq, ev); 661 } 662 663 static Property piix4_pm_properties[] = { 664 DEFINE_PROP_UINT32("smb_io_base", PIIX4PMState, smb_io_base, 0), 665 DEFINE_PROP_UINT8(ACPI_PM_PROP_S3_DISABLED, PIIX4PMState, disable_s3, 0), 666 DEFINE_PROP_UINT8(ACPI_PM_PROP_S4_DISABLED, PIIX4PMState, disable_s4, 0), 667 DEFINE_PROP_UINT8(ACPI_PM_PROP_S4_VAL, PIIX4PMState, s4_val, 2), 668 DEFINE_PROP_BOOL("acpi-pci-hotplug-with-bridge-support", PIIX4PMState, 669 use_acpi_pci_hotplug, true), 670 DEFINE_PROP_BOOL("memory-hotplug-support", PIIX4PMState, 671 acpi_memory_hotplug.is_enabled, true), 672 DEFINE_PROP_END_OF_LIST(), 673 }; 674 675 static void piix4_pm_class_init(ObjectClass *klass, void *data) 676 { 677 DeviceClass *dc = DEVICE_CLASS(klass); 678 PCIDeviceClass *k = PCI_DEVICE_CLASS(klass); 679 HotplugHandlerClass *hc = HOTPLUG_HANDLER_CLASS(klass); 680 AcpiDeviceIfClass *adevc = ACPI_DEVICE_IF_CLASS(klass); 681 682 k->realize = piix4_pm_realize; 683 k->config_write = pm_write_config; 684 k->vendor_id = PCI_VENDOR_ID_INTEL; 685 k->device_id = PCI_DEVICE_ID_INTEL_82371AB_3; 686 k->revision = 0x03; 687 k->class_id = PCI_CLASS_BRIDGE_OTHER; 688 dc->desc = "PM"; 689 dc->vmsd = &vmstate_acpi; 690 dc->props = piix4_pm_properties; 691 /* 692 * Reason: part of PIIX4 southbridge, needs to be wired up, 693 * e.g. by mips_malta_init() 694 */ 695 dc->cannot_instantiate_with_device_add_yet = true; 696 dc->hotpluggable = false; 697 hc->plug = piix4_device_plug_cb; 698 hc->unplug_request = piix4_device_unplug_request_cb; 699 hc->unplug = piix4_device_unplug_cb; 700 adevc->ospm_status = piix4_ospm_status; 701 adevc->send_event = piix4_send_gpe; 702 adevc->madt_cpu = pc_madt_cpu_entry; 703 } 704 705 static const TypeInfo piix4_pm_info = { 706 .name = TYPE_PIIX4_PM, 707 .parent = TYPE_PCI_DEVICE, 708 .instance_size = sizeof(PIIX4PMState), 709 .class_init = piix4_pm_class_init, 710 .interfaces = (InterfaceInfo[]) { 711 { TYPE_HOTPLUG_HANDLER }, 712 { TYPE_ACPI_DEVICE_IF }, 713 { } 714 } 715 }; 716 717 static void piix4_pm_register_types(void) 718 { 719 type_register_static(&piix4_pm_info); 720 } 721 722 type_init(piix4_pm_register_types) 723