153018216SPaolo Bonzini /* 253018216SPaolo Bonzini * QEMU Alpha PCI support functions. 353018216SPaolo Bonzini * 453018216SPaolo Bonzini * Some of this isn't very Alpha specific at all. 553018216SPaolo Bonzini * 653018216SPaolo Bonzini * ??? Sparse memory access not implemented. 753018216SPaolo Bonzini */ 853018216SPaolo Bonzini 953018216SPaolo Bonzini #include "config.h" 10*47b43a1fSPaolo Bonzini #include "alpha_sys.h" 1153018216SPaolo Bonzini #include "qemu/log.h" 1253018216SPaolo Bonzini #include "sysemu/sysemu.h" 1353018216SPaolo Bonzini 1453018216SPaolo Bonzini 1553018216SPaolo Bonzini /* PCI IO reads/writes, to byte-word addressable memory. */ 1653018216SPaolo Bonzini /* ??? Doesn't handle multiple PCI busses. */ 1753018216SPaolo Bonzini 1853018216SPaolo Bonzini static uint64_t bw_io_read(void *opaque, hwaddr addr, unsigned size) 1953018216SPaolo Bonzini { 2053018216SPaolo Bonzini switch (size) { 2153018216SPaolo Bonzini case 1: 2253018216SPaolo Bonzini return cpu_inb(addr); 2353018216SPaolo Bonzini case 2: 2453018216SPaolo Bonzini return cpu_inw(addr); 2553018216SPaolo Bonzini case 4: 2653018216SPaolo Bonzini return cpu_inl(addr); 2753018216SPaolo Bonzini } 2853018216SPaolo Bonzini abort(); 2953018216SPaolo Bonzini } 3053018216SPaolo Bonzini 3153018216SPaolo Bonzini static void bw_io_write(void *opaque, hwaddr addr, 3253018216SPaolo Bonzini uint64_t val, unsigned size) 3353018216SPaolo Bonzini { 3453018216SPaolo Bonzini switch (size) { 3553018216SPaolo Bonzini case 1: 3653018216SPaolo Bonzini cpu_outb(addr, val); 3753018216SPaolo Bonzini break; 3853018216SPaolo Bonzini case 2: 3953018216SPaolo Bonzini cpu_outw(addr, val); 4053018216SPaolo Bonzini break; 4153018216SPaolo Bonzini case 4: 4253018216SPaolo Bonzini cpu_outl(addr, val); 4353018216SPaolo Bonzini break; 4453018216SPaolo Bonzini default: 4553018216SPaolo Bonzini abort(); 4653018216SPaolo Bonzini } 4753018216SPaolo Bonzini } 4853018216SPaolo Bonzini 4953018216SPaolo Bonzini const MemoryRegionOps alpha_pci_bw_io_ops = { 5053018216SPaolo Bonzini .read = bw_io_read, 5153018216SPaolo Bonzini .write = bw_io_write, 5253018216SPaolo Bonzini .endianness = DEVICE_LITTLE_ENDIAN, 5353018216SPaolo Bonzini .impl = { 5453018216SPaolo Bonzini .min_access_size = 1, 5553018216SPaolo Bonzini .max_access_size = 4, 5653018216SPaolo Bonzini }, 5753018216SPaolo Bonzini }; 5853018216SPaolo Bonzini 5953018216SPaolo Bonzini /* PCI config space reads/writes, to byte-word addressable memory. */ 6053018216SPaolo Bonzini static uint64_t bw_conf1_read(void *opaque, hwaddr addr, 6153018216SPaolo Bonzini unsigned size) 6253018216SPaolo Bonzini { 6353018216SPaolo Bonzini PCIBus *b = opaque; 6453018216SPaolo Bonzini return pci_data_read(b, addr, size); 6553018216SPaolo Bonzini } 6653018216SPaolo Bonzini 6753018216SPaolo Bonzini static void bw_conf1_write(void *opaque, hwaddr addr, 6853018216SPaolo Bonzini uint64_t val, unsigned size) 6953018216SPaolo Bonzini { 7053018216SPaolo Bonzini PCIBus *b = opaque; 7153018216SPaolo Bonzini pci_data_write(b, addr, val, size); 7253018216SPaolo Bonzini } 7353018216SPaolo Bonzini 7453018216SPaolo Bonzini const MemoryRegionOps alpha_pci_conf1_ops = { 7553018216SPaolo Bonzini .read = bw_conf1_read, 7653018216SPaolo Bonzini .write = bw_conf1_write, 7753018216SPaolo Bonzini .endianness = DEVICE_LITTLE_ENDIAN, 7853018216SPaolo Bonzini .impl = { 7953018216SPaolo Bonzini .min_access_size = 1, 8053018216SPaolo Bonzini .max_access_size = 4, 8153018216SPaolo Bonzini }, 8253018216SPaolo Bonzini }; 8353018216SPaolo Bonzini 8453018216SPaolo Bonzini /* PCI/EISA Interrupt Acknowledge Cycle. */ 8553018216SPaolo Bonzini 8653018216SPaolo Bonzini static uint64_t iack_read(void *opaque, hwaddr addr, unsigned size) 8753018216SPaolo Bonzini { 8853018216SPaolo Bonzini return pic_read_irq(isa_pic); 8953018216SPaolo Bonzini } 9053018216SPaolo Bonzini 9153018216SPaolo Bonzini static void special_write(void *opaque, hwaddr addr, 9253018216SPaolo Bonzini uint64_t val, unsigned size) 9353018216SPaolo Bonzini { 9453018216SPaolo Bonzini qemu_log("pci: special write cycle"); 9553018216SPaolo Bonzini } 9653018216SPaolo Bonzini 9753018216SPaolo Bonzini const MemoryRegionOps alpha_pci_iack_ops = { 9853018216SPaolo Bonzini .read = iack_read, 9953018216SPaolo Bonzini .write = special_write, 10053018216SPaolo Bonzini .endianness = DEVICE_LITTLE_ENDIAN, 10153018216SPaolo Bonzini .valid = { 10253018216SPaolo Bonzini .min_access_size = 4, 10353018216SPaolo Bonzini .max_access_size = 4, 10453018216SPaolo Bonzini }, 10553018216SPaolo Bonzini .impl = { 10653018216SPaolo Bonzini .min_access_size = 4, 10753018216SPaolo Bonzini .max_access_size = 4, 10853018216SPaolo Bonzini }, 10953018216SPaolo Bonzini }; 110