153018216SPaolo Bonzini /* 253018216SPaolo Bonzini * QEMU Alpha PCI support functions. 353018216SPaolo Bonzini * 453018216SPaolo Bonzini * Some of this isn't very Alpha specific at all. 553018216SPaolo Bonzini * 653018216SPaolo Bonzini * ??? Sparse memory access not implemented. 753018216SPaolo Bonzini */ 853018216SPaolo Bonzini 9*e2e5e114SPeter Maydell #include "qemu/osdep.h" 1047b43a1fSPaolo Bonzini #include "alpha_sys.h" 1153018216SPaolo Bonzini #include "qemu/log.h" 1253018216SPaolo Bonzini #include "sysemu/sysemu.h" 13c6ce9f17SPaolo Bonzini #include "trace.h" 1453018216SPaolo Bonzini 1553018216SPaolo Bonzini 163661049fSRichard Henderson /* Fallback for unassigned PCI I/O operations. Avoids MCHK. */ 173661049fSRichard Henderson 183661049fSRichard Henderson static uint64_t ignore_read(void *opaque, hwaddr addr, unsigned size) 193661049fSRichard Henderson { 203661049fSRichard Henderson return 0; 213661049fSRichard Henderson } 223661049fSRichard Henderson 233661049fSRichard Henderson static void ignore_write(void *opaque, hwaddr addr, uint64_t v, unsigned size) 243661049fSRichard Henderson { 253661049fSRichard Henderson } 263661049fSRichard Henderson 273661049fSRichard Henderson const MemoryRegionOps alpha_pci_ignore_ops = { 283661049fSRichard Henderson .read = ignore_read, 293661049fSRichard Henderson .write = ignore_write, 303661049fSRichard Henderson .endianness = DEVICE_LITTLE_ENDIAN, 313661049fSRichard Henderson .valid = { 323661049fSRichard Henderson .min_access_size = 1, 333661049fSRichard Henderson .max_access_size = 8, 343661049fSRichard Henderson }, 353661049fSRichard Henderson .impl = { 363661049fSRichard Henderson .min_access_size = 1, 373661049fSRichard Henderson .max_access_size = 8, 383661049fSRichard Henderson }, 393661049fSRichard Henderson }; 403661049fSRichard Henderson 413661049fSRichard Henderson 4253018216SPaolo Bonzini /* PCI config space reads/writes, to byte-word addressable memory. */ 4353018216SPaolo Bonzini static uint64_t bw_conf1_read(void *opaque, hwaddr addr, 4453018216SPaolo Bonzini unsigned size) 4553018216SPaolo Bonzini { 4653018216SPaolo Bonzini PCIBus *b = opaque; 4753018216SPaolo Bonzini return pci_data_read(b, addr, size); 4853018216SPaolo Bonzini } 4953018216SPaolo Bonzini 5053018216SPaolo Bonzini static void bw_conf1_write(void *opaque, hwaddr addr, 5153018216SPaolo Bonzini uint64_t val, unsigned size) 5253018216SPaolo Bonzini { 5353018216SPaolo Bonzini PCIBus *b = opaque; 5453018216SPaolo Bonzini pci_data_write(b, addr, val, size); 5553018216SPaolo Bonzini } 5653018216SPaolo Bonzini 5753018216SPaolo Bonzini const MemoryRegionOps alpha_pci_conf1_ops = { 5853018216SPaolo Bonzini .read = bw_conf1_read, 5953018216SPaolo Bonzini .write = bw_conf1_write, 6053018216SPaolo Bonzini .endianness = DEVICE_LITTLE_ENDIAN, 6153018216SPaolo Bonzini .impl = { 6253018216SPaolo Bonzini .min_access_size = 1, 6353018216SPaolo Bonzini .max_access_size = 4, 6453018216SPaolo Bonzini }, 6553018216SPaolo Bonzini }; 6653018216SPaolo Bonzini 6753018216SPaolo Bonzini /* PCI/EISA Interrupt Acknowledge Cycle. */ 6853018216SPaolo Bonzini 6953018216SPaolo Bonzini static uint64_t iack_read(void *opaque, hwaddr addr, unsigned size) 7053018216SPaolo Bonzini { 7153018216SPaolo Bonzini return pic_read_irq(isa_pic); 7253018216SPaolo Bonzini } 7353018216SPaolo Bonzini 7453018216SPaolo Bonzini static void special_write(void *opaque, hwaddr addr, 7553018216SPaolo Bonzini uint64_t val, unsigned size) 7653018216SPaolo Bonzini { 77c6ce9f17SPaolo Bonzini trace_alpha_pci_iack_write(); 7853018216SPaolo Bonzini } 7953018216SPaolo Bonzini 8053018216SPaolo Bonzini const MemoryRegionOps alpha_pci_iack_ops = { 8153018216SPaolo Bonzini .read = iack_read, 8253018216SPaolo Bonzini .write = special_write, 8353018216SPaolo Bonzini .endianness = DEVICE_LITTLE_ENDIAN, 8453018216SPaolo Bonzini .valid = { 8553018216SPaolo Bonzini .min_access_size = 4, 8653018216SPaolo Bonzini .max_access_size = 4, 8753018216SPaolo Bonzini }, 8853018216SPaolo Bonzini .impl = { 8953018216SPaolo Bonzini .min_access_size = 4, 9053018216SPaolo Bonzini .max_access_size = 4, 9153018216SPaolo Bonzini }, 9253018216SPaolo Bonzini }; 93