1 /* 2 * OpenPOWER Palmetto BMC 3 * 4 * Andrew Jeffery <andrew@aj.id.au> 5 * 6 * Copyright 2016 IBM Corp. 7 * 8 * This code is licensed under the GPL version 2 or later. See 9 * the COPYING file in the top-level directory. 10 */ 11 12 #include "qemu/osdep.h" 13 #include "qapi/error.h" 14 #include "hw/arm/boot.h" 15 #include "hw/arm/aspeed.h" 16 #include "hw/arm/aspeed_soc.h" 17 #include "hw/arm/aspeed_eeprom.h" 18 #include "hw/block/flash.h" 19 #include "hw/i2c/i2c_mux_pca954x.h" 20 #include "hw/i2c/smbus_eeprom.h" 21 #include "hw/misc/pca9552.h" 22 #include "hw/nvram/eeprom_at24c.h" 23 #include "hw/sensor/tmp105.h" 24 #include "hw/misc/led.h" 25 #include "hw/qdev-properties.h" 26 #include "sysemu/block-backend.h" 27 #include "sysemu/reset.h" 28 #include "hw/loader.h" 29 #include "qemu/error-report.h" 30 #include "qemu/units.h" 31 #include "hw/qdev-clock.h" 32 #include "sysemu/sysemu.h" 33 34 static struct arm_boot_info aspeed_board_binfo = { 35 .board_id = -1, /* device-tree-only board */ 36 }; 37 38 struct AspeedMachineState { 39 /* Private */ 40 MachineState parent_obj; 41 /* Public */ 42 43 AspeedSoCState *soc; 44 MemoryRegion boot_rom; 45 bool mmio_exec; 46 uint32_t uart_chosen; 47 char *fmc_model; 48 char *spi_model; 49 }; 50 51 /* On 32-bit hosts, lower RAM to 1G because of the 2047 MB limit */ 52 #if HOST_LONG_BITS == 32 53 #define ASPEED_RAM_SIZE(sz) MIN((sz), 1 * GiB) 54 #else 55 #define ASPEED_RAM_SIZE(sz) (sz) 56 #endif 57 58 /* Palmetto hardware value: 0x120CE416 */ 59 #define PALMETTO_BMC_HW_STRAP1 ( \ 60 SCU_AST2400_HW_STRAP_DRAM_SIZE(DRAM_SIZE_256MB) | \ 61 SCU_AST2400_HW_STRAP_DRAM_CONFIG(2 /* DDR3 with CL=6, CWL=5 */) | \ 62 SCU_AST2400_HW_STRAP_ACPI_DIS | \ 63 SCU_AST2400_HW_STRAP_SET_CLK_SOURCE(AST2400_CLK_48M_IN) | \ 64 SCU_HW_STRAP_VGA_CLASS_CODE | \ 65 SCU_HW_STRAP_LPC_RESET_PIN | \ 66 SCU_HW_STRAP_SPI_MODE(SCU_HW_STRAP_SPI_M_S_EN) | \ 67 SCU_AST2400_HW_STRAP_SET_CPU_AHB_RATIO(AST2400_CPU_AHB_RATIO_2_1) | \ 68 SCU_HW_STRAP_SPI_WIDTH | \ 69 SCU_HW_STRAP_VGA_SIZE_SET(VGA_16M_DRAM) | \ 70 SCU_AST2400_HW_STRAP_BOOT_MODE(AST2400_SPI_BOOT)) 71 72 /* TODO: Find the actual hardware value */ 73 #define SUPERMICROX11_BMC_HW_STRAP1 ( \ 74 SCU_AST2400_HW_STRAP_DRAM_SIZE(DRAM_SIZE_128MB) | \ 75 SCU_AST2400_HW_STRAP_DRAM_CONFIG(2) | \ 76 SCU_AST2400_HW_STRAP_ACPI_DIS | \ 77 SCU_AST2400_HW_STRAP_SET_CLK_SOURCE(AST2400_CLK_48M_IN) | \ 78 SCU_HW_STRAP_VGA_CLASS_CODE | \ 79 SCU_HW_STRAP_LPC_RESET_PIN | \ 80 SCU_HW_STRAP_SPI_MODE(SCU_HW_STRAP_SPI_M_S_EN) | \ 81 SCU_AST2400_HW_STRAP_SET_CPU_AHB_RATIO(AST2400_CPU_AHB_RATIO_2_1) | \ 82 SCU_HW_STRAP_SPI_WIDTH | \ 83 SCU_HW_STRAP_VGA_SIZE_SET(VGA_16M_DRAM) | \ 84 SCU_AST2400_HW_STRAP_BOOT_MODE(AST2400_SPI_BOOT)) 85 86 /* TODO: Find the actual hardware value */ 87 #define SUPERMICRO_X11SPI_BMC_HW_STRAP1 ( \ 88 AST2500_HW_STRAP1_DEFAULTS | \ 89 SCU_AST2500_HW_STRAP_SPI_AUTOFETCH_ENABLE | \ 90 SCU_AST2500_HW_STRAP_GPIO_STRAP_ENABLE | \ 91 SCU_AST2500_HW_STRAP_UART_DEBUG | \ 92 SCU_AST2500_HW_STRAP_DDR4_ENABLE | \ 93 SCU_HW_STRAP_SPI_WIDTH | \ 94 SCU_HW_STRAP_SPI_MODE(SCU_HW_STRAP_SPI_M_S_EN)) 95 96 /* AST2500 evb hardware value: 0xF100C2E6 */ 97 #define AST2500_EVB_HW_STRAP1 (( \ 98 AST2500_HW_STRAP1_DEFAULTS | \ 99 SCU_AST2500_HW_STRAP_SPI_AUTOFETCH_ENABLE | \ 100 SCU_AST2500_HW_STRAP_GPIO_STRAP_ENABLE | \ 101 SCU_AST2500_HW_STRAP_UART_DEBUG | \ 102 SCU_AST2500_HW_STRAP_DDR4_ENABLE | \ 103 SCU_HW_STRAP_MAC1_RGMII | \ 104 SCU_HW_STRAP_MAC0_RGMII) & \ 105 ~SCU_HW_STRAP_2ND_BOOT_WDT) 106 107 /* Romulus hardware value: 0xF10AD206 */ 108 #define ROMULUS_BMC_HW_STRAP1 ( \ 109 AST2500_HW_STRAP1_DEFAULTS | \ 110 SCU_AST2500_HW_STRAP_SPI_AUTOFETCH_ENABLE | \ 111 SCU_AST2500_HW_STRAP_GPIO_STRAP_ENABLE | \ 112 SCU_AST2500_HW_STRAP_UART_DEBUG | \ 113 SCU_AST2500_HW_STRAP_DDR4_ENABLE | \ 114 SCU_AST2500_HW_STRAP_ACPI_ENABLE | \ 115 SCU_HW_STRAP_SPI_MODE(SCU_HW_STRAP_SPI_MASTER)) 116 117 /* Sonorapass hardware value: 0xF100D216 */ 118 #define SONORAPASS_BMC_HW_STRAP1 ( \ 119 SCU_AST2500_HW_STRAP_SPI_AUTOFETCH_ENABLE | \ 120 SCU_AST2500_HW_STRAP_GPIO_STRAP_ENABLE | \ 121 SCU_AST2500_HW_STRAP_UART_DEBUG | \ 122 SCU_AST2500_HW_STRAP_RESERVED28 | \ 123 SCU_AST2500_HW_STRAP_DDR4_ENABLE | \ 124 SCU_HW_STRAP_VGA_CLASS_CODE | \ 125 SCU_HW_STRAP_LPC_RESET_PIN | \ 126 SCU_HW_STRAP_SPI_MODE(SCU_HW_STRAP_SPI_MASTER) | \ 127 SCU_AST2500_HW_STRAP_SET_AXI_AHB_RATIO(AXI_AHB_RATIO_2_1) | \ 128 SCU_HW_STRAP_VGA_BIOS_ROM | \ 129 SCU_HW_STRAP_VGA_SIZE_SET(VGA_16M_DRAM) | \ 130 SCU_AST2500_HW_STRAP_RESERVED1) 131 132 #define G220A_BMC_HW_STRAP1 ( \ 133 SCU_AST2500_HW_STRAP_SPI_AUTOFETCH_ENABLE | \ 134 SCU_AST2500_HW_STRAP_GPIO_STRAP_ENABLE | \ 135 SCU_AST2500_HW_STRAP_UART_DEBUG | \ 136 SCU_AST2500_HW_STRAP_RESERVED28 | \ 137 SCU_AST2500_HW_STRAP_DDR4_ENABLE | \ 138 SCU_HW_STRAP_2ND_BOOT_WDT | \ 139 SCU_HW_STRAP_VGA_CLASS_CODE | \ 140 SCU_HW_STRAP_LPC_RESET_PIN | \ 141 SCU_HW_STRAP_SPI_MODE(SCU_HW_STRAP_SPI_MASTER) | \ 142 SCU_AST2500_HW_STRAP_SET_AXI_AHB_RATIO(AXI_AHB_RATIO_2_1) | \ 143 SCU_HW_STRAP_VGA_SIZE_SET(VGA_64M_DRAM) | \ 144 SCU_AST2500_HW_STRAP_RESERVED1) 145 146 /* FP5280G2 hardware value: 0XF100D286 */ 147 #define FP5280G2_BMC_HW_STRAP1 ( \ 148 SCU_AST2500_HW_STRAP_SPI_AUTOFETCH_ENABLE | \ 149 SCU_AST2500_HW_STRAP_GPIO_STRAP_ENABLE | \ 150 SCU_AST2500_HW_STRAP_UART_DEBUG | \ 151 SCU_AST2500_HW_STRAP_RESERVED28 | \ 152 SCU_AST2500_HW_STRAP_DDR4_ENABLE | \ 153 SCU_HW_STRAP_VGA_CLASS_CODE | \ 154 SCU_HW_STRAP_LPC_RESET_PIN | \ 155 SCU_HW_STRAP_SPI_MODE(SCU_HW_STRAP_SPI_MASTER) | \ 156 SCU_AST2500_HW_STRAP_SET_AXI_AHB_RATIO(AXI_AHB_RATIO_2_1) | \ 157 SCU_HW_STRAP_MAC1_RGMII | \ 158 SCU_HW_STRAP_VGA_SIZE_SET(VGA_16M_DRAM) | \ 159 SCU_AST2500_HW_STRAP_RESERVED1) 160 161 /* Witherspoon hardware value: 0xF10AD216 (but use romulus definition) */ 162 #define WITHERSPOON_BMC_HW_STRAP1 ROMULUS_BMC_HW_STRAP1 163 164 /* Quanta-Q71l hardware value */ 165 #define QUANTA_Q71L_BMC_HW_STRAP1 ( \ 166 SCU_AST2400_HW_STRAP_DRAM_SIZE(DRAM_SIZE_128MB) | \ 167 SCU_AST2400_HW_STRAP_DRAM_CONFIG(2/* DDR3 with CL=6, CWL=5 */) | \ 168 SCU_AST2400_HW_STRAP_ACPI_DIS | \ 169 SCU_AST2400_HW_STRAP_SET_CLK_SOURCE(AST2400_CLK_24M_IN) | \ 170 SCU_HW_STRAP_VGA_CLASS_CODE | \ 171 SCU_HW_STRAP_SPI_MODE(SCU_HW_STRAP_SPI_PASS_THROUGH) | \ 172 SCU_AST2400_HW_STRAP_SET_CPU_AHB_RATIO(AST2400_CPU_AHB_RATIO_2_1) | \ 173 SCU_HW_STRAP_SPI_WIDTH | \ 174 SCU_HW_STRAP_VGA_SIZE_SET(VGA_8M_DRAM) | \ 175 SCU_AST2400_HW_STRAP_BOOT_MODE(AST2400_SPI_BOOT)) 176 177 /* AST2600 evb hardware value */ 178 #define AST2600_EVB_HW_STRAP1 0x000000C0 179 #define AST2600_EVB_HW_STRAP2 0x00000003 180 181 /* Tacoma hardware value */ 182 #define TACOMA_BMC_HW_STRAP1 0x00000000 183 #define TACOMA_BMC_HW_STRAP2 0x00000040 184 185 /* Rainier hardware value: (QEMU prototype) */ 186 #define RAINIER_BMC_HW_STRAP1 0x00422016 187 #define RAINIER_BMC_HW_STRAP2 0x80000848 188 189 /* Fuji hardware value */ 190 #define FUJI_BMC_HW_STRAP1 0x00000000 191 #define FUJI_BMC_HW_STRAP2 0x00000000 192 193 /* Bletchley hardware value */ 194 /* TODO: Leave same as EVB for now. */ 195 #define BLETCHLEY_BMC_HW_STRAP1 AST2600_EVB_HW_STRAP1 196 #define BLETCHLEY_BMC_HW_STRAP2 AST2600_EVB_HW_STRAP2 197 198 /* Qualcomm DC-SCM hardware value */ 199 #define QCOM_DC_SCM_V1_BMC_HW_STRAP1 0x00000000 200 #define QCOM_DC_SCM_V1_BMC_HW_STRAP2 0x00000041 201 202 #define AST_SMP_MAILBOX_BASE 0x1e6e2180 203 #define AST_SMP_MBOX_FIELD_ENTRY (AST_SMP_MAILBOX_BASE + 0x0) 204 #define AST_SMP_MBOX_FIELD_GOSIGN (AST_SMP_MAILBOX_BASE + 0x4) 205 #define AST_SMP_MBOX_FIELD_READY (AST_SMP_MAILBOX_BASE + 0x8) 206 #define AST_SMP_MBOX_FIELD_POLLINSN (AST_SMP_MAILBOX_BASE + 0xc) 207 #define AST_SMP_MBOX_CODE (AST_SMP_MAILBOX_BASE + 0x10) 208 #define AST_SMP_MBOX_GOSIGN 0xabbaab00 209 210 static void aspeed_write_smpboot(ARMCPU *cpu, 211 const struct arm_boot_info *info) 212 { 213 AddressSpace *as = arm_boot_address_space(cpu, info); 214 static const ARMInsnFixup poll_mailbox_ready[] = { 215 /* 216 * r2 = per-cpu go sign value 217 * r1 = AST_SMP_MBOX_FIELD_ENTRY 218 * r0 = AST_SMP_MBOX_FIELD_GOSIGN 219 */ 220 { 0xee100fb0 }, /* mrc p15, 0, r0, c0, c0, 5 */ 221 { 0xe21000ff }, /* ands r0, r0, #255 */ 222 { 0xe59f201c }, /* ldr r2, [pc, #28] */ 223 { 0xe1822000 }, /* orr r2, r2, r0 */ 224 225 { 0xe59f1018 }, /* ldr r1, [pc, #24] */ 226 { 0xe59f0018 }, /* ldr r0, [pc, #24] */ 227 228 { 0xe320f002 }, /* wfe */ 229 { 0xe5904000 }, /* ldr r4, [r0] */ 230 { 0xe1520004 }, /* cmp r2, r4 */ 231 { 0x1afffffb }, /* bne <wfe> */ 232 { 0xe591f000 }, /* ldr pc, [r1] */ 233 { AST_SMP_MBOX_GOSIGN }, 234 { AST_SMP_MBOX_FIELD_ENTRY }, 235 { AST_SMP_MBOX_FIELD_GOSIGN }, 236 { 0, FIXUP_TERMINATOR } 237 }; 238 static const uint32_t fixupcontext[FIXUP_MAX] = { 0 }; 239 240 arm_write_bootloader("aspeed.smpboot", as, info->smp_loader_start, 241 poll_mailbox_ready, fixupcontext); 242 } 243 244 static void aspeed_reset_secondary(ARMCPU *cpu, 245 const struct arm_boot_info *info) 246 { 247 AddressSpace *as = arm_boot_address_space(cpu, info); 248 CPUState *cs = CPU(cpu); 249 250 /* info->smp_bootreg_addr */ 251 address_space_stl_notdirty(as, AST_SMP_MBOX_FIELD_GOSIGN, 0, 252 MEMTXATTRS_UNSPECIFIED, NULL); 253 cpu_set_pc(cs, info->smp_loader_start); 254 } 255 256 static void write_boot_rom(BlockBackend *blk, hwaddr addr, size_t rom_size, 257 Error **errp) 258 { 259 g_autofree void *storage = NULL; 260 int64_t size; 261 262 /* The block backend size should have already been 'validated' by 263 * the creation of the m25p80 object. 264 */ 265 size = blk_getlength(blk); 266 if (size <= 0) { 267 error_setg(errp, "failed to get flash size"); 268 return; 269 } 270 271 if (rom_size > size) { 272 rom_size = size; 273 } 274 275 storage = g_malloc0(rom_size); 276 if (blk_pread(blk, 0, rom_size, storage, 0) < 0) { 277 error_setg(errp, "failed to read the initial flash content"); 278 return; 279 } 280 281 rom_add_blob_fixed("aspeed.boot_rom", storage, rom_size, addr); 282 } 283 284 /* 285 * Create a ROM and copy the flash contents at the expected address 286 * (0x0). Boots faster than execute-in-place. 287 */ 288 static void aspeed_install_boot_rom(AspeedMachineState *bmc, BlockBackend *blk, 289 uint64_t rom_size) 290 { 291 AspeedSoCState *soc = bmc->soc; 292 293 memory_region_init_rom(&bmc->boot_rom, NULL, "aspeed.boot_rom", rom_size, 294 &error_abort); 295 memory_region_add_subregion_overlap(&soc->spi_boot_container, 0, 296 &bmc->boot_rom, 1); 297 write_boot_rom(blk, ASPEED_SOC_SPI_BOOT_ADDR, rom_size, &error_abort); 298 } 299 300 void aspeed_board_init_flashes(AspeedSMCState *s, const char *flashtype, 301 unsigned int count, int unit0) 302 { 303 int i; 304 305 if (!flashtype) { 306 return; 307 } 308 309 for (i = 0; i < count; ++i) { 310 DriveInfo *dinfo = drive_get(IF_MTD, 0, unit0 + i); 311 DeviceState *dev; 312 313 dev = qdev_new(flashtype); 314 if (dinfo) { 315 qdev_prop_set_drive(dev, "drive", blk_by_legacy_dinfo(dinfo)); 316 } 317 qdev_prop_set_uint8(dev, "cs", i); 318 qdev_realize_and_unref(dev, BUS(s->spi), &error_fatal); 319 } 320 } 321 322 static void sdhci_attach_drive(SDHCIState *sdhci, DriveInfo *dinfo) 323 { 324 DeviceState *card; 325 326 if (!dinfo) { 327 return; 328 } 329 card = qdev_new(TYPE_SD_CARD); 330 qdev_prop_set_drive_err(card, "drive", blk_by_legacy_dinfo(dinfo), 331 &error_fatal); 332 qdev_realize_and_unref(card, 333 qdev_get_child_bus(DEVICE(sdhci), "sd-bus"), 334 &error_fatal); 335 } 336 337 static void connect_serial_hds_to_uarts(AspeedMachineState *bmc) 338 { 339 AspeedMachineClass *amc = ASPEED_MACHINE_GET_CLASS(bmc); 340 AspeedSoCState *s = bmc->soc; 341 AspeedSoCClass *sc = ASPEED_SOC_GET_CLASS(s); 342 int uart_chosen = bmc->uart_chosen ? bmc->uart_chosen : amc->uart_default; 343 344 aspeed_soc_uart_set_chr(s, uart_chosen, serial_hd(0)); 345 for (int i = 1, uart = ASPEED_DEV_UART1; i < sc->uarts_num; i++, uart++) { 346 if (uart == uart_chosen) { 347 continue; 348 } 349 aspeed_soc_uart_set_chr(s, uart, serial_hd(i)); 350 } 351 } 352 353 static void aspeed_machine_init(MachineState *machine) 354 { 355 AspeedMachineState *bmc = ASPEED_MACHINE(machine); 356 AspeedMachineClass *amc = ASPEED_MACHINE_GET_CLASS(machine); 357 AspeedSoCClass *sc; 358 int i; 359 NICInfo *nd = &nd_table[0]; 360 361 bmc->soc = ASPEED_SOC(object_new(amc->soc_name)); 362 object_property_add_child(OBJECT(machine), "soc", OBJECT(bmc->soc)); 363 object_unref(OBJECT(bmc->soc)); 364 sc = ASPEED_SOC_GET_CLASS(bmc->soc); 365 366 /* 367 * This will error out if the RAM size is not supported by the 368 * memory controller of the SoC. 369 */ 370 object_property_set_uint(OBJECT(bmc->soc), "ram-size", machine->ram_size, 371 &error_fatal); 372 373 for (i = 0; i < sc->macs_num; i++) { 374 if ((amc->macs_mask & (1 << i)) && nd->used) { 375 qemu_check_nic_model(nd, TYPE_FTGMAC100); 376 qdev_set_nic_properties(DEVICE(&bmc->soc->ftgmac100[i]), nd); 377 nd++; 378 } 379 } 380 381 object_property_set_int(OBJECT(bmc->soc), "hw-strap1", amc->hw_strap1, 382 &error_abort); 383 object_property_set_int(OBJECT(bmc->soc), "hw-strap2", amc->hw_strap2, 384 &error_abort); 385 object_property_set_link(OBJECT(bmc->soc), "memory", 386 OBJECT(get_system_memory()), &error_abort); 387 object_property_set_link(OBJECT(bmc->soc), "dram", 388 OBJECT(machine->ram), &error_abort); 389 if (machine->kernel_filename) { 390 /* 391 * When booting with a -kernel command line there is no u-boot 392 * that runs to unlock the SCU. In this case set the default to 393 * be unlocked as the kernel expects 394 */ 395 object_property_set_int(OBJECT(bmc->soc), "hw-prot-key", 396 ASPEED_SCU_PROT_KEY, &error_abort); 397 } 398 connect_serial_hds_to_uarts(bmc); 399 qdev_realize(DEVICE(bmc->soc), NULL, &error_abort); 400 401 if (defaults_enabled()) { 402 aspeed_board_init_flashes(&bmc->soc->fmc, 403 bmc->fmc_model ? bmc->fmc_model : amc->fmc_model, 404 amc->num_cs, 0); 405 aspeed_board_init_flashes(&bmc->soc->spi[0], 406 bmc->spi_model ? bmc->spi_model : amc->spi_model, 407 1, amc->num_cs); 408 } 409 410 if (machine->kernel_filename && sc->num_cpus > 1) { 411 /* With no u-boot we must set up a boot stub for the secondary CPU */ 412 MemoryRegion *smpboot = g_new(MemoryRegion, 1); 413 memory_region_init_ram(smpboot, NULL, "aspeed.smpboot", 414 0x80, &error_abort); 415 memory_region_add_subregion(get_system_memory(), 416 AST_SMP_MAILBOX_BASE, smpboot); 417 418 aspeed_board_binfo.write_secondary_boot = aspeed_write_smpboot; 419 aspeed_board_binfo.secondary_cpu_reset_hook = aspeed_reset_secondary; 420 aspeed_board_binfo.smp_loader_start = AST_SMP_MBOX_CODE; 421 } 422 423 aspeed_board_binfo.ram_size = machine->ram_size; 424 aspeed_board_binfo.loader_start = sc->memmap[ASPEED_DEV_SDRAM]; 425 426 if (amc->i2c_init) { 427 amc->i2c_init(bmc); 428 } 429 430 for (i = 0; i < bmc->soc->sdhci.num_slots; i++) { 431 sdhci_attach_drive(&bmc->soc->sdhci.slots[i], 432 drive_get(IF_SD, 0, i)); 433 } 434 435 if (bmc->soc->emmc.num_slots) { 436 sdhci_attach_drive(&bmc->soc->emmc.slots[0], 437 drive_get(IF_SD, 0, bmc->soc->sdhci.num_slots)); 438 } 439 440 if (!bmc->mmio_exec) { 441 DeviceState *dev = ssi_get_cs(bmc->soc->fmc.spi, 0); 442 BlockBackend *fmc0 = dev ? m25p80_get_blk(dev) : NULL; 443 444 if (fmc0) { 445 uint64_t rom_size = memory_region_size(&bmc->soc->spi_boot); 446 aspeed_install_boot_rom(bmc, fmc0, rom_size); 447 } 448 } 449 450 arm_load_kernel(ARM_CPU(first_cpu), machine, &aspeed_board_binfo); 451 } 452 453 static void palmetto_bmc_i2c_init(AspeedMachineState *bmc) 454 { 455 AspeedSoCState *soc = bmc->soc; 456 DeviceState *dev; 457 uint8_t *eeprom_buf = g_malloc0(32 * 1024); 458 459 /* The palmetto platform expects a ds3231 RTC but a ds1338 is 460 * enough to provide basic RTC features. Alarms will be missing */ 461 i2c_slave_create_simple(aspeed_i2c_get_bus(&soc->i2c, 0), "ds1338", 0x68); 462 463 smbus_eeprom_init_one(aspeed_i2c_get_bus(&soc->i2c, 0), 0x50, 464 eeprom_buf); 465 466 /* add a TMP423 temperature sensor */ 467 dev = DEVICE(i2c_slave_create_simple(aspeed_i2c_get_bus(&soc->i2c, 2), 468 "tmp423", 0x4c)); 469 object_property_set_int(OBJECT(dev), "temperature0", 31000, &error_abort); 470 object_property_set_int(OBJECT(dev), "temperature1", 28000, &error_abort); 471 object_property_set_int(OBJECT(dev), "temperature2", 20000, &error_abort); 472 object_property_set_int(OBJECT(dev), "temperature3", 110000, &error_abort); 473 } 474 475 static void quanta_q71l_bmc_i2c_init(AspeedMachineState *bmc) 476 { 477 AspeedSoCState *soc = bmc->soc; 478 479 /* 480 * The quanta-q71l platform expects tmp75s which are compatible with 481 * tmp105s. 482 */ 483 i2c_slave_create_simple(aspeed_i2c_get_bus(&soc->i2c, 1), "tmp105", 0x4c); 484 i2c_slave_create_simple(aspeed_i2c_get_bus(&soc->i2c, 1), "tmp105", 0x4e); 485 i2c_slave_create_simple(aspeed_i2c_get_bus(&soc->i2c, 1), "tmp105", 0x4f); 486 487 /* TODO: i2c-1: Add baseboard FRU eeprom@54 24c64 */ 488 /* TODO: i2c-1: Add Frontpanel FRU eeprom@57 24c64 */ 489 /* TODO: Add Memory Riser i2c mux and eeproms. */ 490 491 i2c_slave_create_simple(aspeed_i2c_get_bus(&soc->i2c, 2), "pca9546", 0x74); 492 i2c_slave_create_simple(aspeed_i2c_get_bus(&soc->i2c, 2), "pca9548", 0x77); 493 494 /* TODO: i2c-3: Add BIOS FRU eeprom@56 24c64 */ 495 496 /* i2c-7 */ 497 i2c_slave_create_simple(aspeed_i2c_get_bus(&soc->i2c, 7), "pca9546", 0x70); 498 /* - i2c@0: pmbus@59 */ 499 /* - i2c@1: pmbus@58 */ 500 /* - i2c@2: pmbus@58 */ 501 /* - i2c@3: pmbus@59 */ 502 503 /* TODO: i2c-7: Add PDB FRU eeprom@52 */ 504 /* TODO: i2c-8: Add BMC FRU eeprom@50 */ 505 } 506 507 static void ast2500_evb_i2c_init(AspeedMachineState *bmc) 508 { 509 AspeedSoCState *soc = bmc->soc; 510 uint8_t *eeprom_buf = g_malloc0(8 * 1024); 511 512 smbus_eeprom_init_one(aspeed_i2c_get_bus(&soc->i2c, 3), 0x50, 513 eeprom_buf); 514 515 /* The AST2500 EVB expects a LM75 but a TMP105 is compatible */ 516 i2c_slave_create_simple(aspeed_i2c_get_bus(&soc->i2c, 7), 517 TYPE_TMP105, 0x4d); 518 } 519 520 static void ast2600_evb_i2c_init(AspeedMachineState *bmc) 521 { 522 AspeedSoCState *soc = bmc->soc; 523 uint8_t *eeprom_buf = g_malloc0(8 * 1024); 524 525 smbus_eeprom_init_one(aspeed_i2c_get_bus(&soc->i2c, 7), 0x50, 526 eeprom_buf); 527 528 /* LM75 is compatible with TMP105 driver */ 529 i2c_slave_create_simple(aspeed_i2c_get_bus(&soc->i2c, 8), 530 TYPE_TMP105, 0x4d); 531 } 532 533 static void yosemitev2_bmc_i2c_init(AspeedMachineState *bmc) 534 { 535 AspeedSoCState *soc = bmc->soc; 536 537 at24c_eeprom_init(aspeed_i2c_get_bus(&soc->i2c, 4), 0x51, 128 * KiB); 538 at24c_eeprom_init_rom(aspeed_i2c_get_bus(&soc->i2c, 8), 0x51, 128 * KiB, 539 yosemitev2_bmc_fruid, yosemitev2_bmc_fruid_len); 540 /* TMP421 */ 541 i2c_slave_create_simple(aspeed_i2c_get_bus(&soc->i2c, 11), "tmp421", 0x1f); 542 i2c_slave_create_simple(aspeed_i2c_get_bus(&soc->i2c, 9), "tmp421", 0x4e); 543 i2c_slave_create_simple(aspeed_i2c_get_bus(&soc->i2c, 9), "tmp421", 0x4f); 544 545 } 546 547 static void romulus_bmc_i2c_init(AspeedMachineState *bmc) 548 { 549 AspeedSoCState *soc = bmc->soc; 550 551 /* The romulus board expects Epson RX8900 I2C RTC but a ds1338 is 552 * good enough */ 553 i2c_slave_create_simple(aspeed_i2c_get_bus(&soc->i2c, 11), "ds1338", 0x32); 554 } 555 556 static void tiogapass_bmc_i2c_init(AspeedMachineState *bmc) 557 { 558 AspeedSoCState *soc = bmc->soc; 559 560 at24c_eeprom_init(aspeed_i2c_get_bus(&soc->i2c, 4), 0x54, 128 * KiB); 561 at24c_eeprom_init_rom(aspeed_i2c_get_bus(&soc->i2c, 6), 0x54, 128 * KiB, 562 tiogapass_bmc_fruid, tiogapass_bmc_fruid_len); 563 /* TMP421 */ 564 i2c_slave_create_simple(aspeed_i2c_get_bus(&soc->i2c, 8), "tmp421", 0x1f); 565 i2c_slave_create_simple(aspeed_i2c_get_bus(&soc->i2c, 6), "tmp421", 0x4f); 566 i2c_slave_create_simple(aspeed_i2c_get_bus(&soc->i2c, 6), "tmp421", 0x4e); 567 } 568 569 static void create_pca9552(AspeedSoCState *soc, int bus_id, int addr) 570 { 571 i2c_slave_create_simple(aspeed_i2c_get_bus(&soc->i2c, bus_id), 572 TYPE_PCA9552, addr); 573 } 574 575 static void sonorapass_bmc_i2c_init(AspeedMachineState *bmc) 576 { 577 AspeedSoCState *soc = bmc->soc; 578 579 /* bus 2 : */ 580 i2c_slave_create_simple(aspeed_i2c_get_bus(&soc->i2c, 2), "tmp105", 0x48); 581 i2c_slave_create_simple(aspeed_i2c_get_bus(&soc->i2c, 2), "tmp105", 0x49); 582 /* bus 2 : pca9546 @ 0x73 */ 583 584 /* bus 3 : pca9548 @ 0x70 */ 585 586 /* bus 4 : */ 587 uint8_t *eeprom4_54 = g_malloc0(8 * 1024); 588 smbus_eeprom_init_one(aspeed_i2c_get_bus(&soc->i2c, 4), 0x54, 589 eeprom4_54); 590 /* PCA9539 @ 0x76, but PCA9552 is compatible */ 591 create_pca9552(soc, 4, 0x76); 592 /* PCA9539 @ 0x77, but PCA9552 is compatible */ 593 create_pca9552(soc, 4, 0x77); 594 595 /* bus 6 : */ 596 i2c_slave_create_simple(aspeed_i2c_get_bus(&soc->i2c, 6), "tmp105", 0x48); 597 i2c_slave_create_simple(aspeed_i2c_get_bus(&soc->i2c, 6), "tmp105", 0x49); 598 /* bus 6 : pca9546 @ 0x73 */ 599 600 /* bus 8 : */ 601 uint8_t *eeprom8_56 = g_malloc0(8 * 1024); 602 smbus_eeprom_init_one(aspeed_i2c_get_bus(&soc->i2c, 8), 0x56, 603 eeprom8_56); 604 create_pca9552(soc, 8, 0x60); 605 create_pca9552(soc, 8, 0x61); 606 /* bus 8 : adc128d818 @ 0x1d */ 607 /* bus 8 : adc128d818 @ 0x1f */ 608 609 /* 610 * bus 13 : pca9548 @ 0x71 611 * - channel 3: 612 * - tmm421 @ 0x4c 613 * - tmp421 @ 0x4e 614 * - tmp421 @ 0x4f 615 */ 616 617 } 618 619 static void witherspoon_bmc_i2c_init(AspeedMachineState *bmc) 620 { 621 static const struct { 622 unsigned gpio_id; 623 LEDColor color; 624 const char *description; 625 bool gpio_polarity; 626 } pca1_leds[] = { 627 {13, LED_COLOR_GREEN, "front-fault-4", GPIO_POLARITY_ACTIVE_LOW}, 628 {14, LED_COLOR_GREEN, "front-power-3", GPIO_POLARITY_ACTIVE_LOW}, 629 {15, LED_COLOR_GREEN, "front-id-5", GPIO_POLARITY_ACTIVE_LOW}, 630 }; 631 AspeedSoCState *soc = bmc->soc; 632 uint8_t *eeprom_buf = g_malloc0(8 * 1024); 633 DeviceState *dev; 634 LEDState *led; 635 636 /* Bus 3: TODO bmp280@77 */ 637 dev = DEVICE(i2c_slave_new(TYPE_PCA9552, 0x60)); 638 qdev_prop_set_string(dev, "description", "pca1"); 639 i2c_slave_realize_and_unref(I2C_SLAVE(dev), 640 aspeed_i2c_get_bus(&soc->i2c, 3), 641 &error_fatal); 642 643 for (size_t i = 0; i < ARRAY_SIZE(pca1_leds); i++) { 644 led = led_create_simple(OBJECT(bmc), 645 pca1_leds[i].gpio_polarity, 646 pca1_leds[i].color, 647 pca1_leds[i].description); 648 qdev_connect_gpio_out(dev, pca1_leds[i].gpio_id, 649 qdev_get_gpio_in(DEVICE(led), 0)); 650 } 651 i2c_slave_create_simple(aspeed_i2c_get_bus(&soc->i2c, 3), "dps310", 0x76); 652 i2c_slave_create_simple(aspeed_i2c_get_bus(&soc->i2c, 3), "max31785", 0x52); 653 i2c_slave_create_simple(aspeed_i2c_get_bus(&soc->i2c, 4), "tmp423", 0x4c); 654 i2c_slave_create_simple(aspeed_i2c_get_bus(&soc->i2c, 5), "tmp423", 0x4c); 655 656 /* The Witherspoon expects a TMP275 but a TMP105 is compatible */ 657 i2c_slave_create_simple(aspeed_i2c_get_bus(&soc->i2c, 9), TYPE_TMP105, 658 0x4a); 659 660 /* The witherspoon board expects Epson RX8900 I2C RTC but a ds1338 is 661 * good enough */ 662 i2c_slave_create_simple(aspeed_i2c_get_bus(&soc->i2c, 11), "ds1338", 0x32); 663 664 smbus_eeprom_init_one(aspeed_i2c_get_bus(&soc->i2c, 11), 0x51, 665 eeprom_buf); 666 dev = DEVICE(i2c_slave_new(TYPE_PCA9552, 0x60)); 667 qdev_prop_set_string(dev, "description", "pca0"); 668 i2c_slave_realize_and_unref(I2C_SLAVE(dev), 669 aspeed_i2c_get_bus(&soc->i2c, 11), 670 &error_fatal); 671 /* Bus 11: TODO ucd90160@64 */ 672 } 673 674 static void g220a_bmc_i2c_init(AspeedMachineState *bmc) 675 { 676 AspeedSoCState *soc = bmc->soc; 677 DeviceState *dev; 678 679 dev = DEVICE(i2c_slave_create_simple(aspeed_i2c_get_bus(&soc->i2c, 3), 680 "emc1413", 0x4c)); 681 object_property_set_int(OBJECT(dev), "temperature0", 31000, &error_abort); 682 object_property_set_int(OBJECT(dev), "temperature1", 28000, &error_abort); 683 object_property_set_int(OBJECT(dev), "temperature2", 20000, &error_abort); 684 685 dev = DEVICE(i2c_slave_create_simple(aspeed_i2c_get_bus(&soc->i2c, 12), 686 "emc1413", 0x4c)); 687 object_property_set_int(OBJECT(dev), "temperature0", 31000, &error_abort); 688 object_property_set_int(OBJECT(dev), "temperature1", 28000, &error_abort); 689 object_property_set_int(OBJECT(dev), "temperature2", 20000, &error_abort); 690 691 dev = DEVICE(i2c_slave_create_simple(aspeed_i2c_get_bus(&soc->i2c, 13), 692 "emc1413", 0x4c)); 693 object_property_set_int(OBJECT(dev), "temperature0", 31000, &error_abort); 694 object_property_set_int(OBJECT(dev), "temperature1", 28000, &error_abort); 695 object_property_set_int(OBJECT(dev), "temperature2", 20000, &error_abort); 696 697 static uint8_t eeprom_buf[2 * 1024] = { 698 0x01, 0x00, 0x00, 0x00, 0x01, 0x00, 0x00, 0xfe, 699 0x01, 0x06, 0x00, 0xc9, 0x42, 0x79, 0x74, 0x65, 700 0x64, 0x61, 0x6e, 0x63, 0x65, 0xc5, 0x47, 0x32, 701 0x32, 0x30, 0x41, 0xc4, 0x41, 0x41, 0x42, 0x42, 702 0xc4, 0x43, 0x43, 0x44, 0x44, 0xc4, 0x45, 0x45, 703 0x46, 0x46, 0xc4, 0x48, 0x48, 0x47, 0x47, 0xc1, 704 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0xa7, 705 }; 706 smbus_eeprom_init_one(aspeed_i2c_get_bus(&soc->i2c, 4), 0x57, 707 eeprom_buf); 708 } 709 710 static void fp5280g2_bmc_i2c_init(AspeedMachineState *bmc) 711 { 712 AspeedSoCState *soc = bmc->soc; 713 I2CSlave *i2c_mux; 714 715 /* The at24c256 */ 716 at24c_eeprom_init(aspeed_i2c_get_bus(&soc->i2c, 1), 0x50, 32768); 717 718 /* The fp5280g2 expects a TMP112 but a TMP105 is compatible */ 719 i2c_slave_create_simple(aspeed_i2c_get_bus(&soc->i2c, 2), TYPE_TMP105, 720 0x48); 721 i2c_slave_create_simple(aspeed_i2c_get_bus(&soc->i2c, 2), TYPE_TMP105, 722 0x49); 723 724 i2c_mux = i2c_slave_create_simple(aspeed_i2c_get_bus(&soc->i2c, 2), 725 "pca9546", 0x70); 726 /* It expects a TMP112 but a TMP105 is compatible */ 727 i2c_slave_create_simple(pca954x_i2c_get_bus(i2c_mux, 0), TYPE_TMP105, 728 0x4a); 729 730 /* It expects a ds3232 but a ds1338 is good enough */ 731 i2c_slave_create_simple(aspeed_i2c_get_bus(&soc->i2c, 4), "ds1338", 0x68); 732 733 /* It expects a pca9555 but a pca9552 is compatible */ 734 create_pca9552(soc, 8, 0x30); 735 } 736 737 static void rainier_bmc_i2c_init(AspeedMachineState *bmc) 738 { 739 AspeedSoCState *soc = bmc->soc; 740 I2CSlave *i2c_mux; 741 742 at24c_eeprom_init(aspeed_i2c_get_bus(&soc->i2c, 0), 0x51, 32 * KiB); 743 744 create_pca9552(soc, 3, 0x61); 745 746 /* The rainier expects a TMP275 but a TMP105 is compatible */ 747 i2c_slave_create_simple(aspeed_i2c_get_bus(&soc->i2c, 4), TYPE_TMP105, 748 0x48); 749 i2c_slave_create_simple(aspeed_i2c_get_bus(&soc->i2c, 4), TYPE_TMP105, 750 0x49); 751 i2c_slave_create_simple(aspeed_i2c_get_bus(&soc->i2c, 4), TYPE_TMP105, 752 0x4a); 753 i2c_mux = i2c_slave_create_simple(aspeed_i2c_get_bus(&soc->i2c, 4), 754 "pca9546", 0x70); 755 at24c_eeprom_init(pca954x_i2c_get_bus(i2c_mux, 0), 0x50, 64 * KiB); 756 at24c_eeprom_init(pca954x_i2c_get_bus(i2c_mux, 1), 0x51, 64 * KiB); 757 at24c_eeprom_init(pca954x_i2c_get_bus(i2c_mux, 2), 0x52, 64 * KiB); 758 create_pca9552(soc, 4, 0x60); 759 760 i2c_slave_create_simple(aspeed_i2c_get_bus(&soc->i2c, 5), TYPE_TMP105, 761 0x48); 762 i2c_slave_create_simple(aspeed_i2c_get_bus(&soc->i2c, 5), TYPE_TMP105, 763 0x49); 764 create_pca9552(soc, 5, 0x60); 765 create_pca9552(soc, 5, 0x61); 766 i2c_mux = i2c_slave_create_simple(aspeed_i2c_get_bus(&soc->i2c, 5), 767 "pca9546", 0x70); 768 at24c_eeprom_init(pca954x_i2c_get_bus(i2c_mux, 0), 0x50, 64 * KiB); 769 at24c_eeprom_init(pca954x_i2c_get_bus(i2c_mux, 1), 0x51, 64 * KiB); 770 771 i2c_slave_create_simple(aspeed_i2c_get_bus(&soc->i2c, 6), TYPE_TMP105, 772 0x48); 773 i2c_slave_create_simple(aspeed_i2c_get_bus(&soc->i2c, 6), TYPE_TMP105, 774 0x4a); 775 i2c_slave_create_simple(aspeed_i2c_get_bus(&soc->i2c, 6), TYPE_TMP105, 776 0x4b); 777 i2c_mux = i2c_slave_create_simple(aspeed_i2c_get_bus(&soc->i2c, 6), 778 "pca9546", 0x70); 779 at24c_eeprom_init(pca954x_i2c_get_bus(i2c_mux, 0), 0x50, 64 * KiB); 780 at24c_eeprom_init(pca954x_i2c_get_bus(i2c_mux, 1), 0x51, 64 * KiB); 781 at24c_eeprom_init(pca954x_i2c_get_bus(i2c_mux, 2), 0x50, 64 * KiB); 782 at24c_eeprom_init(pca954x_i2c_get_bus(i2c_mux, 3), 0x51, 64 * KiB); 783 784 create_pca9552(soc, 7, 0x30); 785 create_pca9552(soc, 7, 0x31); 786 create_pca9552(soc, 7, 0x32); 787 create_pca9552(soc, 7, 0x33); 788 create_pca9552(soc, 7, 0x60); 789 create_pca9552(soc, 7, 0x61); 790 i2c_slave_create_simple(aspeed_i2c_get_bus(&soc->i2c, 7), "dps310", 0x76); 791 /* Bus 7: TODO si7021-a20@20 */ 792 i2c_slave_create_simple(aspeed_i2c_get_bus(&soc->i2c, 7), TYPE_TMP105, 793 0x48); 794 i2c_slave_create_simple(aspeed_i2c_get_bus(&soc->i2c, 7), "max31785", 0x52); 795 at24c_eeprom_init(aspeed_i2c_get_bus(&soc->i2c, 7), 0x50, 64 * KiB); 796 at24c_eeprom_init(aspeed_i2c_get_bus(&soc->i2c, 7), 0x51, 64 * KiB); 797 798 i2c_slave_create_simple(aspeed_i2c_get_bus(&soc->i2c, 8), TYPE_TMP105, 799 0x48); 800 i2c_slave_create_simple(aspeed_i2c_get_bus(&soc->i2c, 8), TYPE_TMP105, 801 0x4a); 802 at24c_eeprom_init_rom(aspeed_i2c_get_bus(&soc->i2c, 8), 0x50, 803 64 * KiB, rainier_bb_fruid, rainier_bb_fruid_len); 804 at24c_eeprom_init_rom(aspeed_i2c_get_bus(&soc->i2c, 8), 0x51, 805 64 * KiB, rainier_bmc_fruid, rainier_bmc_fruid_len); 806 create_pca9552(soc, 8, 0x60); 807 create_pca9552(soc, 8, 0x61); 808 /* Bus 8: ucd90320@11 */ 809 /* Bus 8: ucd90320@b */ 810 /* Bus 8: ucd90320@c */ 811 812 i2c_slave_create_simple(aspeed_i2c_get_bus(&soc->i2c, 9), "tmp423", 0x4c); 813 i2c_slave_create_simple(aspeed_i2c_get_bus(&soc->i2c, 9), "tmp423", 0x4d); 814 at24c_eeprom_init(aspeed_i2c_get_bus(&soc->i2c, 9), 0x50, 128 * KiB); 815 816 i2c_slave_create_simple(aspeed_i2c_get_bus(&soc->i2c, 10), "tmp423", 0x4c); 817 i2c_slave_create_simple(aspeed_i2c_get_bus(&soc->i2c, 10), "tmp423", 0x4d); 818 at24c_eeprom_init(aspeed_i2c_get_bus(&soc->i2c, 10), 0x50, 128 * KiB); 819 820 i2c_slave_create_simple(aspeed_i2c_get_bus(&soc->i2c, 11), TYPE_TMP105, 821 0x48); 822 i2c_slave_create_simple(aspeed_i2c_get_bus(&soc->i2c, 11), TYPE_TMP105, 823 0x49); 824 i2c_mux = i2c_slave_create_simple(aspeed_i2c_get_bus(&soc->i2c, 11), 825 "pca9546", 0x70); 826 at24c_eeprom_init(pca954x_i2c_get_bus(i2c_mux, 0), 0x50, 64 * KiB); 827 at24c_eeprom_init(pca954x_i2c_get_bus(i2c_mux, 1), 0x51, 64 * KiB); 828 create_pca9552(soc, 11, 0x60); 829 830 831 at24c_eeprom_init(aspeed_i2c_get_bus(&soc->i2c, 13), 0x50, 64 * KiB); 832 create_pca9552(soc, 13, 0x60); 833 834 at24c_eeprom_init(aspeed_i2c_get_bus(&soc->i2c, 14), 0x50, 64 * KiB); 835 create_pca9552(soc, 14, 0x60); 836 837 at24c_eeprom_init(aspeed_i2c_get_bus(&soc->i2c, 15), 0x50, 64 * KiB); 838 create_pca9552(soc, 15, 0x60); 839 } 840 841 static void get_pca9548_channels(I2CBus *bus, uint8_t mux_addr, 842 I2CBus **channels) 843 { 844 I2CSlave *mux = i2c_slave_create_simple(bus, "pca9548", mux_addr); 845 for (int i = 0; i < 8; i++) { 846 channels[i] = pca954x_i2c_get_bus(mux, i); 847 } 848 } 849 850 #define TYPE_LM75 TYPE_TMP105 851 #define TYPE_TMP75 TYPE_TMP105 852 #define TYPE_TMP422 "tmp422" 853 854 static void fuji_bmc_i2c_init(AspeedMachineState *bmc) 855 { 856 AspeedSoCState *soc = bmc->soc; 857 I2CBus *i2c[144] = {}; 858 859 for (int i = 0; i < 16; i++) { 860 i2c[i] = aspeed_i2c_get_bus(&soc->i2c, i); 861 } 862 I2CBus *i2c180 = i2c[2]; 863 I2CBus *i2c480 = i2c[8]; 864 I2CBus *i2c600 = i2c[11]; 865 866 get_pca9548_channels(i2c180, 0x70, &i2c[16]); 867 get_pca9548_channels(i2c480, 0x70, &i2c[24]); 868 /* NOTE: The device tree skips [32, 40) in the alias numbering */ 869 get_pca9548_channels(i2c600, 0x77, &i2c[40]); 870 get_pca9548_channels(i2c[24], 0x71, &i2c[48]); 871 get_pca9548_channels(i2c[25], 0x72, &i2c[56]); 872 get_pca9548_channels(i2c[26], 0x76, &i2c[64]); 873 get_pca9548_channels(i2c[27], 0x76, &i2c[72]); 874 for (int i = 0; i < 8; i++) { 875 get_pca9548_channels(i2c[40 + i], 0x76, &i2c[80 + i * 8]); 876 } 877 878 i2c_slave_create_simple(i2c[17], TYPE_LM75, 0x4c); 879 i2c_slave_create_simple(i2c[17], TYPE_LM75, 0x4d); 880 881 /* 882 * EEPROM 24c64 size is 64Kbits or 8 Kbytes 883 * 24c02 size is 2Kbits or 256 bytes 884 */ 885 at24c_eeprom_init(i2c[19], 0x52, 8 * KiB); 886 at24c_eeprom_init(i2c[20], 0x50, 256); 887 at24c_eeprom_init(i2c[22], 0x52, 256); 888 889 i2c_slave_create_simple(i2c[3], TYPE_LM75, 0x48); 890 i2c_slave_create_simple(i2c[3], TYPE_LM75, 0x49); 891 i2c_slave_create_simple(i2c[3], TYPE_LM75, 0x4a); 892 i2c_slave_create_simple(i2c[3], TYPE_TMP422, 0x4c); 893 894 at24c_eeprom_init(i2c[8], 0x51, 8 * KiB); 895 i2c_slave_create_simple(i2c[8], TYPE_LM75, 0x4a); 896 897 i2c_slave_create_simple(i2c[50], TYPE_LM75, 0x4c); 898 at24c_eeprom_init(i2c[50], 0x52, 8 * KiB); 899 i2c_slave_create_simple(i2c[51], TYPE_TMP75, 0x48); 900 i2c_slave_create_simple(i2c[52], TYPE_TMP75, 0x49); 901 902 i2c_slave_create_simple(i2c[59], TYPE_TMP75, 0x48); 903 i2c_slave_create_simple(i2c[60], TYPE_TMP75, 0x49); 904 905 at24c_eeprom_init(i2c[65], 0x53, 8 * KiB); 906 i2c_slave_create_simple(i2c[66], TYPE_TMP75, 0x49); 907 i2c_slave_create_simple(i2c[66], TYPE_TMP75, 0x48); 908 at24c_eeprom_init(i2c[68], 0x52, 8 * KiB); 909 at24c_eeprom_init(i2c[69], 0x52, 8 * KiB); 910 at24c_eeprom_init(i2c[70], 0x52, 8 * KiB); 911 at24c_eeprom_init(i2c[71], 0x52, 8 * KiB); 912 913 at24c_eeprom_init(i2c[73], 0x53, 8 * KiB); 914 i2c_slave_create_simple(i2c[74], TYPE_TMP75, 0x49); 915 i2c_slave_create_simple(i2c[74], TYPE_TMP75, 0x48); 916 at24c_eeprom_init(i2c[76], 0x52, 8 * KiB); 917 at24c_eeprom_init(i2c[77], 0x52, 8 * KiB); 918 at24c_eeprom_init(i2c[78], 0x52, 8 * KiB); 919 at24c_eeprom_init(i2c[79], 0x52, 8 * KiB); 920 at24c_eeprom_init(i2c[28], 0x50, 256); 921 922 for (int i = 0; i < 8; i++) { 923 at24c_eeprom_init(i2c[81 + i * 8], 0x56, 64 * KiB); 924 i2c_slave_create_simple(i2c[82 + i * 8], TYPE_TMP75, 0x48); 925 i2c_slave_create_simple(i2c[83 + i * 8], TYPE_TMP75, 0x4b); 926 i2c_slave_create_simple(i2c[84 + i * 8], TYPE_TMP75, 0x4a); 927 } 928 } 929 930 #define TYPE_TMP421 "tmp421" 931 932 static void bletchley_bmc_i2c_init(AspeedMachineState *bmc) 933 { 934 AspeedSoCState *soc = bmc->soc; 935 I2CBus *i2c[13] = {}; 936 for (int i = 0; i < 13; i++) { 937 if ((i == 8) || (i == 11)) { 938 continue; 939 } 940 i2c[i] = aspeed_i2c_get_bus(&soc->i2c, i); 941 } 942 943 /* Bus 0 - 5 all have the same config. */ 944 for (int i = 0; i < 6; i++) { 945 /* Missing model: ti,ina230 @ 0x45 */ 946 /* Missing model: mps,mp5023 @ 0x40 */ 947 i2c_slave_create_simple(i2c[i], TYPE_TMP421, 0x4f); 948 /* Missing model: nxp,pca9539 @ 0x76, but PCA9552 works enough */ 949 i2c_slave_create_simple(i2c[i], TYPE_PCA9552, 0x76); 950 i2c_slave_create_simple(i2c[i], TYPE_PCA9552, 0x67); 951 /* Missing model: fsc,fusb302 @ 0x22 */ 952 } 953 954 /* Bus 6 */ 955 at24c_eeprom_init(i2c[6], 0x56, 65536); 956 /* Missing model: nxp,pcf85263 @ 0x51 , but ds1338 works enough */ 957 i2c_slave_create_simple(i2c[6], "ds1338", 0x51); 958 959 960 /* Bus 7 */ 961 at24c_eeprom_init(i2c[7], 0x54, 65536); 962 963 /* Bus 9 */ 964 i2c_slave_create_simple(i2c[9], TYPE_TMP421, 0x4f); 965 966 /* Bus 10 */ 967 i2c_slave_create_simple(i2c[10], TYPE_TMP421, 0x4f); 968 /* Missing model: ti,hdc1080 @ 0x40 */ 969 i2c_slave_create_simple(i2c[10], TYPE_PCA9552, 0x67); 970 971 /* Bus 12 */ 972 /* Missing model: adi,adm1278 @ 0x11 */ 973 i2c_slave_create_simple(i2c[12], TYPE_TMP421, 0x4c); 974 i2c_slave_create_simple(i2c[12], TYPE_TMP421, 0x4d); 975 i2c_slave_create_simple(i2c[12], TYPE_PCA9552, 0x67); 976 } 977 978 static void fby35_i2c_init(AspeedMachineState *bmc) 979 { 980 AspeedSoCState *soc = bmc->soc; 981 I2CBus *i2c[16]; 982 983 for (int i = 0; i < 16; i++) { 984 i2c[i] = aspeed_i2c_get_bus(&soc->i2c, i); 985 } 986 987 i2c_slave_create_simple(i2c[2], TYPE_LM75, 0x4f); 988 i2c_slave_create_simple(i2c[8], TYPE_TMP421, 0x1f); 989 /* Hotswap controller is actually supposed to be mp5920 or ltc4282. */ 990 i2c_slave_create_simple(i2c[11], "adm1272", 0x44); 991 i2c_slave_create_simple(i2c[12], TYPE_LM75, 0x4e); 992 i2c_slave_create_simple(i2c[12], TYPE_LM75, 0x4f); 993 994 at24c_eeprom_init(i2c[4], 0x51, 128 * KiB); 995 at24c_eeprom_init(i2c[6], 0x51, 128 * KiB); 996 at24c_eeprom_init_rom(i2c[8], 0x50, 32 * KiB, fby35_nic_fruid, 997 fby35_nic_fruid_len); 998 at24c_eeprom_init_rom(i2c[11], 0x51, 128 * KiB, fby35_bb_fruid, 999 fby35_bb_fruid_len); 1000 at24c_eeprom_init_rom(i2c[11], 0x54, 128 * KiB, fby35_bmc_fruid, 1001 fby35_bmc_fruid_len); 1002 1003 /* 1004 * TODO: There is a multi-master i2c connection to an AST1030 MiniBMC on 1005 * buses 0, 1, 2, 3, and 9. Source address 0x10, target address 0x20 on 1006 * each. 1007 */ 1008 } 1009 1010 static void qcom_dc_scm_bmc_i2c_init(AspeedMachineState *bmc) 1011 { 1012 AspeedSoCState *soc = bmc->soc; 1013 1014 i2c_slave_create_simple(aspeed_i2c_get_bus(&soc->i2c, 15), "tmp105", 0x4d); 1015 } 1016 1017 static void qcom_dc_scm_firework_i2c_init(AspeedMachineState *bmc) 1018 { 1019 AspeedSoCState *soc = bmc->soc; 1020 I2CSlave *therm_mux, *cpuvr_mux; 1021 1022 /* Create the generic DC-SCM hardware */ 1023 qcom_dc_scm_bmc_i2c_init(bmc); 1024 1025 /* Now create the Firework specific hardware */ 1026 1027 /* I2C7 CPUVR MUX */ 1028 cpuvr_mux = i2c_slave_create_simple(aspeed_i2c_get_bus(&soc->i2c, 7), 1029 "pca9546", 0x70); 1030 i2c_slave_create_simple(pca954x_i2c_get_bus(cpuvr_mux, 0), "pca9548", 0x72); 1031 i2c_slave_create_simple(pca954x_i2c_get_bus(cpuvr_mux, 1), "pca9548", 0x72); 1032 i2c_slave_create_simple(pca954x_i2c_get_bus(cpuvr_mux, 2), "pca9548", 0x72); 1033 i2c_slave_create_simple(pca954x_i2c_get_bus(cpuvr_mux, 3), "pca9548", 0x72); 1034 1035 /* I2C8 Thermal Diodes*/ 1036 therm_mux = i2c_slave_create_simple(aspeed_i2c_get_bus(&soc->i2c, 8), 1037 "pca9548", 0x70); 1038 i2c_slave_create_simple(pca954x_i2c_get_bus(therm_mux, 0), TYPE_LM75, 0x4C); 1039 i2c_slave_create_simple(pca954x_i2c_get_bus(therm_mux, 1), TYPE_LM75, 0x4C); 1040 i2c_slave_create_simple(pca954x_i2c_get_bus(therm_mux, 2), TYPE_LM75, 0x48); 1041 i2c_slave_create_simple(pca954x_i2c_get_bus(therm_mux, 3), TYPE_LM75, 0x48); 1042 i2c_slave_create_simple(pca954x_i2c_get_bus(therm_mux, 4), TYPE_LM75, 0x48); 1043 1044 /* I2C9 Fan Controller (MAX31785) */ 1045 i2c_slave_create_simple(aspeed_i2c_get_bus(&soc->i2c, 9), "max31785", 0x52); 1046 i2c_slave_create_simple(aspeed_i2c_get_bus(&soc->i2c, 9), "max31785", 0x54); 1047 } 1048 1049 static bool aspeed_get_mmio_exec(Object *obj, Error **errp) 1050 { 1051 return ASPEED_MACHINE(obj)->mmio_exec; 1052 } 1053 1054 static void aspeed_set_mmio_exec(Object *obj, bool value, Error **errp) 1055 { 1056 ASPEED_MACHINE(obj)->mmio_exec = value; 1057 } 1058 1059 static void aspeed_machine_instance_init(Object *obj) 1060 { 1061 ASPEED_MACHINE(obj)->mmio_exec = false; 1062 } 1063 1064 static char *aspeed_get_fmc_model(Object *obj, Error **errp) 1065 { 1066 AspeedMachineState *bmc = ASPEED_MACHINE(obj); 1067 return g_strdup(bmc->fmc_model); 1068 } 1069 1070 static void aspeed_set_fmc_model(Object *obj, const char *value, Error **errp) 1071 { 1072 AspeedMachineState *bmc = ASPEED_MACHINE(obj); 1073 1074 g_free(bmc->fmc_model); 1075 bmc->fmc_model = g_strdup(value); 1076 } 1077 1078 static char *aspeed_get_spi_model(Object *obj, Error **errp) 1079 { 1080 AspeedMachineState *bmc = ASPEED_MACHINE(obj); 1081 return g_strdup(bmc->spi_model); 1082 } 1083 1084 static void aspeed_set_spi_model(Object *obj, const char *value, Error **errp) 1085 { 1086 AspeedMachineState *bmc = ASPEED_MACHINE(obj); 1087 1088 g_free(bmc->spi_model); 1089 bmc->spi_model = g_strdup(value); 1090 } 1091 1092 static char *aspeed_get_bmc_console(Object *obj, Error **errp) 1093 { 1094 AspeedMachineState *bmc = ASPEED_MACHINE(obj); 1095 AspeedMachineClass *amc = ASPEED_MACHINE_GET_CLASS(bmc); 1096 int uart_chosen = bmc->uart_chosen ? bmc->uart_chosen : amc->uart_default; 1097 1098 return g_strdup_printf("uart%d", uart_chosen - ASPEED_DEV_UART1 + 1); 1099 } 1100 1101 static void aspeed_set_bmc_console(Object *obj, const char *value, Error **errp) 1102 { 1103 AspeedMachineState *bmc = ASPEED_MACHINE(obj); 1104 AspeedMachineClass *amc = ASPEED_MACHINE_GET_CLASS(bmc); 1105 AspeedSoCClass *sc = ASPEED_SOC_CLASS(object_class_by_name(amc->soc_name)); 1106 int val; 1107 1108 if (sscanf(value, "uart%u", &val) != 1) { 1109 error_setg(errp, "Bad value for \"uart\" property"); 1110 return; 1111 } 1112 1113 /* The number of UART depends on the SoC */ 1114 if (val < 1 || val > sc->uarts_num) { 1115 error_setg(errp, "\"uart\" should be in range [1 - %d]", sc->uarts_num); 1116 return; 1117 } 1118 bmc->uart_chosen = ASPEED_DEV_UART1 + val - 1; 1119 } 1120 1121 static void aspeed_machine_class_props_init(ObjectClass *oc) 1122 { 1123 object_class_property_add_bool(oc, "execute-in-place", 1124 aspeed_get_mmio_exec, 1125 aspeed_set_mmio_exec); 1126 object_class_property_set_description(oc, "execute-in-place", 1127 "boot directly from CE0 flash device"); 1128 1129 object_class_property_add_str(oc, "bmc-console", aspeed_get_bmc_console, 1130 aspeed_set_bmc_console); 1131 object_class_property_set_description(oc, "bmc-console", 1132 "Change the default UART to \"uartX\""); 1133 1134 object_class_property_add_str(oc, "fmc-model", aspeed_get_fmc_model, 1135 aspeed_set_fmc_model); 1136 object_class_property_set_description(oc, "fmc-model", 1137 "Change the FMC Flash model"); 1138 object_class_property_add_str(oc, "spi-model", aspeed_get_spi_model, 1139 aspeed_set_spi_model); 1140 object_class_property_set_description(oc, "spi-model", 1141 "Change the SPI Flash model"); 1142 } 1143 1144 static void aspeed_machine_class_init_cpus_defaults(MachineClass *mc) 1145 { 1146 AspeedMachineClass *amc = ASPEED_MACHINE_CLASS(mc); 1147 AspeedSoCClass *sc = ASPEED_SOC_CLASS(object_class_by_name(amc->soc_name)); 1148 1149 mc->default_cpus = sc->num_cpus; 1150 mc->min_cpus = sc->num_cpus; 1151 mc->max_cpus = sc->num_cpus; 1152 mc->valid_cpu_types = sc->valid_cpu_types; 1153 } 1154 1155 static void aspeed_machine_class_init(ObjectClass *oc, void *data) 1156 { 1157 MachineClass *mc = MACHINE_CLASS(oc); 1158 AspeedMachineClass *amc = ASPEED_MACHINE_CLASS(oc); 1159 1160 mc->init = aspeed_machine_init; 1161 mc->no_floppy = 1; 1162 mc->no_cdrom = 1; 1163 mc->no_parallel = 1; 1164 mc->default_ram_id = "ram"; 1165 amc->macs_mask = ASPEED_MAC0_ON; 1166 amc->uart_default = ASPEED_DEV_UART5; 1167 1168 aspeed_machine_class_props_init(oc); 1169 } 1170 1171 static void aspeed_machine_palmetto_class_init(ObjectClass *oc, void *data) 1172 { 1173 MachineClass *mc = MACHINE_CLASS(oc); 1174 AspeedMachineClass *amc = ASPEED_MACHINE_CLASS(oc); 1175 1176 mc->desc = "OpenPOWER Palmetto BMC (ARM926EJ-S)"; 1177 amc->soc_name = "ast2400-a1"; 1178 amc->hw_strap1 = PALMETTO_BMC_HW_STRAP1; 1179 amc->fmc_model = "n25q256a"; 1180 amc->spi_model = "mx25l25635f"; 1181 amc->num_cs = 1; 1182 amc->i2c_init = palmetto_bmc_i2c_init; 1183 mc->default_ram_size = 256 * MiB; 1184 aspeed_machine_class_init_cpus_defaults(mc); 1185 }; 1186 1187 static void aspeed_machine_quanta_q71l_class_init(ObjectClass *oc, void *data) 1188 { 1189 MachineClass *mc = MACHINE_CLASS(oc); 1190 AspeedMachineClass *amc = ASPEED_MACHINE_CLASS(oc); 1191 1192 mc->desc = "Quanta-Q71l BMC (ARM926EJ-S)"; 1193 amc->soc_name = "ast2400-a1"; 1194 amc->hw_strap1 = QUANTA_Q71L_BMC_HW_STRAP1; 1195 amc->fmc_model = "n25q256a"; 1196 amc->spi_model = "mx25l25635e"; 1197 amc->num_cs = 1; 1198 amc->i2c_init = quanta_q71l_bmc_i2c_init; 1199 mc->default_ram_size = 128 * MiB; 1200 aspeed_machine_class_init_cpus_defaults(mc); 1201 } 1202 1203 static void aspeed_machine_supermicrox11_bmc_class_init(ObjectClass *oc, 1204 void *data) 1205 { 1206 MachineClass *mc = MACHINE_CLASS(oc); 1207 AspeedMachineClass *amc = ASPEED_MACHINE_CLASS(oc); 1208 1209 mc->desc = "Supermicro X11 BMC (ARM926EJ-S)"; 1210 amc->soc_name = "ast2400-a1"; 1211 amc->hw_strap1 = SUPERMICROX11_BMC_HW_STRAP1; 1212 amc->fmc_model = "mx25l25635e"; 1213 amc->spi_model = "mx25l25635e"; 1214 amc->num_cs = 1; 1215 amc->macs_mask = ASPEED_MAC0_ON | ASPEED_MAC1_ON; 1216 amc->i2c_init = palmetto_bmc_i2c_init; 1217 mc->default_ram_size = 256 * MiB; 1218 aspeed_machine_class_init_cpus_defaults(mc); 1219 } 1220 1221 static void aspeed_machine_supermicro_x11spi_bmc_class_init(ObjectClass *oc, 1222 void *data) 1223 { 1224 MachineClass *mc = MACHINE_CLASS(oc); 1225 AspeedMachineClass *amc = ASPEED_MACHINE_CLASS(oc); 1226 1227 mc->desc = "Supermicro X11 SPI BMC (ARM1176)"; 1228 amc->soc_name = "ast2500-a1"; 1229 amc->hw_strap1 = SUPERMICRO_X11SPI_BMC_HW_STRAP1; 1230 amc->fmc_model = "mx25l25635e"; 1231 amc->spi_model = "mx25l25635e"; 1232 amc->num_cs = 1; 1233 amc->macs_mask = ASPEED_MAC0_ON | ASPEED_MAC1_ON; 1234 amc->i2c_init = palmetto_bmc_i2c_init; 1235 mc->default_ram_size = 512 * MiB; 1236 aspeed_machine_class_init_cpus_defaults(mc); 1237 } 1238 1239 static void aspeed_machine_ast2500_evb_class_init(ObjectClass *oc, void *data) 1240 { 1241 MachineClass *mc = MACHINE_CLASS(oc); 1242 AspeedMachineClass *amc = ASPEED_MACHINE_CLASS(oc); 1243 1244 mc->desc = "Aspeed AST2500 EVB (ARM1176)"; 1245 amc->soc_name = "ast2500-a1"; 1246 amc->hw_strap1 = AST2500_EVB_HW_STRAP1; 1247 amc->fmc_model = "mx25l25635e"; 1248 amc->spi_model = "mx25l25635f"; 1249 amc->num_cs = 1; 1250 amc->i2c_init = ast2500_evb_i2c_init; 1251 mc->default_ram_size = 512 * MiB; 1252 aspeed_machine_class_init_cpus_defaults(mc); 1253 }; 1254 1255 static void aspeed_machine_yosemitev2_class_init(ObjectClass *oc, void *data) 1256 { 1257 MachineClass *mc = MACHINE_CLASS(oc); 1258 AspeedMachineClass *amc = ASPEED_MACHINE_CLASS(oc); 1259 1260 mc->desc = "Facebook YosemiteV2 BMC (ARM1176)"; 1261 amc->soc_name = "ast2500-a1"; 1262 amc->hw_strap1 = AST2500_EVB_HW_STRAP1; 1263 amc->hw_strap2 = 0; 1264 amc->fmc_model = "n25q256a"; 1265 amc->spi_model = "mx25l25635e"; 1266 amc->num_cs = 2; 1267 amc->i2c_init = yosemitev2_bmc_i2c_init; 1268 mc->default_ram_size = 512 * MiB; 1269 aspeed_machine_class_init_cpus_defaults(mc); 1270 }; 1271 1272 static void aspeed_machine_romulus_class_init(ObjectClass *oc, void *data) 1273 { 1274 MachineClass *mc = MACHINE_CLASS(oc); 1275 AspeedMachineClass *amc = ASPEED_MACHINE_CLASS(oc); 1276 1277 mc->desc = "OpenPOWER Romulus BMC (ARM1176)"; 1278 amc->soc_name = "ast2500-a1"; 1279 amc->hw_strap1 = ROMULUS_BMC_HW_STRAP1; 1280 amc->fmc_model = "n25q256a"; 1281 amc->spi_model = "mx66l1g45g"; 1282 amc->num_cs = 2; 1283 amc->i2c_init = romulus_bmc_i2c_init; 1284 mc->default_ram_size = 512 * MiB; 1285 aspeed_machine_class_init_cpus_defaults(mc); 1286 }; 1287 1288 static void aspeed_machine_tiogapass_class_init(ObjectClass *oc, void *data) 1289 { 1290 MachineClass *mc = MACHINE_CLASS(oc); 1291 AspeedMachineClass *amc = ASPEED_MACHINE_CLASS(oc); 1292 1293 mc->desc = "Facebook Tiogapass BMC (ARM1176)"; 1294 amc->soc_name = "ast2500-a1"; 1295 amc->hw_strap1 = AST2500_EVB_HW_STRAP1; 1296 amc->hw_strap2 = 0; 1297 amc->fmc_model = "n25q256a"; 1298 amc->spi_model = "mx25l25635e"; 1299 amc->num_cs = 2; 1300 amc->i2c_init = tiogapass_bmc_i2c_init; 1301 mc->default_ram_size = 1 * GiB; 1302 aspeed_machine_class_init_cpus_defaults(mc); 1303 }; 1304 1305 static void aspeed_machine_sonorapass_class_init(ObjectClass *oc, void *data) 1306 { 1307 MachineClass *mc = MACHINE_CLASS(oc); 1308 AspeedMachineClass *amc = ASPEED_MACHINE_CLASS(oc); 1309 1310 mc->desc = "OCP SonoraPass BMC (ARM1176)"; 1311 amc->soc_name = "ast2500-a1"; 1312 amc->hw_strap1 = SONORAPASS_BMC_HW_STRAP1; 1313 amc->fmc_model = "mx66l1g45g"; 1314 amc->spi_model = "mx66l1g45g"; 1315 amc->num_cs = 2; 1316 amc->i2c_init = sonorapass_bmc_i2c_init; 1317 mc->default_ram_size = 512 * MiB; 1318 aspeed_machine_class_init_cpus_defaults(mc); 1319 }; 1320 1321 static void aspeed_machine_witherspoon_class_init(ObjectClass *oc, void *data) 1322 { 1323 MachineClass *mc = MACHINE_CLASS(oc); 1324 AspeedMachineClass *amc = ASPEED_MACHINE_CLASS(oc); 1325 1326 mc->desc = "OpenPOWER Witherspoon BMC (ARM1176)"; 1327 amc->soc_name = "ast2500-a1"; 1328 amc->hw_strap1 = WITHERSPOON_BMC_HW_STRAP1; 1329 amc->fmc_model = "mx25l25635f"; 1330 amc->spi_model = "mx66l1g45g"; 1331 amc->num_cs = 2; 1332 amc->i2c_init = witherspoon_bmc_i2c_init; 1333 mc->default_ram_size = 512 * MiB; 1334 aspeed_machine_class_init_cpus_defaults(mc); 1335 }; 1336 1337 static void aspeed_machine_ast2600_evb_class_init(ObjectClass *oc, void *data) 1338 { 1339 MachineClass *mc = MACHINE_CLASS(oc); 1340 AspeedMachineClass *amc = ASPEED_MACHINE_CLASS(oc); 1341 1342 mc->desc = "Aspeed AST2600 EVB (Cortex-A7)"; 1343 amc->soc_name = "ast2600-a3"; 1344 amc->hw_strap1 = AST2600_EVB_HW_STRAP1; 1345 amc->hw_strap2 = AST2600_EVB_HW_STRAP2; 1346 amc->fmc_model = "mx66u51235f"; 1347 amc->spi_model = "mx66u51235f"; 1348 amc->num_cs = 1; 1349 amc->macs_mask = ASPEED_MAC0_ON | ASPEED_MAC1_ON | ASPEED_MAC2_ON | 1350 ASPEED_MAC3_ON; 1351 amc->i2c_init = ast2600_evb_i2c_init; 1352 mc->default_ram_size = 1 * GiB; 1353 aspeed_machine_class_init_cpus_defaults(mc); 1354 }; 1355 1356 static void aspeed_machine_tacoma_class_init(ObjectClass *oc, void *data) 1357 { 1358 MachineClass *mc = MACHINE_CLASS(oc); 1359 AspeedMachineClass *amc = ASPEED_MACHINE_CLASS(oc); 1360 1361 mc->desc = "OpenPOWER Tacoma BMC (Cortex-A7)"; 1362 amc->soc_name = "ast2600-a3"; 1363 amc->hw_strap1 = TACOMA_BMC_HW_STRAP1; 1364 amc->hw_strap2 = TACOMA_BMC_HW_STRAP2; 1365 amc->fmc_model = "mx66l1g45g"; 1366 amc->spi_model = "mx66l1g45g"; 1367 amc->num_cs = 2; 1368 amc->macs_mask = ASPEED_MAC2_ON; 1369 amc->i2c_init = witherspoon_bmc_i2c_init; /* Same board layout */ 1370 mc->default_ram_size = 1 * GiB; 1371 aspeed_machine_class_init_cpus_defaults(mc); 1372 }; 1373 1374 static void aspeed_machine_g220a_class_init(ObjectClass *oc, void *data) 1375 { 1376 MachineClass *mc = MACHINE_CLASS(oc); 1377 AspeedMachineClass *amc = ASPEED_MACHINE_CLASS(oc); 1378 1379 mc->desc = "Bytedance G220A BMC (ARM1176)"; 1380 amc->soc_name = "ast2500-a1"; 1381 amc->hw_strap1 = G220A_BMC_HW_STRAP1; 1382 amc->fmc_model = "n25q512a"; 1383 amc->spi_model = "mx25l25635e"; 1384 amc->num_cs = 2; 1385 amc->macs_mask = ASPEED_MAC0_ON | ASPEED_MAC1_ON; 1386 amc->i2c_init = g220a_bmc_i2c_init; 1387 mc->default_ram_size = 1024 * MiB; 1388 aspeed_machine_class_init_cpus_defaults(mc); 1389 }; 1390 1391 static void aspeed_machine_fp5280g2_class_init(ObjectClass *oc, void *data) 1392 { 1393 MachineClass *mc = MACHINE_CLASS(oc); 1394 AspeedMachineClass *amc = ASPEED_MACHINE_CLASS(oc); 1395 1396 mc->desc = "Inspur FP5280G2 BMC (ARM1176)"; 1397 amc->soc_name = "ast2500-a1"; 1398 amc->hw_strap1 = FP5280G2_BMC_HW_STRAP1; 1399 amc->fmc_model = "n25q512a"; 1400 amc->spi_model = "mx25l25635e"; 1401 amc->num_cs = 2; 1402 amc->macs_mask = ASPEED_MAC0_ON | ASPEED_MAC1_ON; 1403 amc->i2c_init = fp5280g2_bmc_i2c_init; 1404 mc->default_ram_size = 512 * MiB; 1405 aspeed_machine_class_init_cpus_defaults(mc); 1406 }; 1407 1408 static void aspeed_machine_rainier_class_init(ObjectClass *oc, void *data) 1409 { 1410 MachineClass *mc = MACHINE_CLASS(oc); 1411 AspeedMachineClass *amc = ASPEED_MACHINE_CLASS(oc); 1412 1413 mc->desc = "IBM Rainier BMC (Cortex-A7)"; 1414 amc->soc_name = "ast2600-a3"; 1415 amc->hw_strap1 = RAINIER_BMC_HW_STRAP1; 1416 amc->hw_strap2 = RAINIER_BMC_HW_STRAP2; 1417 amc->fmc_model = "mx66l1g45g"; 1418 amc->spi_model = "mx66l1g45g"; 1419 amc->num_cs = 2; 1420 amc->macs_mask = ASPEED_MAC2_ON | ASPEED_MAC3_ON; 1421 amc->i2c_init = rainier_bmc_i2c_init; 1422 mc->default_ram_size = 1 * GiB; 1423 aspeed_machine_class_init_cpus_defaults(mc); 1424 }; 1425 1426 #define FUJI_BMC_RAM_SIZE ASPEED_RAM_SIZE(2 * GiB) 1427 1428 static void aspeed_machine_fuji_class_init(ObjectClass *oc, void *data) 1429 { 1430 MachineClass *mc = MACHINE_CLASS(oc); 1431 AspeedMachineClass *amc = ASPEED_MACHINE_CLASS(oc); 1432 1433 mc->desc = "Facebook Fuji BMC (Cortex-A7)"; 1434 amc->soc_name = "ast2600-a3"; 1435 amc->hw_strap1 = FUJI_BMC_HW_STRAP1; 1436 amc->hw_strap2 = FUJI_BMC_HW_STRAP2; 1437 amc->fmc_model = "mx66l1g45g"; 1438 amc->spi_model = "mx66l1g45g"; 1439 amc->num_cs = 2; 1440 amc->macs_mask = ASPEED_MAC3_ON; 1441 amc->i2c_init = fuji_bmc_i2c_init; 1442 amc->uart_default = ASPEED_DEV_UART1; 1443 mc->default_ram_size = FUJI_BMC_RAM_SIZE; 1444 aspeed_machine_class_init_cpus_defaults(mc); 1445 }; 1446 1447 #define BLETCHLEY_BMC_RAM_SIZE ASPEED_RAM_SIZE(2 * GiB) 1448 1449 static void aspeed_machine_bletchley_class_init(ObjectClass *oc, void *data) 1450 { 1451 MachineClass *mc = MACHINE_CLASS(oc); 1452 AspeedMachineClass *amc = ASPEED_MACHINE_CLASS(oc); 1453 1454 mc->desc = "Facebook Bletchley BMC (Cortex-A7)"; 1455 amc->soc_name = "ast2600-a3"; 1456 amc->hw_strap1 = BLETCHLEY_BMC_HW_STRAP1; 1457 amc->hw_strap2 = BLETCHLEY_BMC_HW_STRAP2; 1458 amc->fmc_model = "w25q01jvq"; 1459 amc->spi_model = NULL; 1460 amc->num_cs = 2; 1461 amc->macs_mask = ASPEED_MAC2_ON; 1462 amc->i2c_init = bletchley_bmc_i2c_init; 1463 mc->default_ram_size = BLETCHLEY_BMC_RAM_SIZE; 1464 aspeed_machine_class_init_cpus_defaults(mc); 1465 } 1466 1467 static void fby35_reset(MachineState *state, ShutdownCause reason) 1468 { 1469 AspeedMachineState *bmc = ASPEED_MACHINE(state); 1470 AspeedGPIOState *gpio = &bmc->soc->gpio; 1471 1472 qemu_devices_reset(reason); 1473 1474 /* Board ID: 7 (Class-1, 4 slots) */ 1475 object_property_set_bool(OBJECT(gpio), "gpioV4", true, &error_fatal); 1476 object_property_set_bool(OBJECT(gpio), "gpioV5", true, &error_fatal); 1477 object_property_set_bool(OBJECT(gpio), "gpioV6", true, &error_fatal); 1478 object_property_set_bool(OBJECT(gpio), "gpioV7", false, &error_fatal); 1479 1480 /* Slot presence pins, inverse polarity. (False means present) */ 1481 object_property_set_bool(OBJECT(gpio), "gpioH4", false, &error_fatal); 1482 object_property_set_bool(OBJECT(gpio), "gpioH5", true, &error_fatal); 1483 object_property_set_bool(OBJECT(gpio), "gpioH6", true, &error_fatal); 1484 object_property_set_bool(OBJECT(gpio), "gpioH7", true, &error_fatal); 1485 1486 /* Slot 12v power pins, normal polarity. (True means powered-on) */ 1487 object_property_set_bool(OBJECT(gpio), "gpioB2", true, &error_fatal); 1488 object_property_set_bool(OBJECT(gpio), "gpioB3", false, &error_fatal); 1489 object_property_set_bool(OBJECT(gpio), "gpioB4", false, &error_fatal); 1490 object_property_set_bool(OBJECT(gpio), "gpioB5", false, &error_fatal); 1491 } 1492 1493 static void aspeed_machine_fby35_class_init(ObjectClass *oc, void *data) 1494 { 1495 MachineClass *mc = MACHINE_CLASS(oc); 1496 AspeedMachineClass *amc = ASPEED_MACHINE_CLASS(oc); 1497 1498 mc->desc = "Facebook fby35 BMC (Cortex-A7)"; 1499 mc->reset = fby35_reset; 1500 amc->fmc_model = "mx66l1g45g"; 1501 amc->num_cs = 2; 1502 amc->macs_mask = ASPEED_MAC3_ON; 1503 amc->i2c_init = fby35_i2c_init; 1504 /* FIXME: Replace this macro with something more general */ 1505 mc->default_ram_size = FUJI_BMC_RAM_SIZE; 1506 aspeed_machine_class_init_cpus_defaults(mc); 1507 } 1508 1509 #define AST1030_INTERNAL_FLASH_SIZE (1024 * 1024) 1510 /* Main SYSCLK frequency in Hz (200MHz) */ 1511 #define SYSCLK_FRQ 200000000ULL 1512 1513 static void aspeed_minibmc_machine_init(MachineState *machine) 1514 { 1515 AspeedMachineState *bmc = ASPEED_MACHINE(machine); 1516 AspeedMachineClass *amc = ASPEED_MACHINE_GET_CLASS(machine); 1517 Clock *sysclk; 1518 1519 sysclk = clock_new(OBJECT(machine), "SYSCLK"); 1520 clock_set_hz(sysclk, SYSCLK_FRQ); 1521 1522 bmc->soc = ASPEED_SOC(object_new(amc->soc_name)); 1523 object_property_add_child(OBJECT(machine), "soc", OBJECT(bmc->soc)); 1524 object_unref(OBJECT(bmc->soc)); 1525 qdev_connect_clock_in(DEVICE(bmc->soc), "sysclk", sysclk); 1526 1527 object_property_set_link(OBJECT(bmc->soc), "memory", 1528 OBJECT(get_system_memory()), &error_abort); 1529 connect_serial_hds_to_uarts(bmc); 1530 qdev_realize(DEVICE(bmc->soc), NULL, &error_abort); 1531 1532 aspeed_board_init_flashes(&bmc->soc->fmc, 1533 bmc->fmc_model ? bmc->fmc_model : amc->fmc_model, 1534 amc->num_cs, 1535 0); 1536 1537 aspeed_board_init_flashes(&bmc->soc->spi[0], 1538 bmc->spi_model ? bmc->spi_model : amc->spi_model, 1539 amc->num_cs, amc->num_cs); 1540 1541 aspeed_board_init_flashes(&bmc->soc->spi[1], 1542 bmc->spi_model ? bmc->spi_model : amc->spi_model, 1543 amc->num_cs, (amc->num_cs * 2)); 1544 1545 if (amc->i2c_init) { 1546 amc->i2c_init(bmc); 1547 } 1548 1549 armv7m_load_kernel(ARM_CPU(first_cpu), 1550 machine->kernel_filename, 1551 0, 1552 AST1030_INTERNAL_FLASH_SIZE); 1553 } 1554 1555 static void ast1030_evb_i2c_init(AspeedMachineState *bmc) 1556 { 1557 AspeedSoCState *soc = bmc->soc; 1558 1559 /* U10 24C08 connects to SDA/SCL Group 1 by default */ 1560 uint8_t *eeprom_buf = g_malloc0(32 * 1024); 1561 smbus_eeprom_init_one(aspeed_i2c_get_bus(&soc->i2c, 0), 0x50, eeprom_buf); 1562 1563 /* U11 LM75 connects to SDA/SCL Group 2 by default */ 1564 i2c_slave_create_simple(aspeed_i2c_get_bus(&soc->i2c, 1), "tmp105", 0x4d); 1565 } 1566 1567 static void aspeed_minibmc_machine_ast1030_evb_class_init(ObjectClass *oc, 1568 void *data) 1569 { 1570 MachineClass *mc = MACHINE_CLASS(oc); 1571 AspeedMachineClass *amc = ASPEED_MACHINE_CLASS(oc); 1572 1573 mc->desc = "Aspeed AST1030 MiniBMC (Cortex-M4)"; 1574 amc->soc_name = "ast1030-a1"; 1575 amc->hw_strap1 = 0; 1576 amc->hw_strap2 = 0; 1577 mc->init = aspeed_minibmc_machine_init; 1578 amc->i2c_init = ast1030_evb_i2c_init; 1579 mc->default_ram_size = 0; 1580 amc->fmc_model = "sst25vf032b"; 1581 amc->spi_model = "sst25vf032b"; 1582 amc->num_cs = 2; 1583 amc->macs_mask = 0; 1584 aspeed_machine_class_init_cpus_defaults(mc); 1585 } 1586 1587 static void aspeed_machine_qcom_dc_scm_v1_class_init(ObjectClass *oc, 1588 void *data) 1589 { 1590 MachineClass *mc = MACHINE_CLASS(oc); 1591 AspeedMachineClass *amc = ASPEED_MACHINE_CLASS(oc); 1592 1593 mc->desc = "Qualcomm DC-SCM V1 BMC (Cortex A7)"; 1594 amc->soc_name = "ast2600-a3"; 1595 amc->hw_strap1 = QCOM_DC_SCM_V1_BMC_HW_STRAP1; 1596 amc->hw_strap2 = QCOM_DC_SCM_V1_BMC_HW_STRAP2; 1597 amc->fmc_model = "n25q512a"; 1598 amc->spi_model = "n25q512a"; 1599 amc->num_cs = 2; 1600 amc->macs_mask = ASPEED_MAC2_ON | ASPEED_MAC3_ON; 1601 amc->i2c_init = qcom_dc_scm_bmc_i2c_init; 1602 mc->default_ram_size = 1 * GiB; 1603 aspeed_machine_class_init_cpus_defaults(mc); 1604 }; 1605 1606 static void aspeed_machine_qcom_firework_class_init(ObjectClass *oc, 1607 void *data) 1608 { 1609 MachineClass *mc = MACHINE_CLASS(oc); 1610 AspeedMachineClass *amc = ASPEED_MACHINE_CLASS(oc); 1611 1612 mc->desc = "Qualcomm DC-SCM V1/Firework BMC (Cortex A7)"; 1613 amc->soc_name = "ast2600-a3"; 1614 amc->hw_strap1 = QCOM_DC_SCM_V1_BMC_HW_STRAP1; 1615 amc->hw_strap2 = QCOM_DC_SCM_V1_BMC_HW_STRAP2; 1616 amc->fmc_model = "n25q512a"; 1617 amc->spi_model = "n25q512a"; 1618 amc->num_cs = 2; 1619 amc->macs_mask = ASPEED_MAC2_ON | ASPEED_MAC3_ON; 1620 amc->i2c_init = qcom_dc_scm_firework_i2c_init; 1621 mc->default_ram_size = 1 * GiB; 1622 aspeed_machine_class_init_cpus_defaults(mc); 1623 }; 1624 1625 static const TypeInfo aspeed_machine_types[] = { 1626 { 1627 .name = MACHINE_TYPE_NAME("palmetto-bmc"), 1628 .parent = TYPE_ASPEED_MACHINE, 1629 .class_init = aspeed_machine_palmetto_class_init, 1630 }, { 1631 .name = MACHINE_TYPE_NAME("supermicrox11-bmc"), 1632 .parent = TYPE_ASPEED_MACHINE, 1633 .class_init = aspeed_machine_supermicrox11_bmc_class_init, 1634 }, { 1635 .name = MACHINE_TYPE_NAME("supermicro-x11spi-bmc"), 1636 .parent = TYPE_ASPEED_MACHINE, 1637 .class_init = aspeed_machine_supermicro_x11spi_bmc_class_init, 1638 }, { 1639 .name = MACHINE_TYPE_NAME("ast2500-evb"), 1640 .parent = TYPE_ASPEED_MACHINE, 1641 .class_init = aspeed_machine_ast2500_evb_class_init, 1642 }, { 1643 .name = MACHINE_TYPE_NAME("romulus-bmc"), 1644 .parent = TYPE_ASPEED_MACHINE, 1645 .class_init = aspeed_machine_romulus_class_init, 1646 }, { 1647 .name = MACHINE_TYPE_NAME("sonorapass-bmc"), 1648 .parent = TYPE_ASPEED_MACHINE, 1649 .class_init = aspeed_machine_sonorapass_class_init, 1650 }, { 1651 .name = MACHINE_TYPE_NAME("witherspoon-bmc"), 1652 .parent = TYPE_ASPEED_MACHINE, 1653 .class_init = aspeed_machine_witherspoon_class_init, 1654 }, { 1655 .name = MACHINE_TYPE_NAME("ast2600-evb"), 1656 .parent = TYPE_ASPEED_MACHINE, 1657 .class_init = aspeed_machine_ast2600_evb_class_init, 1658 }, { 1659 .name = MACHINE_TYPE_NAME("yosemitev2-bmc"), 1660 .parent = TYPE_ASPEED_MACHINE, 1661 .class_init = aspeed_machine_yosemitev2_class_init, 1662 }, { 1663 .name = MACHINE_TYPE_NAME("tacoma-bmc"), 1664 .parent = TYPE_ASPEED_MACHINE, 1665 .class_init = aspeed_machine_tacoma_class_init, 1666 }, { 1667 .name = MACHINE_TYPE_NAME("tiogapass-bmc"), 1668 .parent = TYPE_ASPEED_MACHINE, 1669 .class_init = aspeed_machine_tiogapass_class_init, 1670 }, { 1671 .name = MACHINE_TYPE_NAME("g220a-bmc"), 1672 .parent = TYPE_ASPEED_MACHINE, 1673 .class_init = aspeed_machine_g220a_class_init, 1674 }, { 1675 .name = MACHINE_TYPE_NAME("qcom-dc-scm-v1-bmc"), 1676 .parent = TYPE_ASPEED_MACHINE, 1677 .class_init = aspeed_machine_qcom_dc_scm_v1_class_init, 1678 }, { 1679 .name = MACHINE_TYPE_NAME("qcom-firework-bmc"), 1680 .parent = TYPE_ASPEED_MACHINE, 1681 .class_init = aspeed_machine_qcom_firework_class_init, 1682 }, { 1683 .name = MACHINE_TYPE_NAME("fp5280g2-bmc"), 1684 .parent = TYPE_ASPEED_MACHINE, 1685 .class_init = aspeed_machine_fp5280g2_class_init, 1686 }, { 1687 .name = MACHINE_TYPE_NAME("quanta-q71l-bmc"), 1688 .parent = TYPE_ASPEED_MACHINE, 1689 .class_init = aspeed_machine_quanta_q71l_class_init, 1690 }, { 1691 .name = MACHINE_TYPE_NAME("rainier-bmc"), 1692 .parent = TYPE_ASPEED_MACHINE, 1693 .class_init = aspeed_machine_rainier_class_init, 1694 }, { 1695 .name = MACHINE_TYPE_NAME("fuji-bmc"), 1696 .parent = TYPE_ASPEED_MACHINE, 1697 .class_init = aspeed_machine_fuji_class_init, 1698 }, { 1699 .name = MACHINE_TYPE_NAME("bletchley-bmc"), 1700 .parent = TYPE_ASPEED_MACHINE, 1701 .class_init = aspeed_machine_bletchley_class_init, 1702 }, { 1703 .name = MACHINE_TYPE_NAME("fby35-bmc"), 1704 .parent = MACHINE_TYPE_NAME("ast2600-evb"), 1705 .class_init = aspeed_machine_fby35_class_init, 1706 }, { 1707 .name = MACHINE_TYPE_NAME("ast1030-evb"), 1708 .parent = TYPE_ASPEED_MACHINE, 1709 .class_init = aspeed_minibmc_machine_ast1030_evb_class_init, 1710 }, { 1711 .name = TYPE_ASPEED_MACHINE, 1712 .parent = TYPE_MACHINE, 1713 .instance_size = sizeof(AspeedMachineState), 1714 .instance_init = aspeed_machine_instance_init, 1715 .class_size = sizeof(AspeedMachineClass), 1716 .class_init = aspeed_machine_class_init, 1717 .abstract = true, 1718 } 1719 }; 1720 1721 DEFINE_TYPES(aspeed_machine_types) 1722