1 /* 2 * OpenPOWER Palmetto BMC 3 * 4 * Andrew Jeffery <andrew@aj.id.au> 5 * 6 * Copyright 2016 IBM Corp. 7 * 8 * This code is licensed under the GPL version 2 or later. See 9 * the COPYING file in the top-level directory. 10 */ 11 12 #include "qemu/osdep.h" 13 #include "qapi/error.h" 14 #include "hw/arm/boot.h" 15 #include "hw/arm/aspeed.h" 16 #include "hw/arm/aspeed_soc.h" 17 #include "hw/i2c/i2c_mux_pca954x.h" 18 #include "hw/i2c/smbus_eeprom.h" 19 #include "hw/misc/pca9552.h" 20 #include "hw/sensor/tmp105.h" 21 #include "hw/misc/led.h" 22 #include "hw/qdev-properties.h" 23 #include "sysemu/block-backend.h" 24 #include "hw/loader.h" 25 #include "qemu/error-report.h" 26 #include "qemu/units.h" 27 28 static struct arm_boot_info aspeed_board_binfo = { 29 .board_id = -1, /* device-tree-only board */ 30 }; 31 32 struct AspeedMachineState { 33 /* Private */ 34 MachineState parent_obj; 35 /* Public */ 36 37 AspeedSoCState soc; 38 MemoryRegion ram_container; 39 MemoryRegion max_ram; 40 bool mmio_exec; 41 char *fmc_model; 42 char *spi_model; 43 }; 44 45 /* Palmetto hardware value: 0x120CE416 */ 46 #define PALMETTO_BMC_HW_STRAP1 ( \ 47 SCU_AST2400_HW_STRAP_DRAM_SIZE(DRAM_SIZE_256MB) | \ 48 SCU_AST2400_HW_STRAP_DRAM_CONFIG(2 /* DDR3 with CL=6, CWL=5 */) | \ 49 SCU_AST2400_HW_STRAP_ACPI_DIS | \ 50 SCU_AST2400_HW_STRAP_SET_CLK_SOURCE(AST2400_CLK_48M_IN) | \ 51 SCU_HW_STRAP_VGA_CLASS_CODE | \ 52 SCU_HW_STRAP_LPC_RESET_PIN | \ 53 SCU_HW_STRAP_SPI_MODE(SCU_HW_STRAP_SPI_M_S_EN) | \ 54 SCU_AST2400_HW_STRAP_SET_CPU_AHB_RATIO(AST2400_CPU_AHB_RATIO_2_1) | \ 55 SCU_HW_STRAP_SPI_WIDTH | \ 56 SCU_HW_STRAP_VGA_SIZE_SET(VGA_16M_DRAM) | \ 57 SCU_AST2400_HW_STRAP_BOOT_MODE(AST2400_SPI_BOOT)) 58 59 /* TODO: Find the actual hardware value */ 60 #define SUPERMICROX11_BMC_HW_STRAP1 ( \ 61 SCU_AST2400_HW_STRAP_DRAM_SIZE(DRAM_SIZE_128MB) | \ 62 SCU_AST2400_HW_STRAP_DRAM_CONFIG(2) | \ 63 SCU_AST2400_HW_STRAP_ACPI_DIS | \ 64 SCU_AST2400_HW_STRAP_SET_CLK_SOURCE(AST2400_CLK_48M_IN) | \ 65 SCU_HW_STRAP_VGA_CLASS_CODE | \ 66 SCU_HW_STRAP_LPC_RESET_PIN | \ 67 SCU_HW_STRAP_SPI_MODE(SCU_HW_STRAP_SPI_M_S_EN) | \ 68 SCU_AST2400_HW_STRAP_SET_CPU_AHB_RATIO(AST2400_CPU_AHB_RATIO_2_1) | \ 69 SCU_HW_STRAP_SPI_WIDTH | \ 70 SCU_HW_STRAP_VGA_SIZE_SET(VGA_16M_DRAM) | \ 71 SCU_AST2400_HW_STRAP_BOOT_MODE(AST2400_SPI_BOOT)) 72 73 /* AST2500 evb hardware value: 0xF100C2E6 */ 74 #define AST2500_EVB_HW_STRAP1 (( \ 75 AST2500_HW_STRAP1_DEFAULTS | \ 76 SCU_AST2500_HW_STRAP_SPI_AUTOFETCH_ENABLE | \ 77 SCU_AST2500_HW_STRAP_GPIO_STRAP_ENABLE | \ 78 SCU_AST2500_HW_STRAP_UART_DEBUG | \ 79 SCU_AST2500_HW_STRAP_DDR4_ENABLE | \ 80 SCU_HW_STRAP_MAC1_RGMII | \ 81 SCU_HW_STRAP_MAC0_RGMII) & \ 82 ~SCU_HW_STRAP_2ND_BOOT_WDT) 83 84 /* Romulus hardware value: 0xF10AD206 */ 85 #define ROMULUS_BMC_HW_STRAP1 ( \ 86 AST2500_HW_STRAP1_DEFAULTS | \ 87 SCU_AST2500_HW_STRAP_SPI_AUTOFETCH_ENABLE | \ 88 SCU_AST2500_HW_STRAP_GPIO_STRAP_ENABLE | \ 89 SCU_AST2500_HW_STRAP_UART_DEBUG | \ 90 SCU_AST2500_HW_STRAP_DDR4_ENABLE | \ 91 SCU_AST2500_HW_STRAP_ACPI_ENABLE | \ 92 SCU_HW_STRAP_SPI_MODE(SCU_HW_STRAP_SPI_MASTER)) 93 94 /* Sonorapass hardware value: 0xF100D216 */ 95 #define SONORAPASS_BMC_HW_STRAP1 ( \ 96 SCU_AST2500_HW_STRAP_SPI_AUTOFETCH_ENABLE | \ 97 SCU_AST2500_HW_STRAP_GPIO_STRAP_ENABLE | \ 98 SCU_AST2500_HW_STRAP_UART_DEBUG | \ 99 SCU_AST2500_HW_STRAP_RESERVED28 | \ 100 SCU_AST2500_HW_STRAP_DDR4_ENABLE | \ 101 SCU_HW_STRAP_VGA_CLASS_CODE | \ 102 SCU_HW_STRAP_LPC_RESET_PIN | \ 103 SCU_HW_STRAP_SPI_MODE(SCU_HW_STRAP_SPI_MASTER) | \ 104 SCU_AST2500_HW_STRAP_SET_AXI_AHB_RATIO(AXI_AHB_RATIO_2_1) | \ 105 SCU_HW_STRAP_VGA_BIOS_ROM | \ 106 SCU_HW_STRAP_VGA_SIZE_SET(VGA_16M_DRAM) | \ 107 SCU_AST2500_HW_STRAP_RESERVED1) 108 109 /* Swift hardware value: 0xF11AD206 */ 110 #define SWIFT_BMC_HW_STRAP1 ( \ 111 AST2500_HW_STRAP1_DEFAULTS | \ 112 SCU_AST2500_HW_STRAP_SPI_AUTOFETCH_ENABLE | \ 113 SCU_AST2500_HW_STRAP_GPIO_STRAP_ENABLE | \ 114 SCU_AST2500_HW_STRAP_UART_DEBUG | \ 115 SCU_AST2500_HW_STRAP_DDR4_ENABLE | \ 116 SCU_H_PLL_BYPASS_EN | \ 117 SCU_AST2500_HW_STRAP_ACPI_ENABLE | \ 118 SCU_HW_STRAP_SPI_MODE(SCU_HW_STRAP_SPI_MASTER)) 119 120 #define G220A_BMC_HW_STRAP1 ( \ 121 SCU_AST2500_HW_STRAP_SPI_AUTOFETCH_ENABLE | \ 122 SCU_AST2500_HW_STRAP_GPIO_STRAP_ENABLE | \ 123 SCU_AST2500_HW_STRAP_UART_DEBUG | \ 124 SCU_AST2500_HW_STRAP_RESERVED28 | \ 125 SCU_AST2500_HW_STRAP_DDR4_ENABLE | \ 126 SCU_HW_STRAP_2ND_BOOT_WDT | \ 127 SCU_HW_STRAP_VGA_CLASS_CODE | \ 128 SCU_HW_STRAP_LPC_RESET_PIN | \ 129 SCU_HW_STRAP_SPI_MODE(SCU_HW_STRAP_SPI_MASTER) | \ 130 SCU_AST2500_HW_STRAP_SET_AXI_AHB_RATIO(AXI_AHB_RATIO_2_1) | \ 131 SCU_HW_STRAP_VGA_SIZE_SET(VGA_64M_DRAM) | \ 132 SCU_AST2500_HW_STRAP_RESERVED1) 133 134 /* Witherspoon hardware value: 0xF10AD216 (but use romulus definition) */ 135 #define WITHERSPOON_BMC_HW_STRAP1 ROMULUS_BMC_HW_STRAP1 136 137 /* Quanta-Q71l hardware value */ 138 #define QUANTA_Q71L_BMC_HW_STRAP1 ( \ 139 SCU_AST2400_HW_STRAP_DRAM_SIZE(DRAM_SIZE_128MB) | \ 140 SCU_AST2400_HW_STRAP_DRAM_CONFIG(2/* DDR3 with CL=6, CWL=5 */) | \ 141 SCU_AST2400_HW_STRAP_ACPI_DIS | \ 142 SCU_AST2400_HW_STRAP_SET_CLK_SOURCE(AST2400_CLK_24M_IN) | \ 143 SCU_HW_STRAP_VGA_CLASS_CODE | \ 144 SCU_HW_STRAP_SPI_MODE(SCU_HW_STRAP_SPI_PASS_THROUGH) | \ 145 SCU_AST2400_HW_STRAP_SET_CPU_AHB_RATIO(AST2400_CPU_AHB_RATIO_2_1) | \ 146 SCU_HW_STRAP_SPI_WIDTH | \ 147 SCU_HW_STRAP_VGA_SIZE_SET(VGA_8M_DRAM) | \ 148 SCU_AST2400_HW_STRAP_BOOT_MODE(AST2400_SPI_BOOT)) 149 150 /* AST2600 evb hardware value */ 151 #define AST2600_EVB_HW_STRAP1 0x000000C0 152 #define AST2600_EVB_HW_STRAP2 0x00000003 153 154 /* Tacoma hardware value */ 155 #define TACOMA_BMC_HW_STRAP1 0x00000000 156 #define TACOMA_BMC_HW_STRAP2 0x00000040 157 158 /* Rainier hardware value: (QEMU prototype) */ 159 #define RAINIER_BMC_HW_STRAP1 0x00000000 160 #define RAINIER_BMC_HW_STRAP2 0x00000000 161 162 /* 163 * The max ram region is for firmwares that scan the address space 164 * with load/store to guess how much RAM the SoC has. 165 */ 166 static uint64_t max_ram_read(void *opaque, hwaddr offset, unsigned size) 167 { 168 return 0; 169 } 170 171 static void max_ram_write(void *opaque, hwaddr offset, uint64_t value, 172 unsigned size) 173 { 174 /* Discard writes */ 175 } 176 177 static const MemoryRegionOps max_ram_ops = { 178 .read = max_ram_read, 179 .write = max_ram_write, 180 .endianness = DEVICE_NATIVE_ENDIAN, 181 }; 182 183 #define AST_SMP_MAILBOX_BASE 0x1e6e2180 184 #define AST_SMP_MBOX_FIELD_ENTRY (AST_SMP_MAILBOX_BASE + 0x0) 185 #define AST_SMP_MBOX_FIELD_GOSIGN (AST_SMP_MAILBOX_BASE + 0x4) 186 #define AST_SMP_MBOX_FIELD_READY (AST_SMP_MAILBOX_BASE + 0x8) 187 #define AST_SMP_MBOX_FIELD_POLLINSN (AST_SMP_MAILBOX_BASE + 0xc) 188 #define AST_SMP_MBOX_CODE (AST_SMP_MAILBOX_BASE + 0x10) 189 #define AST_SMP_MBOX_GOSIGN 0xabbaab00 190 191 static void aspeed_write_smpboot(ARMCPU *cpu, 192 const struct arm_boot_info *info) 193 { 194 static const uint32_t poll_mailbox_ready[] = { 195 /* 196 * r2 = per-cpu go sign value 197 * r1 = AST_SMP_MBOX_FIELD_ENTRY 198 * r0 = AST_SMP_MBOX_FIELD_GOSIGN 199 */ 200 0xee100fb0, /* mrc p15, 0, r0, c0, c0, 5 */ 201 0xe21000ff, /* ands r0, r0, #255 */ 202 0xe59f201c, /* ldr r2, [pc, #28] */ 203 0xe1822000, /* orr r2, r2, r0 */ 204 205 0xe59f1018, /* ldr r1, [pc, #24] */ 206 0xe59f0018, /* ldr r0, [pc, #24] */ 207 208 0xe320f002, /* wfe */ 209 0xe5904000, /* ldr r4, [r0] */ 210 0xe1520004, /* cmp r2, r4 */ 211 0x1afffffb, /* bne <wfe> */ 212 0xe591f000, /* ldr pc, [r1] */ 213 AST_SMP_MBOX_GOSIGN, 214 AST_SMP_MBOX_FIELD_ENTRY, 215 AST_SMP_MBOX_FIELD_GOSIGN, 216 }; 217 218 rom_add_blob_fixed("aspeed.smpboot", poll_mailbox_ready, 219 sizeof(poll_mailbox_ready), 220 info->smp_loader_start); 221 } 222 223 static void aspeed_reset_secondary(ARMCPU *cpu, 224 const struct arm_boot_info *info) 225 { 226 AddressSpace *as = arm_boot_address_space(cpu, info); 227 CPUState *cs = CPU(cpu); 228 229 /* info->smp_bootreg_addr */ 230 address_space_stl_notdirty(as, AST_SMP_MBOX_FIELD_GOSIGN, 0, 231 MEMTXATTRS_UNSPECIFIED, NULL); 232 cpu_set_pc(cs, info->smp_loader_start); 233 } 234 235 #define FIRMWARE_ADDR 0x0 236 237 static void write_boot_rom(DriveInfo *dinfo, hwaddr addr, size_t rom_size, 238 Error **errp) 239 { 240 BlockBackend *blk = blk_by_legacy_dinfo(dinfo); 241 uint8_t *storage; 242 int64_t size; 243 244 /* The block backend size should have already been 'validated' by 245 * the creation of the m25p80 object. 246 */ 247 size = blk_getlength(blk); 248 if (size <= 0) { 249 error_setg(errp, "failed to get flash size"); 250 return; 251 } 252 253 if (rom_size > size) { 254 rom_size = size; 255 } 256 257 storage = g_new0(uint8_t, rom_size); 258 if (blk_pread(blk, 0, storage, rom_size) < 0) { 259 error_setg(errp, "failed to read the initial flash content"); 260 return; 261 } 262 263 rom_add_blob_fixed("aspeed.boot_rom", storage, rom_size, addr); 264 g_free(storage); 265 } 266 267 static void aspeed_board_init_flashes(AspeedSMCState *s, 268 const char *flashtype) 269 { 270 int i ; 271 272 for (i = 0; i < s->num_cs; ++i) { 273 AspeedSMCFlash *fl = &s->flashes[i]; 274 DriveInfo *dinfo = drive_get_next(IF_MTD); 275 qemu_irq cs_line; 276 277 fl->flash = qdev_new(flashtype); 278 if (dinfo) { 279 qdev_prop_set_drive(fl->flash, "drive", 280 blk_by_legacy_dinfo(dinfo)); 281 } 282 qdev_realize_and_unref(fl->flash, BUS(s->spi), &error_fatal); 283 284 cs_line = qdev_get_gpio_in_named(fl->flash, SSI_GPIO_CS, 0); 285 sysbus_connect_irq(SYS_BUS_DEVICE(s), i + 1, cs_line); 286 } 287 } 288 289 static void sdhci_attach_drive(SDHCIState *sdhci, DriveInfo *dinfo) 290 { 291 DeviceState *card; 292 293 if (!dinfo) { 294 return; 295 } 296 card = qdev_new(TYPE_SD_CARD); 297 qdev_prop_set_drive_err(card, "drive", blk_by_legacy_dinfo(dinfo), 298 &error_fatal); 299 qdev_realize_and_unref(card, 300 qdev_get_child_bus(DEVICE(sdhci), "sd-bus"), 301 &error_fatal); 302 } 303 304 static void aspeed_machine_init(MachineState *machine) 305 { 306 AspeedMachineState *bmc = ASPEED_MACHINE(machine); 307 AspeedMachineClass *amc = ASPEED_MACHINE_GET_CLASS(machine); 308 AspeedSoCClass *sc; 309 DriveInfo *drive0 = drive_get(IF_MTD, 0, 0); 310 ram_addr_t max_ram_size; 311 int i; 312 NICInfo *nd = &nd_table[0]; 313 314 memory_region_init(&bmc->ram_container, NULL, "aspeed-ram-container", 315 4 * GiB); 316 memory_region_add_subregion(&bmc->ram_container, 0, machine->ram); 317 318 object_initialize_child(OBJECT(machine), "soc", &bmc->soc, amc->soc_name); 319 320 sc = ASPEED_SOC_GET_CLASS(&bmc->soc); 321 322 /* 323 * This will error out if isize is not supported by memory controller. 324 */ 325 object_property_set_uint(OBJECT(&bmc->soc), "ram-size", machine->ram_size, 326 &error_fatal); 327 328 for (i = 0; i < sc->macs_num; i++) { 329 if ((amc->macs_mask & (1 << i)) && nd->used) { 330 qemu_check_nic_model(nd, TYPE_FTGMAC100); 331 qdev_set_nic_properties(DEVICE(&bmc->soc.ftgmac100[i]), nd); 332 nd++; 333 } 334 } 335 336 object_property_set_int(OBJECT(&bmc->soc), "hw-strap1", amc->hw_strap1, 337 &error_abort); 338 object_property_set_int(OBJECT(&bmc->soc), "hw-strap2", amc->hw_strap2, 339 &error_abort); 340 object_property_set_int(OBJECT(&bmc->soc), "num-cs", amc->num_cs, 341 &error_abort); 342 object_property_set_link(OBJECT(&bmc->soc), "dram", 343 OBJECT(machine->ram), &error_abort); 344 if (machine->kernel_filename) { 345 /* 346 * When booting with a -kernel command line there is no u-boot 347 * that runs to unlock the SCU. In this case set the default to 348 * be unlocked as the kernel expects 349 */ 350 object_property_set_int(OBJECT(&bmc->soc), "hw-prot-key", 351 ASPEED_SCU_PROT_KEY, &error_abort); 352 } 353 qdev_realize(DEVICE(&bmc->soc), NULL, &error_abort); 354 355 memory_region_add_subregion(get_system_memory(), 356 sc->memmap[ASPEED_DEV_SDRAM], 357 &bmc->ram_container); 358 359 max_ram_size = object_property_get_uint(OBJECT(&bmc->soc), "max-ram-size", 360 &error_abort); 361 memory_region_init_io(&bmc->max_ram, NULL, &max_ram_ops, NULL, 362 "max_ram", max_ram_size - machine->ram_size); 363 memory_region_add_subregion(&bmc->ram_container, machine->ram_size, &bmc->max_ram); 364 365 aspeed_board_init_flashes(&bmc->soc.fmc, bmc->fmc_model ? 366 bmc->fmc_model : amc->fmc_model); 367 aspeed_board_init_flashes(&bmc->soc.spi[0], bmc->spi_model ? 368 bmc->spi_model : amc->spi_model); 369 370 /* Install first FMC flash content as a boot rom. */ 371 if (drive0) { 372 AspeedSMCFlash *fl = &bmc->soc.fmc.flashes[0]; 373 MemoryRegion *boot_rom = g_new(MemoryRegion, 1); 374 375 /* 376 * create a ROM region using the default mapping window size of 377 * the flash module. The window size is 64MB for the AST2400 378 * SoC and 128MB for the AST2500 SoC, which is twice as big as 379 * needed by the flash modules of the Aspeed machines. 380 */ 381 if (ASPEED_MACHINE(machine)->mmio_exec) { 382 memory_region_init_alias(boot_rom, NULL, "aspeed.boot_rom", 383 &fl->mmio, 0, fl->size); 384 memory_region_add_subregion(get_system_memory(), FIRMWARE_ADDR, 385 boot_rom); 386 } else { 387 memory_region_init_rom(boot_rom, NULL, "aspeed.boot_rom", 388 fl->size, &error_abort); 389 memory_region_add_subregion(get_system_memory(), FIRMWARE_ADDR, 390 boot_rom); 391 write_boot_rom(drive0, FIRMWARE_ADDR, fl->size, &error_abort); 392 } 393 } 394 395 if (machine->kernel_filename && sc->num_cpus > 1) { 396 /* With no u-boot we must set up a boot stub for the secondary CPU */ 397 MemoryRegion *smpboot = g_new(MemoryRegion, 1); 398 memory_region_init_ram(smpboot, NULL, "aspeed.smpboot", 399 0x80, &error_abort); 400 memory_region_add_subregion(get_system_memory(), 401 AST_SMP_MAILBOX_BASE, smpboot); 402 403 aspeed_board_binfo.write_secondary_boot = aspeed_write_smpboot; 404 aspeed_board_binfo.secondary_cpu_reset_hook = aspeed_reset_secondary; 405 aspeed_board_binfo.smp_loader_start = AST_SMP_MBOX_CODE; 406 } 407 408 aspeed_board_binfo.ram_size = machine->ram_size; 409 aspeed_board_binfo.loader_start = sc->memmap[ASPEED_DEV_SDRAM]; 410 aspeed_board_binfo.nb_cpus = sc->num_cpus; 411 412 if (amc->i2c_init) { 413 amc->i2c_init(bmc); 414 } 415 416 for (i = 0; i < bmc->soc.sdhci.num_slots; i++) { 417 sdhci_attach_drive(&bmc->soc.sdhci.slots[i], drive_get_next(IF_SD)); 418 } 419 420 if (bmc->soc.emmc.num_slots) { 421 sdhci_attach_drive(&bmc->soc.emmc.slots[0], drive_get_next(IF_SD)); 422 } 423 424 arm_load_kernel(ARM_CPU(first_cpu), machine, &aspeed_board_binfo); 425 } 426 427 static void palmetto_bmc_i2c_init(AspeedMachineState *bmc) 428 { 429 AspeedSoCState *soc = &bmc->soc; 430 DeviceState *dev; 431 uint8_t *eeprom_buf = g_malloc0(32 * 1024); 432 433 /* The palmetto platform expects a ds3231 RTC but a ds1338 is 434 * enough to provide basic RTC features. Alarms will be missing */ 435 i2c_slave_create_simple(aspeed_i2c_get_bus(&soc->i2c, 0), "ds1338", 0x68); 436 437 smbus_eeprom_init_one(aspeed_i2c_get_bus(&soc->i2c, 0), 0x50, 438 eeprom_buf); 439 440 /* add a TMP423 temperature sensor */ 441 dev = DEVICE(i2c_slave_create_simple(aspeed_i2c_get_bus(&soc->i2c, 2), 442 "tmp423", 0x4c)); 443 object_property_set_int(OBJECT(dev), "temperature0", 31000, &error_abort); 444 object_property_set_int(OBJECT(dev), "temperature1", 28000, &error_abort); 445 object_property_set_int(OBJECT(dev), "temperature2", 20000, &error_abort); 446 object_property_set_int(OBJECT(dev), "temperature3", 110000, &error_abort); 447 } 448 449 static void quanta_q71l_bmc_i2c_init(AspeedMachineState *bmc) 450 { 451 AspeedSoCState *soc = &bmc->soc; 452 453 /* 454 * The quanta-q71l platform expects tmp75s which are compatible with 455 * tmp105s. 456 */ 457 i2c_slave_create_simple(aspeed_i2c_get_bus(&soc->i2c, 1), "tmp105", 0x4c); 458 i2c_slave_create_simple(aspeed_i2c_get_bus(&soc->i2c, 1), "tmp105", 0x4e); 459 i2c_slave_create_simple(aspeed_i2c_get_bus(&soc->i2c, 1), "tmp105", 0x4f); 460 461 /* TODO: i2c-1: Add baseboard FRU eeprom@54 24c64 */ 462 /* TODO: i2c-1: Add Frontpanel FRU eeprom@57 24c64 */ 463 /* TODO: Add Memory Riser i2c mux and eeproms. */ 464 465 i2c_slave_create_simple(aspeed_i2c_get_bus(&soc->i2c, 2), "pca9546", 0x74); 466 i2c_slave_create_simple(aspeed_i2c_get_bus(&soc->i2c, 2), "pca9548", 0x77); 467 468 /* TODO: i2c-3: Add BIOS FRU eeprom@56 24c64 */ 469 470 /* i2c-7 */ 471 i2c_slave_create_simple(aspeed_i2c_get_bus(&soc->i2c, 7), "pca9546", 0x70); 472 /* - i2c@0: pmbus@59 */ 473 /* - i2c@1: pmbus@58 */ 474 /* - i2c@2: pmbus@58 */ 475 /* - i2c@3: pmbus@59 */ 476 477 /* TODO: i2c-7: Add PDB FRU eeprom@52 */ 478 /* TODO: i2c-8: Add BMC FRU eeprom@50 */ 479 } 480 481 static void ast2500_evb_i2c_init(AspeedMachineState *bmc) 482 { 483 AspeedSoCState *soc = &bmc->soc; 484 uint8_t *eeprom_buf = g_malloc0(8 * 1024); 485 486 smbus_eeprom_init_one(aspeed_i2c_get_bus(&soc->i2c, 3), 0x50, 487 eeprom_buf); 488 489 /* The AST2500 EVB expects a LM75 but a TMP105 is compatible */ 490 i2c_slave_create_simple(aspeed_i2c_get_bus(&soc->i2c, 7), 491 TYPE_TMP105, 0x4d); 492 493 /* The AST2500 EVB does not have an RTC. Let's pretend that one is 494 * plugged on the I2C bus header */ 495 i2c_slave_create_simple(aspeed_i2c_get_bus(&soc->i2c, 11), "ds1338", 0x32); 496 } 497 498 static void ast2600_evb_i2c_init(AspeedMachineState *bmc) 499 { 500 /* Start with some devices on our I2C busses */ 501 ast2500_evb_i2c_init(bmc); 502 } 503 504 static void romulus_bmc_i2c_init(AspeedMachineState *bmc) 505 { 506 AspeedSoCState *soc = &bmc->soc; 507 508 /* The romulus board expects Epson RX8900 I2C RTC but a ds1338 is 509 * good enough */ 510 i2c_slave_create_simple(aspeed_i2c_get_bus(&soc->i2c, 11), "ds1338", 0x32); 511 } 512 513 static void swift_bmc_i2c_init(AspeedMachineState *bmc) 514 { 515 AspeedSoCState *soc = &bmc->soc; 516 517 i2c_slave_create_simple(aspeed_i2c_get_bus(&soc->i2c, 3), "pca9552", 0x60); 518 519 /* The swift board expects a TMP275 but a TMP105 is compatible */ 520 i2c_slave_create_simple(aspeed_i2c_get_bus(&soc->i2c, 7), "tmp105", 0x48); 521 /* The swift board expects a pca9551 but a pca9552 is compatible */ 522 i2c_slave_create_simple(aspeed_i2c_get_bus(&soc->i2c, 7), "pca9552", 0x60); 523 524 /* The swift board expects an Epson RX8900 RTC but a ds1338 is compatible */ 525 i2c_slave_create_simple(aspeed_i2c_get_bus(&soc->i2c, 8), "ds1338", 0x32); 526 i2c_slave_create_simple(aspeed_i2c_get_bus(&soc->i2c, 8), "pca9552", 0x60); 527 528 i2c_slave_create_simple(aspeed_i2c_get_bus(&soc->i2c, 9), "tmp423", 0x4c); 529 /* The swift board expects a pca9539 but a pca9552 is compatible */ 530 i2c_slave_create_simple(aspeed_i2c_get_bus(&soc->i2c, 9), "pca9552", 0x74); 531 532 i2c_slave_create_simple(aspeed_i2c_get_bus(&soc->i2c, 10), "tmp423", 0x4c); 533 /* The swift board expects a pca9539 but a pca9552 is compatible */ 534 i2c_slave_create_simple(aspeed_i2c_get_bus(&soc->i2c, 10), "pca9552", 535 0x74); 536 537 /* The swift board expects a TMP275 but a TMP105 is compatible */ 538 i2c_slave_create_simple(aspeed_i2c_get_bus(&soc->i2c, 12), "tmp105", 0x48); 539 i2c_slave_create_simple(aspeed_i2c_get_bus(&soc->i2c, 12), "tmp105", 0x4a); 540 } 541 542 static void sonorapass_bmc_i2c_init(AspeedMachineState *bmc) 543 { 544 AspeedSoCState *soc = &bmc->soc; 545 546 /* bus 2 : */ 547 i2c_slave_create_simple(aspeed_i2c_get_bus(&soc->i2c, 2), "tmp105", 0x48); 548 i2c_slave_create_simple(aspeed_i2c_get_bus(&soc->i2c, 2), "tmp105", 0x49); 549 /* bus 2 : pca9546 @ 0x73 */ 550 551 /* bus 3 : pca9548 @ 0x70 */ 552 553 /* bus 4 : */ 554 uint8_t *eeprom4_54 = g_malloc0(8 * 1024); 555 smbus_eeprom_init_one(aspeed_i2c_get_bus(&soc->i2c, 4), 0x54, 556 eeprom4_54); 557 /* PCA9539 @ 0x76, but PCA9552 is compatible */ 558 i2c_slave_create_simple(aspeed_i2c_get_bus(&soc->i2c, 4), "pca9552", 0x76); 559 /* PCA9539 @ 0x77, but PCA9552 is compatible */ 560 i2c_slave_create_simple(aspeed_i2c_get_bus(&soc->i2c, 4), "pca9552", 0x77); 561 562 /* bus 6 : */ 563 i2c_slave_create_simple(aspeed_i2c_get_bus(&soc->i2c, 6), "tmp105", 0x48); 564 i2c_slave_create_simple(aspeed_i2c_get_bus(&soc->i2c, 6), "tmp105", 0x49); 565 /* bus 6 : pca9546 @ 0x73 */ 566 567 /* bus 8 : */ 568 uint8_t *eeprom8_56 = g_malloc0(8 * 1024); 569 smbus_eeprom_init_one(aspeed_i2c_get_bus(&soc->i2c, 8), 0x56, 570 eeprom8_56); 571 i2c_slave_create_simple(aspeed_i2c_get_bus(&soc->i2c, 8), "pca9552", 0x60); 572 i2c_slave_create_simple(aspeed_i2c_get_bus(&soc->i2c, 8), "pca9552", 0x61); 573 /* bus 8 : adc128d818 @ 0x1d */ 574 /* bus 8 : adc128d818 @ 0x1f */ 575 576 /* 577 * bus 13 : pca9548 @ 0x71 578 * - channel 3: 579 * - tmm421 @ 0x4c 580 * - tmp421 @ 0x4e 581 * - tmp421 @ 0x4f 582 */ 583 584 } 585 586 static void witherspoon_bmc_i2c_init(AspeedMachineState *bmc) 587 { 588 static const struct { 589 unsigned gpio_id; 590 LEDColor color; 591 const char *description; 592 bool gpio_polarity; 593 } pca1_leds[] = { 594 {13, LED_COLOR_GREEN, "front-fault-4", GPIO_POLARITY_ACTIVE_LOW}, 595 {14, LED_COLOR_GREEN, "front-power-3", GPIO_POLARITY_ACTIVE_LOW}, 596 {15, LED_COLOR_GREEN, "front-id-5", GPIO_POLARITY_ACTIVE_LOW}, 597 }; 598 AspeedSoCState *soc = &bmc->soc; 599 uint8_t *eeprom_buf = g_malloc0(8 * 1024); 600 DeviceState *dev; 601 LEDState *led; 602 603 /* Bus 3: TODO bmp280@77 */ 604 /* Bus 3: TODO max31785@52 */ 605 /* Bus 3: TODO dps310@76 */ 606 dev = DEVICE(i2c_slave_new(TYPE_PCA9552, 0x60)); 607 qdev_prop_set_string(dev, "description", "pca1"); 608 i2c_slave_realize_and_unref(I2C_SLAVE(dev), 609 aspeed_i2c_get_bus(&soc->i2c, 3), 610 &error_fatal); 611 612 for (size_t i = 0; i < ARRAY_SIZE(pca1_leds); i++) { 613 led = led_create_simple(OBJECT(bmc), 614 pca1_leds[i].gpio_polarity, 615 pca1_leds[i].color, 616 pca1_leds[i].description); 617 qdev_connect_gpio_out(dev, pca1_leds[i].gpio_id, 618 qdev_get_gpio_in(DEVICE(led), 0)); 619 } 620 i2c_slave_create_simple(aspeed_i2c_get_bus(&soc->i2c, 4), "tmp423", 0x4c); 621 i2c_slave_create_simple(aspeed_i2c_get_bus(&soc->i2c, 5), "tmp423", 0x4c); 622 623 /* The Witherspoon expects a TMP275 but a TMP105 is compatible */ 624 i2c_slave_create_simple(aspeed_i2c_get_bus(&soc->i2c, 9), TYPE_TMP105, 625 0x4a); 626 627 /* The witherspoon board expects Epson RX8900 I2C RTC but a ds1338 is 628 * good enough */ 629 i2c_slave_create_simple(aspeed_i2c_get_bus(&soc->i2c, 11), "ds1338", 0x32); 630 631 smbus_eeprom_init_one(aspeed_i2c_get_bus(&soc->i2c, 11), 0x51, 632 eeprom_buf); 633 dev = DEVICE(i2c_slave_new(TYPE_PCA9552, 0x60)); 634 qdev_prop_set_string(dev, "description", "pca0"); 635 i2c_slave_realize_and_unref(I2C_SLAVE(dev), 636 aspeed_i2c_get_bus(&soc->i2c, 11), 637 &error_fatal); 638 /* Bus 11: TODO ucd90160@64 */ 639 } 640 641 static void g220a_bmc_i2c_init(AspeedMachineState *bmc) 642 { 643 AspeedSoCState *soc = &bmc->soc; 644 DeviceState *dev; 645 646 dev = DEVICE(i2c_slave_create_simple(aspeed_i2c_get_bus(&soc->i2c, 3), 647 "emc1413", 0x4c)); 648 object_property_set_int(OBJECT(dev), "temperature0", 31000, &error_abort); 649 object_property_set_int(OBJECT(dev), "temperature1", 28000, &error_abort); 650 object_property_set_int(OBJECT(dev), "temperature2", 20000, &error_abort); 651 652 dev = DEVICE(i2c_slave_create_simple(aspeed_i2c_get_bus(&soc->i2c, 12), 653 "emc1413", 0x4c)); 654 object_property_set_int(OBJECT(dev), "temperature0", 31000, &error_abort); 655 object_property_set_int(OBJECT(dev), "temperature1", 28000, &error_abort); 656 object_property_set_int(OBJECT(dev), "temperature2", 20000, &error_abort); 657 658 dev = DEVICE(i2c_slave_create_simple(aspeed_i2c_get_bus(&soc->i2c, 13), 659 "emc1413", 0x4c)); 660 object_property_set_int(OBJECT(dev), "temperature0", 31000, &error_abort); 661 object_property_set_int(OBJECT(dev), "temperature1", 28000, &error_abort); 662 object_property_set_int(OBJECT(dev), "temperature2", 20000, &error_abort); 663 664 static uint8_t eeprom_buf[2 * 1024] = { 665 0x01, 0x00, 0x00, 0x00, 0x01, 0x00, 0x00, 0xfe, 666 0x01, 0x06, 0x00, 0xc9, 0x42, 0x79, 0x74, 0x65, 667 0x64, 0x61, 0x6e, 0x63, 0x65, 0xc5, 0x47, 0x32, 668 0x32, 0x30, 0x41, 0xc4, 0x41, 0x41, 0x42, 0x42, 669 0xc4, 0x43, 0x43, 0x44, 0x44, 0xc4, 0x45, 0x45, 670 0x46, 0x46, 0xc4, 0x48, 0x48, 0x47, 0x47, 0xc1, 671 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0xa7, 672 }; 673 smbus_eeprom_init_one(aspeed_i2c_get_bus(&soc->i2c, 4), 0x57, 674 eeprom_buf); 675 } 676 677 static void aspeed_eeprom_init(I2CBus *bus, uint8_t addr, uint32_t rsize) 678 { 679 I2CSlave *i2c_dev = i2c_slave_new("at24c-eeprom", addr); 680 DeviceState *dev = DEVICE(i2c_dev); 681 682 qdev_prop_set_uint32(dev, "rom-size", rsize); 683 i2c_slave_realize_and_unref(i2c_dev, bus, &error_abort); 684 } 685 686 static void rainier_bmc_i2c_init(AspeedMachineState *bmc) 687 { 688 AspeedSoCState *soc = &bmc->soc; 689 I2CSlave *i2c_mux; 690 691 aspeed_eeprom_init(aspeed_i2c_get_bus(&soc->i2c, 0), 0x51, 32 * KiB); 692 693 /* The rainier expects a TMP275 but a TMP105 is compatible */ 694 i2c_slave_create_simple(aspeed_i2c_get_bus(&soc->i2c, 4), TYPE_TMP105, 695 0x48); 696 i2c_slave_create_simple(aspeed_i2c_get_bus(&soc->i2c, 4), TYPE_TMP105, 697 0x49); 698 i2c_slave_create_simple(aspeed_i2c_get_bus(&soc->i2c, 4), TYPE_TMP105, 699 0x4a); 700 i2c_mux = i2c_slave_create_simple(aspeed_i2c_get_bus(&soc->i2c, 4), 701 "pca9546", 0x70); 702 aspeed_eeprom_init(pca954x_i2c_get_bus(i2c_mux, 0), 0x50, 64 * KiB); 703 aspeed_eeprom_init(pca954x_i2c_get_bus(i2c_mux, 1), 0x51, 64 * KiB); 704 aspeed_eeprom_init(pca954x_i2c_get_bus(i2c_mux, 2), 0x52, 64 * KiB); 705 706 i2c_slave_create_simple(aspeed_i2c_get_bus(&soc->i2c, 5), TYPE_TMP105, 707 0x48); 708 i2c_slave_create_simple(aspeed_i2c_get_bus(&soc->i2c, 5), TYPE_TMP105, 709 0x49); 710 i2c_mux = i2c_slave_create_simple(aspeed_i2c_get_bus(&soc->i2c, 5), 711 "pca9546", 0x70); 712 aspeed_eeprom_init(pca954x_i2c_get_bus(i2c_mux, 0), 0x50, 64 * KiB); 713 aspeed_eeprom_init(pca954x_i2c_get_bus(i2c_mux, 1), 0x51, 64 * KiB); 714 715 i2c_slave_create_simple(aspeed_i2c_get_bus(&soc->i2c, 6), TYPE_TMP105, 716 0x48); 717 i2c_slave_create_simple(aspeed_i2c_get_bus(&soc->i2c, 6), TYPE_TMP105, 718 0x4a); 719 i2c_slave_create_simple(aspeed_i2c_get_bus(&soc->i2c, 6), TYPE_TMP105, 720 0x4b); 721 i2c_mux = i2c_slave_create_simple(aspeed_i2c_get_bus(&soc->i2c, 6), 722 "pca9546", 0x70); 723 aspeed_eeprom_init(pca954x_i2c_get_bus(i2c_mux, 0), 0x50, 64 * KiB); 724 aspeed_eeprom_init(pca954x_i2c_get_bus(i2c_mux, 1), 0x51, 64 * KiB); 725 aspeed_eeprom_init(pca954x_i2c_get_bus(i2c_mux, 2), 0x50, 64 * KiB); 726 aspeed_eeprom_init(pca954x_i2c_get_bus(i2c_mux, 3), 0x51, 64 * KiB); 727 728 /* Bus 7: TODO dps310@76 */ 729 /* Bus 7: TODO max31785@52 */ 730 i2c_slave_create_simple(aspeed_i2c_get_bus(&soc->i2c, 7), "pca9552", 0x61); 731 /* Bus 7: TODO si7021-a20@20 */ 732 i2c_slave_create_simple(aspeed_i2c_get_bus(&soc->i2c, 7), TYPE_TMP105, 733 0x48); 734 aspeed_eeprom_init(aspeed_i2c_get_bus(&soc->i2c, 7), 0x50, 64 * KiB); 735 aspeed_eeprom_init(aspeed_i2c_get_bus(&soc->i2c, 7), 0x51, 64 * KiB); 736 737 i2c_slave_create_simple(aspeed_i2c_get_bus(&soc->i2c, 8), TYPE_TMP105, 738 0x48); 739 i2c_slave_create_simple(aspeed_i2c_get_bus(&soc->i2c, 8), TYPE_TMP105, 740 0x4a); 741 aspeed_eeprom_init(aspeed_i2c_get_bus(&soc->i2c, 8), 0x50, 64 * KiB); 742 aspeed_eeprom_init(aspeed_i2c_get_bus(&soc->i2c, 8), 0x51, 64 * KiB); 743 i2c_slave_create_simple(aspeed_i2c_get_bus(&soc->i2c, 8), "pca9552", 0x61); 744 /* Bus 8: ucd90320@11 */ 745 /* Bus 8: ucd90320@b */ 746 /* Bus 8: ucd90320@c */ 747 748 i2c_slave_create_simple(aspeed_i2c_get_bus(&soc->i2c, 9), "tmp423", 0x4c); 749 i2c_slave_create_simple(aspeed_i2c_get_bus(&soc->i2c, 9), "tmp423", 0x4d); 750 aspeed_eeprom_init(aspeed_i2c_get_bus(&soc->i2c, 9), 0x50, 128 * KiB); 751 752 i2c_slave_create_simple(aspeed_i2c_get_bus(&soc->i2c, 10), "tmp423", 0x4c); 753 i2c_slave_create_simple(aspeed_i2c_get_bus(&soc->i2c, 10), "tmp423", 0x4d); 754 aspeed_eeprom_init(aspeed_i2c_get_bus(&soc->i2c, 10), 0x50, 128 * KiB); 755 756 i2c_slave_create_simple(aspeed_i2c_get_bus(&soc->i2c, 11), TYPE_TMP105, 757 0x48); 758 i2c_slave_create_simple(aspeed_i2c_get_bus(&soc->i2c, 11), TYPE_TMP105, 759 0x49); 760 i2c_mux = i2c_slave_create_simple(aspeed_i2c_get_bus(&soc->i2c, 11), 761 "pca9546", 0x70); 762 aspeed_eeprom_init(pca954x_i2c_get_bus(i2c_mux, 0), 0x50, 64 * KiB); 763 aspeed_eeprom_init(pca954x_i2c_get_bus(i2c_mux, 1), 0x51, 64 * KiB); 764 765 766 aspeed_eeprom_init(aspeed_i2c_get_bus(&soc->i2c, 13), 0x50, 64 * KiB); 767 768 aspeed_eeprom_init(aspeed_i2c_get_bus(&soc->i2c, 14), 0x50, 64 * KiB); 769 770 aspeed_eeprom_init(aspeed_i2c_get_bus(&soc->i2c, 15), 0x50, 64 * KiB); 771 } 772 773 static bool aspeed_get_mmio_exec(Object *obj, Error **errp) 774 { 775 return ASPEED_MACHINE(obj)->mmio_exec; 776 } 777 778 static void aspeed_set_mmio_exec(Object *obj, bool value, Error **errp) 779 { 780 ASPEED_MACHINE(obj)->mmio_exec = value; 781 } 782 783 static void aspeed_machine_instance_init(Object *obj) 784 { 785 ASPEED_MACHINE(obj)->mmio_exec = false; 786 } 787 788 static char *aspeed_get_fmc_model(Object *obj, Error **errp) 789 { 790 AspeedMachineState *bmc = ASPEED_MACHINE(obj); 791 return g_strdup(bmc->fmc_model); 792 } 793 794 static void aspeed_set_fmc_model(Object *obj, const char *value, Error **errp) 795 { 796 AspeedMachineState *bmc = ASPEED_MACHINE(obj); 797 798 g_free(bmc->fmc_model); 799 bmc->fmc_model = g_strdup(value); 800 } 801 802 static char *aspeed_get_spi_model(Object *obj, Error **errp) 803 { 804 AspeedMachineState *bmc = ASPEED_MACHINE(obj); 805 return g_strdup(bmc->spi_model); 806 } 807 808 static void aspeed_set_spi_model(Object *obj, const char *value, Error **errp) 809 { 810 AspeedMachineState *bmc = ASPEED_MACHINE(obj); 811 812 g_free(bmc->spi_model); 813 bmc->spi_model = g_strdup(value); 814 } 815 816 static void aspeed_machine_class_props_init(ObjectClass *oc) 817 { 818 object_class_property_add_bool(oc, "execute-in-place", 819 aspeed_get_mmio_exec, 820 aspeed_set_mmio_exec); 821 object_class_property_set_description(oc, "execute-in-place", 822 "boot directly from CE0 flash device"); 823 824 object_class_property_add_str(oc, "fmc-model", aspeed_get_fmc_model, 825 aspeed_set_fmc_model); 826 object_class_property_set_description(oc, "fmc-model", 827 "Change the FMC Flash model"); 828 object_class_property_add_str(oc, "spi-model", aspeed_get_spi_model, 829 aspeed_set_spi_model); 830 object_class_property_set_description(oc, "spi-model", 831 "Change the SPI Flash model"); 832 } 833 834 static int aspeed_soc_num_cpus(const char *soc_name) 835 { 836 AspeedSoCClass *sc = ASPEED_SOC_CLASS(object_class_by_name(soc_name)); 837 return sc->num_cpus; 838 } 839 840 static void aspeed_machine_class_init(ObjectClass *oc, void *data) 841 { 842 MachineClass *mc = MACHINE_CLASS(oc); 843 AspeedMachineClass *amc = ASPEED_MACHINE_CLASS(oc); 844 845 mc->init = aspeed_machine_init; 846 mc->no_floppy = 1; 847 mc->no_cdrom = 1; 848 mc->no_parallel = 1; 849 mc->default_ram_id = "ram"; 850 amc->macs_mask = ASPEED_MAC0_ON; 851 852 aspeed_machine_class_props_init(oc); 853 } 854 855 static void aspeed_machine_palmetto_class_init(ObjectClass *oc, void *data) 856 { 857 MachineClass *mc = MACHINE_CLASS(oc); 858 AspeedMachineClass *amc = ASPEED_MACHINE_CLASS(oc); 859 860 mc->desc = "OpenPOWER Palmetto BMC (ARM926EJ-S)"; 861 amc->soc_name = "ast2400-a1"; 862 amc->hw_strap1 = PALMETTO_BMC_HW_STRAP1; 863 amc->fmc_model = "n25q256a"; 864 amc->spi_model = "mx25l25635e"; 865 amc->num_cs = 1; 866 amc->i2c_init = palmetto_bmc_i2c_init; 867 mc->default_ram_size = 256 * MiB; 868 mc->default_cpus = mc->min_cpus = mc->max_cpus = 869 aspeed_soc_num_cpus(amc->soc_name); 870 }; 871 872 static void aspeed_machine_quanta_q71l_class_init(ObjectClass *oc, void *data) 873 { 874 MachineClass *mc = MACHINE_CLASS(oc); 875 AspeedMachineClass *amc = ASPEED_MACHINE_CLASS(oc); 876 877 mc->desc = "Quanta-Q71l BMC (ARM926EJ-S)"; 878 amc->soc_name = "ast2400-a1"; 879 amc->hw_strap1 = QUANTA_Q71L_BMC_HW_STRAP1; 880 amc->fmc_model = "n25q256a"; 881 amc->spi_model = "mx25l25635e"; 882 amc->num_cs = 1; 883 amc->i2c_init = quanta_q71l_bmc_i2c_init; 884 mc->default_ram_size = 128 * MiB; 885 mc->default_cpus = mc->min_cpus = mc->max_cpus = 886 aspeed_soc_num_cpus(amc->soc_name); 887 } 888 889 static void aspeed_machine_supermicrox11_bmc_class_init(ObjectClass *oc, 890 void *data) 891 { 892 MachineClass *mc = MACHINE_CLASS(oc); 893 AspeedMachineClass *amc = ASPEED_MACHINE_CLASS(oc); 894 895 mc->desc = "Supermicro X11 BMC (ARM926EJ-S)"; 896 amc->soc_name = "ast2400-a1"; 897 amc->hw_strap1 = SUPERMICROX11_BMC_HW_STRAP1; 898 amc->fmc_model = "mx25l25635e"; 899 amc->spi_model = "mx25l25635e"; 900 amc->num_cs = 1; 901 amc->macs_mask = ASPEED_MAC0_ON | ASPEED_MAC1_ON; 902 amc->i2c_init = palmetto_bmc_i2c_init; 903 mc->default_ram_size = 256 * MiB; 904 } 905 906 static void aspeed_machine_ast2500_evb_class_init(ObjectClass *oc, void *data) 907 { 908 MachineClass *mc = MACHINE_CLASS(oc); 909 AspeedMachineClass *amc = ASPEED_MACHINE_CLASS(oc); 910 911 mc->desc = "Aspeed AST2500 EVB (ARM1176)"; 912 amc->soc_name = "ast2500-a1"; 913 amc->hw_strap1 = AST2500_EVB_HW_STRAP1; 914 amc->fmc_model = "w25q256"; 915 amc->spi_model = "mx25l25635e"; 916 amc->num_cs = 1; 917 amc->i2c_init = ast2500_evb_i2c_init; 918 mc->default_ram_size = 512 * MiB; 919 mc->default_cpus = mc->min_cpus = mc->max_cpus = 920 aspeed_soc_num_cpus(amc->soc_name); 921 }; 922 923 static void aspeed_machine_romulus_class_init(ObjectClass *oc, void *data) 924 { 925 MachineClass *mc = MACHINE_CLASS(oc); 926 AspeedMachineClass *amc = ASPEED_MACHINE_CLASS(oc); 927 928 mc->desc = "OpenPOWER Romulus BMC (ARM1176)"; 929 amc->soc_name = "ast2500-a1"; 930 amc->hw_strap1 = ROMULUS_BMC_HW_STRAP1; 931 amc->fmc_model = "n25q256a"; 932 amc->spi_model = "mx66l1g45g"; 933 amc->num_cs = 2; 934 amc->i2c_init = romulus_bmc_i2c_init; 935 mc->default_ram_size = 512 * MiB; 936 mc->default_cpus = mc->min_cpus = mc->max_cpus = 937 aspeed_soc_num_cpus(amc->soc_name); 938 }; 939 940 static void aspeed_machine_sonorapass_class_init(ObjectClass *oc, void *data) 941 { 942 MachineClass *mc = MACHINE_CLASS(oc); 943 AspeedMachineClass *amc = ASPEED_MACHINE_CLASS(oc); 944 945 mc->desc = "OCP SonoraPass BMC (ARM1176)"; 946 amc->soc_name = "ast2500-a1"; 947 amc->hw_strap1 = SONORAPASS_BMC_HW_STRAP1; 948 amc->fmc_model = "mx66l1g45g"; 949 amc->spi_model = "mx66l1g45g"; 950 amc->num_cs = 2; 951 amc->i2c_init = sonorapass_bmc_i2c_init; 952 mc->default_ram_size = 512 * MiB; 953 mc->default_cpus = mc->min_cpus = mc->max_cpus = 954 aspeed_soc_num_cpus(amc->soc_name); 955 }; 956 957 static void aspeed_machine_swift_class_init(ObjectClass *oc, void *data) 958 { 959 MachineClass *mc = MACHINE_CLASS(oc); 960 AspeedMachineClass *amc = ASPEED_MACHINE_CLASS(oc); 961 962 mc->desc = "OpenPOWER Swift BMC (ARM1176)"; 963 amc->soc_name = "ast2500-a1"; 964 amc->hw_strap1 = SWIFT_BMC_HW_STRAP1; 965 amc->fmc_model = "mx66l1g45g"; 966 amc->spi_model = "mx66l1g45g"; 967 amc->num_cs = 2; 968 amc->i2c_init = swift_bmc_i2c_init; 969 mc->default_ram_size = 512 * MiB; 970 mc->default_cpus = mc->min_cpus = mc->max_cpus = 971 aspeed_soc_num_cpus(amc->soc_name); 972 973 mc->deprecation_reason = "redundant system. Please use a similar " 974 "OpenPOWER BMC, Witherspoon or Romulus."; 975 }; 976 977 static void aspeed_machine_witherspoon_class_init(ObjectClass *oc, void *data) 978 { 979 MachineClass *mc = MACHINE_CLASS(oc); 980 AspeedMachineClass *amc = ASPEED_MACHINE_CLASS(oc); 981 982 mc->desc = "OpenPOWER Witherspoon BMC (ARM1176)"; 983 amc->soc_name = "ast2500-a1"; 984 amc->hw_strap1 = WITHERSPOON_BMC_HW_STRAP1; 985 amc->fmc_model = "mx25l25635e"; 986 amc->spi_model = "mx66l1g45g"; 987 amc->num_cs = 2; 988 amc->i2c_init = witherspoon_bmc_i2c_init; 989 mc->default_ram_size = 512 * MiB; 990 mc->default_cpus = mc->min_cpus = mc->max_cpus = 991 aspeed_soc_num_cpus(amc->soc_name); 992 }; 993 994 static void aspeed_machine_ast2600_evb_class_init(ObjectClass *oc, void *data) 995 { 996 MachineClass *mc = MACHINE_CLASS(oc); 997 AspeedMachineClass *amc = ASPEED_MACHINE_CLASS(oc); 998 999 mc->desc = "Aspeed AST2600 EVB (Cortex-A7)"; 1000 amc->soc_name = "ast2600-a3"; 1001 amc->hw_strap1 = AST2600_EVB_HW_STRAP1; 1002 amc->hw_strap2 = AST2600_EVB_HW_STRAP2; 1003 amc->fmc_model = "w25q512jv"; 1004 amc->spi_model = "mx66u51235f"; 1005 amc->num_cs = 1; 1006 amc->macs_mask = ASPEED_MAC0_ON | ASPEED_MAC1_ON | ASPEED_MAC2_ON | 1007 ASPEED_MAC3_ON; 1008 amc->i2c_init = ast2600_evb_i2c_init; 1009 mc->default_ram_size = 1 * GiB; 1010 mc->default_cpus = mc->min_cpus = mc->max_cpus = 1011 aspeed_soc_num_cpus(amc->soc_name); 1012 }; 1013 1014 static void aspeed_machine_tacoma_class_init(ObjectClass *oc, void *data) 1015 { 1016 MachineClass *mc = MACHINE_CLASS(oc); 1017 AspeedMachineClass *amc = ASPEED_MACHINE_CLASS(oc); 1018 1019 mc->desc = "OpenPOWER Tacoma BMC (Cortex-A7)"; 1020 amc->soc_name = "ast2600-a3"; 1021 amc->hw_strap1 = TACOMA_BMC_HW_STRAP1; 1022 amc->hw_strap2 = TACOMA_BMC_HW_STRAP2; 1023 amc->fmc_model = "mx66l1g45g"; 1024 amc->spi_model = "mx66l1g45g"; 1025 amc->num_cs = 2; 1026 amc->macs_mask = ASPEED_MAC2_ON; 1027 amc->i2c_init = witherspoon_bmc_i2c_init; /* Same board layout */ 1028 mc->default_ram_size = 1 * GiB; 1029 mc->default_cpus = mc->min_cpus = mc->max_cpus = 1030 aspeed_soc_num_cpus(amc->soc_name); 1031 }; 1032 1033 static void aspeed_machine_g220a_class_init(ObjectClass *oc, void *data) 1034 { 1035 MachineClass *mc = MACHINE_CLASS(oc); 1036 AspeedMachineClass *amc = ASPEED_MACHINE_CLASS(oc); 1037 1038 mc->desc = "Bytedance G220A BMC (ARM1176)"; 1039 amc->soc_name = "ast2500-a1"; 1040 amc->hw_strap1 = G220A_BMC_HW_STRAP1; 1041 amc->fmc_model = "n25q512a"; 1042 amc->spi_model = "mx25l25635e"; 1043 amc->num_cs = 2; 1044 amc->macs_mask = ASPEED_MAC0_ON | ASPEED_MAC1_ON; 1045 amc->i2c_init = g220a_bmc_i2c_init; 1046 mc->default_ram_size = 1024 * MiB; 1047 mc->default_cpus = mc->min_cpus = mc->max_cpus = 1048 aspeed_soc_num_cpus(amc->soc_name); 1049 }; 1050 1051 static void aspeed_machine_rainier_class_init(ObjectClass *oc, void *data) 1052 { 1053 MachineClass *mc = MACHINE_CLASS(oc); 1054 AspeedMachineClass *amc = ASPEED_MACHINE_CLASS(oc); 1055 1056 mc->desc = "IBM Rainier BMC (Cortex-A7)"; 1057 amc->soc_name = "ast2600-a3"; 1058 amc->hw_strap1 = RAINIER_BMC_HW_STRAP1; 1059 amc->hw_strap2 = RAINIER_BMC_HW_STRAP2; 1060 amc->fmc_model = "mx66l1g45g"; 1061 amc->spi_model = "mx66l1g45g"; 1062 amc->num_cs = 2; 1063 amc->macs_mask = ASPEED_MAC2_ON | ASPEED_MAC3_ON; 1064 amc->i2c_init = rainier_bmc_i2c_init; 1065 mc->default_ram_size = 1 * GiB; 1066 mc->default_cpus = mc->min_cpus = mc->max_cpus = 1067 aspeed_soc_num_cpus(amc->soc_name); 1068 }; 1069 1070 static const TypeInfo aspeed_machine_types[] = { 1071 { 1072 .name = MACHINE_TYPE_NAME("palmetto-bmc"), 1073 .parent = TYPE_ASPEED_MACHINE, 1074 .class_init = aspeed_machine_palmetto_class_init, 1075 }, { 1076 .name = MACHINE_TYPE_NAME("supermicrox11-bmc"), 1077 .parent = TYPE_ASPEED_MACHINE, 1078 .class_init = aspeed_machine_supermicrox11_bmc_class_init, 1079 }, { 1080 .name = MACHINE_TYPE_NAME("ast2500-evb"), 1081 .parent = TYPE_ASPEED_MACHINE, 1082 .class_init = aspeed_machine_ast2500_evb_class_init, 1083 }, { 1084 .name = MACHINE_TYPE_NAME("romulus-bmc"), 1085 .parent = TYPE_ASPEED_MACHINE, 1086 .class_init = aspeed_machine_romulus_class_init, 1087 }, { 1088 .name = MACHINE_TYPE_NAME("swift-bmc"), 1089 .parent = TYPE_ASPEED_MACHINE, 1090 .class_init = aspeed_machine_swift_class_init, 1091 }, { 1092 .name = MACHINE_TYPE_NAME("sonorapass-bmc"), 1093 .parent = TYPE_ASPEED_MACHINE, 1094 .class_init = aspeed_machine_sonorapass_class_init, 1095 }, { 1096 .name = MACHINE_TYPE_NAME("witherspoon-bmc"), 1097 .parent = TYPE_ASPEED_MACHINE, 1098 .class_init = aspeed_machine_witherspoon_class_init, 1099 }, { 1100 .name = MACHINE_TYPE_NAME("ast2600-evb"), 1101 .parent = TYPE_ASPEED_MACHINE, 1102 .class_init = aspeed_machine_ast2600_evb_class_init, 1103 }, { 1104 .name = MACHINE_TYPE_NAME("tacoma-bmc"), 1105 .parent = TYPE_ASPEED_MACHINE, 1106 .class_init = aspeed_machine_tacoma_class_init, 1107 }, { 1108 .name = MACHINE_TYPE_NAME("g220a-bmc"), 1109 .parent = TYPE_ASPEED_MACHINE, 1110 .class_init = aspeed_machine_g220a_class_init, 1111 }, { 1112 .name = MACHINE_TYPE_NAME("quanta-q71l-bmc"), 1113 .parent = TYPE_ASPEED_MACHINE, 1114 .class_init = aspeed_machine_quanta_q71l_class_init, 1115 }, { 1116 .name = MACHINE_TYPE_NAME("rainier-bmc"), 1117 .parent = TYPE_ASPEED_MACHINE, 1118 .class_init = aspeed_machine_rainier_class_init, 1119 }, { 1120 .name = TYPE_ASPEED_MACHINE, 1121 .parent = TYPE_MACHINE, 1122 .instance_size = sizeof(AspeedMachineState), 1123 .instance_init = aspeed_machine_instance_init, 1124 .class_size = sizeof(AspeedMachineClass), 1125 .class_init = aspeed_machine_class_init, 1126 .abstract = true, 1127 } 1128 }; 1129 1130 DEFINE_TYPES(aspeed_machine_types) 1131