1 /* 2 * ASPEED Ast10x0 SoC 3 * 4 * Copyright (C) 2022 ASPEED Technology Inc. 5 * 6 * This code is licensed under the GPL version 2 or later. See 7 * the COPYING file in the top-level directory. 8 * 9 * Implementation extracted from the AST2600 and adapted for Ast10x0. 10 */ 11 12 #include "qemu/osdep.h" 13 #include "qapi/error.h" 14 #include "exec/address-spaces.h" 15 #include "sysemu/sysemu.h" 16 #include "hw/qdev-clock.h" 17 #include "hw/misc/unimp.h" 18 #include "hw/arm/aspeed_soc.h" 19 20 #define ASPEED_SOC_IOMEM_SIZE 0x00200000 21 22 static const hwaddr aspeed_soc_ast1030_memmap[] = { 23 [ASPEED_DEV_SRAM] = 0x00000000, 24 [ASPEED_DEV_SECSRAM] = 0x79000000, 25 [ASPEED_DEV_IOMEM] = 0x7E600000, 26 [ASPEED_DEV_PWM] = 0x7E610000, 27 [ASPEED_DEV_FMC] = 0x7E620000, 28 [ASPEED_DEV_SPI1] = 0x7E630000, 29 [ASPEED_DEV_SPI2] = 0x7E640000, 30 [ASPEED_DEV_UDC] = 0x7E6A2000, 31 [ASPEED_DEV_HACE] = 0x7E6D0000, 32 [ASPEED_DEV_SCU] = 0x7E6E2000, 33 [ASPEED_DEV_JTAG0] = 0x7E6E4000, 34 [ASPEED_DEV_JTAG1] = 0x7E6E4100, 35 [ASPEED_DEV_ADC] = 0x7E6E9000, 36 [ASPEED_DEV_ESPI] = 0x7E6EE000, 37 [ASPEED_DEV_SBC] = 0x7E6F2000, 38 [ASPEED_DEV_GPIO] = 0x7E780000, 39 [ASPEED_DEV_SGPIOM] = 0x7E780500, 40 [ASPEED_DEV_TIMER1] = 0x7E782000, 41 [ASPEED_DEV_UART1] = 0x7E783000, 42 [ASPEED_DEV_UART2] = 0x7E78D000, 43 [ASPEED_DEV_UART3] = 0x7E78E000, 44 [ASPEED_DEV_UART4] = 0x7E78F000, 45 [ASPEED_DEV_UART5] = 0x7E784000, 46 [ASPEED_DEV_UART6] = 0x7E790000, 47 [ASPEED_DEV_UART7] = 0x7E790100, 48 [ASPEED_DEV_UART8] = 0x7E790200, 49 [ASPEED_DEV_UART9] = 0x7E790300, 50 [ASPEED_DEV_UART10] = 0x7E790400, 51 [ASPEED_DEV_UART11] = 0x7E790500, 52 [ASPEED_DEV_UART12] = 0x7E790600, 53 [ASPEED_DEV_UART13] = 0x7E790700, 54 [ASPEED_DEV_WDT] = 0x7E785000, 55 [ASPEED_DEV_LPC] = 0x7E789000, 56 [ASPEED_DEV_PECI] = 0x7E78B000, 57 [ASPEED_DEV_I3C] = 0x7E7A0000, 58 [ASPEED_DEV_I2C] = 0x7E7B0000, 59 }; 60 61 static const int aspeed_soc_ast1030_irqmap[] = { 62 [ASPEED_DEV_UART1] = 47, 63 [ASPEED_DEV_UART2] = 48, 64 [ASPEED_DEV_UART3] = 49, 65 [ASPEED_DEV_UART4] = 50, 66 [ASPEED_DEV_UART5] = 8, 67 [ASPEED_DEV_UART6] = 57, 68 [ASPEED_DEV_UART7] = 58, 69 [ASPEED_DEV_UART8] = 59, 70 [ASPEED_DEV_UART9] = 60, 71 [ASPEED_DEV_UART10] = 61, 72 [ASPEED_DEV_UART11] = 62, 73 [ASPEED_DEV_UART12] = 63, 74 [ASPEED_DEV_UART13] = 64, 75 [ASPEED_DEV_GPIO] = 11, 76 [ASPEED_DEV_TIMER1] = 16, 77 [ASPEED_DEV_TIMER2] = 17, 78 [ASPEED_DEV_TIMER3] = 18, 79 [ASPEED_DEV_TIMER4] = 19, 80 [ASPEED_DEV_TIMER5] = 20, 81 [ASPEED_DEV_TIMER6] = 21, 82 [ASPEED_DEV_TIMER7] = 22, 83 [ASPEED_DEV_TIMER8] = 23, 84 [ASPEED_DEV_WDT] = 24, 85 [ASPEED_DEV_LPC] = 35, 86 [ASPEED_DEV_PECI] = 38, 87 [ASPEED_DEV_FMC] = 39, 88 [ASPEED_DEV_ESPI] = 42, 89 [ASPEED_DEV_PWM] = 44, 90 [ASPEED_DEV_ADC] = 46, 91 [ASPEED_DEV_SPI1] = 65, 92 [ASPEED_DEV_SPI2] = 66, 93 [ASPEED_DEV_I3C] = 102, /* 102 -> 105 */ 94 [ASPEED_DEV_I2C] = 110, /* 110 ~ 123 */ 95 [ASPEED_DEV_KCS] = 138, /* 138 -> 142 */ 96 [ASPEED_DEV_UDC] = 9, 97 [ASPEED_DEV_SGPIOM] = 51, 98 [ASPEED_DEV_JTAG0] = 27, 99 [ASPEED_DEV_JTAG1] = 53, 100 }; 101 102 static qemu_irq aspeed_soc_ast1030_get_irq(AspeedSoCState *s, int dev) 103 { 104 Aspeed10x0SoCState *a = ASPEED10X0_SOC(s); 105 AspeedSoCClass *sc = ASPEED_SOC_GET_CLASS(s); 106 107 return qdev_get_gpio_in(DEVICE(&a->armv7m), sc->irqmap[dev]); 108 } 109 110 static void aspeed_soc_ast1030_init(Object *obj) 111 { 112 Aspeed10x0SoCState *a = ASPEED10X0_SOC(obj); 113 AspeedSoCState *s = ASPEED_SOC(obj); 114 AspeedSoCClass *sc = ASPEED_SOC_GET_CLASS(s); 115 char socname[8]; 116 char typename[64]; 117 int i; 118 119 if (sscanf(sc->name, "%7s", socname) != 1) { 120 g_assert_not_reached(); 121 } 122 123 object_initialize_child(obj, "armv7m", &a->armv7m, TYPE_ARMV7M); 124 125 s->sysclk = qdev_init_clock_in(DEVICE(s), "sysclk", NULL, NULL, 0); 126 127 snprintf(typename, sizeof(typename), "aspeed.scu-%s", socname); 128 object_initialize_child(obj, "scu", &s->scu, typename); 129 qdev_prop_set_uint32(DEVICE(&s->scu), "silicon-rev", sc->silicon_rev); 130 131 object_property_add_alias(obj, "hw-strap1", OBJECT(&s->scu), "hw-strap1"); 132 object_property_add_alias(obj, "hw-strap2", OBJECT(&s->scu), "hw-strap2"); 133 134 snprintf(typename, sizeof(typename), "aspeed.i2c-%s", socname); 135 object_initialize_child(obj, "i2c", &s->i2c, typename); 136 137 object_initialize_child(obj, "i3c", &s->i3c, TYPE_ASPEED_I3C); 138 139 snprintf(typename, sizeof(typename), "aspeed.timer-%s", socname); 140 object_initialize_child(obj, "timerctrl", &s->timerctrl, typename); 141 142 snprintf(typename, sizeof(typename), "aspeed.adc-%s", socname); 143 object_initialize_child(obj, "adc", &s->adc, typename); 144 145 snprintf(typename, sizeof(typename), "aspeed.fmc-%s", socname); 146 object_initialize_child(obj, "fmc", &s->fmc, typename); 147 148 for (i = 0; i < sc->spis_num; i++) { 149 snprintf(typename, sizeof(typename), "aspeed.spi%d-%s", i + 1, socname); 150 object_initialize_child(obj, "spi[*]", &s->spi[i], typename); 151 } 152 153 object_initialize_child(obj, "lpc", &s->lpc, TYPE_ASPEED_LPC); 154 155 object_initialize_child(obj, "peci", &s->peci, TYPE_ASPEED_PECI); 156 157 object_initialize_child(obj, "sbc", &s->sbc, TYPE_ASPEED_SBC); 158 159 for (i = 0; i < sc->wdts_num; i++) { 160 snprintf(typename, sizeof(typename), "aspeed.wdt-%s", socname); 161 object_initialize_child(obj, "wdt[*]", &s->wdt[i], typename); 162 } 163 164 for (i = 0; i < sc->uarts_num; i++) { 165 object_initialize_child(obj, "uart[*]", &s->uart[i], TYPE_SERIAL_MM); 166 } 167 168 snprintf(typename, sizeof(typename), "aspeed.gpio-%s", socname); 169 object_initialize_child(obj, "gpio", &s->gpio, typename); 170 171 snprintf(typename, sizeof(typename), "aspeed.hace-%s", socname); 172 object_initialize_child(obj, "hace", &s->hace, typename); 173 174 object_initialize_child(obj, "iomem", &s->iomem, TYPE_UNIMPLEMENTED_DEVICE); 175 object_initialize_child(obj, "sbc-unimplemented", &s->sbc_unimplemented, 176 TYPE_UNIMPLEMENTED_DEVICE); 177 object_initialize_child(obj, "pwm", &s->pwm, TYPE_UNIMPLEMENTED_DEVICE); 178 object_initialize_child(obj, "espi", &s->espi, TYPE_UNIMPLEMENTED_DEVICE); 179 object_initialize_child(obj, "udc", &s->udc, TYPE_UNIMPLEMENTED_DEVICE); 180 object_initialize_child(obj, "sgpiom", &s->sgpiom, 181 TYPE_UNIMPLEMENTED_DEVICE); 182 object_initialize_child(obj, "jtag[0]", &s->jtag[0], 183 TYPE_UNIMPLEMENTED_DEVICE); 184 object_initialize_child(obj, "jtag[1]", &s->jtag[1], 185 TYPE_UNIMPLEMENTED_DEVICE); 186 } 187 188 static void aspeed_soc_ast1030_realize(DeviceState *dev_soc, Error **errp) 189 { 190 Aspeed10x0SoCState *a = ASPEED10X0_SOC(dev_soc); 191 AspeedSoCState *s = ASPEED_SOC(dev_soc); 192 AspeedSoCClass *sc = ASPEED_SOC_GET_CLASS(s); 193 DeviceState *armv7m; 194 Error *err = NULL; 195 int i; 196 g_autofree char *sram_name = NULL; 197 198 if (!clock_has_source(s->sysclk)) { 199 error_setg(errp, "sysclk clock must be wired up by the board code"); 200 return; 201 } 202 203 /* General I/O memory space to catch all unimplemented device */ 204 aspeed_mmio_map_unimplemented(s, SYS_BUS_DEVICE(&s->iomem), "aspeed.io", 205 sc->memmap[ASPEED_DEV_IOMEM], 206 ASPEED_SOC_IOMEM_SIZE); 207 aspeed_mmio_map_unimplemented(s, SYS_BUS_DEVICE(&s->sbc_unimplemented), 208 "aspeed.sbc", sc->memmap[ASPEED_DEV_SBC], 209 0x40000); 210 211 /* AST1030 CPU Core */ 212 armv7m = DEVICE(&a->armv7m); 213 qdev_prop_set_uint32(armv7m, "num-irq", 256); 214 qdev_prop_set_string(armv7m, "cpu-type", aspeed_soc_cpu_type(sc)); 215 qdev_connect_clock_in(armv7m, "cpuclk", s->sysclk); 216 object_property_set_link(OBJECT(&a->armv7m), "memory", 217 OBJECT(s->memory), &error_abort); 218 sysbus_realize(SYS_BUS_DEVICE(&a->armv7m), &error_abort); 219 220 /* Internal SRAM */ 221 sram_name = g_strdup_printf("aspeed.sram.%d", 222 CPU(a->armv7m.cpu)->cpu_index); 223 memory_region_init_ram(&s->sram, OBJECT(s), sram_name, sc->sram_size, &err); 224 if (err != NULL) { 225 error_propagate(errp, err); 226 return; 227 } 228 memory_region_add_subregion(s->memory, 229 sc->memmap[ASPEED_DEV_SRAM], 230 &s->sram); 231 memory_region_init_ram(&s->secsram, OBJECT(s), "sec.sram", 232 sc->secsram_size, &err); 233 if (err != NULL) { 234 error_propagate(errp, err); 235 return; 236 } 237 memory_region_add_subregion(s->memory, sc->memmap[ASPEED_DEV_SECSRAM], 238 &s->secsram); 239 240 /* SCU */ 241 if (!sysbus_realize(SYS_BUS_DEVICE(&s->scu), errp)) { 242 return; 243 } 244 aspeed_mmio_map(s, SYS_BUS_DEVICE(&s->scu), 0, sc->memmap[ASPEED_DEV_SCU]); 245 246 /* I2C */ 247 248 object_property_set_link(OBJECT(&s->i2c), "dram", OBJECT(&s->sram), 249 &error_abort); 250 if (!sysbus_realize(SYS_BUS_DEVICE(&s->i2c), errp)) { 251 return; 252 } 253 aspeed_mmio_map(s, SYS_BUS_DEVICE(&s->i2c), 0, sc->memmap[ASPEED_DEV_I2C]); 254 for (i = 0; i < ASPEED_I2C_GET_CLASS(&s->i2c)->num_busses; i++) { 255 qemu_irq irq = qdev_get_gpio_in(DEVICE(&a->armv7m), 256 sc->irqmap[ASPEED_DEV_I2C] + i); 257 /* The AST1030 I2C controller has one IRQ per bus. */ 258 sysbus_connect_irq(SYS_BUS_DEVICE(&s->i2c.busses[i]), 0, irq); 259 } 260 261 /* I3C */ 262 if (!sysbus_realize(SYS_BUS_DEVICE(&s->i3c), errp)) { 263 return; 264 } 265 aspeed_mmio_map(s, SYS_BUS_DEVICE(&s->i3c), 0, sc->memmap[ASPEED_DEV_I3C]); 266 for (i = 0; i < ASPEED_I3C_NR_DEVICES; i++) { 267 qemu_irq irq = qdev_get_gpio_in(DEVICE(&a->armv7m), 268 sc->irqmap[ASPEED_DEV_I3C] + i); 269 /* The AST1030 I3C controller has one IRQ per bus. */ 270 sysbus_connect_irq(SYS_BUS_DEVICE(&s->i3c.devices[i]), 0, irq); 271 } 272 273 /* PECI */ 274 if (!sysbus_realize(SYS_BUS_DEVICE(&s->peci), errp)) { 275 return; 276 } 277 aspeed_mmio_map(s, SYS_BUS_DEVICE(&s->peci), 0, 278 sc->memmap[ASPEED_DEV_PECI]); 279 sysbus_connect_irq(SYS_BUS_DEVICE(&s->peci), 0, 280 aspeed_soc_get_irq(s, ASPEED_DEV_PECI)); 281 282 /* LPC */ 283 if (!sysbus_realize(SYS_BUS_DEVICE(&s->lpc), errp)) { 284 return; 285 } 286 aspeed_mmio_map(s, SYS_BUS_DEVICE(&s->lpc), 0, sc->memmap[ASPEED_DEV_LPC]); 287 288 /* Connect the LPC IRQ to the GIC. It is otherwise unused. */ 289 sysbus_connect_irq(SYS_BUS_DEVICE(&s->lpc), 0, 290 aspeed_soc_get_irq(s, ASPEED_DEV_LPC)); 291 292 /* 293 * On the AST1030 LPC subdevice IRQs are connected straight to the GIC. 294 */ 295 sysbus_connect_irq(SYS_BUS_DEVICE(&s->lpc), 1 + aspeed_lpc_kcs_1, 296 qdev_get_gpio_in(DEVICE(&a->armv7m), 297 sc->irqmap[ASPEED_DEV_KCS] + aspeed_lpc_kcs_1)); 298 299 sysbus_connect_irq(SYS_BUS_DEVICE(&s->lpc), 1 + aspeed_lpc_kcs_2, 300 qdev_get_gpio_in(DEVICE(&a->armv7m), 301 sc->irqmap[ASPEED_DEV_KCS] + aspeed_lpc_kcs_2)); 302 303 sysbus_connect_irq(SYS_BUS_DEVICE(&s->lpc), 1 + aspeed_lpc_kcs_3, 304 qdev_get_gpio_in(DEVICE(&a->armv7m), 305 sc->irqmap[ASPEED_DEV_KCS] + aspeed_lpc_kcs_3)); 306 307 sysbus_connect_irq(SYS_BUS_DEVICE(&s->lpc), 1 + aspeed_lpc_kcs_4, 308 qdev_get_gpio_in(DEVICE(&a->armv7m), 309 sc->irqmap[ASPEED_DEV_KCS] + aspeed_lpc_kcs_4)); 310 311 /* UART */ 312 if (!aspeed_soc_uart_realize(s, errp)) { 313 return; 314 } 315 316 /* Timer */ 317 object_property_set_link(OBJECT(&s->timerctrl), "scu", OBJECT(&s->scu), 318 &error_abort); 319 if (!sysbus_realize(SYS_BUS_DEVICE(&s->timerctrl), errp)) { 320 return; 321 } 322 aspeed_mmio_map(s, SYS_BUS_DEVICE(&s->timerctrl), 0, 323 sc->memmap[ASPEED_DEV_TIMER1]); 324 for (i = 0; i < ASPEED_TIMER_NR_TIMERS; i++) { 325 qemu_irq irq = aspeed_soc_get_irq(s, ASPEED_DEV_TIMER1 + i); 326 sysbus_connect_irq(SYS_BUS_DEVICE(&s->timerctrl), i, irq); 327 } 328 329 /* ADC */ 330 if (!sysbus_realize(SYS_BUS_DEVICE(&s->adc), errp)) { 331 return; 332 } 333 aspeed_mmio_map(s, SYS_BUS_DEVICE(&s->adc), 0, sc->memmap[ASPEED_DEV_ADC]); 334 sysbus_connect_irq(SYS_BUS_DEVICE(&s->adc), 0, 335 aspeed_soc_get_irq(s, ASPEED_DEV_ADC)); 336 337 /* FMC, The number of CS is set at the board level */ 338 object_property_set_link(OBJECT(&s->fmc), "dram", OBJECT(&s->sram), 339 &error_abort); 340 if (!sysbus_realize(SYS_BUS_DEVICE(&s->fmc), errp)) { 341 return; 342 } 343 aspeed_mmio_map(s, SYS_BUS_DEVICE(&s->fmc), 0, sc->memmap[ASPEED_DEV_FMC]); 344 aspeed_mmio_map(s, SYS_BUS_DEVICE(&s->fmc), 1, 345 ASPEED_SMC_GET_CLASS(&s->fmc)->flash_window_base); 346 sysbus_connect_irq(SYS_BUS_DEVICE(&s->fmc), 0, 347 aspeed_soc_get_irq(s, ASPEED_DEV_FMC)); 348 349 /* SPI */ 350 for (i = 0; i < sc->spis_num; i++) { 351 object_property_set_link(OBJECT(&s->spi[i]), "dram", 352 OBJECT(&s->sram), &error_abort); 353 if (!sysbus_realize(SYS_BUS_DEVICE(&s->spi[i]), errp)) { 354 return; 355 } 356 aspeed_mmio_map(s, SYS_BUS_DEVICE(&s->spi[i]), 0, 357 sc->memmap[ASPEED_DEV_SPI1 + i]); 358 aspeed_mmio_map(s, SYS_BUS_DEVICE(&s->spi[i]), 1, 359 ASPEED_SMC_GET_CLASS(&s->spi[i])->flash_window_base); 360 } 361 362 /* Secure Boot Controller */ 363 if (!sysbus_realize(SYS_BUS_DEVICE(&s->sbc), errp)) { 364 return; 365 } 366 aspeed_mmio_map(s, SYS_BUS_DEVICE(&s->sbc), 0, sc->memmap[ASPEED_DEV_SBC]); 367 368 /* HACE */ 369 object_property_set_link(OBJECT(&s->hace), "dram", OBJECT(&s->sram), 370 &error_abort); 371 if (!sysbus_realize(SYS_BUS_DEVICE(&s->hace), errp)) { 372 return; 373 } 374 aspeed_mmio_map(s, SYS_BUS_DEVICE(&s->hace), 0, 375 sc->memmap[ASPEED_DEV_HACE]); 376 sysbus_connect_irq(SYS_BUS_DEVICE(&s->hace), 0, 377 aspeed_soc_get_irq(s, ASPEED_DEV_HACE)); 378 379 /* Watch dog */ 380 for (i = 0; i < sc->wdts_num; i++) { 381 AspeedWDTClass *awc = ASPEED_WDT_GET_CLASS(&s->wdt[i]); 382 hwaddr wdt_offset = sc->memmap[ASPEED_DEV_WDT] + i * awc->iosize; 383 384 object_property_set_link(OBJECT(&s->wdt[i]), "scu", OBJECT(&s->scu), 385 &error_abort); 386 if (!sysbus_realize(SYS_BUS_DEVICE(&s->wdt[i]), errp)) { 387 return; 388 } 389 aspeed_mmio_map(s, SYS_BUS_DEVICE(&s->wdt[i]), 0, wdt_offset); 390 } 391 392 /* GPIO */ 393 if (!sysbus_realize(SYS_BUS_DEVICE(&s->gpio), errp)) { 394 return; 395 } 396 aspeed_mmio_map(s, SYS_BUS_DEVICE(&s->gpio), 0, 397 sc->memmap[ASPEED_DEV_GPIO]); 398 sysbus_connect_irq(SYS_BUS_DEVICE(&s->gpio), 0, 399 aspeed_soc_get_irq(s, ASPEED_DEV_GPIO)); 400 401 aspeed_mmio_map_unimplemented(s, SYS_BUS_DEVICE(&s->pwm), "aspeed.pwm", 402 sc->memmap[ASPEED_DEV_PWM], 0x100); 403 404 aspeed_mmio_map_unimplemented(s, SYS_BUS_DEVICE(&s->espi), "aspeed.espi", 405 sc->memmap[ASPEED_DEV_ESPI], 0x800); 406 407 aspeed_mmio_map_unimplemented(s, SYS_BUS_DEVICE(&s->udc), "aspeed.udc", 408 sc->memmap[ASPEED_DEV_UDC], 0x1000); 409 aspeed_mmio_map_unimplemented(s, SYS_BUS_DEVICE(&s->sgpiom), "aspeed.sgpiom", 410 sc->memmap[ASPEED_DEV_SGPIOM], 0x100); 411 412 aspeed_mmio_map_unimplemented(s, SYS_BUS_DEVICE(&s->jtag[0]), "aspeed.jtag", 413 sc->memmap[ASPEED_DEV_JTAG0], 0x20); 414 aspeed_mmio_map_unimplemented(s, SYS_BUS_DEVICE(&s->jtag[1]), "aspeed.jtag", 415 sc->memmap[ASPEED_DEV_JTAG1], 0x20); 416 } 417 418 static void aspeed_soc_ast1030_class_init(ObjectClass *klass, void *data) 419 { 420 static const char * const valid_cpu_types[] = { 421 ARM_CPU_TYPE_NAME("cortex-m4"), /* TODO cortex-m4f */ 422 NULL 423 }; 424 DeviceClass *dc = DEVICE_CLASS(klass); 425 AspeedSoCClass *sc = ASPEED_SOC_CLASS(dc); 426 427 dc->realize = aspeed_soc_ast1030_realize; 428 429 sc->name = "ast1030-a1"; 430 sc->valid_cpu_types = valid_cpu_types; 431 sc->silicon_rev = AST1030_A1_SILICON_REV; 432 sc->sram_size = 0xc0000; 433 sc->secsram_size = 0x40000; /* 256 * KiB */ 434 sc->spis_num = 2; 435 sc->ehcis_num = 0; 436 sc->wdts_num = 4; 437 sc->macs_num = 1; 438 sc->uarts_num = 13; 439 sc->uarts_base = ASPEED_DEV_UART1; 440 sc->irqmap = aspeed_soc_ast1030_irqmap; 441 sc->memmap = aspeed_soc_ast1030_memmap; 442 sc->num_cpus = 1; 443 sc->get_irq = aspeed_soc_ast1030_get_irq; 444 } 445 446 static const TypeInfo aspeed_soc_ast10x0_types[] = { 447 { 448 .name = TYPE_ASPEED10X0_SOC, 449 .parent = TYPE_ASPEED_SOC, 450 .instance_size = sizeof(Aspeed10x0SoCState), 451 .abstract = true, 452 }, { 453 .name = "ast1030-a1", 454 .parent = TYPE_ASPEED10X0_SOC, 455 .instance_init = aspeed_soc_ast1030_init, 456 .class_init = aspeed_soc_ast1030_class_init, 457 }, 458 }; 459 460 DEFINE_TYPES(aspeed_soc_ast10x0_types) 461