1 /* 2 * ASPEED Ast10x0 SoC 3 * 4 * Copyright (C) 2022 ASPEED Technology Inc. 5 * 6 * This code is licensed under the GPL version 2 or later. See 7 * the COPYING file in the top-level directory. 8 * 9 * Implementation extracted from the AST2600 and adapted for Ast10x0. 10 */ 11 12 #include "qemu/osdep.h" 13 #include "qapi/error.h" 14 #include "exec/address-spaces.h" 15 #include "sysemu/sysemu.h" 16 #include "hw/qdev-clock.h" 17 #include "hw/misc/unimp.h" 18 #include "hw/char/serial.h" 19 #include "hw/arm/aspeed_soc.h" 20 21 #define ASPEED_SOC_IOMEM_SIZE 0x00200000 22 23 static const hwaddr aspeed_soc_ast1030_memmap[] = { 24 [ASPEED_DEV_SRAM] = 0x00000000, 25 [ASPEED_DEV_SBC] = 0x79000000, 26 [ASPEED_DEV_IOMEM] = 0x7E600000, 27 [ASPEED_DEV_PWM] = 0x7E610000, 28 [ASPEED_DEV_FMC] = 0x7E620000, 29 [ASPEED_DEV_SPI1] = 0x7E630000, 30 [ASPEED_DEV_SPI2] = 0x7E640000, 31 [ASPEED_DEV_SCU] = 0x7E6E2000, 32 [ASPEED_DEV_ADC] = 0x7E6E9000, 33 [ASPEED_DEV_SBC] = 0x7E6F2000, 34 [ASPEED_DEV_GPIO] = 0x7E780000, 35 [ASPEED_DEV_TIMER1] = 0x7E782000, 36 [ASPEED_DEV_UART5] = 0x7E784000, 37 [ASPEED_DEV_WDT] = 0x7E785000, 38 [ASPEED_DEV_LPC] = 0x7E789000, 39 [ASPEED_DEV_I2C] = 0x7E7B0000, 40 }; 41 42 static const int aspeed_soc_ast1030_irqmap[] = { 43 [ASPEED_DEV_UART5] = 8, 44 [ASPEED_DEV_GPIO] = 11, 45 [ASPEED_DEV_TIMER1] = 16, 46 [ASPEED_DEV_TIMER2] = 17, 47 [ASPEED_DEV_TIMER3] = 18, 48 [ASPEED_DEV_TIMER4] = 19, 49 [ASPEED_DEV_TIMER5] = 20, 50 [ASPEED_DEV_TIMER6] = 21, 51 [ASPEED_DEV_TIMER7] = 22, 52 [ASPEED_DEV_TIMER8] = 23, 53 [ASPEED_DEV_WDT] = 24, 54 [ASPEED_DEV_LPC] = 35, 55 [ASPEED_DEV_FMC] = 39, 56 [ASPEED_DEV_PWM] = 44, 57 [ASPEED_DEV_ADC] = 46, 58 [ASPEED_DEV_SPI1] = 65, 59 [ASPEED_DEV_SPI2] = 66, 60 [ASPEED_DEV_I2C] = 110, /* 110 ~ 123 */ 61 [ASPEED_DEV_KCS] = 138, /* 138 -> 142 */ 62 }; 63 64 static qemu_irq aspeed_soc_get_irq(AspeedSoCState *s, int ctrl) 65 { 66 AspeedSoCClass *sc = ASPEED_SOC_GET_CLASS(s); 67 68 return qdev_get_gpio_in(DEVICE(&s->armv7m), sc->irqmap[ctrl]); 69 } 70 71 static void aspeed_soc_ast1030_init(Object *obj) 72 { 73 AspeedSoCState *s = ASPEED_SOC(obj); 74 AspeedSoCClass *sc = ASPEED_SOC_GET_CLASS(s); 75 char socname[8]; 76 char typename[64]; 77 int i; 78 79 if (sscanf(sc->name, "%7s", socname) != 1) { 80 g_assert_not_reached(); 81 } 82 83 object_initialize_child(obj, "armv7m", &s->armv7m, TYPE_ARMV7M); 84 85 s->sysclk = qdev_init_clock_in(DEVICE(s), "sysclk", NULL, NULL, 0); 86 87 snprintf(typename, sizeof(typename), "aspeed.scu-%s", socname); 88 object_initialize_child(obj, "scu", &s->scu, typename); 89 qdev_prop_set_uint32(DEVICE(&s->scu), "silicon-rev", sc->silicon_rev); 90 91 object_property_add_alias(obj, "hw-strap1", OBJECT(&s->scu), "hw-strap1"); 92 object_property_add_alias(obj, "hw-strap2", OBJECT(&s->scu), "hw-strap2"); 93 94 snprintf(typename, sizeof(typename), "aspeed.timer-%s", socname); 95 object_initialize_child(obj, "timerctrl", &s->timerctrl, typename); 96 97 snprintf(typename, sizeof(typename), "aspeed.adc-%s", socname); 98 object_initialize_child(obj, "adc", &s->adc, typename); 99 100 snprintf(typename, sizeof(typename), "aspeed.fmc-%s", socname); 101 object_initialize_child(obj, "fmc", &s->fmc, typename); 102 103 for (i = 0; i < sc->spis_num; i++) { 104 snprintf(typename, sizeof(typename), "aspeed.spi%d-%s", i + 1, socname); 105 object_initialize_child(obj, "spi[*]", &s->spi[i], typename); 106 } 107 108 object_initialize_child(obj, "lpc", &s->lpc, TYPE_ASPEED_LPC); 109 110 object_initialize_child(obj, "sbc", &s->sbc, TYPE_ASPEED_SBC); 111 112 for (i = 0; i < sc->wdts_num; i++) { 113 snprintf(typename, sizeof(typename), "aspeed.wdt-%s", socname); 114 object_initialize_child(obj, "wdt[*]", &s->wdt[i], typename); 115 } 116 } 117 118 static void aspeed_soc_ast1030_realize(DeviceState *dev_soc, Error **errp) 119 { 120 AspeedSoCState *s = ASPEED_SOC(dev_soc); 121 AspeedSoCClass *sc = ASPEED_SOC_GET_CLASS(s); 122 MemoryRegion *system_memory = get_system_memory(); 123 DeviceState *armv7m; 124 Error *err = NULL; 125 int i; 126 127 if (!clock_has_source(s->sysclk)) { 128 error_setg(errp, "sysclk clock must be wired up by the board code"); 129 return; 130 } 131 132 /* General I/O memory space to catch all unimplemented device */ 133 create_unimplemented_device("aspeed.sbc", 134 sc->memmap[ASPEED_DEV_SBC], 135 0x40000); 136 create_unimplemented_device("aspeed.io", 137 sc->memmap[ASPEED_DEV_IOMEM], 138 ASPEED_SOC_IOMEM_SIZE); 139 140 /* AST1030 CPU Core */ 141 armv7m = DEVICE(&s->armv7m); 142 qdev_prop_set_uint32(armv7m, "num-irq", 256); 143 qdev_prop_set_string(armv7m, "cpu-type", sc->cpu_type); 144 qdev_connect_clock_in(armv7m, "cpuclk", s->sysclk); 145 object_property_set_link(OBJECT(&s->armv7m), "memory", 146 OBJECT(system_memory), &error_abort); 147 sysbus_realize(SYS_BUS_DEVICE(&s->armv7m), &error_abort); 148 149 /* Internal SRAM */ 150 memory_region_init_ram(&s->sram, NULL, "aspeed.sram", sc->sram_size, &err); 151 if (err != NULL) { 152 error_propagate(errp, err); 153 return; 154 } 155 memory_region_add_subregion(system_memory, 156 sc->memmap[ASPEED_DEV_SRAM], 157 &s->sram); 158 159 /* SCU */ 160 if (!sysbus_realize(SYS_BUS_DEVICE(&s->scu), errp)) { 161 return; 162 } 163 sysbus_mmio_map(SYS_BUS_DEVICE(&s->scu), 0, sc->memmap[ASPEED_DEV_SCU]); 164 165 /* LPC */ 166 if (!sysbus_realize(SYS_BUS_DEVICE(&s->lpc), errp)) { 167 return; 168 } 169 sysbus_mmio_map(SYS_BUS_DEVICE(&s->lpc), 0, sc->memmap[ASPEED_DEV_LPC]); 170 171 /* Connect the LPC IRQ to the GIC. It is otherwise unused. */ 172 sysbus_connect_irq(SYS_BUS_DEVICE(&s->lpc), 0, 173 aspeed_soc_get_irq(s, ASPEED_DEV_LPC)); 174 175 /* 176 * On the AST1030 LPC subdevice IRQs are connected straight to the GIC. 177 */ 178 sysbus_connect_irq(SYS_BUS_DEVICE(&s->lpc), 1 + aspeed_lpc_kcs_1, 179 qdev_get_gpio_in(DEVICE(&s->armv7m), 180 sc->irqmap[ASPEED_DEV_KCS] + aspeed_lpc_kcs_1)); 181 182 sysbus_connect_irq(SYS_BUS_DEVICE(&s->lpc), 1 + aspeed_lpc_kcs_2, 183 qdev_get_gpio_in(DEVICE(&s->armv7m), 184 sc->irqmap[ASPEED_DEV_KCS] + aspeed_lpc_kcs_2)); 185 186 sysbus_connect_irq(SYS_BUS_DEVICE(&s->lpc), 1 + aspeed_lpc_kcs_3, 187 qdev_get_gpio_in(DEVICE(&s->armv7m), 188 sc->irqmap[ASPEED_DEV_KCS] + aspeed_lpc_kcs_3)); 189 190 sysbus_connect_irq(SYS_BUS_DEVICE(&s->lpc), 1 + aspeed_lpc_kcs_4, 191 qdev_get_gpio_in(DEVICE(&s->armv7m), 192 sc->irqmap[ASPEED_DEV_KCS] + aspeed_lpc_kcs_4)); 193 194 /* UART5 - attach an 8250 to the IO space as our UART */ 195 serial_mm_init(get_system_memory(), sc->memmap[ASPEED_DEV_UART5], 2, 196 aspeed_soc_get_irq(s, ASPEED_DEV_UART5), 197 38400, serial_hd(0), DEVICE_LITTLE_ENDIAN); 198 199 /* Timer */ 200 object_property_set_link(OBJECT(&s->timerctrl), "scu", OBJECT(&s->scu), 201 &error_abort); 202 if (!sysbus_realize(SYS_BUS_DEVICE(&s->timerctrl), errp)) { 203 return; 204 } 205 sysbus_mmio_map(SYS_BUS_DEVICE(&s->timerctrl), 0, 206 sc->memmap[ASPEED_DEV_TIMER1]); 207 for (i = 0; i < ASPEED_TIMER_NR_TIMERS; i++) { 208 qemu_irq irq = aspeed_soc_get_irq(s, ASPEED_DEV_TIMER1 + i); 209 sysbus_connect_irq(SYS_BUS_DEVICE(&s->timerctrl), i, irq); 210 } 211 212 /* ADC */ 213 if (!sysbus_realize(SYS_BUS_DEVICE(&s->adc), errp)) { 214 return; 215 } 216 sysbus_mmio_map(SYS_BUS_DEVICE(&s->adc), 0, sc->memmap[ASPEED_DEV_ADC]); 217 sysbus_connect_irq(SYS_BUS_DEVICE(&s->adc), 0, 218 aspeed_soc_get_irq(s, ASPEED_DEV_ADC)); 219 220 /* FMC, The number of CS is set at the board level */ 221 object_property_set_link(OBJECT(&s->fmc), "dram", OBJECT(&s->sram), 222 &error_abort); 223 if (!sysbus_realize(SYS_BUS_DEVICE(&s->fmc), errp)) { 224 return; 225 } 226 sysbus_mmio_map(SYS_BUS_DEVICE(&s->fmc), 0, sc->memmap[ASPEED_DEV_FMC]); 227 sysbus_mmio_map(SYS_BUS_DEVICE(&s->fmc), 1, 228 ASPEED_SMC_GET_CLASS(&s->fmc)->flash_window_base); 229 sysbus_connect_irq(SYS_BUS_DEVICE(&s->fmc), 0, 230 aspeed_soc_get_irq(s, ASPEED_DEV_FMC)); 231 232 /* SPI */ 233 for (i = 0; i < sc->spis_num; i++) { 234 object_property_set_link(OBJECT(&s->spi[i]), "dram", 235 OBJECT(&s->sram), &error_abort); 236 if (!sysbus_realize(SYS_BUS_DEVICE(&s->spi[i]), errp)) { 237 return; 238 } 239 sysbus_mmio_map(SYS_BUS_DEVICE(&s->spi[i]), 0, 240 sc->memmap[ASPEED_DEV_SPI1 + i]); 241 sysbus_mmio_map(SYS_BUS_DEVICE(&s->spi[i]), 1, 242 ASPEED_SMC_GET_CLASS(&s->spi[i])->flash_window_base); 243 } 244 245 /* Secure Boot Controller */ 246 if (!sysbus_realize(SYS_BUS_DEVICE(&s->sbc), errp)) { 247 return; 248 } 249 sysbus_mmio_map(SYS_BUS_DEVICE(&s->sbc), 0, sc->memmap[ASPEED_DEV_SBC]); 250 251 /* Watch dog */ 252 for (i = 0; i < sc->wdts_num; i++) { 253 AspeedWDTClass *awc = ASPEED_WDT_GET_CLASS(&s->wdt[i]); 254 255 object_property_set_link(OBJECT(&s->wdt[i]), "scu", OBJECT(&s->scu), 256 &error_abort); 257 if (!sysbus_realize(SYS_BUS_DEVICE(&s->wdt[i]), errp)) { 258 return; 259 } 260 sysbus_mmio_map(SYS_BUS_DEVICE(&s->wdt[i]), 0, 261 sc->memmap[ASPEED_DEV_WDT] + i * awc->offset); 262 } 263 } 264 265 static void aspeed_soc_ast1030_class_init(ObjectClass *klass, void *data) 266 { 267 DeviceClass *dc = DEVICE_CLASS(klass); 268 AspeedSoCClass *sc = ASPEED_SOC_CLASS(dc); 269 270 dc->realize = aspeed_soc_ast1030_realize; 271 272 sc->name = "ast1030-a1"; 273 sc->cpu_type = ARM_CPU_TYPE_NAME("cortex-m4"); 274 sc->silicon_rev = AST1030_A1_SILICON_REV; 275 sc->sram_size = 0xc0000; 276 sc->spis_num = 2; 277 sc->ehcis_num = 0; 278 sc->wdts_num = 4; 279 sc->macs_num = 1; 280 sc->irqmap = aspeed_soc_ast1030_irqmap; 281 sc->memmap = aspeed_soc_ast1030_memmap; 282 sc->num_cpus = 1; 283 } 284 285 static const TypeInfo aspeed_soc_ast1030_type_info = { 286 .name = "ast1030-a1", 287 .parent = TYPE_ASPEED_SOC, 288 .instance_size = sizeof(AspeedSoCState), 289 .instance_init = aspeed_soc_ast1030_init, 290 .class_init = aspeed_soc_ast1030_class_init, 291 .class_size = sizeof(AspeedSoCClass), 292 }; 293 294 static void aspeed_soc_register_types(void) 295 { 296 type_register_static(&aspeed_soc_ast1030_type_info); 297 } 298 299 type_init(aspeed_soc_register_types) 300