1 /* 2 * ASPEED SoC 2600 family 3 * 4 * Copyright (c) 2016-2019, IBM Corporation. 5 * 6 * This code is licensed under the GPL version 2 or later. See 7 * the COPYING file in the top-level directory. 8 */ 9 10 #include "qemu/osdep.h" 11 #include "qapi/error.h" 12 #include "hw/misc/unimp.h" 13 #include "hw/arm/aspeed_soc.h" 14 #include "hw/char/serial.h" 15 #include "qemu/module.h" 16 #include "qemu/error-report.h" 17 #include "hw/i2c/aspeed_i2c.h" 18 #include "net/net.h" 19 #include "sysemu/sysemu.h" 20 21 #define ASPEED_SOC_IOMEM_SIZE 0x00200000 22 23 static const hwaddr aspeed_soc_ast2600_memmap[] = { 24 [ASPEED_DEV_SRAM] = 0x10000000, 25 /* 0x16000000 0x17FFFFFF : AHB BUS do LPC Bus bridge */ 26 [ASPEED_DEV_IOMEM] = 0x1E600000, 27 [ASPEED_DEV_PWM] = 0x1E610000, 28 [ASPEED_DEV_FMC] = 0x1E620000, 29 [ASPEED_DEV_SPI1] = 0x1E630000, 30 [ASPEED_DEV_SPI2] = 0x1E641000, 31 [ASPEED_DEV_EHCI1] = 0x1E6A1000, 32 [ASPEED_DEV_EHCI2] = 0x1E6A3000, 33 [ASPEED_DEV_MII1] = 0x1E650000, 34 [ASPEED_DEV_MII2] = 0x1E650008, 35 [ASPEED_DEV_MII3] = 0x1E650010, 36 [ASPEED_DEV_MII4] = 0x1E650018, 37 [ASPEED_DEV_ETH1] = 0x1E660000, 38 [ASPEED_DEV_ETH3] = 0x1E670000, 39 [ASPEED_DEV_ETH2] = 0x1E680000, 40 [ASPEED_DEV_ETH4] = 0x1E690000, 41 [ASPEED_DEV_VIC] = 0x1E6C0000, 42 [ASPEED_DEV_HACE] = 0x1E6D0000, 43 [ASPEED_DEV_SDMC] = 0x1E6E0000, 44 [ASPEED_DEV_SCU] = 0x1E6E2000, 45 [ASPEED_DEV_XDMA] = 0x1E6E7000, 46 [ASPEED_DEV_ADC] = 0x1E6E9000, 47 [ASPEED_DEV_VIDEO] = 0x1E700000, 48 [ASPEED_DEV_SDHCI] = 0x1E740000, 49 [ASPEED_DEV_EMMC] = 0x1E750000, 50 [ASPEED_DEV_GPIO] = 0x1E780000, 51 [ASPEED_DEV_GPIO_1_8V] = 0x1E780800, 52 [ASPEED_DEV_RTC] = 0x1E781000, 53 [ASPEED_DEV_TIMER1] = 0x1E782000, 54 [ASPEED_DEV_WDT] = 0x1E785000, 55 [ASPEED_DEV_LPC] = 0x1E789000, 56 [ASPEED_DEV_IBT] = 0x1E789140, 57 [ASPEED_DEV_I2C] = 0x1E78A000, 58 [ASPEED_DEV_UART1] = 0x1E783000, 59 [ASPEED_DEV_UART5] = 0x1E784000, 60 [ASPEED_DEV_VUART] = 0x1E787000, 61 [ASPEED_DEV_SDRAM] = 0x80000000, 62 }; 63 64 #define ASPEED_A7MPCORE_ADDR 0x40460000 65 66 #define AST2600_MAX_IRQ 197 67 68 /* Shared Peripheral Interrupt values below are offset by -32 from datasheet */ 69 static const int aspeed_soc_ast2600_irqmap[] = { 70 [ASPEED_DEV_UART1] = 47, 71 [ASPEED_DEV_UART2] = 48, 72 [ASPEED_DEV_UART3] = 49, 73 [ASPEED_DEV_UART4] = 50, 74 [ASPEED_DEV_UART5] = 8, 75 [ASPEED_DEV_VUART] = 8, 76 [ASPEED_DEV_FMC] = 39, 77 [ASPEED_DEV_SDMC] = 0, 78 [ASPEED_DEV_SCU] = 12, 79 [ASPEED_DEV_ADC] = 78, 80 [ASPEED_DEV_XDMA] = 6, 81 [ASPEED_DEV_SDHCI] = 43, 82 [ASPEED_DEV_EHCI1] = 5, 83 [ASPEED_DEV_EHCI2] = 9, 84 [ASPEED_DEV_EMMC] = 15, 85 [ASPEED_DEV_GPIO] = 40, 86 [ASPEED_DEV_GPIO_1_8V] = 11, 87 [ASPEED_DEV_RTC] = 13, 88 [ASPEED_DEV_TIMER1] = 16, 89 [ASPEED_DEV_TIMER2] = 17, 90 [ASPEED_DEV_TIMER3] = 18, 91 [ASPEED_DEV_TIMER4] = 19, 92 [ASPEED_DEV_TIMER5] = 20, 93 [ASPEED_DEV_TIMER6] = 21, 94 [ASPEED_DEV_TIMER7] = 22, 95 [ASPEED_DEV_TIMER8] = 23, 96 [ASPEED_DEV_WDT] = 24, 97 [ASPEED_DEV_PWM] = 44, 98 [ASPEED_DEV_LPC] = 35, 99 [ASPEED_DEV_IBT] = 143, 100 [ASPEED_DEV_I2C] = 110, /* 110 -> 125 */ 101 [ASPEED_DEV_ETH1] = 2, 102 [ASPEED_DEV_ETH2] = 3, 103 [ASPEED_DEV_HACE] = 4, 104 [ASPEED_DEV_ETH3] = 32, 105 [ASPEED_DEV_ETH4] = 33, 106 [ASPEED_DEV_KCS] = 138, /* 138 -> 142 */ 107 }; 108 109 static qemu_irq aspeed_soc_get_irq(AspeedSoCState *s, int ctrl) 110 { 111 AspeedSoCClass *sc = ASPEED_SOC_GET_CLASS(s); 112 113 return qdev_get_gpio_in(DEVICE(&s->a7mpcore), sc->irqmap[ctrl]); 114 } 115 116 static void aspeed_soc_ast2600_init(Object *obj) 117 { 118 AspeedSoCState *s = ASPEED_SOC(obj); 119 AspeedSoCClass *sc = ASPEED_SOC_GET_CLASS(s); 120 int i; 121 char socname[8]; 122 char typename[64]; 123 124 if (sscanf(sc->name, "%7s", socname) != 1) { 125 g_assert_not_reached(); 126 } 127 128 for (i = 0; i < sc->num_cpus; i++) { 129 object_initialize_child(obj, "cpu[*]", &s->cpu[i], sc->cpu_type); 130 } 131 132 snprintf(typename, sizeof(typename), "aspeed.scu-%s", socname); 133 object_initialize_child(obj, "scu", &s->scu, typename); 134 qdev_prop_set_uint32(DEVICE(&s->scu), "silicon-rev", 135 sc->silicon_rev); 136 object_property_add_alias(obj, "hw-strap1", OBJECT(&s->scu), 137 "hw-strap1"); 138 object_property_add_alias(obj, "hw-strap2", OBJECT(&s->scu), 139 "hw-strap2"); 140 object_property_add_alias(obj, "hw-prot-key", OBJECT(&s->scu), 141 "hw-prot-key"); 142 143 object_initialize_child(obj, "a7mpcore", &s->a7mpcore, 144 TYPE_A15MPCORE_PRIV); 145 146 object_initialize_child(obj, "rtc", &s->rtc, TYPE_ASPEED_RTC); 147 148 snprintf(typename, sizeof(typename), "aspeed.timer-%s", socname); 149 object_initialize_child(obj, "timerctrl", &s->timerctrl, typename); 150 151 snprintf(typename, sizeof(typename), "aspeed.i2c-%s", socname); 152 object_initialize_child(obj, "i2c", &s->i2c, typename); 153 154 snprintf(typename, sizeof(typename), "aspeed.fmc-%s", socname); 155 object_initialize_child(obj, "fmc", &s->fmc, typename); 156 object_property_add_alias(obj, "num-cs", OBJECT(&s->fmc), "num-cs"); 157 158 for (i = 0; i < sc->spis_num; i++) { 159 snprintf(typename, sizeof(typename), "aspeed.spi%d-%s", i + 1, socname); 160 object_initialize_child(obj, "spi[*]", &s->spi[i], typename); 161 } 162 163 for (i = 0; i < sc->ehcis_num; i++) { 164 object_initialize_child(obj, "ehci[*]", &s->ehci[i], 165 TYPE_PLATFORM_EHCI); 166 } 167 168 snprintf(typename, sizeof(typename), "aspeed.sdmc-%s", socname); 169 object_initialize_child(obj, "sdmc", &s->sdmc, typename); 170 object_property_add_alias(obj, "ram-size", OBJECT(&s->sdmc), 171 "ram-size"); 172 object_property_add_alias(obj, "max-ram-size", OBJECT(&s->sdmc), 173 "max-ram-size"); 174 175 for (i = 0; i < sc->wdts_num; i++) { 176 snprintf(typename, sizeof(typename), "aspeed.wdt-%s", socname); 177 object_initialize_child(obj, "wdt[*]", &s->wdt[i], typename); 178 } 179 180 for (i = 0; i < sc->macs_num; i++) { 181 object_initialize_child(obj, "ftgmac100[*]", &s->ftgmac100[i], 182 TYPE_FTGMAC100); 183 184 object_initialize_child(obj, "mii[*]", &s->mii[i], TYPE_ASPEED_MII); 185 } 186 187 snprintf(typename, sizeof(typename), TYPE_ASPEED_XDMA "-%s", socname); 188 object_initialize_child(obj, "xdma", &s->xdma, typename); 189 190 snprintf(typename, sizeof(typename), "aspeed.gpio-%s", socname); 191 object_initialize_child(obj, "gpio", &s->gpio, typename); 192 193 snprintf(typename, sizeof(typename), "aspeed.gpio-%s-1_8v", socname); 194 object_initialize_child(obj, "gpio_1_8v", &s->gpio_1_8v, typename); 195 196 object_initialize_child(obj, "sd-controller", &s->sdhci, 197 TYPE_ASPEED_SDHCI); 198 199 object_property_set_int(OBJECT(&s->sdhci), "num-slots", 2, &error_abort); 200 201 /* Init sd card slot class here so that they're under the correct parent */ 202 for (i = 0; i < ASPEED_SDHCI_NUM_SLOTS; ++i) { 203 object_initialize_child(obj, "sd-controller.sdhci[*]", 204 &s->sdhci.slots[i], TYPE_SYSBUS_SDHCI); 205 } 206 207 object_initialize_child(obj, "emmc-controller", &s->emmc, 208 TYPE_ASPEED_SDHCI); 209 210 object_property_set_int(OBJECT(&s->emmc), "num-slots", 1, &error_abort); 211 212 object_initialize_child(obj, "emmc-controller.sdhci", &s->emmc.slots[0], 213 TYPE_SYSBUS_SDHCI); 214 215 object_initialize_child(obj, "lpc", &s->lpc, TYPE_ASPEED_LPC); 216 217 snprintf(typename, sizeof(typename), "aspeed.hace-%s", socname); 218 object_initialize_child(obj, "hace", &s->hace, typename); 219 } 220 221 /* 222 * ASPEED ast2600 has 0xf as cluster ID 223 * 224 * https://developer.arm.com/documentation/ddi0388/e/the-system-control-coprocessors/summary-of-system-control-coprocessor-registers/multiprocessor-affinity-register 225 */ 226 static uint64_t aspeed_calc_affinity(int cpu) 227 { 228 return (0xf << ARM_AFF1_SHIFT) | cpu; 229 } 230 231 static void aspeed_soc_ast2600_realize(DeviceState *dev, Error **errp) 232 { 233 int i; 234 AspeedSoCState *s = ASPEED_SOC(dev); 235 AspeedSoCClass *sc = ASPEED_SOC_GET_CLASS(s); 236 Error *err = NULL; 237 qemu_irq irq; 238 239 /* IO space */ 240 create_unimplemented_device("aspeed_soc.io", sc->memmap[ASPEED_DEV_IOMEM], 241 ASPEED_SOC_IOMEM_SIZE); 242 243 /* Video engine stub */ 244 create_unimplemented_device("aspeed.video", sc->memmap[ASPEED_DEV_VIDEO], 245 0x1000); 246 247 /* CPU */ 248 for (i = 0; i < sc->num_cpus; i++) { 249 if (sc->num_cpus > 1) { 250 object_property_set_int(OBJECT(&s->cpu[i]), "reset-cbar", 251 ASPEED_A7MPCORE_ADDR, &error_abort); 252 } 253 object_property_set_int(OBJECT(&s->cpu[i]), "mp-affinity", 254 aspeed_calc_affinity(i), &error_abort); 255 256 object_property_set_int(OBJECT(&s->cpu[i]), "cntfrq", 1125000000, 257 &error_abort); 258 259 if (!qdev_realize(DEVICE(&s->cpu[i]), NULL, errp)) { 260 return; 261 } 262 } 263 264 /* A7MPCORE */ 265 object_property_set_int(OBJECT(&s->a7mpcore), "num-cpu", sc->num_cpus, 266 &error_abort); 267 object_property_set_int(OBJECT(&s->a7mpcore), "num-irq", 268 ROUND_UP(AST2600_MAX_IRQ + GIC_INTERNAL, 32), 269 &error_abort); 270 271 sysbus_realize(SYS_BUS_DEVICE(&s->a7mpcore), &error_abort); 272 sysbus_mmio_map(SYS_BUS_DEVICE(&s->a7mpcore), 0, ASPEED_A7MPCORE_ADDR); 273 274 for (i = 0; i < sc->num_cpus; i++) { 275 SysBusDevice *sbd = SYS_BUS_DEVICE(&s->a7mpcore); 276 DeviceState *d = DEVICE(qemu_get_cpu(i)); 277 278 irq = qdev_get_gpio_in(d, ARM_CPU_IRQ); 279 sysbus_connect_irq(sbd, i, irq); 280 irq = qdev_get_gpio_in(d, ARM_CPU_FIQ); 281 sysbus_connect_irq(sbd, i + sc->num_cpus, irq); 282 irq = qdev_get_gpio_in(d, ARM_CPU_VIRQ); 283 sysbus_connect_irq(sbd, i + 2 * sc->num_cpus, irq); 284 irq = qdev_get_gpio_in(d, ARM_CPU_VFIQ); 285 sysbus_connect_irq(sbd, i + 3 * sc->num_cpus, irq); 286 } 287 288 /* SRAM */ 289 memory_region_init_ram(&s->sram, OBJECT(dev), "aspeed.sram", 290 sc->sram_size, &err); 291 if (err) { 292 error_propagate(errp, err); 293 return; 294 } 295 memory_region_add_subregion(get_system_memory(), 296 sc->memmap[ASPEED_DEV_SRAM], &s->sram); 297 298 /* SCU */ 299 if (!sysbus_realize(SYS_BUS_DEVICE(&s->scu), errp)) { 300 return; 301 } 302 sysbus_mmio_map(SYS_BUS_DEVICE(&s->scu), 0, sc->memmap[ASPEED_DEV_SCU]); 303 304 /* RTC */ 305 if (!sysbus_realize(SYS_BUS_DEVICE(&s->rtc), errp)) { 306 return; 307 } 308 sysbus_mmio_map(SYS_BUS_DEVICE(&s->rtc), 0, sc->memmap[ASPEED_DEV_RTC]); 309 sysbus_connect_irq(SYS_BUS_DEVICE(&s->rtc), 0, 310 aspeed_soc_get_irq(s, ASPEED_DEV_RTC)); 311 312 /* Timer */ 313 object_property_set_link(OBJECT(&s->timerctrl), "scu", OBJECT(&s->scu), 314 &error_abort); 315 if (!sysbus_realize(SYS_BUS_DEVICE(&s->timerctrl), errp)) { 316 return; 317 } 318 sysbus_mmio_map(SYS_BUS_DEVICE(&s->timerctrl), 0, 319 sc->memmap[ASPEED_DEV_TIMER1]); 320 for (i = 0; i < ASPEED_TIMER_NR_TIMERS; i++) { 321 qemu_irq irq = aspeed_soc_get_irq(s, ASPEED_DEV_TIMER1 + i); 322 sysbus_connect_irq(SYS_BUS_DEVICE(&s->timerctrl), i, irq); 323 } 324 325 /* UART - attach an 8250 to the IO space as our UART */ 326 serial_mm_init(get_system_memory(), sc->memmap[s->uart_default], 2, 327 aspeed_soc_get_irq(s, s->uart_default), 38400, 328 serial_hd(0), DEVICE_LITTLE_ENDIAN); 329 330 /* I2C */ 331 object_property_set_link(OBJECT(&s->i2c), "dram", OBJECT(s->dram_mr), 332 &error_abort); 333 if (!sysbus_realize(SYS_BUS_DEVICE(&s->i2c), errp)) { 334 return; 335 } 336 sysbus_mmio_map(SYS_BUS_DEVICE(&s->i2c), 0, sc->memmap[ASPEED_DEV_I2C]); 337 for (i = 0; i < ASPEED_I2C_GET_CLASS(&s->i2c)->num_busses; i++) { 338 qemu_irq irq = qdev_get_gpio_in(DEVICE(&s->a7mpcore), 339 sc->irqmap[ASPEED_DEV_I2C] + i); 340 /* The AST2600 I2C controller has one IRQ per bus. */ 341 sysbus_connect_irq(SYS_BUS_DEVICE(&s->i2c.busses[i]), 0, irq); 342 } 343 344 /* FMC, The number of CS is set at the board level */ 345 object_property_set_link(OBJECT(&s->fmc), "dram", OBJECT(s->dram_mr), 346 &error_abort); 347 if (!sysbus_realize(SYS_BUS_DEVICE(&s->fmc), errp)) { 348 return; 349 } 350 sysbus_mmio_map(SYS_BUS_DEVICE(&s->fmc), 0, sc->memmap[ASPEED_DEV_FMC]); 351 sysbus_mmio_map(SYS_BUS_DEVICE(&s->fmc), 1, 352 ASPEED_SMC_GET_CLASS(&s->fmc)->flash_window_base); 353 sysbus_connect_irq(SYS_BUS_DEVICE(&s->fmc), 0, 354 aspeed_soc_get_irq(s, ASPEED_DEV_FMC)); 355 356 /* SPI */ 357 for (i = 0; i < sc->spis_num; i++) { 358 object_property_set_link(OBJECT(&s->spi[i]), "dram", 359 OBJECT(s->dram_mr), &error_abort); 360 object_property_set_int(OBJECT(&s->spi[i]), "num-cs", 1, &error_abort); 361 if (!sysbus_realize(SYS_BUS_DEVICE(&s->spi[i]), errp)) { 362 return; 363 } 364 sysbus_mmio_map(SYS_BUS_DEVICE(&s->spi[i]), 0, 365 sc->memmap[ASPEED_DEV_SPI1 + i]); 366 sysbus_mmio_map(SYS_BUS_DEVICE(&s->spi[i]), 1, 367 ASPEED_SMC_GET_CLASS(&s->spi[i])->flash_window_base); 368 } 369 370 /* EHCI */ 371 for (i = 0; i < sc->ehcis_num; i++) { 372 if (!sysbus_realize(SYS_BUS_DEVICE(&s->ehci[i]), errp)) { 373 return; 374 } 375 sysbus_mmio_map(SYS_BUS_DEVICE(&s->ehci[i]), 0, 376 sc->memmap[ASPEED_DEV_EHCI1 + i]); 377 sysbus_connect_irq(SYS_BUS_DEVICE(&s->ehci[i]), 0, 378 aspeed_soc_get_irq(s, ASPEED_DEV_EHCI1 + i)); 379 } 380 381 /* SDMC - SDRAM Memory Controller */ 382 if (!sysbus_realize(SYS_BUS_DEVICE(&s->sdmc), errp)) { 383 return; 384 } 385 sysbus_mmio_map(SYS_BUS_DEVICE(&s->sdmc), 0, sc->memmap[ASPEED_DEV_SDMC]); 386 387 /* Watch dog */ 388 for (i = 0; i < sc->wdts_num; i++) { 389 AspeedWDTClass *awc = ASPEED_WDT_GET_CLASS(&s->wdt[i]); 390 391 object_property_set_link(OBJECT(&s->wdt[i]), "scu", OBJECT(&s->scu), 392 &error_abort); 393 if (!sysbus_realize(SYS_BUS_DEVICE(&s->wdt[i]), errp)) { 394 return; 395 } 396 sysbus_mmio_map(SYS_BUS_DEVICE(&s->wdt[i]), 0, 397 sc->memmap[ASPEED_DEV_WDT] + i * awc->offset); 398 } 399 400 /* Net */ 401 for (i = 0; i < sc->macs_num; i++) { 402 object_property_set_bool(OBJECT(&s->ftgmac100[i]), "aspeed", true, 403 &error_abort); 404 if (!sysbus_realize(SYS_BUS_DEVICE(&s->ftgmac100[i]), errp)) { 405 return; 406 } 407 sysbus_mmio_map(SYS_BUS_DEVICE(&s->ftgmac100[i]), 0, 408 sc->memmap[ASPEED_DEV_ETH1 + i]); 409 sysbus_connect_irq(SYS_BUS_DEVICE(&s->ftgmac100[i]), 0, 410 aspeed_soc_get_irq(s, ASPEED_DEV_ETH1 + i)); 411 412 object_property_set_link(OBJECT(&s->mii[i]), "nic", 413 OBJECT(&s->ftgmac100[i]), &error_abort); 414 if (!sysbus_realize(SYS_BUS_DEVICE(&s->mii[i]), errp)) { 415 return; 416 } 417 418 sysbus_mmio_map(SYS_BUS_DEVICE(&s->mii[i]), 0, 419 sc->memmap[ASPEED_DEV_MII1 + i]); 420 } 421 422 /* XDMA */ 423 if (!sysbus_realize(SYS_BUS_DEVICE(&s->xdma), errp)) { 424 return; 425 } 426 sysbus_mmio_map(SYS_BUS_DEVICE(&s->xdma), 0, 427 sc->memmap[ASPEED_DEV_XDMA]); 428 sysbus_connect_irq(SYS_BUS_DEVICE(&s->xdma), 0, 429 aspeed_soc_get_irq(s, ASPEED_DEV_XDMA)); 430 431 /* GPIO */ 432 if (!sysbus_realize(SYS_BUS_DEVICE(&s->gpio), errp)) { 433 return; 434 } 435 sysbus_mmio_map(SYS_BUS_DEVICE(&s->gpio), 0, sc->memmap[ASPEED_DEV_GPIO]); 436 sysbus_connect_irq(SYS_BUS_DEVICE(&s->gpio), 0, 437 aspeed_soc_get_irq(s, ASPEED_DEV_GPIO)); 438 439 if (!sysbus_realize(SYS_BUS_DEVICE(&s->gpio_1_8v), errp)) { 440 return; 441 } 442 sysbus_mmio_map(SYS_BUS_DEVICE(&s->gpio_1_8v), 0, 443 sc->memmap[ASPEED_DEV_GPIO_1_8V]); 444 sysbus_connect_irq(SYS_BUS_DEVICE(&s->gpio_1_8v), 0, 445 aspeed_soc_get_irq(s, ASPEED_DEV_GPIO_1_8V)); 446 447 /* SDHCI */ 448 if (!sysbus_realize(SYS_BUS_DEVICE(&s->sdhci), errp)) { 449 return; 450 } 451 sysbus_mmio_map(SYS_BUS_DEVICE(&s->sdhci), 0, 452 sc->memmap[ASPEED_DEV_SDHCI]); 453 sysbus_connect_irq(SYS_BUS_DEVICE(&s->sdhci), 0, 454 aspeed_soc_get_irq(s, ASPEED_DEV_SDHCI)); 455 456 /* eMMC */ 457 if (!sysbus_realize(SYS_BUS_DEVICE(&s->emmc), errp)) { 458 return; 459 } 460 sysbus_mmio_map(SYS_BUS_DEVICE(&s->emmc), 0, sc->memmap[ASPEED_DEV_EMMC]); 461 sysbus_connect_irq(SYS_BUS_DEVICE(&s->emmc), 0, 462 aspeed_soc_get_irq(s, ASPEED_DEV_EMMC)); 463 464 /* LPC */ 465 if (!sysbus_realize(SYS_BUS_DEVICE(&s->lpc), errp)) { 466 return; 467 } 468 sysbus_mmio_map(SYS_BUS_DEVICE(&s->lpc), 0, sc->memmap[ASPEED_DEV_LPC]); 469 470 /* Connect the LPC IRQ to the GIC. It is otherwise unused. */ 471 sysbus_connect_irq(SYS_BUS_DEVICE(&s->lpc), 0, 472 aspeed_soc_get_irq(s, ASPEED_DEV_LPC)); 473 474 /* 475 * On the AST2600 LPC subdevice IRQs are connected straight to the GIC. 476 * 477 * LPC subdevice IRQ sources are offset from 1 because the LPC model caters 478 * to the AST2400 and AST2500. SoCs before the AST2600 have one LPC IRQ 479 * shared across the subdevices, and the shared IRQ output to the VIC is at 480 * offset 0. 481 */ 482 sysbus_connect_irq(SYS_BUS_DEVICE(&s->lpc), 1 + aspeed_lpc_kcs_1, 483 qdev_get_gpio_in(DEVICE(&s->a7mpcore), 484 sc->irqmap[ASPEED_DEV_KCS] + aspeed_lpc_kcs_1)); 485 486 sysbus_connect_irq(SYS_BUS_DEVICE(&s->lpc), 1 + aspeed_lpc_kcs_2, 487 qdev_get_gpio_in(DEVICE(&s->a7mpcore), 488 sc->irqmap[ASPEED_DEV_KCS] + aspeed_lpc_kcs_2)); 489 490 sysbus_connect_irq(SYS_BUS_DEVICE(&s->lpc), 1 + aspeed_lpc_kcs_3, 491 qdev_get_gpio_in(DEVICE(&s->a7mpcore), 492 sc->irqmap[ASPEED_DEV_KCS] + aspeed_lpc_kcs_3)); 493 494 sysbus_connect_irq(SYS_BUS_DEVICE(&s->lpc), 1 + aspeed_lpc_kcs_4, 495 qdev_get_gpio_in(DEVICE(&s->a7mpcore), 496 sc->irqmap[ASPEED_DEV_KCS] + aspeed_lpc_kcs_4)); 497 498 /* HACE */ 499 object_property_set_link(OBJECT(&s->hace), "dram", OBJECT(s->dram_mr), 500 &error_abort); 501 if (!sysbus_realize(SYS_BUS_DEVICE(&s->hace), errp)) { 502 return; 503 } 504 sysbus_mmio_map(SYS_BUS_DEVICE(&s->hace), 0, sc->memmap[ASPEED_DEV_HACE]); 505 sysbus_connect_irq(SYS_BUS_DEVICE(&s->hace), 0, 506 aspeed_soc_get_irq(s, ASPEED_DEV_HACE)); 507 } 508 509 static void aspeed_soc_ast2600_class_init(ObjectClass *oc, void *data) 510 { 511 DeviceClass *dc = DEVICE_CLASS(oc); 512 AspeedSoCClass *sc = ASPEED_SOC_CLASS(oc); 513 514 dc->realize = aspeed_soc_ast2600_realize; 515 516 sc->name = "ast2600-a3"; 517 sc->cpu_type = ARM_CPU_TYPE_NAME("cortex-a7"); 518 sc->silicon_rev = AST2600_A3_SILICON_REV; 519 sc->sram_size = 0x16400; 520 sc->spis_num = 2; 521 sc->ehcis_num = 2; 522 sc->wdts_num = 4; 523 sc->macs_num = 4; 524 sc->irqmap = aspeed_soc_ast2600_irqmap; 525 sc->memmap = aspeed_soc_ast2600_memmap; 526 sc->num_cpus = 2; 527 } 528 529 static const TypeInfo aspeed_soc_ast2600_type_info = { 530 .name = "ast2600-a3", 531 .parent = TYPE_ASPEED_SOC, 532 .instance_size = sizeof(AspeedSoCState), 533 .instance_init = aspeed_soc_ast2600_init, 534 .class_init = aspeed_soc_ast2600_class_init, 535 .class_size = sizeof(AspeedSoCClass), 536 }; 537 538 static void aspeed_soc_register_types(void) 539 { 540 type_register_static(&aspeed_soc_ast2600_type_info); 541 }; 542 543 type_init(aspeed_soc_register_types) 544