1 /* 2 * ASPEED SoC 2600 family 3 * 4 * Copyright (c) 2016-2019, IBM Corporation. 5 * 6 * This code is licensed under the GPL version 2 or later. See 7 * the COPYING file in the top-level directory. 8 */ 9 10 #include "qemu/osdep.h" 11 #include "qapi/error.h" 12 #include "cpu.h" 13 #include "exec/address-spaces.h" 14 #include "hw/misc/unimp.h" 15 #include "hw/arm/aspeed_soc.h" 16 #include "hw/char/serial.h" 17 #include "qemu/log.h" 18 #include "qemu/module.h" 19 #include "qemu/error-report.h" 20 #include "hw/i2c/aspeed_i2c.h" 21 #include "net/net.h" 22 #include "sysemu/sysemu.h" 23 24 #define ASPEED_SOC_IOMEM_SIZE 0x00200000 25 26 static const hwaddr aspeed_soc_ast2600_memmap[] = { 27 [ASPEED_SRAM] = 0x10000000, 28 /* 0x16000000 0x17FFFFFF : AHB BUS do LPC Bus bridge */ 29 [ASPEED_IOMEM] = 0x1E600000, 30 [ASPEED_PWM] = 0x1E610000, 31 [ASPEED_FMC] = 0x1E620000, 32 [ASPEED_SPI1] = 0x1E630000, 33 [ASPEED_SPI2] = 0x1E641000, 34 [ASPEED_EHCI1] = 0x1E6A1000, 35 [ASPEED_EHCI2] = 0x1E6A3000, 36 [ASPEED_MII1] = 0x1E650000, 37 [ASPEED_MII2] = 0x1E650008, 38 [ASPEED_MII3] = 0x1E650010, 39 [ASPEED_MII4] = 0x1E650018, 40 [ASPEED_ETH1] = 0x1E660000, 41 [ASPEED_ETH3] = 0x1E670000, 42 [ASPEED_ETH2] = 0x1E680000, 43 [ASPEED_ETH4] = 0x1E690000, 44 [ASPEED_VIC] = 0x1E6C0000, 45 [ASPEED_SDMC] = 0x1E6E0000, 46 [ASPEED_SCU] = 0x1E6E2000, 47 [ASPEED_XDMA] = 0x1E6E7000, 48 [ASPEED_ADC] = 0x1E6E9000, 49 [ASPEED_VIDEO] = 0x1E700000, 50 [ASPEED_SDHCI] = 0x1E740000, 51 [ASPEED_EMMC] = 0x1E750000, 52 [ASPEED_GPIO] = 0x1E780000, 53 [ASPEED_GPIO_1_8V] = 0x1E780800, 54 [ASPEED_RTC] = 0x1E781000, 55 [ASPEED_TIMER1] = 0x1E782000, 56 [ASPEED_WDT] = 0x1E785000, 57 [ASPEED_LPC] = 0x1E789000, 58 [ASPEED_IBT] = 0x1E789140, 59 [ASPEED_I2C] = 0x1E78A000, 60 [ASPEED_UART1] = 0x1E783000, 61 [ASPEED_UART5] = 0x1E784000, 62 [ASPEED_VUART] = 0x1E787000, 63 [ASPEED_SDRAM] = 0x80000000, 64 }; 65 66 #define ASPEED_A7MPCORE_ADDR 0x40460000 67 68 #define ASPEED_SOC_AST2600_MAX_IRQ 128 69 70 /* Shared Peripheral Interrupt values below are offset by -32 from datasheet */ 71 static const int aspeed_soc_ast2600_irqmap[] = { 72 [ASPEED_UART1] = 47, 73 [ASPEED_UART2] = 48, 74 [ASPEED_UART3] = 49, 75 [ASPEED_UART4] = 50, 76 [ASPEED_UART5] = 8, 77 [ASPEED_VUART] = 8, 78 [ASPEED_FMC] = 39, 79 [ASPEED_SDMC] = 0, 80 [ASPEED_SCU] = 12, 81 [ASPEED_ADC] = 78, 82 [ASPEED_XDMA] = 6, 83 [ASPEED_SDHCI] = 43, 84 [ASPEED_EHCI1] = 5, 85 [ASPEED_EHCI2] = 9, 86 [ASPEED_EMMC] = 15, 87 [ASPEED_GPIO] = 40, 88 [ASPEED_GPIO_1_8V] = 11, 89 [ASPEED_RTC] = 13, 90 [ASPEED_TIMER1] = 16, 91 [ASPEED_TIMER2] = 17, 92 [ASPEED_TIMER3] = 18, 93 [ASPEED_TIMER4] = 19, 94 [ASPEED_TIMER5] = 20, 95 [ASPEED_TIMER6] = 21, 96 [ASPEED_TIMER7] = 22, 97 [ASPEED_TIMER8] = 23, 98 [ASPEED_WDT] = 24, 99 [ASPEED_PWM] = 44, 100 [ASPEED_LPC] = 35, 101 [ASPEED_IBT] = 35, /* LPC */ 102 [ASPEED_I2C] = 110, /* 110 -> 125 */ 103 [ASPEED_ETH1] = 2, 104 [ASPEED_ETH2] = 3, 105 [ASPEED_ETH3] = 32, 106 [ASPEED_ETH4] = 33, 107 108 }; 109 110 static qemu_irq aspeed_soc_get_irq(AspeedSoCState *s, int ctrl) 111 { 112 AspeedSoCClass *sc = ASPEED_SOC_GET_CLASS(s); 113 114 return qdev_get_gpio_in(DEVICE(&s->a7mpcore), sc->irqmap[ctrl]); 115 } 116 117 static void aspeed_soc_ast2600_init(Object *obj) 118 { 119 AspeedSoCState *s = ASPEED_SOC(obj); 120 AspeedSoCClass *sc = ASPEED_SOC_GET_CLASS(s); 121 int i; 122 char socname[8]; 123 char typename[64]; 124 125 if (sscanf(sc->name, "%7s", socname) != 1) { 126 g_assert_not_reached(); 127 } 128 129 for (i = 0; i < sc->num_cpus; i++) { 130 object_initialize_child(obj, "cpu[*]", OBJECT(&s->cpu[i]), 131 sizeof(s->cpu[i]), sc->cpu_type, 132 &error_abort, NULL); 133 } 134 135 snprintf(typename, sizeof(typename), "aspeed.scu-%s", socname); 136 sysbus_init_child_obj(obj, "scu", OBJECT(&s->scu), sizeof(s->scu), 137 typename); 138 qdev_prop_set_uint32(DEVICE(&s->scu), "silicon-rev", 139 sc->silicon_rev); 140 object_property_add_alias(obj, "hw-strap1", OBJECT(&s->scu), 141 "hw-strap1", &error_abort); 142 object_property_add_alias(obj, "hw-strap2", OBJECT(&s->scu), 143 "hw-strap2", &error_abort); 144 object_property_add_alias(obj, "hw-prot-key", OBJECT(&s->scu), 145 "hw-prot-key", &error_abort); 146 147 sysbus_init_child_obj(obj, "a7mpcore", &s->a7mpcore, 148 sizeof(s->a7mpcore), TYPE_A15MPCORE_PRIV); 149 150 sysbus_init_child_obj(obj, "rtc", OBJECT(&s->rtc), sizeof(s->rtc), 151 TYPE_ASPEED_RTC); 152 153 snprintf(typename, sizeof(typename), "aspeed.timer-%s", socname); 154 sysbus_init_child_obj(obj, "timerctrl", OBJECT(&s->timerctrl), 155 sizeof(s->timerctrl), typename); 156 157 snprintf(typename, sizeof(typename), "aspeed.i2c-%s", socname); 158 sysbus_init_child_obj(obj, "i2c", OBJECT(&s->i2c), sizeof(s->i2c), 159 typename); 160 161 snprintf(typename, sizeof(typename), "aspeed.fmc-%s", socname); 162 sysbus_init_child_obj(obj, "fmc", OBJECT(&s->fmc), sizeof(s->fmc), 163 typename); 164 object_property_add_alias(obj, "num-cs", OBJECT(&s->fmc), "num-cs", 165 &error_abort); 166 167 for (i = 0; i < sc->spis_num; i++) { 168 snprintf(typename, sizeof(typename), "aspeed.spi%d-%s", i + 1, socname); 169 sysbus_init_child_obj(obj, "spi[*]", OBJECT(&s->spi[i]), 170 sizeof(s->spi[i]), typename); 171 } 172 173 for (i = 0; i < sc->ehcis_num; i++) { 174 sysbus_init_child_obj(obj, "ehci[*]", OBJECT(&s->ehci[i]), 175 sizeof(s->ehci[i]), TYPE_PLATFORM_EHCI); 176 } 177 178 snprintf(typename, sizeof(typename), "aspeed.sdmc-%s", socname); 179 sysbus_init_child_obj(obj, "sdmc", OBJECT(&s->sdmc), sizeof(s->sdmc), 180 typename); 181 object_property_add_alias(obj, "ram-size", OBJECT(&s->sdmc), 182 "ram-size", &error_abort); 183 object_property_add_alias(obj, "max-ram-size", OBJECT(&s->sdmc), 184 "max-ram-size", &error_abort); 185 186 for (i = 0; i < sc->wdts_num; i++) { 187 snprintf(typename, sizeof(typename), "aspeed.wdt-%s", socname); 188 sysbus_init_child_obj(obj, "wdt[*]", OBJECT(&s->wdt[i]), 189 sizeof(s->wdt[i]), typename); 190 } 191 192 for (i = 0; i < sc->macs_num; i++) { 193 sysbus_init_child_obj(obj, "ftgmac100[*]", OBJECT(&s->ftgmac100[i]), 194 sizeof(s->ftgmac100[i]), TYPE_FTGMAC100); 195 196 sysbus_init_child_obj(obj, "mii[*]", &s->mii[i], sizeof(s->mii[i]), 197 TYPE_ASPEED_MII); 198 } 199 200 sysbus_init_child_obj(obj, "xdma", OBJECT(&s->xdma), sizeof(s->xdma), 201 TYPE_ASPEED_XDMA); 202 203 snprintf(typename, sizeof(typename), "aspeed.gpio-%s", socname); 204 sysbus_init_child_obj(obj, "gpio", OBJECT(&s->gpio), sizeof(s->gpio), 205 typename); 206 207 snprintf(typename, sizeof(typename), "aspeed.gpio-%s-1_8v", socname); 208 sysbus_init_child_obj(obj, "gpio_1_8v", OBJECT(&s->gpio_1_8v), 209 sizeof(s->gpio_1_8v), typename); 210 211 sysbus_init_child_obj(obj, "sd-controller", OBJECT(&s->sdhci), 212 sizeof(s->sdhci), TYPE_ASPEED_SDHCI); 213 214 object_property_set_int(OBJECT(&s->sdhci), 2, "num-slots", &error_abort); 215 216 /* Init sd card slot class here so that they're under the correct parent */ 217 for (i = 0; i < ASPEED_SDHCI_NUM_SLOTS; ++i) { 218 sysbus_init_child_obj(obj, "sd-controller.sdhci[*]", 219 OBJECT(&s->sdhci.slots[i]), 220 sizeof(s->sdhci.slots[i]), TYPE_SYSBUS_SDHCI); 221 } 222 223 sysbus_init_child_obj(obj, "emmc-controller", OBJECT(&s->emmc), 224 sizeof(s->emmc), TYPE_ASPEED_SDHCI); 225 226 object_property_set_int(OBJECT(&s->emmc), 1, "num-slots", &error_abort); 227 228 sysbus_init_child_obj(obj, "emmc-controller.sdhci", 229 OBJECT(&s->emmc.slots[0]), sizeof(s->emmc.slots[0]), 230 TYPE_SYSBUS_SDHCI); 231 } 232 233 /* 234 * ASPEED ast2600 has 0xf as cluster ID 235 * 236 * http://infocenter.arm.com/help/index.jsp?topic=/com.arm.doc.ddi0388e/CIHEBGFG.html 237 */ 238 static uint64_t aspeed_calc_affinity(int cpu) 239 { 240 return (0xf << ARM_AFF1_SHIFT) | cpu; 241 } 242 243 static void aspeed_soc_ast2600_realize(DeviceState *dev, Error **errp) 244 { 245 int i; 246 AspeedSoCState *s = ASPEED_SOC(dev); 247 AspeedSoCClass *sc = ASPEED_SOC_GET_CLASS(s); 248 Error *err = NULL, *local_err = NULL; 249 qemu_irq irq; 250 251 /* IO space */ 252 create_unimplemented_device("aspeed_soc.io", sc->memmap[ASPEED_IOMEM], 253 ASPEED_SOC_IOMEM_SIZE); 254 255 /* Video engine stub */ 256 create_unimplemented_device("aspeed.video", sc->memmap[ASPEED_VIDEO], 257 0x1000); 258 259 if (s->num_cpus > sc->num_cpus) { 260 warn_report("%s: invalid number of CPUs %d, using default %d", 261 sc->name, s->num_cpus, sc->num_cpus); 262 s->num_cpus = sc->num_cpus; 263 } 264 265 /* CPU */ 266 for (i = 0; i < s->num_cpus; i++) { 267 object_property_set_int(OBJECT(&s->cpu[i]), QEMU_PSCI_CONDUIT_SMC, 268 "psci-conduit", &error_abort); 269 if (s->num_cpus > 1) { 270 object_property_set_int(OBJECT(&s->cpu[i]), 271 ASPEED_A7MPCORE_ADDR, 272 "reset-cbar", &error_abort); 273 } 274 object_property_set_int(OBJECT(&s->cpu[i]), aspeed_calc_affinity(i), 275 "mp-affinity", &error_abort); 276 277 object_property_set_int(OBJECT(&s->cpu[i]), 1125000000, "cntfrq", 278 &error_abort); 279 280 /* 281 * TODO: the secondary CPUs are started and a boot helper 282 * is needed when using -kernel 283 */ 284 285 object_property_set_bool(OBJECT(&s->cpu[i]), true, "realized", &err); 286 if (err) { 287 error_propagate(errp, err); 288 return; 289 } 290 } 291 292 /* A7MPCORE */ 293 object_property_set_int(OBJECT(&s->a7mpcore), s->num_cpus, "num-cpu", 294 &error_abort); 295 object_property_set_int(OBJECT(&s->a7mpcore), 296 ASPEED_SOC_AST2600_MAX_IRQ + GIC_INTERNAL, 297 "num-irq", &error_abort); 298 299 object_property_set_bool(OBJECT(&s->a7mpcore), true, "realized", 300 &error_abort); 301 sysbus_mmio_map(SYS_BUS_DEVICE(&s->a7mpcore), 0, ASPEED_A7MPCORE_ADDR); 302 303 for (i = 0; i < s->num_cpus; i++) { 304 SysBusDevice *sbd = SYS_BUS_DEVICE(&s->a7mpcore); 305 DeviceState *d = DEVICE(qemu_get_cpu(i)); 306 307 irq = qdev_get_gpio_in(d, ARM_CPU_IRQ); 308 sysbus_connect_irq(sbd, i, irq); 309 irq = qdev_get_gpio_in(d, ARM_CPU_FIQ); 310 sysbus_connect_irq(sbd, i + s->num_cpus, irq); 311 irq = qdev_get_gpio_in(d, ARM_CPU_VIRQ); 312 sysbus_connect_irq(sbd, i + 2 * s->num_cpus, irq); 313 irq = qdev_get_gpio_in(d, ARM_CPU_VFIQ); 314 sysbus_connect_irq(sbd, i + 3 * s->num_cpus, irq); 315 } 316 317 /* SRAM */ 318 memory_region_init_ram(&s->sram, OBJECT(dev), "aspeed.sram", 319 sc->sram_size, &err); 320 if (err) { 321 error_propagate(errp, err); 322 return; 323 } 324 memory_region_add_subregion(get_system_memory(), 325 sc->memmap[ASPEED_SRAM], &s->sram); 326 327 /* SCU */ 328 object_property_set_bool(OBJECT(&s->scu), true, "realized", &err); 329 if (err) { 330 error_propagate(errp, err); 331 return; 332 } 333 sysbus_mmio_map(SYS_BUS_DEVICE(&s->scu), 0, sc->memmap[ASPEED_SCU]); 334 335 /* RTC */ 336 object_property_set_bool(OBJECT(&s->rtc), true, "realized", &err); 337 if (err) { 338 error_propagate(errp, err); 339 return; 340 } 341 sysbus_mmio_map(SYS_BUS_DEVICE(&s->rtc), 0, sc->memmap[ASPEED_RTC]); 342 sysbus_connect_irq(SYS_BUS_DEVICE(&s->rtc), 0, 343 aspeed_soc_get_irq(s, ASPEED_RTC)); 344 345 /* Timer */ 346 object_property_set_link(OBJECT(&s->timerctrl), 347 OBJECT(&s->scu), "scu", &error_abort); 348 object_property_set_bool(OBJECT(&s->timerctrl), true, "realized", &err); 349 if (err) { 350 error_propagate(errp, err); 351 return; 352 } 353 sysbus_mmio_map(SYS_BUS_DEVICE(&s->timerctrl), 0, 354 sc->memmap[ASPEED_TIMER1]); 355 for (i = 0; i < ASPEED_TIMER_NR_TIMERS; i++) { 356 qemu_irq irq = aspeed_soc_get_irq(s, ASPEED_TIMER1 + i); 357 sysbus_connect_irq(SYS_BUS_DEVICE(&s->timerctrl), i, irq); 358 } 359 360 /* UART - attach an 8250 to the IO space as our UART5 */ 361 if (serial_hd(0)) { 362 qemu_irq uart5 = aspeed_soc_get_irq(s, ASPEED_UART5); 363 serial_mm_init(get_system_memory(), sc->memmap[ASPEED_UART5], 2, 364 uart5, 38400, serial_hd(0), DEVICE_LITTLE_ENDIAN); 365 } 366 367 /* I2C */ 368 object_property_set_link(OBJECT(&s->i2c), OBJECT(s->dram_mr), "dram", &err); 369 if (err) { 370 error_propagate(errp, err); 371 return; 372 } 373 object_property_set_bool(OBJECT(&s->i2c), true, "realized", &err); 374 if (err) { 375 error_propagate(errp, err); 376 return; 377 } 378 sysbus_mmio_map(SYS_BUS_DEVICE(&s->i2c), 0, sc->memmap[ASPEED_I2C]); 379 for (i = 0; i < ASPEED_I2C_GET_CLASS(&s->i2c)->num_busses; i++) { 380 qemu_irq irq = qdev_get_gpio_in(DEVICE(&s->a7mpcore), 381 sc->irqmap[ASPEED_I2C] + i); 382 /* 383 * The AST2600 SoC has one IRQ per I2C bus. Skip the common 384 * IRQ (AST2400 and AST2500) and connect all bussses. 385 */ 386 sysbus_connect_irq(SYS_BUS_DEVICE(&s->i2c), i + 1, irq); 387 } 388 389 /* FMC, The number of CS is set at the board level */ 390 object_property_set_link(OBJECT(&s->fmc), OBJECT(s->dram_mr), "dram", &err); 391 if (err) { 392 error_propagate(errp, err); 393 return; 394 } 395 object_property_set_int(OBJECT(&s->fmc), sc->memmap[ASPEED_SDRAM], 396 "sdram-base", &err); 397 if (err) { 398 error_propagate(errp, err); 399 return; 400 } 401 object_property_set_bool(OBJECT(&s->fmc), true, "realized", &err); 402 if (err) { 403 error_propagate(errp, err); 404 return; 405 } 406 sysbus_mmio_map(SYS_BUS_DEVICE(&s->fmc), 0, sc->memmap[ASPEED_FMC]); 407 sysbus_mmio_map(SYS_BUS_DEVICE(&s->fmc), 1, 408 s->fmc.ctrl->flash_window_base); 409 sysbus_connect_irq(SYS_BUS_DEVICE(&s->fmc), 0, 410 aspeed_soc_get_irq(s, ASPEED_FMC)); 411 412 /* SPI */ 413 for (i = 0; i < sc->spis_num; i++) { 414 object_property_set_link(OBJECT(&s->spi[i]), OBJECT(s->dram_mr), 415 "dram", &err); 416 if (err) { 417 error_propagate(errp, err); 418 return; 419 } 420 object_property_set_int(OBJECT(&s->spi[i]), 1, "num-cs", &err); 421 object_property_set_bool(OBJECT(&s->spi[i]), true, "realized", 422 &local_err); 423 error_propagate(&err, local_err); 424 if (err) { 425 error_propagate(errp, err); 426 return; 427 } 428 sysbus_mmio_map(SYS_BUS_DEVICE(&s->spi[i]), 0, 429 sc->memmap[ASPEED_SPI1 + i]); 430 sysbus_mmio_map(SYS_BUS_DEVICE(&s->spi[i]), 1, 431 s->spi[i].ctrl->flash_window_base); 432 } 433 434 /* EHCI */ 435 for (i = 0; i < sc->ehcis_num; i++) { 436 object_property_set_bool(OBJECT(&s->ehci[i]), true, "realized", &err); 437 if (err) { 438 error_propagate(errp, err); 439 return; 440 } 441 sysbus_mmio_map(SYS_BUS_DEVICE(&s->ehci[i]), 0, 442 sc->memmap[ASPEED_EHCI1 + i]); 443 sysbus_connect_irq(SYS_BUS_DEVICE(&s->ehci[i]), 0, 444 aspeed_soc_get_irq(s, ASPEED_EHCI1 + i)); 445 } 446 447 /* SDMC - SDRAM Memory Controller */ 448 object_property_set_bool(OBJECT(&s->sdmc), true, "realized", &err); 449 if (err) { 450 error_propagate(errp, err); 451 return; 452 } 453 sysbus_mmio_map(SYS_BUS_DEVICE(&s->sdmc), 0, sc->memmap[ASPEED_SDMC]); 454 455 /* Watch dog */ 456 for (i = 0; i < sc->wdts_num; i++) { 457 AspeedWDTClass *awc = ASPEED_WDT_GET_CLASS(&s->wdt[i]); 458 459 object_property_set_link(OBJECT(&s->wdt[i]), 460 OBJECT(&s->scu), "scu", &error_abort); 461 object_property_set_bool(OBJECT(&s->wdt[i]), true, "realized", &err); 462 if (err) { 463 error_propagate(errp, err); 464 return; 465 } 466 sysbus_mmio_map(SYS_BUS_DEVICE(&s->wdt[i]), 0, 467 sc->memmap[ASPEED_WDT] + i * awc->offset); 468 } 469 470 /* Net */ 471 for (i = 0; i < nb_nics && i < sc->macs_num; i++) { 472 qdev_set_nic_properties(DEVICE(&s->ftgmac100[i]), &nd_table[i]); 473 object_property_set_bool(OBJECT(&s->ftgmac100[i]), true, "aspeed", 474 &err); 475 object_property_set_bool(OBJECT(&s->ftgmac100[i]), true, "realized", 476 &local_err); 477 error_propagate(&err, local_err); 478 if (err) { 479 error_propagate(errp, err); 480 return; 481 } 482 sysbus_mmio_map(SYS_BUS_DEVICE(&s->ftgmac100[i]), 0, 483 sc->memmap[ASPEED_ETH1 + i]); 484 sysbus_connect_irq(SYS_BUS_DEVICE(&s->ftgmac100[i]), 0, 485 aspeed_soc_get_irq(s, ASPEED_ETH1 + i)); 486 487 object_property_set_link(OBJECT(&s->mii[i]), OBJECT(&s->ftgmac100[i]), 488 "nic", &error_abort); 489 object_property_set_bool(OBJECT(&s->mii[i]), true, "realized", 490 &err); 491 if (err) { 492 error_propagate(errp, err); 493 return; 494 } 495 496 sysbus_mmio_map(SYS_BUS_DEVICE(&s->mii[i]), 0, 497 sc->memmap[ASPEED_MII1 + i]); 498 } 499 500 /* XDMA */ 501 object_property_set_bool(OBJECT(&s->xdma), true, "realized", &err); 502 if (err) { 503 error_propagate(errp, err); 504 return; 505 } 506 sysbus_mmio_map(SYS_BUS_DEVICE(&s->xdma), 0, 507 sc->memmap[ASPEED_XDMA]); 508 sysbus_connect_irq(SYS_BUS_DEVICE(&s->xdma), 0, 509 aspeed_soc_get_irq(s, ASPEED_XDMA)); 510 511 /* GPIO */ 512 object_property_set_bool(OBJECT(&s->gpio), true, "realized", &err); 513 if (err) { 514 error_propagate(errp, err); 515 return; 516 } 517 sysbus_mmio_map(SYS_BUS_DEVICE(&s->gpio), 0, sc->memmap[ASPEED_GPIO]); 518 sysbus_connect_irq(SYS_BUS_DEVICE(&s->gpio), 0, 519 aspeed_soc_get_irq(s, ASPEED_GPIO)); 520 521 object_property_set_bool(OBJECT(&s->gpio_1_8v), true, "realized", &err); 522 if (err) { 523 error_propagate(errp, err); 524 return; 525 } 526 sysbus_mmio_map(SYS_BUS_DEVICE(&s->gpio_1_8v), 0, 527 sc->memmap[ASPEED_GPIO_1_8V]); 528 sysbus_connect_irq(SYS_BUS_DEVICE(&s->gpio_1_8v), 0, 529 aspeed_soc_get_irq(s, ASPEED_GPIO_1_8V)); 530 531 /* SDHCI */ 532 object_property_set_bool(OBJECT(&s->sdhci), true, "realized", &err); 533 if (err) { 534 error_propagate(errp, err); 535 return; 536 } 537 sysbus_mmio_map(SYS_BUS_DEVICE(&s->sdhci), 0, 538 sc->memmap[ASPEED_SDHCI]); 539 sysbus_connect_irq(SYS_BUS_DEVICE(&s->sdhci), 0, 540 aspeed_soc_get_irq(s, ASPEED_SDHCI)); 541 542 /* eMMC */ 543 object_property_set_bool(OBJECT(&s->emmc), true, "realized", &err); 544 if (err) { 545 error_propagate(errp, err); 546 return; 547 } 548 sysbus_mmio_map(SYS_BUS_DEVICE(&s->emmc), 0, sc->memmap[ASPEED_EMMC]); 549 sysbus_connect_irq(SYS_BUS_DEVICE(&s->emmc), 0, 550 aspeed_soc_get_irq(s, ASPEED_EMMC)); 551 } 552 553 static void aspeed_soc_ast2600_class_init(ObjectClass *oc, void *data) 554 { 555 DeviceClass *dc = DEVICE_CLASS(oc); 556 AspeedSoCClass *sc = ASPEED_SOC_CLASS(oc); 557 558 dc->realize = aspeed_soc_ast2600_realize; 559 560 sc->name = "ast2600-a1"; 561 sc->cpu_type = ARM_CPU_TYPE_NAME("cortex-a7"); 562 sc->silicon_rev = AST2600_A1_SILICON_REV; 563 sc->sram_size = 0x10000; 564 sc->spis_num = 2; 565 sc->ehcis_num = 2; 566 sc->wdts_num = 4; 567 sc->macs_num = 4; 568 sc->irqmap = aspeed_soc_ast2600_irqmap; 569 sc->memmap = aspeed_soc_ast2600_memmap; 570 sc->num_cpus = 2; 571 } 572 573 static const TypeInfo aspeed_soc_ast2600_type_info = { 574 .name = "ast2600-a1", 575 .parent = TYPE_ASPEED_SOC, 576 .instance_size = sizeof(AspeedSoCState), 577 .instance_init = aspeed_soc_ast2600_init, 578 .class_init = aspeed_soc_ast2600_class_init, 579 .class_size = sizeof(AspeedSoCClass), 580 }; 581 582 static void aspeed_soc_register_types(void) 583 { 584 type_register_static(&aspeed_soc_ast2600_type_info); 585 }; 586 587 type_init(aspeed_soc_register_types) 588