1 /* 2 * ASPEED SoC 2600 family 3 * 4 * Copyright (c) 2016-2019, IBM Corporation. 5 * 6 * This code is licensed under the GPL version 2 or later. See 7 * the COPYING file in the top-level directory. 8 */ 9 10 #include "qemu/osdep.h" 11 #include "qapi/error.h" 12 #include "hw/misc/unimp.h" 13 #include "hw/arm/aspeed_soc.h" 14 #include "hw/char/serial.h" 15 #include "qemu/module.h" 16 #include "qemu/error-report.h" 17 #include "hw/i2c/aspeed_i2c.h" 18 #include "net/net.h" 19 #include "sysemu/sysemu.h" 20 21 #define ASPEED_SOC_IOMEM_SIZE 0x00200000 22 #define ASPEED_SOC_DPMCU_SIZE 0x00040000 23 24 static const hwaddr aspeed_soc_ast2600_memmap[] = { 25 [ASPEED_DEV_SRAM] = 0x10000000, 26 [ASPEED_DEV_DPMCU] = 0x18000000, 27 /* 0x16000000 0x17FFFFFF : AHB BUS do LPC Bus bridge */ 28 [ASPEED_DEV_IOMEM] = 0x1E600000, 29 [ASPEED_DEV_PWM] = 0x1E610000, 30 [ASPEED_DEV_FMC] = 0x1E620000, 31 [ASPEED_DEV_SPI1] = 0x1E630000, 32 [ASPEED_DEV_SPI2] = 0x1E641000, 33 [ASPEED_DEV_EHCI1] = 0x1E6A1000, 34 [ASPEED_DEV_EHCI2] = 0x1E6A3000, 35 [ASPEED_DEV_MII1] = 0x1E650000, 36 [ASPEED_DEV_MII2] = 0x1E650008, 37 [ASPEED_DEV_MII3] = 0x1E650010, 38 [ASPEED_DEV_MII4] = 0x1E650018, 39 [ASPEED_DEV_ETH1] = 0x1E660000, 40 [ASPEED_DEV_ETH3] = 0x1E670000, 41 [ASPEED_DEV_ETH2] = 0x1E680000, 42 [ASPEED_DEV_ETH4] = 0x1E690000, 43 [ASPEED_DEV_VIC] = 0x1E6C0000, 44 [ASPEED_DEV_HACE] = 0x1E6D0000, 45 [ASPEED_DEV_SDMC] = 0x1E6E0000, 46 [ASPEED_DEV_SCU] = 0x1E6E2000, 47 [ASPEED_DEV_XDMA] = 0x1E6E7000, 48 [ASPEED_DEV_ADC] = 0x1E6E9000, 49 [ASPEED_DEV_DP] = 0x1E6EB000, 50 [ASPEED_DEV_VIDEO] = 0x1E700000, 51 [ASPEED_DEV_SDHCI] = 0x1E740000, 52 [ASPEED_DEV_EMMC] = 0x1E750000, 53 [ASPEED_DEV_GPIO] = 0x1E780000, 54 [ASPEED_DEV_GPIO_1_8V] = 0x1E780800, 55 [ASPEED_DEV_RTC] = 0x1E781000, 56 [ASPEED_DEV_TIMER1] = 0x1E782000, 57 [ASPEED_DEV_WDT] = 0x1E785000, 58 [ASPEED_DEV_LPC] = 0x1E789000, 59 [ASPEED_DEV_IBT] = 0x1E789140, 60 [ASPEED_DEV_I2C] = 0x1E78A000, 61 [ASPEED_DEV_UART1] = 0x1E783000, 62 [ASPEED_DEV_UART5] = 0x1E784000, 63 [ASPEED_DEV_VUART] = 0x1E787000, 64 [ASPEED_DEV_SDRAM] = 0x80000000, 65 }; 66 67 #define ASPEED_A7MPCORE_ADDR 0x40460000 68 69 #define AST2600_MAX_IRQ 197 70 71 /* Shared Peripheral Interrupt values below are offset by -32 from datasheet */ 72 static const int aspeed_soc_ast2600_irqmap[] = { 73 [ASPEED_DEV_UART1] = 47, 74 [ASPEED_DEV_UART2] = 48, 75 [ASPEED_DEV_UART3] = 49, 76 [ASPEED_DEV_UART4] = 50, 77 [ASPEED_DEV_UART5] = 8, 78 [ASPEED_DEV_VUART] = 8, 79 [ASPEED_DEV_FMC] = 39, 80 [ASPEED_DEV_SDMC] = 0, 81 [ASPEED_DEV_SCU] = 12, 82 [ASPEED_DEV_ADC] = 78, 83 [ASPEED_DEV_XDMA] = 6, 84 [ASPEED_DEV_SDHCI] = 43, 85 [ASPEED_DEV_EHCI1] = 5, 86 [ASPEED_DEV_EHCI2] = 9, 87 [ASPEED_DEV_EMMC] = 15, 88 [ASPEED_DEV_GPIO] = 40, 89 [ASPEED_DEV_GPIO_1_8V] = 11, 90 [ASPEED_DEV_RTC] = 13, 91 [ASPEED_DEV_TIMER1] = 16, 92 [ASPEED_DEV_TIMER2] = 17, 93 [ASPEED_DEV_TIMER3] = 18, 94 [ASPEED_DEV_TIMER4] = 19, 95 [ASPEED_DEV_TIMER5] = 20, 96 [ASPEED_DEV_TIMER6] = 21, 97 [ASPEED_DEV_TIMER7] = 22, 98 [ASPEED_DEV_TIMER8] = 23, 99 [ASPEED_DEV_WDT] = 24, 100 [ASPEED_DEV_PWM] = 44, 101 [ASPEED_DEV_LPC] = 35, 102 [ASPEED_DEV_IBT] = 143, 103 [ASPEED_DEV_I2C] = 110, /* 110 -> 125 */ 104 [ASPEED_DEV_ETH1] = 2, 105 [ASPEED_DEV_ETH2] = 3, 106 [ASPEED_DEV_HACE] = 4, 107 [ASPEED_DEV_ETH3] = 32, 108 [ASPEED_DEV_ETH4] = 33, 109 [ASPEED_DEV_KCS] = 138, /* 138 -> 142 */ 110 [ASPEED_DEV_DP] = 62, 111 }; 112 113 static qemu_irq aspeed_soc_get_irq(AspeedSoCState *s, int ctrl) 114 { 115 AspeedSoCClass *sc = ASPEED_SOC_GET_CLASS(s); 116 117 return qdev_get_gpio_in(DEVICE(&s->a7mpcore), sc->irqmap[ctrl]); 118 } 119 120 static void aspeed_soc_ast2600_init(Object *obj) 121 { 122 AspeedSoCState *s = ASPEED_SOC(obj); 123 AspeedSoCClass *sc = ASPEED_SOC_GET_CLASS(s); 124 int i; 125 char socname[8]; 126 char typename[64]; 127 128 if (sscanf(sc->name, "%7s", socname) != 1) { 129 g_assert_not_reached(); 130 } 131 132 for (i = 0; i < sc->num_cpus; i++) { 133 object_initialize_child(obj, "cpu[*]", &s->cpu[i], sc->cpu_type); 134 } 135 136 snprintf(typename, sizeof(typename), "aspeed.scu-%s", socname); 137 object_initialize_child(obj, "scu", &s->scu, typename); 138 qdev_prop_set_uint32(DEVICE(&s->scu), "silicon-rev", 139 sc->silicon_rev); 140 object_property_add_alias(obj, "hw-strap1", OBJECT(&s->scu), 141 "hw-strap1"); 142 object_property_add_alias(obj, "hw-strap2", OBJECT(&s->scu), 143 "hw-strap2"); 144 object_property_add_alias(obj, "hw-prot-key", OBJECT(&s->scu), 145 "hw-prot-key"); 146 147 object_initialize_child(obj, "a7mpcore", &s->a7mpcore, 148 TYPE_A15MPCORE_PRIV); 149 150 object_initialize_child(obj, "rtc", &s->rtc, TYPE_ASPEED_RTC); 151 152 snprintf(typename, sizeof(typename), "aspeed.timer-%s", socname); 153 object_initialize_child(obj, "timerctrl", &s->timerctrl, typename); 154 155 snprintf(typename, sizeof(typename), "aspeed.adc-%s", socname); 156 object_initialize_child(obj, "adc", &s->adc, typename); 157 158 snprintf(typename, sizeof(typename), "aspeed.i2c-%s", socname); 159 object_initialize_child(obj, "i2c", &s->i2c, typename); 160 161 snprintf(typename, sizeof(typename), "aspeed.fmc-%s", socname); 162 object_initialize_child(obj, "fmc", &s->fmc, typename); 163 object_property_add_alias(obj, "num-cs", OBJECT(&s->fmc), "num-cs"); 164 165 for (i = 0; i < sc->spis_num; i++) { 166 snprintf(typename, sizeof(typename), "aspeed.spi%d-%s", i + 1, socname); 167 object_initialize_child(obj, "spi[*]", &s->spi[i], typename); 168 } 169 170 for (i = 0; i < sc->ehcis_num; i++) { 171 object_initialize_child(obj, "ehci[*]", &s->ehci[i], 172 TYPE_PLATFORM_EHCI); 173 } 174 175 snprintf(typename, sizeof(typename), "aspeed.sdmc-%s", socname); 176 object_initialize_child(obj, "sdmc", &s->sdmc, typename); 177 object_property_add_alias(obj, "ram-size", OBJECT(&s->sdmc), 178 "ram-size"); 179 object_property_add_alias(obj, "max-ram-size", OBJECT(&s->sdmc), 180 "max-ram-size"); 181 182 for (i = 0; i < sc->wdts_num; i++) { 183 snprintf(typename, sizeof(typename), "aspeed.wdt-%s", socname); 184 object_initialize_child(obj, "wdt[*]", &s->wdt[i], typename); 185 } 186 187 for (i = 0; i < sc->macs_num; i++) { 188 object_initialize_child(obj, "ftgmac100[*]", &s->ftgmac100[i], 189 TYPE_FTGMAC100); 190 191 object_initialize_child(obj, "mii[*]", &s->mii[i], TYPE_ASPEED_MII); 192 } 193 194 snprintf(typename, sizeof(typename), TYPE_ASPEED_XDMA "-%s", socname); 195 object_initialize_child(obj, "xdma", &s->xdma, typename); 196 197 snprintf(typename, sizeof(typename), "aspeed.gpio-%s", socname); 198 object_initialize_child(obj, "gpio", &s->gpio, typename); 199 200 snprintf(typename, sizeof(typename), "aspeed.gpio-%s-1_8v", socname); 201 object_initialize_child(obj, "gpio_1_8v", &s->gpio_1_8v, typename); 202 203 object_initialize_child(obj, "sd-controller", &s->sdhci, 204 TYPE_ASPEED_SDHCI); 205 206 object_property_set_int(OBJECT(&s->sdhci), "num-slots", 2, &error_abort); 207 208 /* Init sd card slot class here so that they're under the correct parent */ 209 for (i = 0; i < ASPEED_SDHCI_NUM_SLOTS; ++i) { 210 object_initialize_child(obj, "sd-controller.sdhci[*]", 211 &s->sdhci.slots[i], TYPE_SYSBUS_SDHCI); 212 } 213 214 object_initialize_child(obj, "emmc-controller", &s->emmc, 215 TYPE_ASPEED_SDHCI); 216 217 object_property_set_int(OBJECT(&s->emmc), "num-slots", 1, &error_abort); 218 219 object_initialize_child(obj, "emmc-controller.sdhci", &s->emmc.slots[0], 220 TYPE_SYSBUS_SDHCI); 221 222 object_initialize_child(obj, "lpc", &s->lpc, TYPE_ASPEED_LPC); 223 224 snprintf(typename, sizeof(typename), "aspeed.hace-%s", socname); 225 object_initialize_child(obj, "hace", &s->hace, typename); 226 } 227 228 /* 229 * ASPEED ast2600 has 0xf as cluster ID 230 * 231 * https://developer.arm.com/documentation/ddi0388/e/the-system-control-coprocessors/summary-of-system-control-coprocessor-registers/multiprocessor-affinity-register 232 */ 233 static uint64_t aspeed_calc_affinity(int cpu) 234 { 235 return (0xf << ARM_AFF1_SHIFT) | cpu; 236 } 237 238 static void aspeed_soc_ast2600_realize(DeviceState *dev, Error **errp) 239 { 240 int i; 241 AspeedSoCState *s = ASPEED_SOC(dev); 242 AspeedSoCClass *sc = ASPEED_SOC_GET_CLASS(s); 243 Error *err = NULL; 244 qemu_irq irq; 245 246 /* IO space */ 247 create_unimplemented_device("aspeed_soc.io", sc->memmap[ASPEED_DEV_IOMEM], 248 ASPEED_SOC_IOMEM_SIZE); 249 250 /* Video engine stub */ 251 create_unimplemented_device("aspeed.video", sc->memmap[ASPEED_DEV_VIDEO], 252 0x1000); 253 254 /* CPU */ 255 for (i = 0; i < sc->num_cpus; i++) { 256 if (sc->num_cpus > 1) { 257 object_property_set_int(OBJECT(&s->cpu[i]), "reset-cbar", 258 ASPEED_A7MPCORE_ADDR, &error_abort); 259 } 260 object_property_set_int(OBJECT(&s->cpu[i]), "mp-affinity", 261 aspeed_calc_affinity(i), &error_abort); 262 263 object_property_set_int(OBJECT(&s->cpu[i]), "cntfrq", 1125000000, 264 &error_abort); 265 266 if (!qdev_realize(DEVICE(&s->cpu[i]), NULL, errp)) { 267 return; 268 } 269 } 270 271 /* A7MPCORE */ 272 object_property_set_int(OBJECT(&s->a7mpcore), "num-cpu", sc->num_cpus, 273 &error_abort); 274 object_property_set_int(OBJECT(&s->a7mpcore), "num-irq", 275 ROUND_UP(AST2600_MAX_IRQ + GIC_INTERNAL, 32), 276 &error_abort); 277 278 sysbus_realize(SYS_BUS_DEVICE(&s->a7mpcore), &error_abort); 279 sysbus_mmio_map(SYS_BUS_DEVICE(&s->a7mpcore), 0, ASPEED_A7MPCORE_ADDR); 280 281 for (i = 0; i < sc->num_cpus; i++) { 282 SysBusDevice *sbd = SYS_BUS_DEVICE(&s->a7mpcore); 283 DeviceState *d = DEVICE(qemu_get_cpu(i)); 284 285 irq = qdev_get_gpio_in(d, ARM_CPU_IRQ); 286 sysbus_connect_irq(sbd, i, irq); 287 irq = qdev_get_gpio_in(d, ARM_CPU_FIQ); 288 sysbus_connect_irq(sbd, i + sc->num_cpus, irq); 289 irq = qdev_get_gpio_in(d, ARM_CPU_VIRQ); 290 sysbus_connect_irq(sbd, i + 2 * sc->num_cpus, irq); 291 irq = qdev_get_gpio_in(d, ARM_CPU_VFIQ); 292 sysbus_connect_irq(sbd, i + 3 * sc->num_cpus, irq); 293 } 294 295 /* SRAM */ 296 memory_region_init_ram(&s->sram, OBJECT(dev), "aspeed.sram", 297 sc->sram_size, &err); 298 if (err) { 299 error_propagate(errp, err); 300 return; 301 } 302 memory_region_add_subregion(get_system_memory(), 303 sc->memmap[ASPEED_DEV_SRAM], &s->sram); 304 305 /* DPMCU */ 306 create_unimplemented_device("aspeed.dpmcu", sc->memmap[ASPEED_DEV_DPMCU], 307 ASPEED_SOC_DPMCU_SIZE); 308 309 /* SCU */ 310 if (!sysbus_realize(SYS_BUS_DEVICE(&s->scu), errp)) { 311 return; 312 } 313 sysbus_mmio_map(SYS_BUS_DEVICE(&s->scu), 0, sc->memmap[ASPEED_DEV_SCU]); 314 315 /* RTC */ 316 if (!sysbus_realize(SYS_BUS_DEVICE(&s->rtc), errp)) { 317 return; 318 } 319 sysbus_mmio_map(SYS_BUS_DEVICE(&s->rtc), 0, sc->memmap[ASPEED_DEV_RTC]); 320 sysbus_connect_irq(SYS_BUS_DEVICE(&s->rtc), 0, 321 aspeed_soc_get_irq(s, ASPEED_DEV_RTC)); 322 323 /* Timer */ 324 object_property_set_link(OBJECT(&s->timerctrl), "scu", OBJECT(&s->scu), 325 &error_abort); 326 if (!sysbus_realize(SYS_BUS_DEVICE(&s->timerctrl), errp)) { 327 return; 328 } 329 sysbus_mmio_map(SYS_BUS_DEVICE(&s->timerctrl), 0, 330 sc->memmap[ASPEED_DEV_TIMER1]); 331 for (i = 0; i < ASPEED_TIMER_NR_TIMERS; i++) { 332 qemu_irq irq = aspeed_soc_get_irq(s, ASPEED_DEV_TIMER1 + i); 333 sysbus_connect_irq(SYS_BUS_DEVICE(&s->timerctrl), i, irq); 334 } 335 336 /* ADC */ 337 if (!sysbus_realize(SYS_BUS_DEVICE(&s->adc), errp)) { 338 return; 339 } 340 sysbus_mmio_map(SYS_BUS_DEVICE(&s->adc), 0, sc->memmap[ASPEED_DEV_ADC]); 341 sysbus_connect_irq(SYS_BUS_DEVICE(&s->adc), 0, 342 aspeed_soc_get_irq(s, ASPEED_DEV_ADC)); 343 344 /* UART - attach an 8250 to the IO space as our UART */ 345 serial_mm_init(get_system_memory(), sc->memmap[s->uart_default], 2, 346 aspeed_soc_get_irq(s, s->uart_default), 38400, 347 serial_hd(0), DEVICE_LITTLE_ENDIAN); 348 349 /* I2C */ 350 object_property_set_link(OBJECT(&s->i2c), "dram", OBJECT(s->dram_mr), 351 &error_abort); 352 if (!sysbus_realize(SYS_BUS_DEVICE(&s->i2c), errp)) { 353 return; 354 } 355 sysbus_mmio_map(SYS_BUS_DEVICE(&s->i2c), 0, sc->memmap[ASPEED_DEV_I2C]); 356 for (i = 0; i < ASPEED_I2C_GET_CLASS(&s->i2c)->num_busses; i++) { 357 qemu_irq irq = qdev_get_gpio_in(DEVICE(&s->a7mpcore), 358 sc->irqmap[ASPEED_DEV_I2C] + i); 359 /* The AST2600 I2C controller has one IRQ per bus. */ 360 sysbus_connect_irq(SYS_BUS_DEVICE(&s->i2c.busses[i]), 0, irq); 361 } 362 363 /* FMC, The number of CS is set at the board level */ 364 object_property_set_link(OBJECT(&s->fmc), "dram", OBJECT(s->dram_mr), 365 &error_abort); 366 if (!sysbus_realize(SYS_BUS_DEVICE(&s->fmc), errp)) { 367 return; 368 } 369 sysbus_mmio_map(SYS_BUS_DEVICE(&s->fmc), 0, sc->memmap[ASPEED_DEV_FMC]); 370 sysbus_mmio_map(SYS_BUS_DEVICE(&s->fmc), 1, 371 ASPEED_SMC_GET_CLASS(&s->fmc)->flash_window_base); 372 sysbus_connect_irq(SYS_BUS_DEVICE(&s->fmc), 0, 373 aspeed_soc_get_irq(s, ASPEED_DEV_FMC)); 374 375 /* SPI */ 376 for (i = 0; i < sc->spis_num; i++) { 377 object_property_set_link(OBJECT(&s->spi[i]), "dram", 378 OBJECT(s->dram_mr), &error_abort); 379 object_property_set_int(OBJECT(&s->spi[i]), "num-cs", 1, &error_abort); 380 if (!sysbus_realize(SYS_BUS_DEVICE(&s->spi[i]), errp)) { 381 return; 382 } 383 sysbus_mmio_map(SYS_BUS_DEVICE(&s->spi[i]), 0, 384 sc->memmap[ASPEED_DEV_SPI1 + i]); 385 sysbus_mmio_map(SYS_BUS_DEVICE(&s->spi[i]), 1, 386 ASPEED_SMC_GET_CLASS(&s->spi[i])->flash_window_base); 387 } 388 389 /* EHCI */ 390 for (i = 0; i < sc->ehcis_num; i++) { 391 if (!sysbus_realize(SYS_BUS_DEVICE(&s->ehci[i]), errp)) { 392 return; 393 } 394 sysbus_mmio_map(SYS_BUS_DEVICE(&s->ehci[i]), 0, 395 sc->memmap[ASPEED_DEV_EHCI1 + i]); 396 sysbus_connect_irq(SYS_BUS_DEVICE(&s->ehci[i]), 0, 397 aspeed_soc_get_irq(s, ASPEED_DEV_EHCI1 + i)); 398 } 399 400 /* SDMC - SDRAM Memory Controller */ 401 if (!sysbus_realize(SYS_BUS_DEVICE(&s->sdmc), errp)) { 402 return; 403 } 404 sysbus_mmio_map(SYS_BUS_DEVICE(&s->sdmc), 0, sc->memmap[ASPEED_DEV_SDMC]); 405 406 /* Watch dog */ 407 for (i = 0; i < sc->wdts_num; i++) { 408 AspeedWDTClass *awc = ASPEED_WDT_GET_CLASS(&s->wdt[i]); 409 410 object_property_set_link(OBJECT(&s->wdt[i]), "scu", OBJECT(&s->scu), 411 &error_abort); 412 if (!sysbus_realize(SYS_BUS_DEVICE(&s->wdt[i]), errp)) { 413 return; 414 } 415 sysbus_mmio_map(SYS_BUS_DEVICE(&s->wdt[i]), 0, 416 sc->memmap[ASPEED_DEV_WDT] + i * awc->offset); 417 } 418 419 /* Net */ 420 for (i = 0; i < sc->macs_num; i++) { 421 object_property_set_bool(OBJECT(&s->ftgmac100[i]), "aspeed", true, 422 &error_abort); 423 if (!sysbus_realize(SYS_BUS_DEVICE(&s->ftgmac100[i]), errp)) { 424 return; 425 } 426 sysbus_mmio_map(SYS_BUS_DEVICE(&s->ftgmac100[i]), 0, 427 sc->memmap[ASPEED_DEV_ETH1 + i]); 428 sysbus_connect_irq(SYS_BUS_DEVICE(&s->ftgmac100[i]), 0, 429 aspeed_soc_get_irq(s, ASPEED_DEV_ETH1 + i)); 430 431 object_property_set_link(OBJECT(&s->mii[i]), "nic", 432 OBJECT(&s->ftgmac100[i]), &error_abort); 433 if (!sysbus_realize(SYS_BUS_DEVICE(&s->mii[i]), errp)) { 434 return; 435 } 436 437 sysbus_mmio_map(SYS_BUS_DEVICE(&s->mii[i]), 0, 438 sc->memmap[ASPEED_DEV_MII1 + i]); 439 } 440 441 /* XDMA */ 442 if (!sysbus_realize(SYS_BUS_DEVICE(&s->xdma), errp)) { 443 return; 444 } 445 sysbus_mmio_map(SYS_BUS_DEVICE(&s->xdma), 0, 446 sc->memmap[ASPEED_DEV_XDMA]); 447 sysbus_connect_irq(SYS_BUS_DEVICE(&s->xdma), 0, 448 aspeed_soc_get_irq(s, ASPEED_DEV_XDMA)); 449 450 /* GPIO */ 451 if (!sysbus_realize(SYS_BUS_DEVICE(&s->gpio), errp)) { 452 return; 453 } 454 sysbus_mmio_map(SYS_BUS_DEVICE(&s->gpio), 0, sc->memmap[ASPEED_DEV_GPIO]); 455 sysbus_connect_irq(SYS_BUS_DEVICE(&s->gpio), 0, 456 aspeed_soc_get_irq(s, ASPEED_DEV_GPIO)); 457 458 if (!sysbus_realize(SYS_BUS_DEVICE(&s->gpio_1_8v), errp)) { 459 return; 460 } 461 sysbus_mmio_map(SYS_BUS_DEVICE(&s->gpio_1_8v), 0, 462 sc->memmap[ASPEED_DEV_GPIO_1_8V]); 463 sysbus_connect_irq(SYS_BUS_DEVICE(&s->gpio_1_8v), 0, 464 aspeed_soc_get_irq(s, ASPEED_DEV_GPIO_1_8V)); 465 466 /* SDHCI */ 467 if (!sysbus_realize(SYS_BUS_DEVICE(&s->sdhci), errp)) { 468 return; 469 } 470 sysbus_mmio_map(SYS_BUS_DEVICE(&s->sdhci), 0, 471 sc->memmap[ASPEED_DEV_SDHCI]); 472 sysbus_connect_irq(SYS_BUS_DEVICE(&s->sdhci), 0, 473 aspeed_soc_get_irq(s, ASPEED_DEV_SDHCI)); 474 475 /* eMMC */ 476 if (!sysbus_realize(SYS_BUS_DEVICE(&s->emmc), errp)) { 477 return; 478 } 479 sysbus_mmio_map(SYS_BUS_DEVICE(&s->emmc), 0, sc->memmap[ASPEED_DEV_EMMC]); 480 sysbus_connect_irq(SYS_BUS_DEVICE(&s->emmc), 0, 481 aspeed_soc_get_irq(s, ASPEED_DEV_EMMC)); 482 483 /* LPC */ 484 if (!sysbus_realize(SYS_BUS_DEVICE(&s->lpc), errp)) { 485 return; 486 } 487 sysbus_mmio_map(SYS_BUS_DEVICE(&s->lpc), 0, sc->memmap[ASPEED_DEV_LPC]); 488 489 /* Connect the LPC IRQ to the GIC. It is otherwise unused. */ 490 sysbus_connect_irq(SYS_BUS_DEVICE(&s->lpc), 0, 491 aspeed_soc_get_irq(s, ASPEED_DEV_LPC)); 492 493 /* 494 * On the AST2600 LPC subdevice IRQs are connected straight to the GIC. 495 * 496 * LPC subdevice IRQ sources are offset from 1 because the LPC model caters 497 * to the AST2400 and AST2500. SoCs before the AST2600 have one LPC IRQ 498 * shared across the subdevices, and the shared IRQ output to the VIC is at 499 * offset 0. 500 */ 501 sysbus_connect_irq(SYS_BUS_DEVICE(&s->lpc), 1 + aspeed_lpc_kcs_1, 502 qdev_get_gpio_in(DEVICE(&s->a7mpcore), 503 sc->irqmap[ASPEED_DEV_KCS] + aspeed_lpc_kcs_1)); 504 505 sysbus_connect_irq(SYS_BUS_DEVICE(&s->lpc), 1 + aspeed_lpc_kcs_2, 506 qdev_get_gpio_in(DEVICE(&s->a7mpcore), 507 sc->irqmap[ASPEED_DEV_KCS] + aspeed_lpc_kcs_2)); 508 509 sysbus_connect_irq(SYS_BUS_DEVICE(&s->lpc), 1 + aspeed_lpc_kcs_3, 510 qdev_get_gpio_in(DEVICE(&s->a7mpcore), 511 sc->irqmap[ASPEED_DEV_KCS] + aspeed_lpc_kcs_3)); 512 513 sysbus_connect_irq(SYS_BUS_DEVICE(&s->lpc), 1 + aspeed_lpc_kcs_4, 514 qdev_get_gpio_in(DEVICE(&s->a7mpcore), 515 sc->irqmap[ASPEED_DEV_KCS] + aspeed_lpc_kcs_4)); 516 517 /* HACE */ 518 object_property_set_link(OBJECT(&s->hace), "dram", OBJECT(s->dram_mr), 519 &error_abort); 520 if (!sysbus_realize(SYS_BUS_DEVICE(&s->hace), errp)) { 521 return; 522 } 523 sysbus_mmio_map(SYS_BUS_DEVICE(&s->hace), 0, sc->memmap[ASPEED_DEV_HACE]); 524 sysbus_connect_irq(SYS_BUS_DEVICE(&s->hace), 0, 525 aspeed_soc_get_irq(s, ASPEED_DEV_HACE)); 526 } 527 528 static void aspeed_soc_ast2600_class_init(ObjectClass *oc, void *data) 529 { 530 DeviceClass *dc = DEVICE_CLASS(oc); 531 AspeedSoCClass *sc = ASPEED_SOC_CLASS(oc); 532 533 dc->realize = aspeed_soc_ast2600_realize; 534 535 sc->name = "ast2600-a3"; 536 sc->cpu_type = ARM_CPU_TYPE_NAME("cortex-a7"); 537 sc->silicon_rev = AST2600_A3_SILICON_REV; 538 sc->sram_size = 0x16400; 539 sc->spis_num = 2; 540 sc->ehcis_num = 2; 541 sc->wdts_num = 4; 542 sc->macs_num = 4; 543 sc->irqmap = aspeed_soc_ast2600_irqmap; 544 sc->memmap = aspeed_soc_ast2600_memmap; 545 sc->num_cpus = 2; 546 } 547 548 static const TypeInfo aspeed_soc_ast2600_type_info = { 549 .name = "ast2600-a3", 550 .parent = TYPE_ASPEED_SOC, 551 .instance_size = sizeof(AspeedSoCState), 552 .instance_init = aspeed_soc_ast2600_init, 553 .class_init = aspeed_soc_ast2600_class_init, 554 .class_size = sizeof(AspeedSoCClass), 555 }; 556 557 static void aspeed_soc_register_types(void) 558 { 559 type_register_static(&aspeed_soc_ast2600_type_info); 560 }; 561 562 type_init(aspeed_soc_register_types) 563