12f4ec776SPhilippe Mathieu-Daudé /* 22f4ec776SPhilippe Mathieu-Daudé * ASPEED SoC family 32f4ec776SPhilippe Mathieu-Daudé * 42f4ec776SPhilippe Mathieu-Daudé * Andrew Jeffery <andrew@aj.id.au> 52f4ec776SPhilippe Mathieu-Daudé * Jeremy Kerr <jk@ozlabs.org> 62f4ec776SPhilippe Mathieu-Daudé * 72f4ec776SPhilippe Mathieu-Daudé * Copyright 2016 IBM Corp. 82f4ec776SPhilippe Mathieu-Daudé * 92f4ec776SPhilippe Mathieu-Daudé * This code is licensed under the GPL version 2 or later. See 102f4ec776SPhilippe Mathieu-Daudé * the COPYING file in the top-level directory. 112f4ec776SPhilippe Mathieu-Daudé */ 122f4ec776SPhilippe Mathieu-Daudé 132f4ec776SPhilippe Mathieu-Daudé #include "qemu/osdep.h" 142f4ec776SPhilippe Mathieu-Daudé #include "qapi/error.h" 151a94fae4SPhilippe Mathieu-Daudé #include "hw/qdev-properties.h" 162f4ec776SPhilippe Mathieu-Daudé #include "hw/misc/unimp.h" 172f4ec776SPhilippe Mathieu-Daudé #include "hw/arm/aspeed_soc.h" 182f4ec776SPhilippe Mathieu-Daudé #include "hw/char/serial.h" 192f4ec776SPhilippe Mathieu-Daudé 202f4ec776SPhilippe Mathieu-Daudé 212f4ec776SPhilippe Mathieu-Daudé qemu_irq aspeed_soc_get_irq(AspeedSoCState *s, int dev) 222f4ec776SPhilippe Mathieu-Daudé { 232f4ec776SPhilippe Mathieu-Daudé return ASPEED_SOC_GET_CLASS(s)->get_irq(s, dev); 242f4ec776SPhilippe Mathieu-Daudé } 252f4ec776SPhilippe Mathieu-Daudé 262f4ec776SPhilippe Mathieu-Daudé bool aspeed_soc_uart_realize(AspeedSoCState *s, Error **errp) 272f4ec776SPhilippe Mathieu-Daudé { 282f4ec776SPhilippe Mathieu-Daudé AspeedSoCClass *sc = ASPEED_SOC_GET_CLASS(s); 292f4ec776SPhilippe Mathieu-Daudé SerialMM *smm; 302f4ec776SPhilippe Mathieu-Daudé 312f4ec776SPhilippe Mathieu-Daudé for (int i = 0, uart = ASPEED_DEV_UART1; i < sc->uarts_num; i++, uart++) { 322f4ec776SPhilippe Mathieu-Daudé smm = &s->uart[i]; 332f4ec776SPhilippe Mathieu-Daudé 342f4ec776SPhilippe Mathieu-Daudé /* Chardev property is set by the machine. */ 352f4ec776SPhilippe Mathieu-Daudé qdev_prop_set_uint8(DEVICE(smm), "regshift", 2); 362f4ec776SPhilippe Mathieu-Daudé qdev_prop_set_uint32(DEVICE(smm), "baudbase", 38400); 372f4ec776SPhilippe Mathieu-Daudé qdev_set_legacy_instance_id(DEVICE(smm), sc->memmap[uart], 2); 382f4ec776SPhilippe Mathieu-Daudé qdev_prop_set_uint8(DEVICE(smm), "endianness", DEVICE_LITTLE_ENDIAN); 392f4ec776SPhilippe Mathieu-Daudé if (!sysbus_realize(SYS_BUS_DEVICE(smm), errp)) { 402f4ec776SPhilippe Mathieu-Daudé return false; 412f4ec776SPhilippe Mathieu-Daudé } 422f4ec776SPhilippe Mathieu-Daudé 432f4ec776SPhilippe Mathieu-Daudé sysbus_connect_irq(SYS_BUS_DEVICE(smm), 0, aspeed_soc_get_irq(s, uart)); 442f4ec776SPhilippe Mathieu-Daudé aspeed_mmio_map(s, SYS_BUS_DEVICE(smm), 0, sc->memmap[uart]); 452f4ec776SPhilippe Mathieu-Daudé } 462f4ec776SPhilippe Mathieu-Daudé 472f4ec776SPhilippe Mathieu-Daudé return true; 482f4ec776SPhilippe Mathieu-Daudé } 492f4ec776SPhilippe Mathieu-Daudé 502f4ec776SPhilippe Mathieu-Daudé void aspeed_soc_uart_set_chr(AspeedSoCState *s, int dev, Chardev *chr) 512f4ec776SPhilippe Mathieu-Daudé { 522f4ec776SPhilippe Mathieu-Daudé AspeedSoCClass *sc = ASPEED_SOC_GET_CLASS(s); 532f4ec776SPhilippe Mathieu-Daudé int i = dev - ASPEED_DEV_UART1; 542f4ec776SPhilippe Mathieu-Daudé 552f4ec776SPhilippe Mathieu-Daudé g_assert(0 <= i && i < ARRAY_SIZE(s->uart) && i < sc->uarts_num); 562f4ec776SPhilippe Mathieu-Daudé qdev_prop_set_chr(DEVICE(&s->uart[i]), "chardev", chr); 572f4ec776SPhilippe Mathieu-Daudé } 582f4ec776SPhilippe Mathieu-Daudé 592f4ec776SPhilippe Mathieu-Daudé /* 602f4ec776SPhilippe Mathieu-Daudé * SDMC should be realized first to get correct RAM size and max size 612f4ec776SPhilippe Mathieu-Daudé * values 622f4ec776SPhilippe Mathieu-Daudé */ 632f4ec776SPhilippe Mathieu-Daudé bool aspeed_soc_dram_init(AspeedSoCState *s, Error **errp) 642f4ec776SPhilippe Mathieu-Daudé { 652f4ec776SPhilippe Mathieu-Daudé AspeedSoCClass *sc = ASPEED_SOC_GET_CLASS(s); 662f4ec776SPhilippe Mathieu-Daudé ram_addr_t ram_size, max_ram_size; 672f4ec776SPhilippe Mathieu-Daudé 682f4ec776SPhilippe Mathieu-Daudé ram_size = object_property_get_uint(OBJECT(&s->sdmc), "ram-size", 692f4ec776SPhilippe Mathieu-Daudé &error_abort); 702f4ec776SPhilippe Mathieu-Daudé max_ram_size = object_property_get_uint(OBJECT(&s->sdmc), "max-ram-size", 712f4ec776SPhilippe Mathieu-Daudé &error_abort); 722f4ec776SPhilippe Mathieu-Daudé 732f4ec776SPhilippe Mathieu-Daudé memory_region_init(&s->dram_container, OBJECT(s), "ram-container", 742f4ec776SPhilippe Mathieu-Daudé max_ram_size); 752f4ec776SPhilippe Mathieu-Daudé memory_region_add_subregion(&s->dram_container, 0, s->dram_mr); 762f4ec776SPhilippe Mathieu-Daudé 772f4ec776SPhilippe Mathieu-Daudé /* 782f4ec776SPhilippe Mathieu-Daudé * Add a memory region beyond the RAM region to let firmwares scan 792f4ec776SPhilippe Mathieu-Daudé * the address space with load/store and guess how much RAM the 802f4ec776SPhilippe Mathieu-Daudé * SoC has. 812f4ec776SPhilippe Mathieu-Daudé */ 822f4ec776SPhilippe Mathieu-Daudé if (ram_size < max_ram_size) { 832f4ec776SPhilippe Mathieu-Daudé DeviceState *dev = qdev_new(TYPE_UNIMPLEMENTED_DEVICE); 842f4ec776SPhilippe Mathieu-Daudé 852f4ec776SPhilippe Mathieu-Daudé qdev_prop_set_string(dev, "name", "ram-empty"); 862f4ec776SPhilippe Mathieu-Daudé qdev_prop_set_uint64(dev, "size", max_ram_size - ram_size); 872f4ec776SPhilippe Mathieu-Daudé if (!sysbus_realize_and_unref(SYS_BUS_DEVICE(dev), errp)) { 882f4ec776SPhilippe Mathieu-Daudé return false; 892f4ec776SPhilippe Mathieu-Daudé } 902f4ec776SPhilippe Mathieu-Daudé 912f4ec776SPhilippe Mathieu-Daudé memory_region_add_subregion_overlap(&s->dram_container, ram_size, 922f4ec776SPhilippe Mathieu-Daudé sysbus_mmio_get_region(SYS_BUS_DEVICE(dev), 0), -1000); 932f4ec776SPhilippe Mathieu-Daudé } 942f4ec776SPhilippe Mathieu-Daudé 952f4ec776SPhilippe Mathieu-Daudé memory_region_add_subregion(s->memory, 962f4ec776SPhilippe Mathieu-Daudé sc->memmap[ASPEED_DEV_SDRAM], &s->dram_container); 972f4ec776SPhilippe Mathieu-Daudé return true; 982f4ec776SPhilippe Mathieu-Daudé } 992f4ec776SPhilippe Mathieu-Daudé 1002f4ec776SPhilippe Mathieu-Daudé void aspeed_mmio_map(AspeedSoCState *s, SysBusDevice *dev, int n, hwaddr addr) 1012f4ec776SPhilippe Mathieu-Daudé { 1022f4ec776SPhilippe Mathieu-Daudé memory_region_add_subregion(s->memory, addr, 1032f4ec776SPhilippe Mathieu-Daudé sysbus_mmio_get_region(dev, n)); 1042f4ec776SPhilippe Mathieu-Daudé } 1052f4ec776SPhilippe Mathieu-Daudé 1062f4ec776SPhilippe Mathieu-Daudé void aspeed_mmio_map_unimplemented(AspeedSoCState *s, SysBusDevice *dev, 1072f4ec776SPhilippe Mathieu-Daudé const char *name, hwaddr addr, uint64_t size) 1082f4ec776SPhilippe Mathieu-Daudé { 1092f4ec776SPhilippe Mathieu-Daudé qdev_prop_set_string(DEVICE(dev), "name", name); 1102f4ec776SPhilippe Mathieu-Daudé qdev_prop_set_uint64(DEVICE(dev), "size", size); 1112f4ec776SPhilippe Mathieu-Daudé sysbus_realize(dev, &error_abort); 1122f4ec776SPhilippe Mathieu-Daudé 1132f4ec776SPhilippe Mathieu-Daudé memory_region_add_subregion_overlap(s->memory, addr, 1142f4ec776SPhilippe Mathieu-Daudé sysbus_mmio_get_region(dev, 0), -1000); 1152f4ec776SPhilippe Mathieu-Daudé } 1161a94fae4SPhilippe Mathieu-Daudé 11724a88476SPhilippe Mathieu-Daudé static void aspeed_soc_realize(DeviceState *dev, Error **errp) 11824a88476SPhilippe Mathieu-Daudé { 11924a88476SPhilippe Mathieu-Daudé AspeedSoCState *s = ASPEED_SOC(dev); 12024a88476SPhilippe Mathieu-Daudé 12124a88476SPhilippe Mathieu-Daudé if (!s->memory) { 12224a88476SPhilippe Mathieu-Daudé error_setg(errp, "'memory' link is not set"); 12324a88476SPhilippe Mathieu-Daudé return; 12424a88476SPhilippe Mathieu-Daudé } 12524a88476SPhilippe Mathieu-Daudé } 12624a88476SPhilippe Mathieu-Daudé 1271a94fae4SPhilippe Mathieu-Daudé static Property aspeed_soc_properties[] = { 1281a94fae4SPhilippe Mathieu-Daudé DEFINE_PROP_LINK("dram", AspeedSoCState, dram_mr, TYPE_MEMORY_REGION, 1291a94fae4SPhilippe Mathieu-Daudé MemoryRegion *), 1301a94fae4SPhilippe Mathieu-Daudé DEFINE_PROP_LINK("memory", AspeedSoCState, memory, TYPE_MEMORY_REGION, 1311a94fae4SPhilippe Mathieu-Daudé MemoryRegion *), 1321a94fae4SPhilippe Mathieu-Daudé DEFINE_PROP_END_OF_LIST(), 1331a94fae4SPhilippe Mathieu-Daudé }; 1341a94fae4SPhilippe Mathieu-Daudé 1351a94fae4SPhilippe Mathieu-Daudé static void aspeed_soc_class_init(ObjectClass *oc, void *data) 1361a94fae4SPhilippe Mathieu-Daudé { 1371a94fae4SPhilippe Mathieu-Daudé DeviceClass *dc = DEVICE_CLASS(oc); 1381a94fae4SPhilippe Mathieu-Daudé 13924a88476SPhilippe Mathieu-Daudé dc->realize = aspeed_soc_realize; 1401a94fae4SPhilippe Mathieu-Daudé device_class_set_props(dc, aspeed_soc_properties); 1411a94fae4SPhilippe Mathieu-Daudé } 1421a94fae4SPhilippe Mathieu-Daudé 1431a94fae4SPhilippe Mathieu-Daudé static const TypeInfo aspeed_soc_types[] = { 1441a94fae4SPhilippe Mathieu-Daudé { 1451a94fae4SPhilippe Mathieu-Daudé .name = TYPE_ASPEED_SOC, 1461a94fae4SPhilippe Mathieu-Daudé .parent = TYPE_DEVICE, 1471a94fae4SPhilippe Mathieu-Daudé .instance_size = sizeof(AspeedSoCState), 1481a94fae4SPhilippe Mathieu-Daudé .class_size = sizeof(AspeedSoCClass), 1491a94fae4SPhilippe Mathieu-Daudé .class_init = aspeed_soc_class_init, 1501a94fae4SPhilippe Mathieu-Daudé .abstract = true, 1511a94fae4SPhilippe Mathieu-Daudé }, 1521a94fae4SPhilippe Mathieu-Daudé }; 1531a94fae4SPhilippe Mathieu-Daudé 1541a94fae4SPhilippe Mathieu-Daudé DEFINE_TYPES(aspeed_soc_types) 155