1 /* 2 * Raspberry Pi emulation (c) 2012 Gregory Estrade 3 * Upstreaming code cleanup [including bcm2835_*] (c) 2013 Jan Petrous 4 * 5 * Rasperry Pi 2 emulation and refactoring Copyright (c) 2015, Microsoft 6 * Written by Andrew Baumann 7 * 8 * This work is licensed under the terms of the GNU GPL, version 2 or later. 9 * See the COPYING file in the top-level directory. 10 */ 11 12 #include "qemu/osdep.h" 13 #include "qapi/error.h" 14 #include "qemu/module.h" 15 #include "hw/arm/bcm2835_peripherals.h" 16 #include "hw/misc/bcm2835_mbox_defs.h" 17 #include "hw/arm/raspi_platform.h" 18 #include "sysemu/sysemu.h" 19 20 /* Peripheral base address on the VC (GPU) system bus */ 21 #define BCM2835_VC_PERI_BASE 0x7e000000 22 23 /* Capabilities for SD controller: no DMA, high-speed, default clocks etc. */ 24 #define BCM2835_SDHC_CAPAREG 0x52134b4 25 26 /* 27 * According to Linux driver & DTS, dma channels 0--10 have separate IRQ, 28 * while channels 11--14 share one IRQ: 29 */ 30 #define SEPARATE_DMA_IRQ_MAX 10 31 #define ORGATED_DMA_IRQ_COUNT 4 32 33 static void create_unimp(BCM2835PeripheralState *ps, 34 UnimplementedDeviceState *uds, 35 const char *name, hwaddr ofs, hwaddr size) 36 { 37 object_initialize_child(OBJECT(ps), name, uds, TYPE_UNIMPLEMENTED_DEVICE); 38 qdev_prop_set_string(DEVICE(uds), "name", name); 39 qdev_prop_set_uint64(DEVICE(uds), "size", size); 40 sysbus_realize(SYS_BUS_DEVICE(uds), &error_fatal); 41 memory_region_add_subregion_overlap(&ps->peri_mr, ofs, 42 sysbus_mmio_get_region(SYS_BUS_DEVICE(uds), 0), -1000); 43 } 44 45 static void bcm2835_peripherals_init(Object *obj) 46 { 47 BCM2835PeripheralState *s = BCM2835_PERIPHERALS(obj); 48 49 /* Memory region for peripheral devices, which we export to our parent */ 50 memory_region_init(&s->peri_mr, obj,"bcm2835-peripherals", 0x1000000); 51 sysbus_init_mmio(SYS_BUS_DEVICE(s), &s->peri_mr); 52 53 /* Internal memory region for peripheral bus addresses (not exported) */ 54 memory_region_init(&s->gpu_bus_mr, obj, "bcm2835-gpu", (uint64_t)1 << 32); 55 56 /* Internal memory region for request/response communication with 57 * mailbox-addressable peripherals (not exported) 58 */ 59 memory_region_init(&s->mbox_mr, obj, "bcm2835-mbox", 60 MBOX_CHAN_COUNT << MBOX_AS_CHAN_SHIFT); 61 62 /* Interrupt Controller */ 63 object_initialize_child(obj, "ic", &s->ic, TYPE_BCM2835_IC); 64 65 /* SYS Timer */ 66 object_initialize_child(obj, "systimer", &s->systmr, 67 TYPE_BCM2835_SYSTIMER); 68 69 /* UART0 */ 70 object_initialize_child(obj, "uart0", &s->uart0, TYPE_PL011); 71 72 /* AUX / UART1 */ 73 object_initialize_child(obj, "aux", &s->aux, TYPE_BCM2835_AUX); 74 75 /* Mailboxes */ 76 object_initialize_child(obj, "mbox", &s->mboxes, TYPE_BCM2835_MBOX); 77 78 object_property_add_const_link(OBJECT(&s->mboxes), "mbox-mr", 79 OBJECT(&s->mbox_mr)); 80 81 /* Framebuffer */ 82 object_initialize_child(obj, "fb", &s->fb, TYPE_BCM2835_FB); 83 object_property_add_alias(obj, "vcram-size", OBJECT(&s->fb), "vcram-size"); 84 85 object_property_add_const_link(OBJECT(&s->fb), "dma-mr", 86 OBJECT(&s->gpu_bus_mr)); 87 88 /* Property channel */ 89 object_initialize_child(obj, "property", &s->property, 90 TYPE_BCM2835_PROPERTY); 91 object_property_add_alias(obj, "board-rev", OBJECT(&s->property), 92 "board-rev"); 93 object_property_add_alias(obj, "command-line", OBJECT(&s->property), 94 "command-line"); 95 96 object_property_add_const_link(OBJECT(&s->property), "fb", 97 OBJECT(&s->fb)); 98 object_property_add_const_link(OBJECT(&s->property), "dma-mr", 99 OBJECT(&s->gpu_bus_mr)); 100 101 /* Random Number Generator */ 102 object_initialize_child(obj, "rng", &s->rng, TYPE_BCM2835_RNG); 103 104 /* Extended Mass Media Controller */ 105 object_initialize_child(obj, "sdhci", &s->sdhci, TYPE_SYSBUS_SDHCI); 106 107 /* SDHOST */ 108 object_initialize_child(obj, "sdhost", &s->sdhost, TYPE_BCM2835_SDHOST); 109 110 /* DMA Channels */ 111 object_initialize_child(obj, "dma", &s->dma, TYPE_BCM2835_DMA); 112 113 object_initialize_child(obj, "orgated-dma-irq", 114 &s->orgated_dma_irq, TYPE_OR_IRQ); 115 object_property_set_int(OBJECT(&s->orgated_dma_irq), "num-lines", 116 ORGATED_DMA_IRQ_COUNT, &error_abort); 117 118 object_property_add_const_link(OBJECT(&s->dma), "dma-mr", 119 OBJECT(&s->gpu_bus_mr)); 120 121 /* Thermal */ 122 object_initialize_child(obj, "thermal", &s->thermal, TYPE_BCM2835_THERMAL); 123 124 /* GPIO */ 125 object_initialize_child(obj, "gpio", &s->gpio, TYPE_BCM2835_GPIO); 126 127 object_property_add_const_link(OBJECT(&s->gpio), "sdbus-sdhci", 128 OBJECT(&s->sdhci.sdbus)); 129 object_property_add_const_link(OBJECT(&s->gpio), "sdbus-sdhost", 130 OBJECT(&s->sdhost.sdbus)); 131 132 /* Mphi */ 133 object_initialize_child(obj, "mphi", &s->mphi, TYPE_BCM2835_MPHI); 134 135 /* DWC2 */ 136 object_initialize_child(obj, "dwc2", &s->dwc2, TYPE_DWC2_USB); 137 138 /* CPRMAN clock manager */ 139 object_initialize_child(obj, "cprman", &s->cprman, TYPE_BCM2835_CPRMAN); 140 141 object_property_add_const_link(OBJECT(&s->dwc2), "dma-mr", 142 OBJECT(&s->gpu_bus_mr)); 143 144 /* Power Management */ 145 object_initialize_child(obj, "powermgt", &s->powermgt, 146 TYPE_BCM2835_POWERMGT); 147 148 /* SPI */ 149 object_initialize_child(obj, "bcm2835-spi0", &s->spi[0], 150 TYPE_BCM2835_SPI); 151 } 152 153 static void bcm2835_peripherals_realize(DeviceState *dev, Error **errp) 154 { 155 BCM2835PeripheralState *s = BCM2835_PERIPHERALS(dev); 156 Object *obj; 157 MemoryRegion *ram; 158 Error *err = NULL; 159 uint64_t ram_size, vcram_size; 160 int n; 161 162 obj = object_property_get_link(OBJECT(dev), "ram", &error_abort); 163 164 ram = MEMORY_REGION(obj); 165 ram_size = memory_region_size(ram); 166 167 /* Map peripherals and RAM into the GPU address space. */ 168 memory_region_init_alias(&s->peri_mr_alias, OBJECT(s), 169 "bcm2835-peripherals", &s->peri_mr, 0, 170 memory_region_size(&s->peri_mr)); 171 172 memory_region_add_subregion_overlap(&s->gpu_bus_mr, BCM2835_VC_PERI_BASE, 173 &s->peri_mr_alias, 1); 174 175 /* RAM is aliased four times (different cache configurations) on the GPU */ 176 for (n = 0; n < 4; n++) { 177 memory_region_init_alias(&s->ram_alias[n], OBJECT(s), 178 "bcm2835-gpu-ram-alias[*]", ram, 0, ram_size); 179 memory_region_add_subregion_overlap(&s->gpu_bus_mr, (hwaddr)n << 30, 180 &s->ram_alias[n], 0); 181 } 182 183 /* Interrupt Controller */ 184 if (!sysbus_realize(SYS_BUS_DEVICE(&s->ic), errp)) { 185 return; 186 } 187 188 /* CPRMAN clock manager */ 189 if (!sysbus_realize(SYS_BUS_DEVICE(&s->cprman), errp)) { 190 return; 191 } 192 memory_region_add_subregion(&s->peri_mr, CPRMAN_OFFSET, 193 sysbus_mmio_get_region(SYS_BUS_DEVICE(&s->cprman), 0)); 194 qdev_connect_clock_in(DEVICE(&s->uart0), "clk", 195 qdev_get_clock_out(DEVICE(&s->cprman), "uart-out")); 196 197 memory_region_add_subregion(&s->peri_mr, ARMCTRL_IC_OFFSET, 198 sysbus_mmio_get_region(SYS_BUS_DEVICE(&s->ic), 0)); 199 sysbus_pass_irq(SYS_BUS_DEVICE(s), SYS_BUS_DEVICE(&s->ic)); 200 201 /* Sys Timer */ 202 if (!sysbus_realize(SYS_BUS_DEVICE(&s->systmr), errp)) { 203 return; 204 } 205 memory_region_add_subregion(&s->peri_mr, ST_OFFSET, 206 sysbus_mmio_get_region(SYS_BUS_DEVICE(&s->systmr), 0)); 207 sysbus_connect_irq(SYS_BUS_DEVICE(&s->systmr), 0, 208 qdev_get_gpio_in_named(DEVICE(&s->ic), BCM2835_IC_GPU_IRQ, 209 INTERRUPT_TIMER0)); 210 sysbus_connect_irq(SYS_BUS_DEVICE(&s->systmr), 1, 211 qdev_get_gpio_in_named(DEVICE(&s->ic), BCM2835_IC_GPU_IRQ, 212 INTERRUPT_TIMER1)); 213 sysbus_connect_irq(SYS_BUS_DEVICE(&s->systmr), 2, 214 qdev_get_gpio_in_named(DEVICE(&s->ic), BCM2835_IC_GPU_IRQ, 215 INTERRUPT_TIMER2)); 216 sysbus_connect_irq(SYS_BUS_DEVICE(&s->systmr), 3, 217 qdev_get_gpio_in_named(DEVICE(&s->ic), BCM2835_IC_GPU_IRQ, 218 INTERRUPT_TIMER3)); 219 220 /* UART0 */ 221 qdev_prop_set_chr(DEVICE(&s->uart0), "chardev", serial_hd(0)); 222 if (!sysbus_realize(SYS_BUS_DEVICE(&s->uart0), errp)) { 223 return; 224 } 225 226 memory_region_add_subregion(&s->peri_mr, UART0_OFFSET, 227 sysbus_mmio_get_region(SYS_BUS_DEVICE(&s->uart0), 0)); 228 sysbus_connect_irq(SYS_BUS_DEVICE(&s->uart0), 0, 229 qdev_get_gpio_in_named(DEVICE(&s->ic), BCM2835_IC_GPU_IRQ, 230 INTERRUPT_UART0)); 231 232 /* AUX / UART1 */ 233 qdev_prop_set_chr(DEVICE(&s->aux), "chardev", serial_hd(1)); 234 235 if (!sysbus_realize(SYS_BUS_DEVICE(&s->aux), errp)) { 236 return; 237 } 238 239 memory_region_add_subregion(&s->peri_mr, AUX_OFFSET, 240 sysbus_mmio_get_region(SYS_BUS_DEVICE(&s->aux), 0)); 241 sysbus_connect_irq(SYS_BUS_DEVICE(&s->aux), 0, 242 qdev_get_gpio_in_named(DEVICE(&s->ic), BCM2835_IC_GPU_IRQ, 243 INTERRUPT_AUX)); 244 245 /* Mailboxes */ 246 if (!sysbus_realize(SYS_BUS_DEVICE(&s->mboxes), errp)) { 247 return; 248 } 249 250 memory_region_add_subregion(&s->peri_mr, ARMCTRL_0_SBM_OFFSET, 251 sysbus_mmio_get_region(SYS_BUS_DEVICE(&s->mboxes), 0)); 252 sysbus_connect_irq(SYS_BUS_DEVICE(&s->mboxes), 0, 253 qdev_get_gpio_in_named(DEVICE(&s->ic), BCM2835_IC_ARM_IRQ, 254 INTERRUPT_ARM_MAILBOX)); 255 256 /* Framebuffer */ 257 vcram_size = object_property_get_uint(OBJECT(s), "vcram-size", &err); 258 if (err) { 259 error_propagate(errp, err); 260 return; 261 } 262 263 if (!object_property_set_uint(OBJECT(&s->fb), "vcram-base", 264 ram_size - vcram_size, errp)) { 265 return; 266 } 267 268 if (!sysbus_realize(SYS_BUS_DEVICE(&s->fb), errp)) { 269 return; 270 } 271 272 memory_region_add_subregion(&s->mbox_mr, MBOX_CHAN_FB << MBOX_AS_CHAN_SHIFT, 273 sysbus_mmio_get_region(SYS_BUS_DEVICE(&s->fb), 0)); 274 sysbus_connect_irq(SYS_BUS_DEVICE(&s->fb), 0, 275 qdev_get_gpio_in(DEVICE(&s->mboxes), MBOX_CHAN_FB)); 276 277 /* Property channel */ 278 if (!sysbus_realize(SYS_BUS_DEVICE(&s->property), errp)) { 279 return; 280 } 281 282 memory_region_add_subregion(&s->mbox_mr, 283 MBOX_CHAN_PROPERTY << MBOX_AS_CHAN_SHIFT, 284 sysbus_mmio_get_region(SYS_BUS_DEVICE(&s->property), 0)); 285 sysbus_connect_irq(SYS_BUS_DEVICE(&s->property), 0, 286 qdev_get_gpio_in(DEVICE(&s->mboxes), MBOX_CHAN_PROPERTY)); 287 288 /* Random Number Generator */ 289 if (!sysbus_realize(SYS_BUS_DEVICE(&s->rng), errp)) { 290 return; 291 } 292 293 memory_region_add_subregion(&s->peri_mr, RNG_OFFSET, 294 sysbus_mmio_get_region(SYS_BUS_DEVICE(&s->rng), 0)); 295 296 /* Extended Mass Media Controller 297 * 298 * Compatible with: 299 * - SD Host Controller Specification Version 3.0 Draft 1.0 300 * - SDIO Specification Version 3.0 301 * - MMC Specification Version 4.4 302 * 303 * For the exact details please refer to the Arasan documentation: 304 * SD3.0_Host_AHB_eMMC4.4_Usersguide_ver5.9_jan11_10.pdf 305 */ 306 object_property_set_uint(OBJECT(&s->sdhci), "sd-spec-version", 3, 307 &error_abort); 308 object_property_set_uint(OBJECT(&s->sdhci), "capareg", 309 BCM2835_SDHC_CAPAREG, &error_abort); 310 object_property_set_bool(OBJECT(&s->sdhci), "pending-insert-quirk", true, 311 &error_abort); 312 if (!sysbus_realize(SYS_BUS_DEVICE(&s->sdhci), errp)) { 313 return; 314 } 315 316 memory_region_add_subregion(&s->peri_mr, EMMC1_OFFSET, 317 sysbus_mmio_get_region(SYS_BUS_DEVICE(&s->sdhci), 0)); 318 sysbus_connect_irq(SYS_BUS_DEVICE(&s->sdhci), 0, 319 qdev_get_gpio_in_named(DEVICE(&s->ic), BCM2835_IC_GPU_IRQ, 320 INTERRUPT_ARASANSDIO)); 321 322 /* SDHOST */ 323 if (!sysbus_realize(SYS_BUS_DEVICE(&s->sdhost), errp)) { 324 return; 325 } 326 327 memory_region_add_subregion(&s->peri_mr, MMCI0_OFFSET, 328 sysbus_mmio_get_region(SYS_BUS_DEVICE(&s->sdhost), 0)); 329 sysbus_connect_irq(SYS_BUS_DEVICE(&s->sdhost), 0, 330 qdev_get_gpio_in_named(DEVICE(&s->ic), BCM2835_IC_GPU_IRQ, 331 INTERRUPT_SDIO)); 332 333 /* DMA Channels */ 334 if (!sysbus_realize(SYS_BUS_DEVICE(&s->dma), errp)) { 335 return; 336 } 337 338 memory_region_add_subregion(&s->peri_mr, DMA_OFFSET, 339 sysbus_mmio_get_region(SYS_BUS_DEVICE(&s->dma), 0)); 340 memory_region_add_subregion(&s->peri_mr, DMA15_OFFSET, 341 sysbus_mmio_get_region(SYS_BUS_DEVICE(&s->dma), 1)); 342 343 for (n = 0; n <= SEPARATE_DMA_IRQ_MAX; n++) { 344 sysbus_connect_irq(SYS_BUS_DEVICE(&s->dma), n, 345 qdev_get_gpio_in_named(DEVICE(&s->ic), 346 BCM2835_IC_GPU_IRQ, 347 INTERRUPT_DMA0 + n)); 348 } 349 if (!qdev_realize(DEVICE(&s->orgated_dma_irq), NULL, errp)) { 350 return; 351 } 352 for (n = 0; n < ORGATED_DMA_IRQ_COUNT; n++) { 353 sysbus_connect_irq(SYS_BUS_DEVICE(&s->dma), 354 SEPARATE_DMA_IRQ_MAX + 1 + n, 355 qdev_get_gpio_in(DEVICE(&s->orgated_dma_irq), n)); 356 } 357 qdev_connect_gpio_out(DEVICE(&s->orgated_dma_irq), 0, 358 qdev_get_gpio_in_named(DEVICE(&s->ic), 359 BCM2835_IC_GPU_IRQ, 360 INTERRUPT_DMA0 + SEPARATE_DMA_IRQ_MAX + 1)); 361 362 /* THERMAL */ 363 if (!sysbus_realize(SYS_BUS_DEVICE(&s->thermal), errp)) { 364 return; 365 } 366 memory_region_add_subregion(&s->peri_mr, THERMAL_OFFSET, 367 sysbus_mmio_get_region(SYS_BUS_DEVICE(&s->thermal), 0)); 368 369 /* GPIO */ 370 if (!sysbus_realize(SYS_BUS_DEVICE(&s->gpio), errp)) { 371 return; 372 } 373 374 memory_region_add_subregion(&s->peri_mr, GPIO_OFFSET, 375 sysbus_mmio_get_region(SYS_BUS_DEVICE(&s->gpio), 0)); 376 377 object_property_add_alias(OBJECT(s), "sd-bus", OBJECT(&s->gpio), "sd-bus"); 378 379 /* Mphi */ 380 if (!sysbus_realize(SYS_BUS_DEVICE(&s->mphi), errp)) { 381 return; 382 } 383 384 memory_region_add_subregion(&s->peri_mr, MPHI_OFFSET, 385 sysbus_mmio_get_region(SYS_BUS_DEVICE(&s->mphi), 0)); 386 sysbus_connect_irq(SYS_BUS_DEVICE(&s->mphi), 0, 387 qdev_get_gpio_in_named(DEVICE(&s->ic), BCM2835_IC_GPU_IRQ, 388 INTERRUPT_HOSTPORT)); 389 390 /* DWC2 */ 391 if (!sysbus_realize(SYS_BUS_DEVICE(&s->dwc2), errp)) { 392 return; 393 } 394 395 memory_region_add_subregion(&s->peri_mr, USB_OTG_OFFSET, 396 sysbus_mmio_get_region(SYS_BUS_DEVICE(&s->dwc2), 0)); 397 sysbus_connect_irq(SYS_BUS_DEVICE(&s->dwc2), 0, 398 qdev_get_gpio_in_named(DEVICE(&s->ic), BCM2835_IC_GPU_IRQ, 399 INTERRUPT_USB)); 400 401 /* Power Management */ 402 if (!sysbus_realize(SYS_BUS_DEVICE(&s->powermgt), errp)) { 403 return; 404 } 405 406 memory_region_add_subregion(&s->peri_mr, PM_OFFSET, 407 sysbus_mmio_get_region(SYS_BUS_DEVICE(&s->powermgt), 0)); 408 409 /* SPI */ 410 if (!sysbus_realize(SYS_BUS_DEVICE(&s->spi[0]), errp)) { 411 return; 412 } 413 414 memory_region_add_subregion(&s->peri_mr, SPI0_OFFSET, 415 sysbus_mmio_get_region(SYS_BUS_DEVICE(&s->spi[0]), 0)); 416 sysbus_connect_irq(SYS_BUS_DEVICE(&s->spi[0]), 0, 417 qdev_get_gpio_in_named(DEVICE(&s->ic), 418 BCM2835_IC_GPU_IRQ, 419 INTERRUPT_SPI)); 420 421 create_unimp(s, &s->txp, "bcm2835-txp", TXP_OFFSET, 0x1000); 422 create_unimp(s, &s->armtmr, "bcm2835-sp804", ARMCTRL_TIMER0_1_OFFSET, 0x40); 423 create_unimp(s, &s->i2s, "bcm2835-i2s", I2S_OFFSET, 0x100); 424 create_unimp(s, &s->smi, "bcm2835-smi", SMI_OFFSET, 0x100); 425 create_unimp(s, &s->bscsl, "bcm2835-spis", BSC_SL_OFFSET, 0x100); 426 create_unimp(s, &s->i2c[0], "bcm2835-i2c0", BSC0_OFFSET, 0x20); 427 create_unimp(s, &s->i2c[1], "bcm2835-i2c1", BSC1_OFFSET, 0x20); 428 create_unimp(s, &s->i2c[2], "bcm2835-i2c2", BSC2_OFFSET, 0x20); 429 create_unimp(s, &s->otp, "bcm2835-otp", OTP_OFFSET, 0x80); 430 create_unimp(s, &s->dbus, "bcm2835-dbus", DBUS_OFFSET, 0x8000); 431 create_unimp(s, &s->ave0, "bcm2835-ave0", AVE0_OFFSET, 0x8000); 432 create_unimp(s, &s->v3d, "bcm2835-v3d", V3D_OFFSET, 0x1000); 433 create_unimp(s, &s->sdramc, "bcm2835-sdramc", SDRAMC_OFFSET, 0x100); 434 } 435 436 static void bcm2835_peripherals_class_init(ObjectClass *oc, void *data) 437 { 438 DeviceClass *dc = DEVICE_CLASS(oc); 439 440 dc->realize = bcm2835_peripherals_realize; 441 } 442 443 static const TypeInfo bcm2835_peripherals_type_info = { 444 .name = TYPE_BCM2835_PERIPHERALS, 445 .parent = TYPE_SYS_BUS_DEVICE, 446 .instance_size = sizeof(BCM2835PeripheralState), 447 .instance_init = bcm2835_peripherals_init, 448 .class_init = bcm2835_peripherals_class_init, 449 }; 450 451 static void bcm2835_peripherals_register_types(void) 452 { 453 type_register_static(&bcm2835_peripherals_type_info); 454 } 455 456 type_init(bcm2835_peripherals_register_types) 457