1 /* 2 * Raspberry Pi emulation (c) 2012 Gregory Estrade 3 * Upstreaming code cleanup [including bcm2835_*] (c) 2013 Jan Petrous 4 * 5 * Rasperry Pi 2 emulation and refactoring Copyright (c) 2015, Microsoft 6 * Written by Andrew Baumann 7 * 8 * This work is licensed under the terms of the GNU GPL, version 2 or later. 9 * See the COPYING file in the top-level directory. 10 */ 11 12 #include "qemu/osdep.h" 13 #include "qapi/error.h" 14 #include "qemu/module.h" 15 #include "hw/arm/bcm2836.h" 16 #include "hw/arm/raspi_platform.h" 17 #include "hw/sysbus.h" 18 #include "target/arm/cpu-qom.h" 19 20 struct BCM283XClass { 21 /*< private >*/ 22 DeviceClass parent_class; 23 /*< public >*/ 24 const char *name; 25 const char *cpu_type; 26 unsigned core_count; 27 hwaddr peri_base; /* Peripheral base address seen by the CPU */ 28 hwaddr ctrl_base; /* Interrupt controller and mailboxes etc. */ 29 int clusterid; 30 }; 31 32 static Property bcm2836_enabled_cores_property = 33 DEFINE_PROP_UINT32("enabled-cpus", BCM283XState, enabled_cpus, 0); 34 35 static void bcm2836_init(Object *obj) 36 { 37 BCM283XState *s = BCM283X(obj); 38 BCM283XClass *bc = BCM283X_GET_CLASS(obj); 39 int n; 40 41 for (n = 0; n < bc->core_count; n++) { 42 object_initialize_child(obj, "cpu[*]", &s->cpu[n].core, 43 bc->cpu_type); 44 } 45 if (bc->core_count > 1) { 46 qdev_property_add_static(DEVICE(obj), &bcm2836_enabled_cores_property); 47 qdev_prop_set_uint32(DEVICE(obj), "enabled-cpus", bc->core_count); 48 } 49 50 if (bc->ctrl_base) { 51 object_initialize_child(obj, "control", &s->control, 52 TYPE_BCM2836_CONTROL); 53 } 54 55 object_initialize_child(obj, "peripherals", &s->peripherals, 56 TYPE_BCM2835_PERIPHERALS); 57 object_property_add_alias(obj, "board-rev", OBJECT(&s->peripherals), 58 "board-rev"); 59 object_property_add_alias(obj, "command-line", OBJECT(&s->peripherals), 60 "command-line"); 61 object_property_add_alias(obj, "vcram-size", OBJECT(&s->peripherals), 62 "vcram-size"); 63 } 64 65 static bool bcm283x_common_realize(DeviceState *dev, Error **errp) 66 { 67 BCM283XState *s = BCM283X(dev); 68 BCM283XClass *bc = BCM283X_GET_CLASS(dev); 69 Object *obj; 70 71 /* common peripherals from bcm2835 */ 72 73 obj = object_property_get_link(OBJECT(dev), "ram", &error_abort); 74 75 object_property_add_const_link(OBJECT(&s->peripherals), "ram", obj); 76 77 if (!sysbus_realize(SYS_BUS_DEVICE(&s->peripherals), errp)) { 78 return false; 79 } 80 81 object_property_add_alias(OBJECT(s), "sd-bus", OBJECT(&s->peripherals), 82 "sd-bus"); 83 84 sysbus_mmio_map_overlap(SYS_BUS_DEVICE(&s->peripherals), 0, 85 bc->peri_base, 1); 86 return true; 87 } 88 89 static void bcm2835_realize(DeviceState *dev, Error **errp) 90 { 91 BCM283XState *s = BCM283X(dev); 92 93 if (!bcm283x_common_realize(dev, errp)) { 94 return; 95 } 96 97 if (!qdev_realize(DEVICE(&s->cpu[0].core), NULL, errp)) { 98 return; 99 } 100 101 /* Connect irq/fiq outputs from the interrupt controller. */ 102 sysbus_connect_irq(SYS_BUS_DEVICE(&s->peripherals), 0, 103 qdev_get_gpio_in(DEVICE(&s->cpu[0].core), ARM_CPU_IRQ)); 104 sysbus_connect_irq(SYS_BUS_DEVICE(&s->peripherals), 1, 105 qdev_get_gpio_in(DEVICE(&s->cpu[0].core), ARM_CPU_FIQ)); 106 } 107 108 static void bcm2836_realize(DeviceState *dev, Error **errp) 109 { 110 BCM283XState *s = BCM283X(dev); 111 BCM283XClass *bc = BCM283X_GET_CLASS(dev); 112 int n; 113 114 if (!bcm283x_common_realize(dev, errp)) { 115 return; 116 } 117 118 /* bcm2836 interrupt controller (and mailboxes, etc.) */ 119 if (!sysbus_realize(SYS_BUS_DEVICE(&s->control), errp)) { 120 return; 121 } 122 123 sysbus_mmio_map(SYS_BUS_DEVICE(&s->control), 0, bc->ctrl_base); 124 125 sysbus_connect_irq(SYS_BUS_DEVICE(&s->peripherals), 0, 126 qdev_get_gpio_in_named(DEVICE(&s->control), "gpu-irq", 0)); 127 sysbus_connect_irq(SYS_BUS_DEVICE(&s->peripherals), 1, 128 qdev_get_gpio_in_named(DEVICE(&s->control), "gpu-fiq", 0)); 129 130 for (n = 0; n < BCM283X_NCPUS; n++) { 131 object_property_set_int(OBJECT(&s->cpu[n].core), "mp-affinity", 132 (bc->clusterid << 8) | n, &error_abort); 133 134 /* set periphbase/CBAR value for CPU-local registers */ 135 object_property_set_int(OBJECT(&s->cpu[n].core), "reset-cbar", 136 bc->peri_base, &error_abort); 137 138 /* start powered off if not enabled */ 139 object_property_set_bool(OBJECT(&s->cpu[n].core), "start-powered-off", 140 n >= s->enabled_cpus, &error_abort); 141 142 if (!qdev_realize(DEVICE(&s->cpu[n].core), NULL, errp)) { 143 return; 144 } 145 146 /* Connect irq/fiq outputs from the interrupt controller. */ 147 qdev_connect_gpio_out_named(DEVICE(&s->control), "irq", n, 148 qdev_get_gpio_in(DEVICE(&s->cpu[n].core), ARM_CPU_IRQ)); 149 qdev_connect_gpio_out_named(DEVICE(&s->control), "fiq", n, 150 qdev_get_gpio_in(DEVICE(&s->cpu[n].core), ARM_CPU_FIQ)); 151 152 /* Connect timers from the CPU to the interrupt controller */ 153 qdev_connect_gpio_out(DEVICE(&s->cpu[n].core), GTIMER_PHYS, 154 qdev_get_gpio_in_named(DEVICE(&s->control), "cntpnsirq", n)); 155 qdev_connect_gpio_out(DEVICE(&s->cpu[n].core), GTIMER_VIRT, 156 qdev_get_gpio_in_named(DEVICE(&s->control), "cntvirq", n)); 157 qdev_connect_gpio_out(DEVICE(&s->cpu[n].core), GTIMER_HYP, 158 qdev_get_gpio_in_named(DEVICE(&s->control), "cnthpirq", n)); 159 qdev_connect_gpio_out(DEVICE(&s->cpu[n].core), GTIMER_SEC, 160 qdev_get_gpio_in_named(DEVICE(&s->control), "cntpsirq", n)); 161 } 162 } 163 164 static void bcm283x_class_init(ObjectClass *oc, void *data) 165 { 166 DeviceClass *dc = DEVICE_CLASS(oc); 167 168 /* Reason: Must be wired up in code (see raspi_init() function) */ 169 dc->user_creatable = false; 170 } 171 172 static void bcm2835_class_init(ObjectClass *oc, void *data) 173 { 174 DeviceClass *dc = DEVICE_CLASS(oc); 175 BCM283XClass *bc = BCM283X_CLASS(oc); 176 177 bc->cpu_type = ARM_CPU_TYPE_NAME("arm1176"); 178 bc->core_count = 1; 179 bc->peri_base = 0x20000000; 180 dc->realize = bcm2835_realize; 181 }; 182 183 static void bcm2836_class_init(ObjectClass *oc, void *data) 184 { 185 DeviceClass *dc = DEVICE_CLASS(oc); 186 BCM283XClass *bc = BCM283X_CLASS(oc); 187 188 bc->cpu_type = ARM_CPU_TYPE_NAME("cortex-a7"); 189 bc->core_count = BCM283X_NCPUS; 190 bc->peri_base = 0x3f000000; 191 bc->ctrl_base = 0x40000000; 192 bc->clusterid = 0xf; 193 dc->realize = bcm2836_realize; 194 }; 195 196 #ifdef TARGET_AARCH64 197 static void bcm2837_class_init(ObjectClass *oc, void *data) 198 { 199 DeviceClass *dc = DEVICE_CLASS(oc); 200 BCM283XClass *bc = BCM283X_CLASS(oc); 201 202 bc->cpu_type = ARM_CPU_TYPE_NAME("cortex-a53"); 203 bc->core_count = BCM283X_NCPUS; 204 bc->peri_base = 0x3f000000; 205 bc->ctrl_base = 0x40000000; 206 bc->clusterid = 0x0; 207 dc->realize = bcm2836_realize; 208 }; 209 #endif 210 211 static const TypeInfo bcm283x_types[] = { 212 { 213 .name = TYPE_BCM2835, 214 .parent = TYPE_BCM283X, 215 .class_init = bcm2835_class_init, 216 }, { 217 .name = TYPE_BCM2836, 218 .parent = TYPE_BCM283X, 219 .class_init = bcm2836_class_init, 220 #ifdef TARGET_AARCH64 221 }, { 222 .name = TYPE_BCM2837, 223 .parent = TYPE_BCM283X, 224 .class_init = bcm2837_class_init, 225 #endif 226 }, { 227 .name = TYPE_BCM283X, 228 .parent = TYPE_DEVICE, 229 .instance_size = sizeof(BCM283XState), 230 .instance_init = bcm2836_init, 231 .class_size = sizeof(BCM283XClass), 232 .class_init = bcm283x_class_init, 233 .abstract = true, 234 } 235 }; 236 237 DEFINE_TYPES(bcm283x_types) 238