1 /* 2 * Raspberry Pi emulation (c) 2012 Gregory Estrade 3 * Upstreaming code cleanup [including bcm2835_*] (c) 2013 Jan Petrous 4 * 5 * Rasperry Pi 2 emulation and refactoring Copyright (c) 2015, Microsoft 6 * Written by Andrew Baumann 7 * 8 * This work is licensed under the terms of the GNU GPL, version 2 or later. 9 * See the COPYING file in the top-level directory. 10 */ 11 12 #include "qemu/osdep.h" 13 #include "qapi/error.h" 14 #include "qemu/module.h" 15 #include "cpu.h" 16 #include "hw/arm/bcm2836.h" 17 #include "hw/arm/raspi_platform.h" 18 #include "hw/sysbus.h" 19 20 typedef struct BCM283XClass { 21 /*< private >*/ 22 DeviceClass parent_class; 23 /*< public >*/ 24 const char *name; 25 const char *cpu_type; 26 unsigned core_count; 27 hwaddr peri_base; /* Peripheral base address seen by the CPU */ 28 hwaddr ctrl_base; /* Interrupt controller and mailboxes etc. */ 29 int clusterid; 30 } BCM283XClass; 31 32 #define BCM283X_CLASS(klass) \ 33 OBJECT_CLASS_CHECK(BCM283XClass, (klass), TYPE_BCM283X) 34 #define BCM283X_GET_CLASS(obj) \ 35 OBJECT_GET_CLASS(BCM283XClass, (obj), TYPE_BCM283X) 36 37 static Property bcm2836_enabled_cores_property = 38 DEFINE_PROP_UINT32("enabled-cpus", BCM283XState, enabled_cpus, 0); 39 40 static void bcm2836_init(Object *obj) 41 { 42 BCM283XState *s = BCM283X(obj); 43 BCM283XClass *bc = BCM283X_GET_CLASS(obj); 44 int n; 45 46 for (n = 0; n < bc->core_count; n++) { 47 object_initialize_child(obj, "cpu[*]", &s->cpu[n].core, 48 bc->cpu_type); 49 } 50 if (bc->core_count > 1) { 51 qdev_property_add_static(DEVICE(obj), &bcm2836_enabled_cores_property); 52 qdev_prop_set_uint32(DEVICE(obj), "enabled-cpus", bc->core_count); 53 } 54 55 if (bc->ctrl_base) { 56 object_initialize_child(obj, "control", &s->control, 57 TYPE_BCM2836_CONTROL); 58 } 59 60 object_initialize_child(obj, "peripherals", &s->peripherals, 61 TYPE_BCM2835_PERIPHERALS); 62 object_property_add_alias(obj, "board-rev", OBJECT(&s->peripherals), 63 "board-rev"); 64 object_property_add_alias(obj, "vcram-size", OBJECT(&s->peripherals), 65 "vcram-size"); 66 } 67 68 static bool bcm283x_common_realize(DeviceState *dev, Error **errp) 69 { 70 BCM283XState *s = BCM283X(dev); 71 BCM283XClass *bc = BCM283X_GET_CLASS(dev); 72 Object *obj; 73 74 /* common peripherals from bcm2835 */ 75 76 obj = object_property_get_link(OBJECT(dev), "ram", &error_abort); 77 78 object_property_add_const_link(OBJECT(&s->peripherals), "ram", obj); 79 80 if (!sysbus_realize(SYS_BUS_DEVICE(&s->peripherals), errp)) { 81 return false; 82 } 83 84 object_property_add_alias(OBJECT(s), "sd-bus", OBJECT(&s->peripherals), 85 "sd-bus"); 86 87 sysbus_mmio_map_overlap(SYS_BUS_DEVICE(&s->peripherals), 0, 88 bc->peri_base, 1); 89 return true; 90 } 91 92 static void bcm2836_realize(DeviceState *dev, Error **errp) 93 { 94 BCM283XState *s = BCM283X(dev); 95 BCM283XClass *bc = BCM283X_GET_CLASS(dev); 96 int n; 97 98 if (!bcm283x_common_realize(dev, errp)) { 99 return; 100 } 101 102 /* bcm2836 interrupt controller (and mailboxes, etc.) */ 103 if (!sysbus_realize(SYS_BUS_DEVICE(&s->control), errp)) { 104 return; 105 } 106 107 sysbus_mmio_map(SYS_BUS_DEVICE(&s->control), 0, bc->ctrl_base); 108 109 sysbus_connect_irq(SYS_BUS_DEVICE(&s->peripherals), 0, 110 qdev_get_gpio_in_named(DEVICE(&s->control), "gpu-irq", 0)); 111 sysbus_connect_irq(SYS_BUS_DEVICE(&s->peripherals), 1, 112 qdev_get_gpio_in_named(DEVICE(&s->control), "gpu-fiq", 0)); 113 114 for (n = 0; n < BCM283X_NCPUS; n++) { 115 /* TODO: this should be converted to a property of ARM_CPU */ 116 s->cpu[n].core.mp_affinity = (bc->clusterid << 8) | n; 117 118 /* set periphbase/CBAR value for CPU-local registers */ 119 if (!object_property_set_int(OBJECT(&s->cpu[n].core), "reset-cbar", 120 bc->peri_base, errp)) { 121 return; 122 } 123 124 /* start powered off if not enabled */ 125 if (!object_property_set_bool(OBJECT(&s->cpu[n].core), 126 "start-powered-off", 127 n >= s->enabled_cpus, 128 errp)) { 129 return; 130 } 131 132 if (!qdev_realize(DEVICE(&s->cpu[n].core), NULL, errp)) { 133 return; 134 } 135 136 /* Connect irq/fiq outputs from the interrupt controller. */ 137 qdev_connect_gpio_out_named(DEVICE(&s->control), "irq", n, 138 qdev_get_gpio_in(DEVICE(&s->cpu[n].core), ARM_CPU_IRQ)); 139 qdev_connect_gpio_out_named(DEVICE(&s->control), "fiq", n, 140 qdev_get_gpio_in(DEVICE(&s->cpu[n].core), ARM_CPU_FIQ)); 141 142 /* Connect timers from the CPU to the interrupt controller */ 143 qdev_connect_gpio_out(DEVICE(&s->cpu[n].core), GTIMER_PHYS, 144 qdev_get_gpio_in_named(DEVICE(&s->control), "cntpnsirq", n)); 145 qdev_connect_gpio_out(DEVICE(&s->cpu[n].core), GTIMER_VIRT, 146 qdev_get_gpio_in_named(DEVICE(&s->control), "cntvirq", n)); 147 qdev_connect_gpio_out(DEVICE(&s->cpu[n].core), GTIMER_HYP, 148 qdev_get_gpio_in_named(DEVICE(&s->control), "cnthpirq", n)); 149 qdev_connect_gpio_out(DEVICE(&s->cpu[n].core), GTIMER_SEC, 150 qdev_get_gpio_in_named(DEVICE(&s->control), "cntpsirq", n)); 151 } 152 } 153 154 static void bcm283x_class_init(ObjectClass *oc, void *data) 155 { 156 DeviceClass *dc = DEVICE_CLASS(oc); 157 158 /* Reason: Must be wired up in code (see raspi_init() function) */ 159 dc->user_creatable = false; 160 } 161 162 static void bcm2836_class_init(ObjectClass *oc, void *data) 163 { 164 DeviceClass *dc = DEVICE_CLASS(oc); 165 BCM283XClass *bc = BCM283X_CLASS(oc); 166 167 bc->cpu_type = ARM_CPU_TYPE_NAME("cortex-a7"); 168 bc->core_count = BCM283X_NCPUS; 169 bc->peri_base = 0x3f000000; 170 bc->ctrl_base = 0x40000000; 171 bc->clusterid = 0xf; 172 dc->realize = bcm2836_realize; 173 }; 174 175 #ifdef TARGET_AARCH64 176 static void bcm2837_class_init(ObjectClass *oc, void *data) 177 { 178 DeviceClass *dc = DEVICE_CLASS(oc); 179 BCM283XClass *bc = BCM283X_CLASS(oc); 180 181 bc->cpu_type = ARM_CPU_TYPE_NAME("cortex-a53"); 182 bc->core_count = BCM283X_NCPUS; 183 bc->peri_base = 0x3f000000; 184 bc->ctrl_base = 0x40000000; 185 bc->clusterid = 0x0; 186 dc->realize = bcm2836_realize; 187 }; 188 #endif 189 190 static const TypeInfo bcm283x_types[] = { 191 { 192 .name = TYPE_BCM2836, 193 .parent = TYPE_BCM283X, 194 .class_init = bcm2836_class_init, 195 #ifdef TARGET_AARCH64 196 }, { 197 .name = TYPE_BCM2837, 198 .parent = TYPE_BCM283X, 199 .class_init = bcm2837_class_init, 200 #endif 201 }, { 202 .name = TYPE_BCM283X, 203 .parent = TYPE_DEVICE, 204 .instance_size = sizeof(BCM283XState), 205 .instance_init = bcm2836_init, 206 .class_size = sizeof(BCM283XClass), 207 .class_init = bcm283x_class_init, 208 .abstract = true, 209 } 210 }; 211 212 DEFINE_TYPES(bcm283x_types) 213