1 /* 2 * Copyright (c) 2018, Impinj, Inc. 3 * 4 * i.MX7 SoC definitions 5 * 6 * Author: Andrey Smirnov <andrew.smirnov@gmail.com> 7 * 8 * Based on hw/arm/fsl-imx6.c 9 * 10 * This program is free software; you can redistribute it and/or modify 11 * it under the terms of the GNU General Public License as published by 12 * the Free Software Foundation; either version 2 of the License, or 13 * (at your option) any later version. 14 * 15 * This program is distributed in the hope that it will be useful, 16 * but WITHOUT ANY WARRANTY; without even the implied warranty of 17 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the 18 * GNU General Public License for more details. 19 */ 20 21 #include "qemu/osdep.h" 22 #include "qapi/error.h" 23 #include "hw/arm/fsl-imx7.h" 24 #include "hw/misc/unimp.h" 25 #include "hw/boards.h" 26 #include "sysemu/sysemu.h" 27 #include "qemu/error-report.h" 28 #include "qemu/module.h" 29 30 #define NAME_SIZE 20 31 32 static void fsl_imx7_init(Object *obj) 33 { 34 MachineState *ms = MACHINE(qdev_get_machine()); 35 FslIMX7State *s = FSL_IMX7(obj); 36 char name[NAME_SIZE]; 37 int i; 38 39 for (i = 0; i < MIN(ms->smp.cpus, FSL_IMX7_NUM_CPUS); i++) { 40 snprintf(name, NAME_SIZE, "cpu%d", i); 41 object_initialize_child(obj, name, &s->cpu[i], 42 ARM_CPU_TYPE_NAME("cortex-a7")); 43 } 44 45 /* 46 * A7MPCORE 47 */ 48 sysbus_init_child_obj(obj, "a7mpcore", &s->a7mpcore, sizeof(s->a7mpcore), 49 TYPE_A15MPCORE_PRIV); 50 51 /* 52 * GPIOs 1 to 7 53 */ 54 for (i = 0; i < FSL_IMX7_NUM_GPIOS; i++) { 55 snprintf(name, NAME_SIZE, "gpio%d", i); 56 sysbus_init_child_obj(obj, name, &s->gpio[i], sizeof(s->gpio[i]), 57 TYPE_IMX_GPIO); 58 } 59 60 /* 61 * GPT1, 2, 3, 4 62 */ 63 for (i = 0; i < FSL_IMX7_NUM_GPTS; i++) { 64 snprintf(name, NAME_SIZE, "gpt%d", i); 65 sysbus_init_child_obj(obj, name, &s->gpt[i], sizeof(s->gpt[i]), 66 TYPE_IMX7_GPT); 67 } 68 69 /* 70 * CCM 71 */ 72 sysbus_init_child_obj(obj, "ccm", &s->ccm, sizeof(s->ccm), TYPE_IMX7_CCM); 73 74 /* 75 * Analog 76 */ 77 sysbus_init_child_obj(obj, "analog", &s->analog, sizeof(s->analog), 78 TYPE_IMX7_ANALOG); 79 80 /* 81 * GPCv2 82 */ 83 sysbus_init_child_obj(obj, "gpcv2", &s->gpcv2, sizeof(s->gpcv2), 84 TYPE_IMX_GPCV2); 85 86 for (i = 0; i < FSL_IMX7_NUM_ECSPIS; i++) { 87 snprintf(name, NAME_SIZE, "spi%d", i + 1); 88 sysbus_init_child_obj(obj, name, &s->spi[i], sizeof(s->spi[i]), 89 TYPE_IMX_SPI); 90 } 91 92 93 for (i = 0; i < FSL_IMX7_NUM_I2CS; i++) { 94 snprintf(name, NAME_SIZE, "i2c%d", i + 1); 95 sysbus_init_child_obj(obj, name, &s->i2c[i], sizeof(s->i2c[i]), 96 TYPE_IMX_I2C); 97 } 98 99 /* 100 * UART 101 */ 102 for (i = 0; i < FSL_IMX7_NUM_UARTS; i++) { 103 snprintf(name, NAME_SIZE, "uart%d", i); 104 sysbus_init_child_obj(obj, name, &s->uart[i], sizeof(s->uart[i]), 105 TYPE_IMX_SERIAL); 106 } 107 108 /* 109 * Ethernet 110 */ 111 for (i = 0; i < FSL_IMX7_NUM_ETHS; i++) { 112 snprintf(name, NAME_SIZE, "eth%d", i); 113 sysbus_init_child_obj(obj, name, &s->eth[i], sizeof(s->eth[i]), 114 TYPE_IMX_ENET); 115 } 116 117 /* 118 * SDHCI 119 */ 120 for (i = 0; i < FSL_IMX7_NUM_USDHCS; i++) { 121 snprintf(name, NAME_SIZE, "usdhc%d", i); 122 sysbus_init_child_obj(obj, name, &s->usdhc[i], sizeof(s->usdhc[i]), 123 TYPE_IMX_USDHC); 124 } 125 126 /* 127 * SNVS 128 */ 129 sysbus_init_child_obj(obj, "snvs", &s->snvs, sizeof(s->snvs), 130 TYPE_IMX7_SNVS); 131 132 /* 133 * Watchdog 134 */ 135 for (i = 0; i < FSL_IMX7_NUM_WDTS; i++) { 136 snprintf(name, NAME_SIZE, "wdt%d", i); 137 sysbus_init_child_obj(obj, name, &s->wdt[i], sizeof(s->wdt[i]), 138 TYPE_IMX2_WDT); 139 } 140 141 /* 142 * GPR 143 */ 144 sysbus_init_child_obj(obj, "gpr", &s->gpr, sizeof(s->gpr), TYPE_IMX7_GPR); 145 146 sysbus_init_child_obj(obj, "pcie", &s->pcie, sizeof(s->pcie), 147 TYPE_DESIGNWARE_PCIE_HOST); 148 149 for (i = 0; i < FSL_IMX7_NUM_USBS; i++) { 150 snprintf(name, NAME_SIZE, "usb%d", i); 151 sysbus_init_child_obj(obj, name, &s->usb[i], sizeof(s->usb[i]), 152 TYPE_CHIPIDEA); 153 } 154 } 155 156 static void fsl_imx7_realize(DeviceState *dev, Error **errp) 157 { 158 MachineState *ms = MACHINE(qdev_get_machine()); 159 FslIMX7State *s = FSL_IMX7(dev); 160 Object *o; 161 int i; 162 qemu_irq irq; 163 char name[NAME_SIZE]; 164 unsigned int smp_cpus = ms->smp.cpus; 165 166 if (smp_cpus > FSL_IMX7_NUM_CPUS) { 167 error_setg(errp, "%s: Only %d CPUs are supported (%d requested)", 168 TYPE_FSL_IMX7, FSL_IMX7_NUM_CPUS, smp_cpus); 169 return; 170 } 171 172 for (i = 0; i < smp_cpus; i++) { 173 o = OBJECT(&s->cpu[i]); 174 175 object_property_set_int(o, QEMU_PSCI_CONDUIT_SMC, 176 "psci-conduit", &error_abort); 177 178 /* On uniprocessor, the CBAR is set to 0 */ 179 if (smp_cpus > 1) { 180 object_property_set_int(o, FSL_IMX7_A7MPCORE_ADDR, 181 "reset-cbar", &error_abort); 182 } 183 184 if (i) { 185 /* Secondary CPUs start in PSCI powered-down state */ 186 object_property_set_bool(o, true, 187 "start-powered-off", &error_abort); 188 } 189 190 object_property_set_bool(o, true, "realized", &error_abort); 191 } 192 193 /* 194 * A7MPCORE 195 */ 196 object_property_set_int(OBJECT(&s->a7mpcore), smp_cpus, "num-cpu", 197 &error_abort); 198 object_property_set_int(OBJECT(&s->a7mpcore), 199 FSL_IMX7_MAX_IRQ + GIC_INTERNAL, 200 "num-irq", &error_abort); 201 202 object_property_set_bool(OBJECT(&s->a7mpcore), true, "realized", 203 &error_abort); 204 sysbus_mmio_map(SYS_BUS_DEVICE(&s->a7mpcore), 0, FSL_IMX7_A7MPCORE_ADDR); 205 206 for (i = 0; i < smp_cpus; i++) { 207 SysBusDevice *sbd = SYS_BUS_DEVICE(&s->a7mpcore); 208 DeviceState *d = DEVICE(qemu_get_cpu(i)); 209 210 irq = qdev_get_gpio_in(d, ARM_CPU_IRQ); 211 sysbus_connect_irq(sbd, i, irq); 212 irq = qdev_get_gpio_in(d, ARM_CPU_FIQ); 213 sysbus_connect_irq(sbd, i + smp_cpus, irq); 214 irq = qdev_get_gpio_in(d, ARM_CPU_VIRQ); 215 sysbus_connect_irq(sbd, i + 2 * smp_cpus, irq); 216 irq = qdev_get_gpio_in(d, ARM_CPU_VFIQ); 217 sysbus_connect_irq(sbd, i + 3 * smp_cpus, irq); 218 } 219 220 /* 221 * A7MPCORE DAP 222 */ 223 create_unimplemented_device("a7mpcore-dap", FSL_IMX7_A7MPCORE_DAP_ADDR, 224 0x100000); 225 226 /* 227 * GPT1, 2, 3, 4 228 */ 229 for (i = 0; i < FSL_IMX7_NUM_GPTS; i++) { 230 static const hwaddr FSL_IMX7_GPTn_ADDR[FSL_IMX7_NUM_GPTS] = { 231 FSL_IMX7_GPT1_ADDR, 232 FSL_IMX7_GPT2_ADDR, 233 FSL_IMX7_GPT3_ADDR, 234 FSL_IMX7_GPT4_ADDR, 235 }; 236 237 s->gpt[i].ccm = IMX_CCM(&s->ccm); 238 object_property_set_bool(OBJECT(&s->gpt[i]), true, "realized", 239 &error_abort); 240 sysbus_mmio_map(SYS_BUS_DEVICE(&s->gpt[i]), 0, FSL_IMX7_GPTn_ADDR[i]); 241 } 242 243 for (i = 0; i < FSL_IMX7_NUM_GPIOS; i++) { 244 static const hwaddr FSL_IMX7_GPIOn_ADDR[FSL_IMX7_NUM_GPIOS] = { 245 FSL_IMX7_GPIO1_ADDR, 246 FSL_IMX7_GPIO2_ADDR, 247 FSL_IMX7_GPIO3_ADDR, 248 FSL_IMX7_GPIO4_ADDR, 249 FSL_IMX7_GPIO5_ADDR, 250 FSL_IMX7_GPIO6_ADDR, 251 FSL_IMX7_GPIO7_ADDR, 252 }; 253 254 object_property_set_bool(OBJECT(&s->gpio[i]), true, "realized", 255 &error_abort); 256 sysbus_mmio_map(SYS_BUS_DEVICE(&s->gpio[i]), 0, FSL_IMX7_GPIOn_ADDR[i]); 257 } 258 259 /* 260 * IOMUXC and IOMUXC_LPSR 261 */ 262 for (i = 0; i < FSL_IMX7_NUM_IOMUXCS; i++) { 263 static const hwaddr FSL_IMX7_IOMUXCn_ADDR[FSL_IMX7_NUM_IOMUXCS] = { 264 FSL_IMX7_IOMUXC_ADDR, 265 FSL_IMX7_IOMUXC_LPSR_ADDR, 266 }; 267 268 snprintf(name, NAME_SIZE, "iomuxc%d", i); 269 create_unimplemented_device(name, FSL_IMX7_IOMUXCn_ADDR[i], 270 FSL_IMX7_IOMUXCn_SIZE); 271 } 272 273 /* 274 * CCM 275 */ 276 object_property_set_bool(OBJECT(&s->ccm), true, "realized", &error_abort); 277 sysbus_mmio_map(SYS_BUS_DEVICE(&s->ccm), 0, FSL_IMX7_CCM_ADDR); 278 279 /* 280 * Analog 281 */ 282 object_property_set_bool(OBJECT(&s->analog), true, "realized", 283 &error_abort); 284 sysbus_mmio_map(SYS_BUS_DEVICE(&s->analog), 0, FSL_IMX7_ANALOG_ADDR); 285 286 /* 287 * GPCv2 288 */ 289 object_property_set_bool(OBJECT(&s->gpcv2), true, 290 "realized", &error_abort); 291 sysbus_mmio_map(SYS_BUS_DEVICE(&s->gpcv2), 0, FSL_IMX7_GPC_ADDR); 292 293 /* Initialize all ECSPI */ 294 for (i = 0; i < FSL_IMX7_NUM_ECSPIS; i++) { 295 static const hwaddr FSL_IMX7_SPIn_ADDR[FSL_IMX7_NUM_ECSPIS] = { 296 FSL_IMX7_ECSPI1_ADDR, 297 FSL_IMX7_ECSPI2_ADDR, 298 FSL_IMX7_ECSPI3_ADDR, 299 FSL_IMX7_ECSPI4_ADDR, 300 }; 301 302 static const int FSL_IMX7_SPIn_IRQ[FSL_IMX7_NUM_ECSPIS] = { 303 FSL_IMX7_ECSPI1_IRQ, 304 FSL_IMX7_ECSPI2_IRQ, 305 FSL_IMX7_ECSPI3_IRQ, 306 FSL_IMX7_ECSPI4_IRQ, 307 }; 308 309 /* Initialize the SPI */ 310 object_property_set_bool(OBJECT(&s->spi[i]), true, "realized", 311 &error_abort); 312 sysbus_mmio_map(SYS_BUS_DEVICE(&s->spi[i]), 0, 313 FSL_IMX7_SPIn_ADDR[i]); 314 sysbus_connect_irq(SYS_BUS_DEVICE(&s->spi[i]), 0, 315 qdev_get_gpio_in(DEVICE(&s->a7mpcore), 316 FSL_IMX7_SPIn_IRQ[i])); 317 } 318 319 for (i = 0; i < FSL_IMX7_NUM_I2CS; i++) { 320 static const hwaddr FSL_IMX7_I2Cn_ADDR[FSL_IMX7_NUM_I2CS] = { 321 FSL_IMX7_I2C1_ADDR, 322 FSL_IMX7_I2C2_ADDR, 323 FSL_IMX7_I2C3_ADDR, 324 FSL_IMX7_I2C4_ADDR, 325 }; 326 327 static const int FSL_IMX7_I2Cn_IRQ[FSL_IMX7_NUM_I2CS] = { 328 FSL_IMX7_I2C1_IRQ, 329 FSL_IMX7_I2C2_IRQ, 330 FSL_IMX7_I2C3_IRQ, 331 FSL_IMX7_I2C4_IRQ, 332 }; 333 334 object_property_set_bool(OBJECT(&s->i2c[i]), true, "realized", 335 &error_abort); 336 sysbus_mmio_map(SYS_BUS_DEVICE(&s->i2c[i]), 0, FSL_IMX7_I2Cn_ADDR[i]); 337 338 sysbus_connect_irq(SYS_BUS_DEVICE(&s->i2c[i]), 0, 339 qdev_get_gpio_in(DEVICE(&s->a7mpcore), 340 FSL_IMX7_I2Cn_IRQ[i])); 341 } 342 343 /* 344 * UART 345 */ 346 for (i = 0; i < FSL_IMX7_NUM_UARTS; i++) { 347 static const hwaddr FSL_IMX7_UARTn_ADDR[FSL_IMX7_NUM_UARTS] = { 348 FSL_IMX7_UART1_ADDR, 349 FSL_IMX7_UART2_ADDR, 350 FSL_IMX7_UART3_ADDR, 351 FSL_IMX7_UART4_ADDR, 352 FSL_IMX7_UART5_ADDR, 353 FSL_IMX7_UART6_ADDR, 354 FSL_IMX7_UART7_ADDR, 355 }; 356 357 static const int FSL_IMX7_UARTn_IRQ[FSL_IMX7_NUM_UARTS] = { 358 FSL_IMX7_UART1_IRQ, 359 FSL_IMX7_UART2_IRQ, 360 FSL_IMX7_UART3_IRQ, 361 FSL_IMX7_UART4_IRQ, 362 FSL_IMX7_UART5_IRQ, 363 FSL_IMX7_UART6_IRQ, 364 FSL_IMX7_UART7_IRQ, 365 }; 366 367 368 qdev_prop_set_chr(DEVICE(&s->uart[i]), "chardev", serial_hd(i)); 369 370 object_property_set_bool(OBJECT(&s->uart[i]), true, "realized", 371 &error_abort); 372 373 sysbus_mmio_map(SYS_BUS_DEVICE(&s->uart[i]), 0, FSL_IMX7_UARTn_ADDR[i]); 374 375 irq = qdev_get_gpio_in(DEVICE(&s->a7mpcore), FSL_IMX7_UARTn_IRQ[i]); 376 sysbus_connect_irq(SYS_BUS_DEVICE(&s->uart[i]), 0, irq); 377 } 378 379 /* 380 * Ethernet 381 */ 382 for (i = 0; i < FSL_IMX7_NUM_ETHS; i++) { 383 static const hwaddr FSL_IMX7_ENETn_ADDR[FSL_IMX7_NUM_ETHS] = { 384 FSL_IMX7_ENET1_ADDR, 385 FSL_IMX7_ENET2_ADDR, 386 }; 387 388 object_property_set_uint(OBJECT(&s->eth[i]), FSL_IMX7_ETH_NUM_TX_RINGS, 389 "tx-ring-num", &error_abort); 390 qdev_set_nic_properties(DEVICE(&s->eth[i]), &nd_table[i]); 391 object_property_set_bool(OBJECT(&s->eth[i]), true, "realized", 392 &error_abort); 393 394 sysbus_mmio_map(SYS_BUS_DEVICE(&s->eth[i]), 0, FSL_IMX7_ENETn_ADDR[i]); 395 396 irq = qdev_get_gpio_in(DEVICE(&s->a7mpcore), FSL_IMX7_ENET_IRQ(i, 0)); 397 sysbus_connect_irq(SYS_BUS_DEVICE(&s->eth[i]), 0, irq); 398 irq = qdev_get_gpio_in(DEVICE(&s->a7mpcore), FSL_IMX7_ENET_IRQ(i, 3)); 399 sysbus_connect_irq(SYS_BUS_DEVICE(&s->eth[i]), 1, irq); 400 } 401 402 /* 403 * USDHC 404 */ 405 for (i = 0; i < FSL_IMX7_NUM_USDHCS; i++) { 406 static const hwaddr FSL_IMX7_USDHCn_ADDR[FSL_IMX7_NUM_USDHCS] = { 407 FSL_IMX7_USDHC1_ADDR, 408 FSL_IMX7_USDHC2_ADDR, 409 FSL_IMX7_USDHC3_ADDR, 410 }; 411 412 static const int FSL_IMX7_USDHCn_IRQ[FSL_IMX7_NUM_USDHCS] = { 413 FSL_IMX7_USDHC1_IRQ, 414 FSL_IMX7_USDHC2_IRQ, 415 FSL_IMX7_USDHC3_IRQ, 416 }; 417 418 object_property_set_bool(OBJECT(&s->usdhc[i]), true, "realized", 419 &error_abort); 420 421 sysbus_mmio_map(SYS_BUS_DEVICE(&s->usdhc[i]), 0, 422 FSL_IMX7_USDHCn_ADDR[i]); 423 424 irq = qdev_get_gpio_in(DEVICE(&s->a7mpcore), FSL_IMX7_USDHCn_IRQ[i]); 425 sysbus_connect_irq(SYS_BUS_DEVICE(&s->usdhc[i]), 0, irq); 426 } 427 428 /* 429 * SNVS 430 */ 431 object_property_set_bool(OBJECT(&s->snvs), true, "realized", &error_abort); 432 sysbus_mmio_map(SYS_BUS_DEVICE(&s->snvs), 0, FSL_IMX7_SNVS_ADDR); 433 434 /* 435 * SRC 436 */ 437 create_unimplemented_device("src", FSL_IMX7_SRC_ADDR, FSL_IMX7_SRC_SIZE); 438 439 /* 440 * Watchdog 441 */ 442 for (i = 0; i < FSL_IMX7_NUM_WDTS; i++) { 443 static const hwaddr FSL_IMX7_WDOGn_ADDR[FSL_IMX7_NUM_WDTS] = { 444 FSL_IMX7_WDOG1_ADDR, 445 FSL_IMX7_WDOG2_ADDR, 446 FSL_IMX7_WDOG3_ADDR, 447 FSL_IMX7_WDOG4_ADDR, 448 }; 449 static const int FSL_IMX7_WDOGn_IRQ[FSL_IMX7_NUM_WDTS] = { 450 FSL_IMX7_WDOG1_IRQ, 451 FSL_IMX7_WDOG2_IRQ, 452 FSL_IMX7_WDOG3_IRQ, 453 FSL_IMX7_WDOG4_IRQ, 454 }; 455 456 object_property_set_bool(OBJECT(&s->wdt[i]), true, "pretimeout-support", 457 &error_abort); 458 object_property_set_bool(OBJECT(&s->wdt[i]), true, "realized", 459 &error_abort); 460 461 sysbus_mmio_map(SYS_BUS_DEVICE(&s->wdt[i]), 0, FSL_IMX7_WDOGn_ADDR[i]); 462 sysbus_connect_irq(SYS_BUS_DEVICE(&s->wdt[i]), 0, 463 qdev_get_gpio_in(DEVICE(&s->a7mpcore), 464 FSL_IMX7_WDOGn_IRQ[i])); 465 } 466 467 /* 468 * SDMA 469 */ 470 create_unimplemented_device("sdma", FSL_IMX7_SDMA_ADDR, FSL_IMX7_SDMA_SIZE); 471 472 /* 473 * CAAM 474 */ 475 create_unimplemented_device("caam", FSL_IMX7_CAAM_ADDR, FSL_IMX7_CAAM_SIZE); 476 477 /* 478 * PWM 479 */ 480 create_unimplemented_device("pwm1", FSL_IMX7_PWM1_ADDR, FSL_IMX7_PWMn_SIZE); 481 create_unimplemented_device("pwm2", FSL_IMX7_PWM2_ADDR, FSL_IMX7_PWMn_SIZE); 482 create_unimplemented_device("pwm3", FSL_IMX7_PWM3_ADDR, FSL_IMX7_PWMn_SIZE); 483 create_unimplemented_device("pwm4", FSL_IMX7_PWM4_ADDR, FSL_IMX7_PWMn_SIZE); 484 485 /* 486 * CAN 487 */ 488 create_unimplemented_device("can1", FSL_IMX7_CAN1_ADDR, FSL_IMX7_CANn_SIZE); 489 create_unimplemented_device("can2", FSL_IMX7_CAN2_ADDR, FSL_IMX7_CANn_SIZE); 490 491 /* 492 * OCOTP 493 */ 494 create_unimplemented_device("ocotp", FSL_IMX7_OCOTP_ADDR, 495 FSL_IMX7_OCOTP_SIZE); 496 497 object_property_set_bool(OBJECT(&s->gpr), true, "realized", 498 &error_abort); 499 sysbus_mmio_map(SYS_BUS_DEVICE(&s->gpr), 0, FSL_IMX7_GPR_ADDR); 500 501 object_property_set_bool(OBJECT(&s->pcie), true, 502 "realized", &error_abort); 503 sysbus_mmio_map(SYS_BUS_DEVICE(&s->pcie), 0, FSL_IMX7_PCIE_REG_ADDR); 504 505 irq = qdev_get_gpio_in(DEVICE(&s->a7mpcore), FSL_IMX7_PCI_INTA_IRQ); 506 sysbus_connect_irq(SYS_BUS_DEVICE(&s->pcie), 0, irq); 507 irq = qdev_get_gpio_in(DEVICE(&s->a7mpcore), FSL_IMX7_PCI_INTB_IRQ); 508 sysbus_connect_irq(SYS_BUS_DEVICE(&s->pcie), 1, irq); 509 irq = qdev_get_gpio_in(DEVICE(&s->a7mpcore), FSL_IMX7_PCI_INTC_IRQ); 510 sysbus_connect_irq(SYS_BUS_DEVICE(&s->pcie), 2, irq); 511 irq = qdev_get_gpio_in(DEVICE(&s->a7mpcore), FSL_IMX7_PCI_INTD_IRQ); 512 sysbus_connect_irq(SYS_BUS_DEVICE(&s->pcie), 3, irq); 513 514 515 for (i = 0; i < FSL_IMX7_NUM_USBS; i++) { 516 static const hwaddr FSL_IMX7_USBMISCn_ADDR[FSL_IMX7_NUM_USBS] = { 517 FSL_IMX7_USBMISC1_ADDR, 518 FSL_IMX7_USBMISC2_ADDR, 519 FSL_IMX7_USBMISC3_ADDR, 520 }; 521 522 static const hwaddr FSL_IMX7_USBn_ADDR[FSL_IMX7_NUM_USBS] = { 523 FSL_IMX7_USB1_ADDR, 524 FSL_IMX7_USB2_ADDR, 525 FSL_IMX7_USB3_ADDR, 526 }; 527 528 static const int FSL_IMX7_USBn_IRQ[FSL_IMX7_NUM_USBS] = { 529 FSL_IMX7_USB1_IRQ, 530 FSL_IMX7_USB2_IRQ, 531 FSL_IMX7_USB3_IRQ, 532 }; 533 534 object_property_set_bool(OBJECT(&s->usb[i]), true, "realized", 535 &error_abort); 536 sysbus_mmio_map(SYS_BUS_DEVICE(&s->usb[i]), 0, 537 FSL_IMX7_USBn_ADDR[i]); 538 539 irq = qdev_get_gpio_in(DEVICE(&s->a7mpcore), FSL_IMX7_USBn_IRQ[i]); 540 sysbus_connect_irq(SYS_BUS_DEVICE(&s->usb[i]), 0, irq); 541 542 snprintf(name, NAME_SIZE, "usbmisc%d", i); 543 create_unimplemented_device(name, FSL_IMX7_USBMISCn_ADDR[i], 544 FSL_IMX7_USBMISCn_SIZE); 545 } 546 547 /* 548 * ADCs 549 */ 550 for (i = 0; i < FSL_IMX7_NUM_ADCS; i++) { 551 static const hwaddr FSL_IMX7_ADCn_ADDR[FSL_IMX7_NUM_ADCS] = { 552 FSL_IMX7_ADC1_ADDR, 553 FSL_IMX7_ADC2_ADDR, 554 }; 555 556 snprintf(name, NAME_SIZE, "adc%d", i); 557 create_unimplemented_device(name, FSL_IMX7_ADCn_ADDR[i], 558 FSL_IMX7_ADCn_SIZE); 559 } 560 561 /* 562 * LCD 563 */ 564 create_unimplemented_device("lcdif", FSL_IMX7_LCDIF_ADDR, 565 FSL_IMX7_LCDIF_SIZE); 566 567 /* 568 * DMA APBH 569 */ 570 create_unimplemented_device("dma-apbh", FSL_IMX7_DMA_APBH_ADDR, 571 FSL_IMX7_DMA_APBH_SIZE); 572 /* 573 * PCIe PHY 574 */ 575 create_unimplemented_device("pcie-phy", FSL_IMX7_PCIE_PHY_ADDR, 576 FSL_IMX7_PCIE_PHY_SIZE); 577 } 578 579 static void fsl_imx7_class_init(ObjectClass *oc, void *data) 580 { 581 DeviceClass *dc = DEVICE_CLASS(oc); 582 583 dc->realize = fsl_imx7_realize; 584 585 /* Reason: Uses serial_hds and nd_table in realize() directly */ 586 dc->user_creatable = false; 587 dc->desc = "i.MX7 SOC"; 588 } 589 590 static const TypeInfo fsl_imx7_type_info = { 591 .name = TYPE_FSL_IMX7, 592 .parent = TYPE_DEVICE, 593 .instance_size = sizeof(FslIMX7State), 594 .instance_init = fsl_imx7_init, 595 .class_init = fsl_imx7_class_init, 596 }; 597 598 static void fsl_imx7_register_types(void) 599 { 600 type_register_static(&fsl_imx7_type_info); 601 } 602 type_init(fsl_imx7_register_types) 603