1 /* 2 * ARM Integrator CP System emulation. 3 * 4 * Copyright (c) 2005-2007 CodeSourcery. 5 * Written by Paul Brook 6 * 7 * This code is licensed under the GPL 8 */ 9 10 #include "qemu/osdep.h" 11 #include "qapi/error.h" 12 #include "qemu-common.h" 13 #include "cpu.h" 14 #include "hw/sysbus.h" 15 #include "hw/devices.h" 16 #include "hw/boards.h" 17 #include "hw/arm/arm.h" 18 #include "hw/misc/arm_integrator_debug.h" 19 #include "net/net.h" 20 #include "exec/address-spaces.h" 21 #include "sysemu/sysemu.h" 22 #include "qemu/error-report.h" 23 #include "hw/char/pl011.h" 24 25 #define TYPE_INTEGRATOR_CM "integrator_core" 26 #define INTEGRATOR_CM(obj) \ 27 OBJECT_CHECK(IntegratorCMState, (obj), TYPE_INTEGRATOR_CM) 28 29 typedef struct IntegratorCMState { 30 /*< private >*/ 31 SysBusDevice parent_obj; 32 /*< public >*/ 33 34 MemoryRegion iomem; 35 uint32_t memsz; 36 MemoryRegion flash; 37 uint32_t cm_osc; 38 uint32_t cm_ctrl; 39 uint32_t cm_lock; 40 uint32_t cm_auxosc; 41 uint32_t cm_sdram; 42 uint32_t cm_init; 43 uint32_t cm_flags; 44 uint32_t cm_nvflags; 45 uint32_t cm_refcnt_offset; 46 uint32_t int_level; 47 uint32_t irq_enabled; 48 uint32_t fiq_enabled; 49 } IntegratorCMState; 50 51 static uint8_t integrator_spd[128] = { 52 128, 8, 4, 11, 9, 1, 64, 0, 2, 0xa0, 0xa0, 0, 0, 8, 0, 1, 53 0xe, 4, 0x1c, 1, 2, 0x20, 0xc0, 0, 0, 0, 0, 0x30, 0x28, 0x30, 0x28, 0x40 54 }; 55 56 static uint64_t integratorcm_read(void *opaque, hwaddr offset, 57 unsigned size) 58 { 59 IntegratorCMState *s = opaque; 60 if (offset >= 0x100 && offset < 0x200) { 61 /* CM_SPD */ 62 if (offset >= 0x180) 63 return 0; 64 return integrator_spd[offset >> 2]; 65 } 66 switch (offset >> 2) { 67 case 0: /* CM_ID */ 68 return 0x411a3001; 69 case 1: /* CM_PROC */ 70 return 0; 71 case 2: /* CM_OSC */ 72 return s->cm_osc; 73 case 3: /* CM_CTRL */ 74 return s->cm_ctrl; 75 case 4: /* CM_STAT */ 76 return 0x00100000; 77 case 5: /* CM_LOCK */ 78 if (s->cm_lock == 0xa05f) { 79 return 0x1a05f; 80 } else { 81 return s->cm_lock; 82 } 83 case 6: /* CM_LMBUSCNT */ 84 /* ??? High frequency timer. */ 85 hw_error("integratorcm_read: CM_LMBUSCNT"); 86 case 7: /* CM_AUXOSC */ 87 return s->cm_auxosc; 88 case 8: /* CM_SDRAM */ 89 return s->cm_sdram; 90 case 9: /* CM_INIT */ 91 return s->cm_init; 92 case 10: /* CM_REFCNT */ 93 /* This register, CM_REFCNT, provides a 32-bit count value. 94 * The count increments at the fixed reference clock frequency of 24MHz 95 * and can be used as a real-time counter. 96 */ 97 return (uint32_t)muldiv64(qemu_clock_get_ns(QEMU_CLOCK_VIRTUAL), 24, 98 1000) - s->cm_refcnt_offset; 99 case 12: /* CM_FLAGS */ 100 return s->cm_flags; 101 case 14: /* CM_NVFLAGS */ 102 return s->cm_nvflags; 103 case 16: /* CM_IRQ_STAT */ 104 return s->int_level & s->irq_enabled; 105 case 17: /* CM_IRQ_RSTAT */ 106 return s->int_level; 107 case 18: /* CM_IRQ_ENSET */ 108 return s->irq_enabled; 109 case 20: /* CM_SOFT_INTSET */ 110 return s->int_level & 1; 111 case 24: /* CM_FIQ_STAT */ 112 return s->int_level & s->fiq_enabled; 113 case 25: /* CM_FIQ_RSTAT */ 114 return s->int_level; 115 case 26: /* CM_FIQ_ENSET */ 116 return s->fiq_enabled; 117 case 32: /* CM_VOLTAGE_CTL0 */ 118 case 33: /* CM_VOLTAGE_CTL1 */ 119 case 34: /* CM_VOLTAGE_CTL2 */ 120 case 35: /* CM_VOLTAGE_CTL3 */ 121 /* ??? Voltage control unimplemented. */ 122 return 0; 123 default: 124 hw_error("integratorcm_read: Unimplemented offset 0x%x\n", 125 (int)offset); 126 return 0; 127 } 128 } 129 130 static void integratorcm_do_remap(IntegratorCMState *s) 131 { 132 /* Sync memory region state with CM_CTRL REMAP bit: 133 * bit 0 => flash at address 0; bit 1 => RAM 134 */ 135 memory_region_set_enabled(&s->flash, !(s->cm_ctrl & 4)); 136 } 137 138 static void integratorcm_set_ctrl(IntegratorCMState *s, uint32_t value) 139 { 140 if (value & 8) { 141 qemu_system_reset_request(); 142 } 143 if ((s->cm_ctrl ^ value) & 1) { 144 /* (value & 1) != 0 means the green "MISC LED" is lit. 145 * We don't have any nice place to display LEDs. printf is a bad 146 * idea because Linux uses the LED as a heartbeat and the output 147 * will swamp anything else on the terminal. 148 */ 149 } 150 /* Note that the RESET bit [3] always reads as zero */ 151 s->cm_ctrl = (s->cm_ctrl & ~5) | (value & 5); 152 integratorcm_do_remap(s); 153 } 154 155 static void integratorcm_update(IntegratorCMState *s) 156 { 157 /* ??? The CPU irq/fiq is raised when either the core module or base PIC 158 are active. */ 159 if (s->int_level & (s->irq_enabled | s->fiq_enabled)) 160 hw_error("Core module interrupt\n"); 161 } 162 163 static void integratorcm_write(void *opaque, hwaddr offset, 164 uint64_t value, unsigned size) 165 { 166 IntegratorCMState *s = opaque; 167 switch (offset >> 2) { 168 case 2: /* CM_OSC */ 169 if (s->cm_lock == 0xa05f) 170 s->cm_osc = value; 171 break; 172 case 3: /* CM_CTRL */ 173 integratorcm_set_ctrl(s, value); 174 break; 175 case 5: /* CM_LOCK */ 176 s->cm_lock = value & 0xffff; 177 break; 178 case 7: /* CM_AUXOSC */ 179 if (s->cm_lock == 0xa05f) 180 s->cm_auxosc = value; 181 break; 182 case 8: /* CM_SDRAM */ 183 s->cm_sdram = value; 184 break; 185 case 9: /* CM_INIT */ 186 /* ??? This can change the memory bus frequency. */ 187 s->cm_init = value; 188 break; 189 case 12: /* CM_FLAGSS */ 190 s->cm_flags |= value; 191 break; 192 case 13: /* CM_FLAGSC */ 193 s->cm_flags &= ~value; 194 break; 195 case 14: /* CM_NVFLAGSS */ 196 s->cm_nvflags |= value; 197 break; 198 case 15: /* CM_NVFLAGSS */ 199 s->cm_nvflags &= ~value; 200 break; 201 case 18: /* CM_IRQ_ENSET */ 202 s->irq_enabled |= value; 203 integratorcm_update(s); 204 break; 205 case 19: /* CM_IRQ_ENCLR */ 206 s->irq_enabled &= ~value; 207 integratorcm_update(s); 208 break; 209 case 20: /* CM_SOFT_INTSET */ 210 s->int_level |= (value & 1); 211 integratorcm_update(s); 212 break; 213 case 21: /* CM_SOFT_INTCLR */ 214 s->int_level &= ~(value & 1); 215 integratorcm_update(s); 216 break; 217 case 26: /* CM_FIQ_ENSET */ 218 s->fiq_enabled |= value; 219 integratorcm_update(s); 220 break; 221 case 27: /* CM_FIQ_ENCLR */ 222 s->fiq_enabled &= ~value; 223 integratorcm_update(s); 224 break; 225 case 32: /* CM_VOLTAGE_CTL0 */ 226 case 33: /* CM_VOLTAGE_CTL1 */ 227 case 34: /* CM_VOLTAGE_CTL2 */ 228 case 35: /* CM_VOLTAGE_CTL3 */ 229 /* ??? Voltage control unimplemented. */ 230 break; 231 default: 232 hw_error("integratorcm_write: Unimplemented offset 0x%x\n", 233 (int)offset); 234 break; 235 } 236 } 237 238 /* Integrator/CM control registers. */ 239 240 static const MemoryRegionOps integratorcm_ops = { 241 .read = integratorcm_read, 242 .write = integratorcm_write, 243 .endianness = DEVICE_NATIVE_ENDIAN, 244 }; 245 246 static void integratorcm_init(Object *obj) 247 { 248 IntegratorCMState *s = INTEGRATOR_CM(obj); 249 SysBusDevice *dev = SYS_BUS_DEVICE(obj); 250 251 s->cm_osc = 0x01000048; 252 /* ??? What should the high bits of this value be? */ 253 s->cm_auxosc = 0x0007feff; 254 s->cm_sdram = 0x00011122; 255 memcpy(integrator_spd + 73, "QEMU-MEMORY", 11); 256 s->cm_init = 0x00000112; 257 s->cm_refcnt_offset = muldiv64(qemu_clock_get_ns(QEMU_CLOCK_VIRTUAL), 24, 258 1000); 259 memory_region_init_ram(&s->flash, obj, "integrator.flash", 0x100000, 260 &error_fatal); 261 vmstate_register_ram_global(&s->flash); 262 263 memory_region_init_io(&s->iomem, obj, &integratorcm_ops, s, 264 "integratorcm", 0x00800000); 265 sysbus_init_mmio(dev, &s->iomem); 266 267 integratorcm_do_remap(s); 268 /* ??? Save/restore. */ 269 } 270 271 static void integratorcm_realize(DeviceState *d, Error **errp) 272 { 273 IntegratorCMState *s = INTEGRATOR_CM(d); 274 275 if (s->memsz >= 256) { 276 integrator_spd[31] = 64; 277 s->cm_sdram |= 0x10; 278 } else if (s->memsz >= 128) { 279 integrator_spd[31] = 32; 280 s->cm_sdram |= 0x0c; 281 } else if (s->memsz >= 64) { 282 integrator_spd[31] = 16; 283 s->cm_sdram |= 0x08; 284 } else if (s->memsz >= 32) { 285 integrator_spd[31] = 4; 286 s->cm_sdram |= 0x04; 287 } else { 288 integrator_spd[31] = 2; 289 } 290 } 291 292 /* Integrator/CP hardware emulation. */ 293 /* Primary interrupt controller. */ 294 295 #define TYPE_INTEGRATOR_PIC "integrator_pic" 296 #define INTEGRATOR_PIC(obj) \ 297 OBJECT_CHECK(icp_pic_state, (obj), TYPE_INTEGRATOR_PIC) 298 299 typedef struct icp_pic_state { 300 /*< private >*/ 301 SysBusDevice parent_obj; 302 /*< public >*/ 303 304 MemoryRegion iomem; 305 uint32_t level; 306 uint32_t irq_enabled; 307 uint32_t fiq_enabled; 308 qemu_irq parent_irq; 309 qemu_irq parent_fiq; 310 } icp_pic_state; 311 312 static void icp_pic_update(icp_pic_state *s) 313 { 314 uint32_t flags; 315 316 flags = (s->level & s->irq_enabled); 317 qemu_set_irq(s->parent_irq, flags != 0); 318 flags = (s->level & s->fiq_enabled); 319 qemu_set_irq(s->parent_fiq, flags != 0); 320 } 321 322 static void icp_pic_set_irq(void *opaque, int irq, int level) 323 { 324 icp_pic_state *s = (icp_pic_state *)opaque; 325 if (level) 326 s->level |= 1 << irq; 327 else 328 s->level &= ~(1 << irq); 329 icp_pic_update(s); 330 } 331 332 static uint64_t icp_pic_read(void *opaque, hwaddr offset, 333 unsigned size) 334 { 335 icp_pic_state *s = (icp_pic_state *)opaque; 336 337 switch (offset >> 2) { 338 case 0: /* IRQ_STATUS */ 339 return s->level & s->irq_enabled; 340 case 1: /* IRQ_RAWSTAT */ 341 return s->level; 342 case 2: /* IRQ_ENABLESET */ 343 return s->irq_enabled; 344 case 4: /* INT_SOFTSET */ 345 return s->level & 1; 346 case 8: /* FRQ_STATUS */ 347 return s->level & s->fiq_enabled; 348 case 9: /* FRQ_RAWSTAT */ 349 return s->level; 350 case 10: /* FRQ_ENABLESET */ 351 return s->fiq_enabled; 352 case 3: /* IRQ_ENABLECLR */ 353 case 5: /* INT_SOFTCLR */ 354 case 11: /* FRQ_ENABLECLR */ 355 default: 356 printf ("icp_pic_read: Bad register offset 0x%x\n", (int)offset); 357 return 0; 358 } 359 } 360 361 static void icp_pic_write(void *opaque, hwaddr offset, 362 uint64_t value, unsigned size) 363 { 364 icp_pic_state *s = (icp_pic_state *)opaque; 365 366 switch (offset >> 2) { 367 case 2: /* IRQ_ENABLESET */ 368 s->irq_enabled |= value; 369 break; 370 case 3: /* IRQ_ENABLECLR */ 371 s->irq_enabled &= ~value; 372 break; 373 case 4: /* INT_SOFTSET */ 374 if (value & 1) 375 icp_pic_set_irq(s, 0, 1); 376 break; 377 case 5: /* INT_SOFTCLR */ 378 if (value & 1) 379 icp_pic_set_irq(s, 0, 0); 380 break; 381 case 10: /* FRQ_ENABLESET */ 382 s->fiq_enabled |= value; 383 break; 384 case 11: /* FRQ_ENABLECLR */ 385 s->fiq_enabled &= ~value; 386 break; 387 case 0: /* IRQ_STATUS */ 388 case 1: /* IRQ_RAWSTAT */ 389 case 8: /* FRQ_STATUS */ 390 case 9: /* FRQ_RAWSTAT */ 391 default: 392 printf ("icp_pic_write: Bad register offset 0x%x\n", (int)offset); 393 return; 394 } 395 icp_pic_update(s); 396 } 397 398 static const MemoryRegionOps icp_pic_ops = { 399 .read = icp_pic_read, 400 .write = icp_pic_write, 401 .endianness = DEVICE_NATIVE_ENDIAN, 402 }; 403 404 static void icp_pic_init(Object *obj) 405 { 406 DeviceState *dev = DEVICE(obj); 407 icp_pic_state *s = INTEGRATOR_PIC(obj); 408 SysBusDevice *sbd = SYS_BUS_DEVICE(obj); 409 410 qdev_init_gpio_in(dev, icp_pic_set_irq, 32); 411 sysbus_init_irq(sbd, &s->parent_irq); 412 sysbus_init_irq(sbd, &s->parent_fiq); 413 memory_region_init_io(&s->iomem, obj, &icp_pic_ops, s, 414 "icp-pic", 0x00800000); 415 sysbus_init_mmio(sbd, &s->iomem); 416 } 417 418 /* CP control registers. */ 419 420 #define TYPE_ICP_CONTROL_REGS "icp-ctrl-regs" 421 #define ICP_CONTROL_REGS(obj) \ 422 OBJECT_CHECK(ICPCtrlRegsState, (obj), TYPE_ICP_CONTROL_REGS) 423 424 typedef struct ICPCtrlRegsState { 425 /*< private >*/ 426 SysBusDevice parent_obj; 427 /*< public >*/ 428 429 MemoryRegion iomem; 430 431 qemu_irq mmc_irq; 432 uint32_t intreg_state; 433 } ICPCtrlRegsState; 434 435 #define ICP_GPIO_MMC_WPROT "mmc-wprot" 436 #define ICP_GPIO_MMC_CARDIN "mmc-cardin" 437 438 #define ICP_INTREG_WPROT (1 << 0) 439 #define ICP_INTREG_CARDIN (1 << 3) 440 441 static uint64_t icp_control_read(void *opaque, hwaddr offset, 442 unsigned size) 443 { 444 ICPCtrlRegsState *s = opaque; 445 446 switch (offset >> 2) { 447 case 0: /* CP_IDFIELD */ 448 return 0x41034003; 449 case 1: /* CP_FLASHPROG */ 450 return 0; 451 case 2: /* CP_INTREG */ 452 return s->intreg_state; 453 case 3: /* CP_DECODE */ 454 return 0x11; 455 default: 456 hw_error("icp_control_read: Bad offset %x\n", (int)offset); 457 return 0; 458 } 459 } 460 461 static void icp_control_write(void *opaque, hwaddr offset, 462 uint64_t value, unsigned size) 463 { 464 ICPCtrlRegsState *s = opaque; 465 466 switch (offset >> 2) { 467 case 2: /* CP_INTREG */ 468 s->intreg_state &= ~(value & ICP_INTREG_CARDIN); 469 qemu_set_irq(s->mmc_irq, !!(s->intreg_state & ICP_INTREG_CARDIN)); 470 break; 471 case 1: /* CP_FLASHPROG */ 472 case 3: /* CP_DECODE */ 473 /* Nothing interesting implemented yet. */ 474 break; 475 default: 476 hw_error("icp_control_write: Bad offset %x\n", (int)offset); 477 } 478 } 479 480 static const MemoryRegionOps icp_control_ops = { 481 .read = icp_control_read, 482 .write = icp_control_write, 483 .endianness = DEVICE_NATIVE_ENDIAN, 484 }; 485 486 static void icp_control_mmc_wprot(void *opaque, int line, int level) 487 { 488 ICPCtrlRegsState *s = opaque; 489 490 s->intreg_state &= ~ICP_INTREG_WPROT; 491 if (level) { 492 s->intreg_state |= ICP_INTREG_WPROT; 493 } 494 } 495 496 static void icp_control_mmc_cardin(void *opaque, int line, int level) 497 { 498 ICPCtrlRegsState *s = opaque; 499 500 /* line is released by writing to CP_INTREG */ 501 if (level) { 502 s->intreg_state |= ICP_INTREG_CARDIN; 503 qemu_set_irq(s->mmc_irq, 1); 504 } 505 } 506 507 static void icp_control_init(Object *obj) 508 { 509 SysBusDevice *sbd = SYS_BUS_DEVICE(obj); 510 ICPCtrlRegsState *s = ICP_CONTROL_REGS(obj); 511 DeviceState *dev = DEVICE(obj); 512 513 memory_region_init_io(&s->iomem, OBJECT(s), &icp_control_ops, s, 514 "icp_ctrl_regs", 0x00800000); 515 sysbus_init_mmio(sbd, &s->iomem); 516 517 qdev_init_gpio_in_named(dev, icp_control_mmc_wprot, ICP_GPIO_MMC_WPROT, 1); 518 qdev_init_gpio_in_named(dev, icp_control_mmc_cardin, 519 ICP_GPIO_MMC_CARDIN, 1); 520 sysbus_init_irq(sbd, &s->mmc_irq); 521 } 522 523 524 /* Board init. */ 525 526 static struct arm_boot_info integrator_binfo = { 527 .loader_start = 0x0, 528 .board_id = 0x113, 529 }; 530 531 static void integratorcp_init(MachineState *machine) 532 { 533 ram_addr_t ram_size = machine->ram_size; 534 const char *cpu_model = machine->cpu_model; 535 const char *kernel_filename = machine->kernel_filename; 536 const char *kernel_cmdline = machine->kernel_cmdline; 537 const char *initrd_filename = machine->initrd_filename; 538 ObjectClass *cpu_oc; 539 Object *cpuobj; 540 ARMCPU *cpu; 541 MemoryRegion *address_space_mem = get_system_memory(); 542 MemoryRegion *ram = g_new(MemoryRegion, 1); 543 MemoryRegion *ram_alias = g_new(MemoryRegion, 1); 544 qemu_irq pic[32]; 545 DeviceState *dev, *sic, *icp; 546 int i; 547 548 if (!cpu_model) { 549 cpu_model = "arm926"; 550 } 551 552 cpu_oc = cpu_class_by_name(TYPE_ARM_CPU, cpu_model); 553 if (!cpu_oc) { 554 fprintf(stderr, "Unable to find CPU definition\n"); 555 exit(1); 556 } 557 558 cpuobj = object_new(object_class_get_name(cpu_oc)); 559 560 /* By default ARM1176 CPUs have EL3 enabled. This board does not 561 * currently support EL3 so the CPU EL3 property is disabled before 562 * realization. 563 */ 564 if (object_property_find(cpuobj, "has_el3", NULL)) { 565 object_property_set_bool(cpuobj, false, "has_el3", &error_fatal); 566 } 567 568 object_property_set_bool(cpuobj, true, "realized", &error_fatal); 569 570 cpu = ARM_CPU(cpuobj); 571 572 memory_region_allocate_system_memory(ram, NULL, "integrator.ram", 573 ram_size); 574 /* ??? On a real system the first 1Mb is mapped as SSRAM or boot flash. */ 575 /* ??? RAM should repeat to fill physical memory space. */ 576 /* SDRAM at address zero*/ 577 memory_region_add_subregion(address_space_mem, 0, ram); 578 /* And again at address 0x80000000 */ 579 memory_region_init_alias(ram_alias, NULL, "ram.alias", ram, 0, ram_size); 580 memory_region_add_subregion(address_space_mem, 0x80000000, ram_alias); 581 582 dev = qdev_create(NULL, TYPE_INTEGRATOR_CM); 583 qdev_prop_set_uint32(dev, "memsz", ram_size >> 20); 584 qdev_init_nofail(dev); 585 sysbus_mmio_map((SysBusDevice *)dev, 0, 0x10000000); 586 587 dev = sysbus_create_varargs(TYPE_INTEGRATOR_PIC, 0x14000000, 588 qdev_get_gpio_in(DEVICE(cpu), ARM_CPU_IRQ), 589 qdev_get_gpio_in(DEVICE(cpu), ARM_CPU_FIQ), 590 NULL); 591 for (i = 0; i < 32; i++) { 592 pic[i] = qdev_get_gpio_in(dev, i); 593 } 594 sic = sysbus_create_simple(TYPE_INTEGRATOR_PIC, 0xca000000, pic[26]); 595 sysbus_create_varargs("integrator_pit", 0x13000000, 596 pic[5], pic[6], pic[7], NULL); 597 sysbus_create_simple("pl031", 0x15000000, pic[8]); 598 pl011_create(0x16000000, pic[1], serial_hds[0]); 599 pl011_create(0x17000000, pic[2], serial_hds[1]); 600 icp = sysbus_create_simple(TYPE_ICP_CONTROL_REGS, 0xcb000000, 601 qdev_get_gpio_in(sic, 3)); 602 sysbus_create_simple("pl050_keyboard", 0x18000000, pic[3]); 603 sysbus_create_simple("pl050_mouse", 0x19000000, pic[4]); 604 sysbus_create_simple(TYPE_INTEGRATOR_DEBUG, 0x1a000000, 0); 605 606 dev = sysbus_create_varargs("pl181", 0x1c000000, pic[23], pic[24], NULL); 607 qdev_connect_gpio_out(dev, 0, 608 qdev_get_gpio_in_named(icp, ICP_GPIO_MMC_WPROT, 0)); 609 qdev_connect_gpio_out(dev, 1, 610 qdev_get_gpio_in_named(icp, ICP_GPIO_MMC_CARDIN, 0)); 611 612 if (nd_table[0].used) 613 smc91c111_init(&nd_table[0], 0xc8000000, pic[27]); 614 615 sysbus_create_simple("pl110", 0xc0000000, pic[22]); 616 617 integrator_binfo.ram_size = ram_size; 618 integrator_binfo.kernel_filename = kernel_filename; 619 integrator_binfo.kernel_cmdline = kernel_cmdline; 620 integrator_binfo.initrd_filename = initrd_filename; 621 arm_load_kernel(cpu, &integrator_binfo); 622 } 623 624 static void integratorcp_machine_init(MachineClass *mc) 625 { 626 mc->desc = "ARM Integrator/CP (ARM926EJ-S)"; 627 mc->init = integratorcp_init; 628 } 629 630 DEFINE_MACHINE("integratorcp", integratorcp_machine_init) 631 632 static Property core_properties[] = { 633 DEFINE_PROP_UINT32("memsz", IntegratorCMState, memsz, 0), 634 DEFINE_PROP_END_OF_LIST(), 635 }; 636 637 static void core_class_init(ObjectClass *klass, void *data) 638 { 639 DeviceClass *dc = DEVICE_CLASS(klass); 640 641 dc->props = core_properties; 642 dc->realize = integratorcm_realize; 643 } 644 645 static const TypeInfo core_info = { 646 .name = TYPE_INTEGRATOR_CM, 647 .parent = TYPE_SYS_BUS_DEVICE, 648 .instance_size = sizeof(IntegratorCMState), 649 .instance_init = integratorcm_init, 650 .class_init = core_class_init, 651 }; 652 653 static const TypeInfo icp_pic_info = { 654 .name = TYPE_INTEGRATOR_PIC, 655 .parent = TYPE_SYS_BUS_DEVICE, 656 .instance_size = sizeof(icp_pic_state), 657 .instance_init = icp_pic_init, 658 }; 659 660 static const TypeInfo icp_ctrl_regs_info = { 661 .name = TYPE_ICP_CONTROL_REGS, 662 .parent = TYPE_SYS_BUS_DEVICE, 663 .instance_size = sizeof(ICPCtrlRegsState), 664 .instance_init = icp_control_init, 665 }; 666 667 static void integratorcp_register_types(void) 668 { 669 type_register_static(&icp_pic_info); 670 type_register_static(&core_info); 671 type_register_static(&icp_ctrl_regs_info); 672 } 673 674 type_init(integratorcp_register_types) 675