1 /* 2 * Marvell MV88W8618 / Freecom MusicPal emulation. 3 * 4 * Copyright (c) 2008 Jan Kiszka 5 * 6 * This code is licensed under the GNU GPL v2. 7 * 8 * Contributions after 2012-01-13 are licensed under the terms of the 9 * GNU GPL, version 2 or (at your option) any later version. 10 */ 11 12 #include "qemu/osdep.h" 13 #include "hw/sysbus.h" 14 #include "hw/arm/arm.h" 15 #include "hw/devices.h" 16 #include "net/net.h" 17 #include "sysemu/sysemu.h" 18 #include "hw/boards.h" 19 #include "hw/char/serial.h" 20 #include "qemu/timer.h" 21 #include "hw/ptimer.h" 22 #include "hw/block/flash.h" 23 #include "ui/console.h" 24 #include "hw/i2c/i2c.h" 25 #include "sysemu/block-backend.h" 26 #include "exec/address-spaces.h" 27 #include "ui/pixel_ops.h" 28 29 #define MP_MISC_BASE 0x80002000 30 #define MP_MISC_SIZE 0x00001000 31 32 #define MP_ETH_BASE 0x80008000 33 #define MP_ETH_SIZE 0x00001000 34 35 #define MP_WLAN_BASE 0x8000C000 36 #define MP_WLAN_SIZE 0x00000800 37 38 #define MP_UART1_BASE 0x8000C840 39 #define MP_UART2_BASE 0x8000C940 40 41 #define MP_GPIO_BASE 0x8000D000 42 #define MP_GPIO_SIZE 0x00001000 43 44 #define MP_FLASHCFG_BASE 0x90006000 45 #define MP_FLASHCFG_SIZE 0x00001000 46 47 #define MP_AUDIO_BASE 0x90007000 48 49 #define MP_PIC_BASE 0x90008000 50 #define MP_PIC_SIZE 0x00001000 51 52 #define MP_PIT_BASE 0x90009000 53 #define MP_PIT_SIZE 0x00001000 54 55 #define MP_LCD_BASE 0x9000c000 56 #define MP_LCD_SIZE 0x00001000 57 58 #define MP_SRAM_BASE 0xC0000000 59 #define MP_SRAM_SIZE 0x00020000 60 61 #define MP_RAM_DEFAULT_SIZE 32*1024*1024 62 #define MP_FLASH_SIZE_MAX 32*1024*1024 63 64 #define MP_TIMER1_IRQ 4 65 #define MP_TIMER2_IRQ 5 66 #define MP_TIMER3_IRQ 6 67 #define MP_TIMER4_IRQ 7 68 #define MP_EHCI_IRQ 8 69 #define MP_ETH_IRQ 9 70 #define MP_UART1_IRQ 11 71 #define MP_UART2_IRQ 11 72 #define MP_GPIO_IRQ 12 73 #define MP_RTC_IRQ 28 74 #define MP_AUDIO_IRQ 30 75 76 /* Wolfson 8750 I2C address */ 77 #define MP_WM_ADDR 0x1A 78 79 /* Ethernet register offsets */ 80 #define MP_ETH_SMIR 0x010 81 #define MP_ETH_PCXR 0x408 82 #define MP_ETH_SDCMR 0x448 83 #define MP_ETH_ICR 0x450 84 #define MP_ETH_IMR 0x458 85 #define MP_ETH_FRDP0 0x480 86 #define MP_ETH_FRDP1 0x484 87 #define MP_ETH_FRDP2 0x488 88 #define MP_ETH_FRDP3 0x48C 89 #define MP_ETH_CRDP0 0x4A0 90 #define MP_ETH_CRDP1 0x4A4 91 #define MP_ETH_CRDP2 0x4A8 92 #define MP_ETH_CRDP3 0x4AC 93 #define MP_ETH_CTDP0 0x4E0 94 #define MP_ETH_CTDP1 0x4E4 95 96 /* MII PHY access */ 97 #define MP_ETH_SMIR_DATA 0x0000FFFF 98 #define MP_ETH_SMIR_ADDR 0x03FF0000 99 #define MP_ETH_SMIR_OPCODE (1 << 26) /* Read value */ 100 #define MP_ETH_SMIR_RDVALID (1 << 27) 101 102 /* PHY registers */ 103 #define MP_ETH_PHY1_BMSR 0x00210000 104 #define MP_ETH_PHY1_PHYSID1 0x00410000 105 #define MP_ETH_PHY1_PHYSID2 0x00610000 106 107 #define MP_PHY_BMSR_LINK 0x0004 108 #define MP_PHY_BMSR_AUTONEG 0x0008 109 110 #define MP_PHY_88E3015 0x01410E20 111 112 /* TX descriptor status */ 113 #define MP_ETH_TX_OWN (1U << 31) 114 115 /* RX descriptor status */ 116 #define MP_ETH_RX_OWN (1U << 31) 117 118 /* Interrupt cause/mask bits */ 119 #define MP_ETH_IRQ_RX_BIT 0 120 #define MP_ETH_IRQ_RX (1 << MP_ETH_IRQ_RX_BIT) 121 #define MP_ETH_IRQ_TXHI_BIT 2 122 #define MP_ETH_IRQ_TXLO_BIT 3 123 124 /* Port config bits */ 125 #define MP_ETH_PCXR_2BSM_BIT 28 /* 2-byte incoming suffix */ 126 127 /* SDMA command bits */ 128 #define MP_ETH_CMD_TXHI (1 << 23) 129 #define MP_ETH_CMD_TXLO (1 << 22) 130 131 typedef struct mv88w8618_tx_desc { 132 uint32_t cmdstat; 133 uint16_t res; 134 uint16_t bytes; 135 uint32_t buffer; 136 uint32_t next; 137 } mv88w8618_tx_desc; 138 139 typedef struct mv88w8618_rx_desc { 140 uint32_t cmdstat; 141 uint16_t bytes; 142 uint16_t buffer_size; 143 uint32_t buffer; 144 uint32_t next; 145 } mv88w8618_rx_desc; 146 147 #define TYPE_MV88W8618_ETH "mv88w8618_eth" 148 #define MV88W8618_ETH(obj) \ 149 OBJECT_CHECK(mv88w8618_eth_state, (obj), TYPE_MV88W8618_ETH) 150 151 typedef struct mv88w8618_eth_state { 152 /*< private >*/ 153 SysBusDevice parent_obj; 154 /*< public >*/ 155 156 MemoryRegion iomem; 157 qemu_irq irq; 158 uint32_t smir; 159 uint32_t icr; 160 uint32_t imr; 161 int mmio_index; 162 uint32_t vlan_header; 163 uint32_t tx_queue[2]; 164 uint32_t rx_queue[4]; 165 uint32_t frx_queue[4]; 166 uint32_t cur_rx[4]; 167 NICState *nic; 168 NICConf conf; 169 } mv88w8618_eth_state; 170 171 static void eth_rx_desc_put(uint32_t addr, mv88w8618_rx_desc *desc) 172 { 173 cpu_to_le32s(&desc->cmdstat); 174 cpu_to_le16s(&desc->bytes); 175 cpu_to_le16s(&desc->buffer_size); 176 cpu_to_le32s(&desc->buffer); 177 cpu_to_le32s(&desc->next); 178 cpu_physical_memory_write(addr, desc, sizeof(*desc)); 179 } 180 181 static void eth_rx_desc_get(uint32_t addr, mv88w8618_rx_desc *desc) 182 { 183 cpu_physical_memory_read(addr, desc, sizeof(*desc)); 184 le32_to_cpus(&desc->cmdstat); 185 le16_to_cpus(&desc->bytes); 186 le16_to_cpus(&desc->buffer_size); 187 le32_to_cpus(&desc->buffer); 188 le32_to_cpus(&desc->next); 189 } 190 191 static ssize_t eth_receive(NetClientState *nc, const uint8_t *buf, size_t size) 192 { 193 mv88w8618_eth_state *s = qemu_get_nic_opaque(nc); 194 uint32_t desc_addr; 195 mv88w8618_rx_desc desc; 196 int i; 197 198 for (i = 0; i < 4; i++) { 199 desc_addr = s->cur_rx[i]; 200 if (!desc_addr) { 201 continue; 202 } 203 do { 204 eth_rx_desc_get(desc_addr, &desc); 205 if ((desc.cmdstat & MP_ETH_RX_OWN) && desc.buffer_size >= size) { 206 cpu_physical_memory_write(desc.buffer + s->vlan_header, 207 buf, size); 208 desc.bytes = size + s->vlan_header; 209 desc.cmdstat &= ~MP_ETH_RX_OWN; 210 s->cur_rx[i] = desc.next; 211 212 s->icr |= MP_ETH_IRQ_RX; 213 if (s->icr & s->imr) { 214 qemu_irq_raise(s->irq); 215 } 216 eth_rx_desc_put(desc_addr, &desc); 217 return size; 218 } 219 desc_addr = desc.next; 220 } while (desc_addr != s->rx_queue[i]); 221 } 222 return size; 223 } 224 225 static void eth_tx_desc_put(uint32_t addr, mv88w8618_tx_desc *desc) 226 { 227 cpu_to_le32s(&desc->cmdstat); 228 cpu_to_le16s(&desc->res); 229 cpu_to_le16s(&desc->bytes); 230 cpu_to_le32s(&desc->buffer); 231 cpu_to_le32s(&desc->next); 232 cpu_physical_memory_write(addr, desc, sizeof(*desc)); 233 } 234 235 static void eth_tx_desc_get(uint32_t addr, mv88w8618_tx_desc *desc) 236 { 237 cpu_physical_memory_read(addr, desc, sizeof(*desc)); 238 le32_to_cpus(&desc->cmdstat); 239 le16_to_cpus(&desc->res); 240 le16_to_cpus(&desc->bytes); 241 le32_to_cpus(&desc->buffer); 242 le32_to_cpus(&desc->next); 243 } 244 245 static void eth_send(mv88w8618_eth_state *s, int queue_index) 246 { 247 uint32_t desc_addr = s->tx_queue[queue_index]; 248 mv88w8618_tx_desc desc; 249 uint32_t next_desc; 250 uint8_t buf[2048]; 251 int len; 252 253 do { 254 eth_tx_desc_get(desc_addr, &desc); 255 next_desc = desc.next; 256 if (desc.cmdstat & MP_ETH_TX_OWN) { 257 len = desc.bytes; 258 if (len < 2048) { 259 cpu_physical_memory_read(desc.buffer, buf, len); 260 qemu_send_packet(qemu_get_queue(s->nic), buf, len); 261 } 262 desc.cmdstat &= ~MP_ETH_TX_OWN; 263 s->icr |= 1 << (MP_ETH_IRQ_TXLO_BIT - queue_index); 264 eth_tx_desc_put(desc_addr, &desc); 265 } 266 desc_addr = next_desc; 267 } while (desc_addr != s->tx_queue[queue_index]); 268 } 269 270 static uint64_t mv88w8618_eth_read(void *opaque, hwaddr offset, 271 unsigned size) 272 { 273 mv88w8618_eth_state *s = opaque; 274 275 switch (offset) { 276 case MP_ETH_SMIR: 277 if (s->smir & MP_ETH_SMIR_OPCODE) { 278 switch (s->smir & MP_ETH_SMIR_ADDR) { 279 case MP_ETH_PHY1_BMSR: 280 return MP_PHY_BMSR_LINK | MP_PHY_BMSR_AUTONEG | 281 MP_ETH_SMIR_RDVALID; 282 case MP_ETH_PHY1_PHYSID1: 283 return (MP_PHY_88E3015 >> 16) | MP_ETH_SMIR_RDVALID; 284 case MP_ETH_PHY1_PHYSID2: 285 return (MP_PHY_88E3015 & 0xFFFF) | MP_ETH_SMIR_RDVALID; 286 default: 287 return MP_ETH_SMIR_RDVALID; 288 } 289 } 290 return 0; 291 292 case MP_ETH_ICR: 293 return s->icr; 294 295 case MP_ETH_IMR: 296 return s->imr; 297 298 case MP_ETH_FRDP0 ... MP_ETH_FRDP3: 299 return s->frx_queue[(offset - MP_ETH_FRDP0)/4]; 300 301 case MP_ETH_CRDP0 ... MP_ETH_CRDP3: 302 return s->rx_queue[(offset - MP_ETH_CRDP0)/4]; 303 304 case MP_ETH_CTDP0 ... MP_ETH_CTDP1: 305 return s->tx_queue[(offset - MP_ETH_CTDP0)/4]; 306 307 default: 308 return 0; 309 } 310 } 311 312 static void mv88w8618_eth_write(void *opaque, hwaddr offset, 313 uint64_t value, unsigned size) 314 { 315 mv88w8618_eth_state *s = opaque; 316 317 switch (offset) { 318 case MP_ETH_SMIR: 319 s->smir = value; 320 break; 321 322 case MP_ETH_PCXR: 323 s->vlan_header = ((value >> MP_ETH_PCXR_2BSM_BIT) & 1) * 2; 324 break; 325 326 case MP_ETH_SDCMR: 327 if (value & MP_ETH_CMD_TXHI) { 328 eth_send(s, 1); 329 } 330 if (value & MP_ETH_CMD_TXLO) { 331 eth_send(s, 0); 332 } 333 if (value & (MP_ETH_CMD_TXHI | MP_ETH_CMD_TXLO) && s->icr & s->imr) { 334 qemu_irq_raise(s->irq); 335 } 336 break; 337 338 case MP_ETH_ICR: 339 s->icr &= value; 340 break; 341 342 case MP_ETH_IMR: 343 s->imr = value; 344 if (s->icr & s->imr) { 345 qemu_irq_raise(s->irq); 346 } 347 break; 348 349 case MP_ETH_FRDP0 ... MP_ETH_FRDP3: 350 s->frx_queue[(offset - MP_ETH_FRDP0)/4] = value; 351 break; 352 353 case MP_ETH_CRDP0 ... MP_ETH_CRDP3: 354 s->rx_queue[(offset - MP_ETH_CRDP0)/4] = 355 s->cur_rx[(offset - MP_ETH_CRDP0)/4] = value; 356 break; 357 358 case MP_ETH_CTDP0 ... MP_ETH_CTDP1: 359 s->tx_queue[(offset - MP_ETH_CTDP0)/4] = value; 360 break; 361 } 362 } 363 364 static const MemoryRegionOps mv88w8618_eth_ops = { 365 .read = mv88w8618_eth_read, 366 .write = mv88w8618_eth_write, 367 .endianness = DEVICE_NATIVE_ENDIAN, 368 }; 369 370 static void eth_cleanup(NetClientState *nc) 371 { 372 mv88w8618_eth_state *s = qemu_get_nic_opaque(nc); 373 374 s->nic = NULL; 375 } 376 377 static NetClientInfo net_mv88w8618_info = { 378 .type = NET_CLIENT_OPTIONS_KIND_NIC, 379 .size = sizeof(NICState), 380 .receive = eth_receive, 381 .cleanup = eth_cleanup, 382 }; 383 384 static int mv88w8618_eth_init(SysBusDevice *sbd) 385 { 386 DeviceState *dev = DEVICE(sbd); 387 mv88w8618_eth_state *s = MV88W8618_ETH(dev); 388 389 sysbus_init_irq(sbd, &s->irq); 390 s->nic = qemu_new_nic(&net_mv88w8618_info, &s->conf, 391 object_get_typename(OBJECT(dev)), dev->id, s); 392 memory_region_init_io(&s->iomem, OBJECT(s), &mv88w8618_eth_ops, s, 393 "mv88w8618-eth", MP_ETH_SIZE); 394 sysbus_init_mmio(sbd, &s->iomem); 395 return 0; 396 } 397 398 static const VMStateDescription mv88w8618_eth_vmsd = { 399 .name = "mv88w8618_eth", 400 .version_id = 1, 401 .minimum_version_id = 1, 402 .fields = (VMStateField[]) { 403 VMSTATE_UINT32(smir, mv88w8618_eth_state), 404 VMSTATE_UINT32(icr, mv88w8618_eth_state), 405 VMSTATE_UINT32(imr, mv88w8618_eth_state), 406 VMSTATE_UINT32(vlan_header, mv88w8618_eth_state), 407 VMSTATE_UINT32_ARRAY(tx_queue, mv88w8618_eth_state, 2), 408 VMSTATE_UINT32_ARRAY(rx_queue, mv88w8618_eth_state, 4), 409 VMSTATE_UINT32_ARRAY(frx_queue, mv88w8618_eth_state, 4), 410 VMSTATE_UINT32_ARRAY(cur_rx, mv88w8618_eth_state, 4), 411 VMSTATE_END_OF_LIST() 412 } 413 }; 414 415 static Property mv88w8618_eth_properties[] = { 416 DEFINE_NIC_PROPERTIES(mv88w8618_eth_state, conf), 417 DEFINE_PROP_END_OF_LIST(), 418 }; 419 420 static void mv88w8618_eth_class_init(ObjectClass *klass, void *data) 421 { 422 DeviceClass *dc = DEVICE_CLASS(klass); 423 SysBusDeviceClass *k = SYS_BUS_DEVICE_CLASS(klass); 424 425 k->init = mv88w8618_eth_init; 426 dc->vmsd = &mv88w8618_eth_vmsd; 427 dc->props = mv88w8618_eth_properties; 428 } 429 430 static const TypeInfo mv88w8618_eth_info = { 431 .name = TYPE_MV88W8618_ETH, 432 .parent = TYPE_SYS_BUS_DEVICE, 433 .instance_size = sizeof(mv88w8618_eth_state), 434 .class_init = mv88w8618_eth_class_init, 435 }; 436 437 /* LCD register offsets */ 438 #define MP_LCD_IRQCTRL 0x180 439 #define MP_LCD_IRQSTAT 0x184 440 #define MP_LCD_SPICTRL 0x1ac 441 #define MP_LCD_INST 0x1bc 442 #define MP_LCD_DATA 0x1c0 443 444 /* Mode magics */ 445 #define MP_LCD_SPI_DATA 0x00100011 446 #define MP_LCD_SPI_CMD 0x00104011 447 #define MP_LCD_SPI_INVALID 0x00000000 448 449 /* Commmands */ 450 #define MP_LCD_INST_SETPAGE0 0xB0 451 /* ... */ 452 #define MP_LCD_INST_SETPAGE7 0xB7 453 454 #define MP_LCD_TEXTCOLOR 0xe0e0ff /* RRGGBB */ 455 456 #define TYPE_MUSICPAL_LCD "musicpal_lcd" 457 #define MUSICPAL_LCD(obj) \ 458 OBJECT_CHECK(musicpal_lcd_state, (obj), TYPE_MUSICPAL_LCD) 459 460 typedef struct musicpal_lcd_state { 461 /*< private >*/ 462 SysBusDevice parent_obj; 463 /*< public >*/ 464 465 MemoryRegion iomem; 466 uint32_t brightness; 467 uint32_t mode; 468 uint32_t irqctrl; 469 uint32_t page; 470 uint32_t page_off; 471 QemuConsole *con; 472 uint8_t video_ram[128*64/8]; 473 } musicpal_lcd_state; 474 475 static uint8_t scale_lcd_color(musicpal_lcd_state *s, uint8_t col) 476 { 477 switch (s->brightness) { 478 case 7: 479 return col; 480 case 0: 481 return 0; 482 default: 483 return (col * s->brightness) / 7; 484 } 485 } 486 487 #define SET_LCD_PIXEL(depth, type) \ 488 static inline void glue(set_lcd_pixel, depth) \ 489 (musicpal_lcd_state *s, int x, int y, type col) \ 490 { \ 491 int dx, dy; \ 492 DisplaySurface *surface = qemu_console_surface(s->con); \ 493 type *pixel = &((type *) surface_data(surface))[(y * 128 * 3 + x) * 3]; \ 494 \ 495 for (dy = 0; dy < 3; dy++, pixel += 127 * 3) \ 496 for (dx = 0; dx < 3; dx++, pixel++) \ 497 *pixel = col; \ 498 } 499 SET_LCD_PIXEL(8, uint8_t) 500 SET_LCD_PIXEL(16, uint16_t) 501 SET_LCD_PIXEL(32, uint32_t) 502 503 static void lcd_refresh(void *opaque) 504 { 505 musicpal_lcd_state *s = opaque; 506 DisplaySurface *surface = qemu_console_surface(s->con); 507 int x, y, col; 508 509 switch (surface_bits_per_pixel(surface)) { 510 case 0: 511 return; 512 #define LCD_REFRESH(depth, func) \ 513 case depth: \ 514 col = func(scale_lcd_color(s, (MP_LCD_TEXTCOLOR >> 16) & 0xff), \ 515 scale_lcd_color(s, (MP_LCD_TEXTCOLOR >> 8) & 0xff), \ 516 scale_lcd_color(s, MP_LCD_TEXTCOLOR & 0xff)); \ 517 for (x = 0; x < 128; x++) { \ 518 for (y = 0; y < 64; y++) { \ 519 if (s->video_ram[x + (y/8)*128] & (1 << (y % 8))) { \ 520 glue(set_lcd_pixel, depth)(s, x, y, col); \ 521 } else { \ 522 glue(set_lcd_pixel, depth)(s, x, y, 0); \ 523 } \ 524 } \ 525 } \ 526 break; 527 LCD_REFRESH(8, rgb_to_pixel8) 528 LCD_REFRESH(16, rgb_to_pixel16) 529 LCD_REFRESH(32, (is_surface_bgr(surface) ? 530 rgb_to_pixel32bgr : rgb_to_pixel32)) 531 default: 532 hw_error("unsupported colour depth %i\n", 533 surface_bits_per_pixel(surface)); 534 } 535 536 dpy_gfx_update(s->con, 0, 0, 128*3, 64*3); 537 } 538 539 static void lcd_invalidate(void *opaque) 540 { 541 } 542 543 static void musicpal_lcd_gpio_brightness_in(void *opaque, int irq, int level) 544 { 545 musicpal_lcd_state *s = opaque; 546 s->brightness &= ~(1 << irq); 547 s->brightness |= level << irq; 548 } 549 550 static uint64_t musicpal_lcd_read(void *opaque, hwaddr offset, 551 unsigned size) 552 { 553 musicpal_lcd_state *s = opaque; 554 555 switch (offset) { 556 case MP_LCD_IRQCTRL: 557 return s->irqctrl; 558 559 default: 560 return 0; 561 } 562 } 563 564 static void musicpal_lcd_write(void *opaque, hwaddr offset, 565 uint64_t value, unsigned size) 566 { 567 musicpal_lcd_state *s = opaque; 568 569 switch (offset) { 570 case MP_LCD_IRQCTRL: 571 s->irqctrl = value; 572 break; 573 574 case MP_LCD_SPICTRL: 575 if (value == MP_LCD_SPI_DATA || value == MP_LCD_SPI_CMD) { 576 s->mode = value; 577 } else { 578 s->mode = MP_LCD_SPI_INVALID; 579 } 580 break; 581 582 case MP_LCD_INST: 583 if (value >= MP_LCD_INST_SETPAGE0 && value <= MP_LCD_INST_SETPAGE7) { 584 s->page = value - MP_LCD_INST_SETPAGE0; 585 s->page_off = 0; 586 } 587 break; 588 589 case MP_LCD_DATA: 590 if (s->mode == MP_LCD_SPI_CMD) { 591 if (value >= MP_LCD_INST_SETPAGE0 && 592 value <= MP_LCD_INST_SETPAGE7) { 593 s->page = value - MP_LCD_INST_SETPAGE0; 594 s->page_off = 0; 595 } 596 } else if (s->mode == MP_LCD_SPI_DATA) { 597 s->video_ram[s->page*128 + s->page_off] = value; 598 s->page_off = (s->page_off + 1) & 127; 599 } 600 break; 601 } 602 } 603 604 static const MemoryRegionOps musicpal_lcd_ops = { 605 .read = musicpal_lcd_read, 606 .write = musicpal_lcd_write, 607 .endianness = DEVICE_NATIVE_ENDIAN, 608 }; 609 610 static const GraphicHwOps musicpal_gfx_ops = { 611 .invalidate = lcd_invalidate, 612 .gfx_update = lcd_refresh, 613 }; 614 615 static int musicpal_lcd_init(SysBusDevice *sbd) 616 { 617 DeviceState *dev = DEVICE(sbd); 618 musicpal_lcd_state *s = MUSICPAL_LCD(dev); 619 620 s->brightness = 7; 621 622 memory_region_init_io(&s->iomem, OBJECT(s), &musicpal_lcd_ops, s, 623 "musicpal-lcd", MP_LCD_SIZE); 624 sysbus_init_mmio(sbd, &s->iomem); 625 626 s->con = graphic_console_init(dev, 0, &musicpal_gfx_ops, s); 627 qemu_console_resize(s->con, 128*3, 64*3); 628 629 qdev_init_gpio_in(dev, musicpal_lcd_gpio_brightness_in, 3); 630 631 return 0; 632 } 633 634 static const VMStateDescription musicpal_lcd_vmsd = { 635 .name = "musicpal_lcd", 636 .version_id = 1, 637 .minimum_version_id = 1, 638 .fields = (VMStateField[]) { 639 VMSTATE_UINT32(brightness, musicpal_lcd_state), 640 VMSTATE_UINT32(mode, musicpal_lcd_state), 641 VMSTATE_UINT32(irqctrl, musicpal_lcd_state), 642 VMSTATE_UINT32(page, musicpal_lcd_state), 643 VMSTATE_UINT32(page_off, musicpal_lcd_state), 644 VMSTATE_BUFFER(video_ram, musicpal_lcd_state), 645 VMSTATE_END_OF_LIST() 646 } 647 }; 648 649 static void musicpal_lcd_class_init(ObjectClass *klass, void *data) 650 { 651 DeviceClass *dc = DEVICE_CLASS(klass); 652 SysBusDeviceClass *k = SYS_BUS_DEVICE_CLASS(klass); 653 654 k->init = musicpal_lcd_init; 655 dc->vmsd = &musicpal_lcd_vmsd; 656 } 657 658 static const TypeInfo musicpal_lcd_info = { 659 .name = TYPE_MUSICPAL_LCD, 660 .parent = TYPE_SYS_BUS_DEVICE, 661 .instance_size = sizeof(musicpal_lcd_state), 662 .class_init = musicpal_lcd_class_init, 663 }; 664 665 /* PIC register offsets */ 666 #define MP_PIC_STATUS 0x00 667 #define MP_PIC_ENABLE_SET 0x08 668 #define MP_PIC_ENABLE_CLR 0x0C 669 670 #define TYPE_MV88W8618_PIC "mv88w8618_pic" 671 #define MV88W8618_PIC(obj) \ 672 OBJECT_CHECK(mv88w8618_pic_state, (obj), TYPE_MV88W8618_PIC) 673 674 typedef struct mv88w8618_pic_state { 675 /*< private >*/ 676 SysBusDevice parent_obj; 677 /*< public >*/ 678 679 MemoryRegion iomem; 680 uint32_t level; 681 uint32_t enabled; 682 qemu_irq parent_irq; 683 } mv88w8618_pic_state; 684 685 static void mv88w8618_pic_update(mv88w8618_pic_state *s) 686 { 687 qemu_set_irq(s->parent_irq, (s->level & s->enabled)); 688 } 689 690 static void mv88w8618_pic_set_irq(void *opaque, int irq, int level) 691 { 692 mv88w8618_pic_state *s = opaque; 693 694 if (level) { 695 s->level |= 1 << irq; 696 } else { 697 s->level &= ~(1 << irq); 698 } 699 mv88w8618_pic_update(s); 700 } 701 702 static uint64_t mv88w8618_pic_read(void *opaque, hwaddr offset, 703 unsigned size) 704 { 705 mv88w8618_pic_state *s = opaque; 706 707 switch (offset) { 708 case MP_PIC_STATUS: 709 return s->level & s->enabled; 710 711 default: 712 return 0; 713 } 714 } 715 716 static void mv88w8618_pic_write(void *opaque, hwaddr offset, 717 uint64_t value, unsigned size) 718 { 719 mv88w8618_pic_state *s = opaque; 720 721 switch (offset) { 722 case MP_PIC_ENABLE_SET: 723 s->enabled |= value; 724 break; 725 726 case MP_PIC_ENABLE_CLR: 727 s->enabled &= ~value; 728 s->level &= ~value; 729 break; 730 } 731 mv88w8618_pic_update(s); 732 } 733 734 static void mv88w8618_pic_reset(DeviceState *d) 735 { 736 mv88w8618_pic_state *s = MV88W8618_PIC(d); 737 738 s->level = 0; 739 s->enabled = 0; 740 } 741 742 static const MemoryRegionOps mv88w8618_pic_ops = { 743 .read = mv88w8618_pic_read, 744 .write = mv88w8618_pic_write, 745 .endianness = DEVICE_NATIVE_ENDIAN, 746 }; 747 748 static int mv88w8618_pic_init(SysBusDevice *dev) 749 { 750 mv88w8618_pic_state *s = MV88W8618_PIC(dev); 751 752 qdev_init_gpio_in(DEVICE(dev), mv88w8618_pic_set_irq, 32); 753 sysbus_init_irq(dev, &s->parent_irq); 754 memory_region_init_io(&s->iomem, OBJECT(s), &mv88w8618_pic_ops, s, 755 "musicpal-pic", MP_PIC_SIZE); 756 sysbus_init_mmio(dev, &s->iomem); 757 return 0; 758 } 759 760 static const VMStateDescription mv88w8618_pic_vmsd = { 761 .name = "mv88w8618_pic", 762 .version_id = 1, 763 .minimum_version_id = 1, 764 .fields = (VMStateField[]) { 765 VMSTATE_UINT32(level, mv88w8618_pic_state), 766 VMSTATE_UINT32(enabled, mv88w8618_pic_state), 767 VMSTATE_END_OF_LIST() 768 } 769 }; 770 771 static void mv88w8618_pic_class_init(ObjectClass *klass, void *data) 772 { 773 DeviceClass *dc = DEVICE_CLASS(klass); 774 SysBusDeviceClass *k = SYS_BUS_DEVICE_CLASS(klass); 775 776 k->init = mv88w8618_pic_init; 777 dc->reset = mv88w8618_pic_reset; 778 dc->vmsd = &mv88w8618_pic_vmsd; 779 } 780 781 static const TypeInfo mv88w8618_pic_info = { 782 .name = TYPE_MV88W8618_PIC, 783 .parent = TYPE_SYS_BUS_DEVICE, 784 .instance_size = sizeof(mv88w8618_pic_state), 785 .class_init = mv88w8618_pic_class_init, 786 }; 787 788 /* PIT register offsets */ 789 #define MP_PIT_TIMER1_LENGTH 0x00 790 /* ... */ 791 #define MP_PIT_TIMER4_LENGTH 0x0C 792 #define MP_PIT_CONTROL 0x10 793 #define MP_PIT_TIMER1_VALUE 0x14 794 /* ... */ 795 #define MP_PIT_TIMER4_VALUE 0x20 796 #define MP_BOARD_RESET 0x34 797 798 /* Magic board reset value (probably some watchdog behind it) */ 799 #define MP_BOARD_RESET_MAGIC 0x10000 800 801 typedef struct mv88w8618_timer_state { 802 ptimer_state *ptimer; 803 uint32_t limit; 804 int freq; 805 qemu_irq irq; 806 } mv88w8618_timer_state; 807 808 #define TYPE_MV88W8618_PIT "mv88w8618_pit" 809 #define MV88W8618_PIT(obj) \ 810 OBJECT_CHECK(mv88w8618_pit_state, (obj), TYPE_MV88W8618_PIT) 811 812 typedef struct mv88w8618_pit_state { 813 /*< private >*/ 814 SysBusDevice parent_obj; 815 /*< public >*/ 816 817 MemoryRegion iomem; 818 mv88w8618_timer_state timer[4]; 819 } mv88w8618_pit_state; 820 821 static void mv88w8618_timer_tick(void *opaque) 822 { 823 mv88w8618_timer_state *s = opaque; 824 825 qemu_irq_raise(s->irq); 826 } 827 828 static void mv88w8618_timer_init(SysBusDevice *dev, mv88w8618_timer_state *s, 829 uint32_t freq) 830 { 831 QEMUBH *bh; 832 833 sysbus_init_irq(dev, &s->irq); 834 s->freq = freq; 835 836 bh = qemu_bh_new(mv88w8618_timer_tick, s); 837 s->ptimer = ptimer_init(bh); 838 } 839 840 static uint64_t mv88w8618_pit_read(void *opaque, hwaddr offset, 841 unsigned size) 842 { 843 mv88w8618_pit_state *s = opaque; 844 mv88w8618_timer_state *t; 845 846 switch (offset) { 847 case MP_PIT_TIMER1_VALUE ... MP_PIT_TIMER4_VALUE: 848 t = &s->timer[(offset-MP_PIT_TIMER1_VALUE) >> 2]; 849 return ptimer_get_count(t->ptimer); 850 851 default: 852 return 0; 853 } 854 } 855 856 static void mv88w8618_pit_write(void *opaque, hwaddr offset, 857 uint64_t value, unsigned size) 858 { 859 mv88w8618_pit_state *s = opaque; 860 mv88w8618_timer_state *t; 861 int i; 862 863 switch (offset) { 864 case MP_PIT_TIMER1_LENGTH ... MP_PIT_TIMER4_LENGTH: 865 t = &s->timer[offset >> 2]; 866 t->limit = value; 867 if (t->limit > 0) { 868 ptimer_set_limit(t->ptimer, t->limit, 1); 869 } else { 870 ptimer_stop(t->ptimer); 871 } 872 break; 873 874 case MP_PIT_CONTROL: 875 for (i = 0; i < 4; i++) { 876 t = &s->timer[i]; 877 if (value & 0xf && t->limit > 0) { 878 ptimer_set_limit(t->ptimer, t->limit, 0); 879 ptimer_set_freq(t->ptimer, t->freq); 880 ptimer_run(t->ptimer, 0); 881 } else { 882 ptimer_stop(t->ptimer); 883 } 884 value >>= 4; 885 } 886 break; 887 888 case MP_BOARD_RESET: 889 if (value == MP_BOARD_RESET_MAGIC) { 890 qemu_system_reset_request(); 891 } 892 break; 893 } 894 } 895 896 static void mv88w8618_pit_reset(DeviceState *d) 897 { 898 mv88w8618_pit_state *s = MV88W8618_PIT(d); 899 int i; 900 901 for (i = 0; i < 4; i++) { 902 ptimer_stop(s->timer[i].ptimer); 903 s->timer[i].limit = 0; 904 } 905 } 906 907 static const MemoryRegionOps mv88w8618_pit_ops = { 908 .read = mv88w8618_pit_read, 909 .write = mv88w8618_pit_write, 910 .endianness = DEVICE_NATIVE_ENDIAN, 911 }; 912 913 static int mv88w8618_pit_init(SysBusDevice *dev) 914 { 915 mv88w8618_pit_state *s = MV88W8618_PIT(dev); 916 int i; 917 918 /* Letting them all run at 1 MHz is likely just a pragmatic 919 * simplification. */ 920 for (i = 0; i < 4; i++) { 921 mv88w8618_timer_init(dev, &s->timer[i], 1000000); 922 } 923 924 memory_region_init_io(&s->iomem, OBJECT(s), &mv88w8618_pit_ops, s, 925 "musicpal-pit", MP_PIT_SIZE); 926 sysbus_init_mmio(dev, &s->iomem); 927 return 0; 928 } 929 930 static const VMStateDescription mv88w8618_timer_vmsd = { 931 .name = "timer", 932 .version_id = 1, 933 .minimum_version_id = 1, 934 .fields = (VMStateField[]) { 935 VMSTATE_PTIMER(ptimer, mv88w8618_timer_state), 936 VMSTATE_UINT32(limit, mv88w8618_timer_state), 937 VMSTATE_END_OF_LIST() 938 } 939 }; 940 941 static const VMStateDescription mv88w8618_pit_vmsd = { 942 .name = "mv88w8618_pit", 943 .version_id = 1, 944 .minimum_version_id = 1, 945 .fields = (VMStateField[]) { 946 VMSTATE_STRUCT_ARRAY(timer, mv88w8618_pit_state, 4, 1, 947 mv88w8618_timer_vmsd, mv88w8618_timer_state), 948 VMSTATE_END_OF_LIST() 949 } 950 }; 951 952 static void mv88w8618_pit_class_init(ObjectClass *klass, void *data) 953 { 954 DeviceClass *dc = DEVICE_CLASS(klass); 955 SysBusDeviceClass *k = SYS_BUS_DEVICE_CLASS(klass); 956 957 k->init = mv88w8618_pit_init; 958 dc->reset = mv88w8618_pit_reset; 959 dc->vmsd = &mv88w8618_pit_vmsd; 960 } 961 962 static const TypeInfo mv88w8618_pit_info = { 963 .name = TYPE_MV88W8618_PIT, 964 .parent = TYPE_SYS_BUS_DEVICE, 965 .instance_size = sizeof(mv88w8618_pit_state), 966 .class_init = mv88w8618_pit_class_init, 967 }; 968 969 /* Flash config register offsets */ 970 #define MP_FLASHCFG_CFGR0 0x04 971 972 #define TYPE_MV88W8618_FLASHCFG "mv88w8618_flashcfg" 973 #define MV88W8618_FLASHCFG(obj) \ 974 OBJECT_CHECK(mv88w8618_flashcfg_state, (obj), TYPE_MV88W8618_FLASHCFG) 975 976 typedef struct mv88w8618_flashcfg_state { 977 /*< private >*/ 978 SysBusDevice parent_obj; 979 /*< public >*/ 980 981 MemoryRegion iomem; 982 uint32_t cfgr0; 983 } mv88w8618_flashcfg_state; 984 985 static uint64_t mv88w8618_flashcfg_read(void *opaque, 986 hwaddr offset, 987 unsigned size) 988 { 989 mv88w8618_flashcfg_state *s = opaque; 990 991 switch (offset) { 992 case MP_FLASHCFG_CFGR0: 993 return s->cfgr0; 994 995 default: 996 return 0; 997 } 998 } 999 1000 static void mv88w8618_flashcfg_write(void *opaque, hwaddr offset, 1001 uint64_t value, unsigned size) 1002 { 1003 mv88w8618_flashcfg_state *s = opaque; 1004 1005 switch (offset) { 1006 case MP_FLASHCFG_CFGR0: 1007 s->cfgr0 = value; 1008 break; 1009 } 1010 } 1011 1012 static const MemoryRegionOps mv88w8618_flashcfg_ops = { 1013 .read = mv88w8618_flashcfg_read, 1014 .write = mv88w8618_flashcfg_write, 1015 .endianness = DEVICE_NATIVE_ENDIAN, 1016 }; 1017 1018 static int mv88w8618_flashcfg_init(SysBusDevice *dev) 1019 { 1020 mv88w8618_flashcfg_state *s = MV88W8618_FLASHCFG(dev); 1021 1022 s->cfgr0 = 0xfffe4285; /* Default as set by U-Boot for 8 MB flash */ 1023 memory_region_init_io(&s->iomem, OBJECT(s), &mv88w8618_flashcfg_ops, s, 1024 "musicpal-flashcfg", MP_FLASHCFG_SIZE); 1025 sysbus_init_mmio(dev, &s->iomem); 1026 return 0; 1027 } 1028 1029 static const VMStateDescription mv88w8618_flashcfg_vmsd = { 1030 .name = "mv88w8618_flashcfg", 1031 .version_id = 1, 1032 .minimum_version_id = 1, 1033 .fields = (VMStateField[]) { 1034 VMSTATE_UINT32(cfgr0, mv88w8618_flashcfg_state), 1035 VMSTATE_END_OF_LIST() 1036 } 1037 }; 1038 1039 static void mv88w8618_flashcfg_class_init(ObjectClass *klass, void *data) 1040 { 1041 DeviceClass *dc = DEVICE_CLASS(klass); 1042 SysBusDeviceClass *k = SYS_BUS_DEVICE_CLASS(klass); 1043 1044 k->init = mv88w8618_flashcfg_init; 1045 dc->vmsd = &mv88w8618_flashcfg_vmsd; 1046 } 1047 1048 static const TypeInfo mv88w8618_flashcfg_info = { 1049 .name = TYPE_MV88W8618_FLASHCFG, 1050 .parent = TYPE_SYS_BUS_DEVICE, 1051 .instance_size = sizeof(mv88w8618_flashcfg_state), 1052 .class_init = mv88w8618_flashcfg_class_init, 1053 }; 1054 1055 /* Misc register offsets */ 1056 #define MP_MISC_BOARD_REVISION 0x18 1057 1058 #define MP_BOARD_REVISION 0x31 1059 1060 typedef struct { 1061 SysBusDevice parent_obj; 1062 MemoryRegion iomem; 1063 } MusicPalMiscState; 1064 1065 #define TYPE_MUSICPAL_MISC "musicpal-misc" 1066 #define MUSICPAL_MISC(obj) \ 1067 OBJECT_CHECK(MusicPalMiscState, (obj), TYPE_MUSICPAL_MISC) 1068 1069 static uint64_t musicpal_misc_read(void *opaque, hwaddr offset, 1070 unsigned size) 1071 { 1072 switch (offset) { 1073 case MP_MISC_BOARD_REVISION: 1074 return MP_BOARD_REVISION; 1075 1076 default: 1077 return 0; 1078 } 1079 } 1080 1081 static void musicpal_misc_write(void *opaque, hwaddr offset, 1082 uint64_t value, unsigned size) 1083 { 1084 } 1085 1086 static const MemoryRegionOps musicpal_misc_ops = { 1087 .read = musicpal_misc_read, 1088 .write = musicpal_misc_write, 1089 .endianness = DEVICE_NATIVE_ENDIAN, 1090 }; 1091 1092 static void musicpal_misc_init(Object *obj) 1093 { 1094 SysBusDevice *sd = SYS_BUS_DEVICE(obj); 1095 MusicPalMiscState *s = MUSICPAL_MISC(obj); 1096 1097 memory_region_init_io(&s->iomem, OBJECT(s), &musicpal_misc_ops, NULL, 1098 "musicpal-misc", MP_MISC_SIZE); 1099 sysbus_init_mmio(sd, &s->iomem); 1100 } 1101 1102 static const TypeInfo musicpal_misc_info = { 1103 .name = TYPE_MUSICPAL_MISC, 1104 .parent = TYPE_SYS_BUS_DEVICE, 1105 .instance_init = musicpal_misc_init, 1106 .instance_size = sizeof(MusicPalMiscState), 1107 }; 1108 1109 /* WLAN register offsets */ 1110 #define MP_WLAN_MAGIC1 0x11c 1111 #define MP_WLAN_MAGIC2 0x124 1112 1113 static uint64_t mv88w8618_wlan_read(void *opaque, hwaddr offset, 1114 unsigned size) 1115 { 1116 switch (offset) { 1117 /* Workaround to allow loading the binary-only wlandrv.ko crap 1118 * from the original Freecom firmware. */ 1119 case MP_WLAN_MAGIC1: 1120 return ~3; 1121 case MP_WLAN_MAGIC2: 1122 return -1; 1123 1124 default: 1125 return 0; 1126 } 1127 } 1128 1129 static void mv88w8618_wlan_write(void *opaque, hwaddr offset, 1130 uint64_t value, unsigned size) 1131 { 1132 } 1133 1134 static const MemoryRegionOps mv88w8618_wlan_ops = { 1135 .read = mv88w8618_wlan_read, 1136 .write =mv88w8618_wlan_write, 1137 .endianness = DEVICE_NATIVE_ENDIAN, 1138 }; 1139 1140 static int mv88w8618_wlan_init(SysBusDevice *dev) 1141 { 1142 MemoryRegion *iomem = g_new(MemoryRegion, 1); 1143 1144 memory_region_init_io(iomem, OBJECT(dev), &mv88w8618_wlan_ops, NULL, 1145 "musicpal-wlan", MP_WLAN_SIZE); 1146 sysbus_init_mmio(dev, iomem); 1147 return 0; 1148 } 1149 1150 /* GPIO register offsets */ 1151 #define MP_GPIO_OE_LO 0x008 1152 #define MP_GPIO_OUT_LO 0x00c 1153 #define MP_GPIO_IN_LO 0x010 1154 #define MP_GPIO_IER_LO 0x014 1155 #define MP_GPIO_IMR_LO 0x018 1156 #define MP_GPIO_ISR_LO 0x020 1157 #define MP_GPIO_OE_HI 0x508 1158 #define MP_GPIO_OUT_HI 0x50c 1159 #define MP_GPIO_IN_HI 0x510 1160 #define MP_GPIO_IER_HI 0x514 1161 #define MP_GPIO_IMR_HI 0x518 1162 #define MP_GPIO_ISR_HI 0x520 1163 1164 /* GPIO bits & masks */ 1165 #define MP_GPIO_LCD_BRIGHTNESS 0x00070000 1166 #define MP_GPIO_I2C_DATA_BIT 29 1167 #define MP_GPIO_I2C_CLOCK_BIT 30 1168 1169 /* LCD brightness bits in GPIO_OE_HI */ 1170 #define MP_OE_LCD_BRIGHTNESS 0x0007 1171 1172 #define TYPE_MUSICPAL_GPIO "musicpal_gpio" 1173 #define MUSICPAL_GPIO(obj) \ 1174 OBJECT_CHECK(musicpal_gpio_state, (obj), TYPE_MUSICPAL_GPIO) 1175 1176 typedef struct musicpal_gpio_state { 1177 /*< private >*/ 1178 SysBusDevice parent_obj; 1179 /*< public >*/ 1180 1181 MemoryRegion iomem; 1182 uint32_t lcd_brightness; 1183 uint32_t out_state; 1184 uint32_t in_state; 1185 uint32_t ier; 1186 uint32_t imr; 1187 uint32_t isr; 1188 qemu_irq irq; 1189 qemu_irq out[5]; /* 3 brightness out + 2 lcd (data and clock ) */ 1190 } musicpal_gpio_state; 1191 1192 static void musicpal_gpio_brightness_update(musicpal_gpio_state *s) { 1193 int i; 1194 uint32_t brightness; 1195 1196 /* compute brightness ratio */ 1197 switch (s->lcd_brightness) { 1198 case 0x00000007: 1199 brightness = 0; 1200 break; 1201 1202 case 0x00020000: 1203 brightness = 1; 1204 break; 1205 1206 case 0x00020001: 1207 brightness = 2; 1208 break; 1209 1210 case 0x00040000: 1211 brightness = 3; 1212 break; 1213 1214 case 0x00010006: 1215 brightness = 4; 1216 break; 1217 1218 case 0x00020005: 1219 brightness = 5; 1220 break; 1221 1222 case 0x00040003: 1223 brightness = 6; 1224 break; 1225 1226 case 0x00030004: 1227 default: 1228 brightness = 7; 1229 } 1230 1231 /* set lcd brightness GPIOs */ 1232 for (i = 0; i <= 2; i++) { 1233 qemu_set_irq(s->out[i], (brightness >> i) & 1); 1234 } 1235 } 1236 1237 static void musicpal_gpio_pin_event(void *opaque, int pin, int level) 1238 { 1239 musicpal_gpio_state *s = opaque; 1240 uint32_t mask = 1 << pin; 1241 uint32_t delta = level << pin; 1242 uint32_t old = s->in_state & mask; 1243 1244 s->in_state &= ~mask; 1245 s->in_state |= delta; 1246 1247 if ((old ^ delta) && 1248 ((level && (s->imr & mask)) || (!level && (s->ier & mask)))) { 1249 s->isr = mask; 1250 qemu_irq_raise(s->irq); 1251 } 1252 } 1253 1254 static uint64_t musicpal_gpio_read(void *opaque, hwaddr offset, 1255 unsigned size) 1256 { 1257 musicpal_gpio_state *s = opaque; 1258 1259 switch (offset) { 1260 case MP_GPIO_OE_HI: /* used for LCD brightness control */ 1261 return s->lcd_brightness & MP_OE_LCD_BRIGHTNESS; 1262 1263 case MP_GPIO_OUT_LO: 1264 return s->out_state & 0xFFFF; 1265 case MP_GPIO_OUT_HI: 1266 return s->out_state >> 16; 1267 1268 case MP_GPIO_IN_LO: 1269 return s->in_state & 0xFFFF; 1270 case MP_GPIO_IN_HI: 1271 return s->in_state >> 16; 1272 1273 case MP_GPIO_IER_LO: 1274 return s->ier & 0xFFFF; 1275 case MP_GPIO_IER_HI: 1276 return s->ier >> 16; 1277 1278 case MP_GPIO_IMR_LO: 1279 return s->imr & 0xFFFF; 1280 case MP_GPIO_IMR_HI: 1281 return s->imr >> 16; 1282 1283 case MP_GPIO_ISR_LO: 1284 return s->isr & 0xFFFF; 1285 case MP_GPIO_ISR_HI: 1286 return s->isr >> 16; 1287 1288 default: 1289 return 0; 1290 } 1291 } 1292 1293 static void musicpal_gpio_write(void *opaque, hwaddr offset, 1294 uint64_t value, unsigned size) 1295 { 1296 musicpal_gpio_state *s = opaque; 1297 switch (offset) { 1298 case MP_GPIO_OE_HI: /* used for LCD brightness control */ 1299 s->lcd_brightness = (s->lcd_brightness & MP_GPIO_LCD_BRIGHTNESS) | 1300 (value & MP_OE_LCD_BRIGHTNESS); 1301 musicpal_gpio_brightness_update(s); 1302 break; 1303 1304 case MP_GPIO_OUT_LO: 1305 s->out_state = (s->out_state & 0xFFFF0000) | (value & 0xFFFF); 1306 break; 1307 case MP_GPIO_OUT_HI: 1308 s->out_state = (s->out_state & 0xFFFF) | (value << 16); 1309 s->lcd_brightness = (s->lcd_brightness & 0xFFFF) | 1310 (s->out_state & MP_GPIO_LCD_BRIGHTNESS); 1311 musicpal_gpio_brightness_update(s); 1312 qemu_set_irq(s->out[3], (s->out_state >> MP_GPIO_I2C_DATA_BIT) & 1); 1313 qemu_set_irq(s->out[4], (s->out_state >> MP_GPIO_I2C_CLOCK_BIT) & 1); 1314 break; 1315 1316 case MP_GPIO_IER_LO: 1317 s->ier = (s->ier & 0xFFFF0000) | (value & 0xFFFF); 1318 break; 1319 case MP_GPIO_IER_HI: 1320 s->ier = (s->ier & 0xFFFF) | (value << 16); 1321 break; 1322 1323 case MP_GPIO_IMR_LO: 1324 s->imr = (s->imr & 0xFFFF0000) | (value & 0xFFFF); 1325 break; 1326 case MP_GPIO_IMR_HI: 1327 s->imr = (s->imr & 0xFFFF) | (value << 16); 1328 break; 1329 } 1330 } 1331 1332 static const MemoryRegionOps musicpal_gpio_ops = { 1333 .read = musicpal_gpio_read, 1334 .write = musicpal_gpio_write, 1335 .endianness = DEVICE_NATIVE_ENDIAN, 1336 }; 1337 1338 static void musicpal_gpio_reset(DeviceState *d) 1339 { 1340 musicpal_gpio_state *s = MUSICPAL_GPIO(d); 1341 1342 s->lcd_brightness = 0; 1343 s->out_state = 0; 1344 s->in_state = 0xffffffff; 1345 s->ier = 0; 1346 s->imr = 0; 1347 s->isr = 0; 1348 } 1349 1350 static int musicpal_gpio_init(SysBusDevice *sbd) 1351 { 1352 DeviceState *dev = DEVICE(sbd); 1353 musicpal_gpio_state *s = MUSICPAL_GPIO(dev); 1354 1355 sysbus_init_irq(sbd, &s->irq); 1356 1357 memory_region_init_io(&s->iomem, OBJECT(s), &musicpal_gpio_ops, s, 1358 "musicpal-gpio", MP_GPIO_SIZE); 1359 sysbus_init_mmio(sbd, &s->iomem); 1360 1361 qdev_init_gpio_out(dev, s->out, ARRAY_SIZE(s->out)); 1362 1363 qdev_init_gpio_in(dev, musicpal_gpio_pin_event, 32); 1364 1365 return 0; 1366 } 1367 1368 static const VMStateDescription musicpal_gpio_vmsd = { 1369 .name = "musicpal_gpio", 1370 .version_id = 1, 1371 .minimum_version_id = 1, 1372 .fields = (VMStateField[]) { 1373 VMSTATE_UINT32(lcd_brightness, musicpal_gpio_state), 1374 VMSTATE_UINT32(out_state, musicpal_gpio_state), 1375 VMSTATE_UINT32(in_state, musicpal_gpio_state), 1376 VMSTATE_UINT32(ier, musicpal_gpio_state), 1377 VMSTATE_UINT32(imr, musicpal_gpio_state), 1378 VMSTATE_UINT32(isr, musicpal_gpio_state), 1379 VMSTATE_END_OF_LIST() 1380 } 1381 }; 1382 1383 static void musicpal_gpio_class_init(ObjectClass *klass, void *data) 1384 { 1385 DeviceClass *dc = DEVICE_CLASS(klass); 1386 SysBusDeviceClass *k = SYS_BUS_DEVICE_CLASS(klass); 1387 1388 k->init = musicpal_gpio_init; 1389 dc->reset = musicpal_gpio_reset; 1390 dc->vmsd = &musicpal_gpio_vmsd; 1391 } 1392 1393 static const TypeInfo musicpal_gpio_info = { 1394 .name = TYPE_MUSICPAL_GPIO, 1395 .parent = TYPE_SYS_BUS_DEVICE, 1396 .instance_size = sizeof(musicpal_gpio_state), 1397 .class_init = musicpal_gpio_class_init, 1398 }; 1399 1400 /* Keyboard codes & masks */ 1401 #define KEY_RELEASED 0x80 1402 #define KEY_CODE 0x7f 1403 1404 #define KEYCODE_TAB 0x0f 1405 #define KEYCODE_ENTER 0x1c 1406 #define KEYCODE_F 0x21 1407 #define KEYCODE_M 0x32 1408 1409 #define KEYCODE_EXTENDED 0xe0 1410 #define KEYCODE_UP 0x48 1411 #define KEYCODE_DOWN 0x50 1412 #define KEYCODE_LEFT 0x4b 1413 #define KEYCODE_RIGHT 0x4d 1414 1415 #define MP_KEY_WHEEL_VOL (1 << 0) 1416 #define MP_KEY_WHEEL_VOL_INV (1 << 1) 1417 #define MP_KEY_WHEEL_NAV (1 << 2) 1418 #define MP_KEY_WHEEL_NAV_INV (1 << 3) 1419 #define MP_KEY_BTN_FAVORITS (1 << 4) 1420 #define MP_KEY_BTN_MENU (1 << 5) 1421 #define MP_KEY_BTN_VOLUME (1 << 6) 1422 #define MP_KEY_BTN_NAVIGATION (1 << 7) 1423 1424 #define TYPE_MUSICPAL_KEY "musicpal_key" 1425 #define MUSICPAL_KEY(obj) \ 1426 OBJECT_CHECK(musicpal_key_state, (obj), TYPE_MUSICPAL_KEY) 1427 1428 typedef struct musicpal_key_state { 1429 /*< private >*/ 1430 SysBusDevice parent_obj; 1431 /*< public >*/ 1432 1433 MemoryRegion iomem; 1434 uint32_t kbd_extended; 1435 uint32_t pressed_keys; 1436 qemu_irq out[8]; 1437 } musicpal_key_state; 1438 1439 static void musicpal_key_event(void *opaque, int keycode) 1440 { 1441 musicpal_key_state *s = opaque; 1442 uint32_t event = 0; 1443 int i; 1444 1445 if (keycode == KEYCODE_EXTENDED) { 1446 s->kbd_extended = 1; 1447 return; 1448 } 1449 1450 if (s->kbd_extended) { 1451 switch (keycode & KEY_CODE) { 1452 case KEYCODE_UP: 1453 event = MP_KEY_WHEEL_NAV | MP_KEY_WHEEL_NAV_INV; 1454 break; 1455 1456 case KEYCODE_DOWN: 1457 event = MP_KEY_WHEEL_NAV; 1458 break; 1459 1460 case KEYCODE_LEFT: 1461 event = MP_KEY_WHEEL_VOL | MP_KEY_WHEEL_VOL_INV; 1462 break; 1463 1464 case KEYCODE_RIGHT: 1465 event = MP_KEY_WHEEL_VOL; 1466 break; 1467 } 1468 } else { 1469 switch (keycode & KEY_CODE) { 1470 case KEYCODE_F: 1471 event = MP_KEY_BTN_FAVORITS; 1472 break; 1473 1474 case KEYCODE_TAB: 1475 event = MP_KEY_BTN_VOLUME; 1476 break; 1477 1478 case KEYCODE_ENTER: 1479 event = MP_KEY_BTN_NAVIGATION; 1480 break; 1481 1482 case KEYCODE_M: 1483 event = MP_KEY_BTN_MENU; 1484 break; 1485 } 1486 /* Do not repeat already pressed buttons */ 1487 if (!(keycode & KEY_RELEASED) && (s->pressed_keys & event)) { 1488 event = 0; 1489 } 1490 } 1491 1492 if (event) { 1493 /* Raise GPIO pin first if repeating a key */ 1494 if (!(keycode & KEY_RELEASED) && (s->pressed_keys & event)) { 1495 for (i = 0; i <= 7; i++) { 1496 if (event & (1 << i)) { 1497 qemu_set_irq(s->out[i], 1); 1498 } 1499 } 1500 } 1501 for (i = 0; i <= 7; i++) { 1502 if (event & (1 << i)) { 1503 qemu_set_irq(s->out[i], !!(keycode & KEY_RELEASED)); 1504 } 1505 } 1506 if (keycode & KEY_RELEASED) { 1507 s->pressed_keys &= ~event; 1508 } else { 1509 s->pressed_keys |= event; 1510 } 1511 } 1512 1513 s->kbd_extended = 0; 1514 } 1515 1516 static int musicpal_key_init(SysBusDevice *sbd) 1517 { 1518 DeviceState *dev = DEVICE(sbd); 1519 musicpal_key_state *s = MUSICPAL_KEY(dev); 1520 1521 memory_region_init(&s->iomem, OBJECT(s), "dummy", 0); 1522 sysbus_init_mmio(sbd, &s->iomem); 1523 1524 s->kbd_extended = 0; 1525 s->pressed_keys = 0; 1526 1527 qdev_init_gpio_out(dev, s->out, ARRAY_SIZE(s->out)); 1528 1529 qemu_add_kbd_event_handler(musicpal_key_event, s); 1530 1531 return 0; 1532 } 1533 1534 static const VMStateDescription musicpal_key_vmsd = { 1535 .name = "musicpal_key", 1536 .version_id = 1, 1537 .minimum_version_id = 1, 1538 .fields = (VMStateField[]) { 1539 VMSTATE_UINT32(kbd_extended, musicpal_key_state), 1540 VMSTATE_UINT32(pressed_keys, musicpal_key_state), 1541 VMSTATE_END_OF_LIST() 1542 } 1543 }; 1544 1545 static void musicpal_key_class_init(ObjectClass *klass, void *data) 1546 { 1547 DeviceClass *dc = DEVICE_CLASS(klass); 1548 SysBusDeviceClass *k = SYS_BUS_DEVICE_CLASS(klass); 1549 1550 k->init = musicpal_key_init; 1551 dc->vmsd = &musicpal_key_vmsd; 1552 } 1553 1554 static const TypeInfo musicpal_key_info = { 1555 .name = TYPE_MUSICPAL_KEY, 1556 .parent = TYPE_SYS_BUS_DEVICE, 1557 .instance_size = sizeof(musicpal_key_state), 1558 .class_init = musicpal_key_class_init, 1559 }; 1560 1561 static struct arm_boot_info musicpal_binfo = { 1562 .loader_start = 0x0, 1563 .board_id = 0x20e, 1564 }; 1565 1566 static void musicpal_init(MachineState *machine) 1567 { 1568 const char *cpu_model = machine->cpu_model; 1569 const char *kernel_filename = machine->kernel_filename; 1570 const char *kernel_cmdline = machine->kernel_cmdline; 1571 const char *initrd_filename = machine->initrd_filename; 1572 ARMCPU *cpu; 1573 qemu_irq pic[32]; 1574 DeviceState *dev; 1575 DeviceState *i2c_dev; 1576 DeviceState *lcd_dev; 1577 DeviceState *key_dev; 1578 DeviceState *wm8750_dev; 1579 SysBusDevice *s; 1580 I2CBus *i2c; 1581 int i; 1582 unsigned long flash_size; 1583 DriveInfo *dinfo; 1584 MemoryRegion *address_space_mem = get_system_memory(); 1585 MemoryRegion *ram = g_new(MemoryRegion, 1); 1586 MemoryRegion *sram = g_new(MemoryRegion, 1); 1587 1588 if (!cpu_model) { 1589 cpu_model = "arm926"; 1590 } 1591 cpu = cpu_arm_init(cpu_model); 1592 if (!cpu) { 1593 fprintf(stderr, "Unable to find CPU definition\n"); 1594 exit(1); 1595 } 1596 1597 /* For now we use a fixed - the original - RAM size */ 1598 memory_region_allocate_system_memory(ram, NULL, "musicpal.ram", 1599 MP_RAM_DEFAULT_SIZE); 1600 memory_region_add_subregion(address_space_mem, 0, ram); 1601 1602 memory_region_init_ram(sram, NULL, "musicpal.sram", MP_SRAM_SIZE, 1603 &error_fatal); 1604 vmstate_register_ram_global(sram); 1605 memory_region_add_subregion(address_space_mem, MP_SRAM_BASE, sram); 1606 1607 dev = sysbus_create_simple(TYPE_MV88W8618_PIC, MP_PIC_BASE, 1608 qdev_get_gpio_in(DEVICE(cpu), ARM_CPU_IRQ)); 1609 for (i = 0; i < 32; i++) { 1610 pic[i] = qdev_get_gpio_in(dev, i); 1611 } 1612 sysbus_create_varargs(TYPE_MV88W8618_PIT, MP_PIT_BASE, pic[MP_TIMER1_IRQ], 1613 pic[MP_TIMER2_IRQ], pic[MP_TIMER3_IRQ], 1614 pic[MP_TIMER4_IRQ], NULL); 1615 1616 if (serial_hds[0]) { 1617 serial_mm_init(address_space_mem, MP_UART1_BASE, 2, pic[MP_UART1_IRQ], 1618 1825000, serial_hds[0], DEVICE_NATIVE_ENDIAN); 1619 } 1620 if (serial_hds[1]) { 1621 serial_mm_init(address_space_mem, MP_UART2_BASE, 2, pic[MP_UART2_IRQ], 1622 1825000, serial_hds[1], DEVICE_NATIVE_ENDIAN); 1623 } 1624 1625 /* Register flash */ 1626 dinfo = drive_get(IF_PFLASH, 0, 0); 1627 if (dinfo) { 1628 BlockBackend *blk = blk_by_legacy_dinfo(dinfo); 1629 1630 flash_size = blk_getlength(blk); 1631 if (flash_size != 8*1024*1024 && flash_size != 16*1024*1024 && 1632 flash_size != 32*1024*1024) { 1633 fprintf(stderr, "Invalid flash image size\n"); 1634 exit(1); 1635 } 1636 1637 /* 1638 * The original U-Boot accesses the flash at 0xFE000000 instead of 1639 * 0xFF800000 (if there is 8 MB flash). So remap flash access if the 1640 * image is smaller than 32 MB. 1641 */ 1642 #ifdef TARGET_WORDS_BIGENDIAN 1643 pflash_cfi02_register(0x100000000ULL-MP_FLASH_SIZE_MAX, NULL, 1644 "musicpal.flash", flash_size, 1645 blk, 0x10000, (flash_size + 0xffff) >> 16, 1646 MP_FLASH_SIZE_MAX / flash_size, 1647 2, 0x00BF, 0x236D, 0x0000, 0x0000, 1648 0x5555, 0x2AAA, 1); 1649 #else 1650 pflash_cfi02_register(0x100000000ULL-MP_FLASH_SIZE_MAX, NULL, 1651 "musicpal.flash", flash_size, 1652 blk, 0x10000, (flash_size + 0xffff) >> 16, 1653 MP_FLASH_SIZE_MAX / flash_size, 1654 2, 0x00BF, 0x236D, 0x0000, 0x0000, 1655 0x5555, 0x2AAA, 0); 1656 #endif 1657 1658 } 1659 sysbus_create_simple(TYPE_MV88W8618_FLASHCFG, MP_FLASHCFG_BASE, NULL); 1660 1661 qemu_check_nic_model(&nd_table[0], "mv88w8618"); 1662 dev = qdev_create(NULL, TYPE_MV88W8618_ETH); 1663 qdev_set_nic_properties(dev, &nd_table[0]); 1664 qdev_init_nofail(dev); 1665 sysbus_mmio_map(SYS_BUS_DEVICE(dev), 0, MP_ETH_BASE); 1666 sysbus_connect_irq(SYS_BUS_DEVICE(dev), 0, pic[MP_ETH_IRQ]); 1667 1668 sysbus_create_simple("mv88w8618_wlan", MP_WLAN_BASE, NULL); 1669 1670 sysbus_create_simple(TYPE_MUSICPAL_MISC, MP_MISC_BASE, NULL); 1671 1672 dev = sysbus_create_simple(TYPE_MUSICPAL_GPIO, MP_GPIO_BASE, 1673 pic[MP_GPIO_IRQ]); 1674 i2c_dev = sysbus_create_simple("gpio_i2c", -1, NULL); 1675 i2c = (I2CBus *)qdev_get_child_bus(i2c_dev, "i2c"); 1676 1677 lcd_dev = sysbus_create_simple(TYPE_MUSICPAL_LCD, MP_LCD_BASE, NULL); 1678 key_dev = sysbus_create_simple(TYPE_MUSICPAL_KEY, -1, NULL); 1679 1680 /* I2C read data */ 1681 qdev_connect_gpio_out(i2c_dev, 0, 1682 qdev_get_gpio_in(dev, MP_GPIO_I2C_DATA_BIT)); 1683 /* I2C data */ 1684 qdev_connect_gpio_out(dev, 3, qdev_get_gpio_in(i2c_dev, 0)); 1685 /* I2C clock */ 1686 qdev_connect_gpio_out(dev, 4, qdev_get_gpio_in(i2c_dev, 1)); 1687 1688 for (i = 0; i < 3; i++) { 1689 qdev_connect_gpio_out(dev, i, qdev_get_gpio_in(lcd_dev, i)); 1690 } 1691 for (i = 0; i < 4; i++) { 1692 qdev_connect_gpio_out(key_dev, i, qdev_get_gpio_in(dev, i + 8)); 1693 } 1694 for (i = 4; i < 8; i++) { 1695 qdev_connect_gpio_out(key_dev, i, qdev_get_gpio_in(dev, i + 15)); 1696 } 1697 1698 wm8750_dev = i2c_create_slave(i2c, "wm8750", MP_WM_ADDR); 1699 dev = qdev_create(NULL, "mv88w8618_audio"); 1700 s = SYS_BUS_DEVICE(dev); 1701 qdev_prop_set_ptr(dev, "wm8750", wm8750_dev); 1702 qdev_init_nofail(dev); 1703 sysbus_mmio_map(s, 0, MP_AUDIO_BASE); 1704 sysbus_connect_irq(s, 0, pic[MP_AUDIO_IRQ]); 1705 1706 musicpal_binfo.ram_size = MP_RAM_DEFAULT_SIZE; 1707 musicpal_binfo.kernel_filename = kernel_filename; 1708 musicpal_binfo.kernel_cmdline = kernel_cmdline; 1709 musicpal_binfo.initrd_filename = initrd_filename; 1710 arm_load_kernel(cpu, &musicpal_binfo); 1711 } 1712 1713 static void musicpal_machine_init(MachineClass *mc) 1714 { 1715 mc->desc = "Marvell 88w8618 / MusicPal (ARM926EJ-S)"; 1716 mc->init = musicpal_init; 1717 } 1718 1719 DEFINE_MACHINE("musicpal", musicpal_machine_init) 1720 1721 static void mv88w8618_wlan_class_init(ObjectClass *klass, void *data) 1722 { 1723 SysBusDeviceClass *sdc = SYS_BUS_DEVICE_CLASS(klass); 1724 1725 sdc->init = mv88w8618_wlan_init; 1726 } 1727 1728 static const TypeInfo mv88w8618_wlan_info = { 1729 .name = "mv88w8618_wlan", 1730 .parent = TYPE_SYS_BUS_DEVICE, 1731 .instance_size = sizeof(SysBusDevice), 1732 .class_init = mv88w8618_wlan_class_init, 1733 }; 1734 1735 static void musicpal_register_types(void) 1736 { 1737 type_register_static(&mv88w8618_pic_info); 1738 type_register_static(&mv88w8618_pit_info); 1739 type_register_static(&mv88w8618_flashcfg_info); 1740 type_register_static(&mv88w8618_eth_info); 1741 type_register_static(&mv88w8618_wlan_info); 1742 type_register_static(&musicpal_lcd_info); 1743 type_register_static(&musicpal_gpio_info); 1744 type_register_static(&musicpal_key_info); 1745 type_register_static(&musicpal_misc_info); 1746 } 1747 1748 type_init(musicpal_register_types) 1749