1 /* 2 * Machine definitions for boards featuring an NPCM7xx SoC. 3 * 4 * Copyright 2020 Google LLC 5 * 6 * This program is free software; you can redistribute it and/or modify it 7 * under the terms of the GNU General Public License as published by the 8 * Free Software Foundation; either version 2 of the License, or 9 * (at your option) any later version. 10 * 11 * This program is distributed in the hope that it will be useful, but WITHOUT 12 * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or 13 * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License 14 * for more details. 15 */ 16 17 #include "qemu/osdep.h" 18 19 #include "hw/arm/npcm7xx.h" 20 #include "hw/core/cpu.h" 21 #include "hw/i2c/i2c_mux_pca954x.h" 22 #include "hw/i2c/smbus_eeprom.h" 23 #include "hw/loader.h" 24 #include "hw/qdev-core.h" 25 #include "hw/qdev-properties.h" 26 #include "qapi/error.h" 27 #include "qemu/datadir.h" 28 #include "qemu/units.h" 29 #include "sysemu/blockdev.h" 30 #include "sysemu/sysemu.h" 31 #include "sysemu/block-backend.h" 32 33 #define NPCM750_EVB_POWER_ON_STRAPS 0x00001ff7 34 #define QUANTA_GSJ_POWER_ON_STRAPS 0x00001fff 35 #define QUANTA_GBS_POWER_ON_STRAPS 0x000017ff 36 #define KUDO_BMC_POWER_ON_STRAPS 0x00001fff 37 38 static const char npcm7xx_default_bootrom[] = "npcm7xx_bootrom.bin"; 39 40 static void npcm7xx_load_bootrom(MachineState *machine, NPCM7xxState *soc) 41 { 42 const char *bios_name = machine->firmware ?: npcm7xx_default_bootrom; 43 g_autofree char *filename = NULL; 44 int ret; 45 46 filename = qemu_find_file(QEMU_FILE_TYPE_BIOS, bios_name); 47 if (!filename) { 48 error_report("Could not find ROM image '%s'", bios_name); 49 if (!machine->kernel_filename) { 50 /* We can't boot without a bootrom or a kernel image. */ 51 exit(1); 52 } 53 return; 54 } 55 ret = load_image_mr(filename, &soc->irom); 56 if (ret < 0) { 57 error_report("Failed to load ROM image '%s'", filename); 58 exit(1); 59 } 60 } 61 62 static void npcm7xx_connect_flash(NPCM7xxFIUState *fiu, int cs_no, 63 const char *flash_type, DriveInfo *dinfo) 64 { 65 DeviceState *flash; 66 qemu_irq flash_cs; 67 68 flash = qdev_new(flash_type); 69 if (dinfo) { 70 qdev_prop_set_drive(flash, "drive", blk_by_legacy_dinfo(dinfo)); 71 } 72 qdev_realize_and_unref(flash, BUS(fiu->spi), &error_fatal); 73 74 flash_cs = qdev_get_gpio_in_named(flash, SSI_GPIO_CS, 0); 75 qdev_connect_gpio_out_named(DEVICE(fiu), "cs", cs_no, flash_cs); 76 } 77 78 static void npcm7xx_connect_dram(NPCM7xxState *soc, MemoryRegion *dram) 79 { 80 memory_region_add_subregion(get_system_memory(), NPCM7XX_DRAM_BA, dram); 81 82 object_property_set_link(OBJECT(soc), "dram-mr", OBJECT(dram), 83 &error_abort); 84 } 85 86 static void sdhci_attach_drive(SDHCIState *sdhci, int unit) 87 { 88 DriveInfo *di = drive_get(IF_SD, 0, unit); 89 BlockBackend *blk = di ? blk_by_legacy_dinfo(di) : NULL; 90 91 BusState *bus = qdev_get_child_bus(DEVICE(sdhci), "sd-bus"); 92 if (bus == NULL) { 93 error_report("No SD bus found in SOC object"); 94 exit(1); 95 } 96 97 DeviceState *carddev = qdev_new(TYPE_SD_CARD); 98 qdev_prop_set_drive_err(carddev, "drive", blk, &error_fatal); 99 qdev_realize_and_unref(carddev, bus, &error_fatal); 100 } 101 102 static NPCM7xxState *npcm7xx_create_soc(MachineState *machine, 103 uint32_t hw_straps) 104 { 105 NPCM7xxMachineClass *nmc = NPCM7XX_MACHINE_GET_CLASS(machine); 106 MachineClass *mc = MACHINE_CLASS(nmc); 107 Object *obj; 108 109 if (strcmp(machine->cpu_type, mc->default_cpu_type) != 0) { 110 error_report("This board can only be used with %s", 111 mc->default_cpu_type); 112 exit(1); 113 } 114 115 obj = object_new_with_props(nmc->soc_type, OBJECT(machine), "soc", 116 &error_abort, NULL); 117 object_property_set_uint(obj, "power-on-straps", hw_straps, &error_abort); 118 119 return NPCM7XX(obj); 120 } 121 122 static I2CBus *npcm7xx_i2c_get_bus(NPCM7xxState *soc, uint32_t num) 123 { 124 g_assert(num < ARRAY_SIZE(soc->smbus)); 125 return I2C_BUS(qdev_get_child_bus(DEVICE(&soc->smbus[num]), "i2c-bus")); 126 } 127 128 static void at24c_eeprom_init(NPCM7xxState *soc, int bus, uint8_t addr, 129 uint32_t rsize) 130 { 131 I2CBus *i2c_bus = npcm7xx_i2c_get_bus(soc, bus); 132 I2CSlave *i2c_dev = i2c_slave_new("at24c-eeprom", addr); 133 DeviceState *dev = DEVICE(i2c_dev); 134 135 qdev_prop_set_uint32(dev, "rom-size", rsize); 136 i2c_slave_realize_and_unref(i2c_dev, i2c_bus, &error_abort); 137 } 138 139 static void npcm7xx_init_pwm_splitter(NPCM7xxMachine *machine, 140 NPCM7xxState *soc, const int *fan_counts) 141 { 142 SplitIRQ *splitters = machine->fan_splitter; 143 144 /* 145 * PWM 0~3 belong to module 0 output 0~3. 146 * PWM 4~7 belong to module 1 output 0~3. 147 */ 148 for (int i = 0; i < NPCM7XX_NR_PWM_MODULES; ++i) { 149 for (int j = 0; j < NPCM7XX_PWM_PER_MODULE; ++j) { 150 int splitter_no = i * NPCM7XX_PWM_PER_MODULE + j; 151 DeviceState *splitter; 152 153 if (fan_counts[splitter_no] < 1) { 154 continue; 155 } 156 object_initialize_child(OBJECT(machine), "fan-splitter[*]", 157 &splitters[splitter_no], TYPE_SPLIT_IRQ); 158 splitter = DEVICE(&splitters[splitter_no]); 159 qdev_prop_set_uint16(splitter, "num-lines", 160 fan_counts[splitter_no]); 161 qdev_realize(splitter, NULL, &error_abort); 162 qdev_connect_gpio_out_named(DEVICE(&soc->pwm[i]), "duty-gpio-out", 163 j, qdev_get_gpio_in(splitter, 0)); 164 } 165 } 166 } 167 168 static void npcm7xx_connect_pwm_fan(NPCM7xxState *soc, SplitIRQ *splitter, 169 int fan_no, int output_no) 170 { 171 DeviceState *fan; 172 int fan_input; 173 qemu_irq fan_duty_gpio; 174 175 g_assert(fan_no >= 0 && fan_no <= NPCM7XX_MFT_MAX_FAN_INPUT); 176 /* 177 * Fan 0~1 belong to module 0 input 0~1. 178 * Fan 2~3 belong to module 1 input 0~1. 179 * ... 180 * Fan 14~15 belong to module 7 input 0~1. 181 * Fan 16~17 belong to module 0 input 2~3. 182 * Fan 18~19 belong to module 1 input 2~3. 183 */ 184 if (fan_no < 16) { 185 fan = DEVICE(&soc->mft[fan_no / 2]); 186 fan_input = fan_no % 2; 187 } else { 188 fan = DEVICE(&soc->mft[(fan_no - 16) / 2]); 189 fan_input = fan_no % 2 + 2; 190 } 191 192 /* Connect the Fan to PWM module */ 193 fan_duty_gpio = qdev_get_gpio_in_named(fan, "duty", fan_input); 194 qdev_connect_gpio_out(DEVICE(splitter), output_no, fan_duty_gpio); 195 } 196 197 static void npcm750_evb_i2c_init(NPCM7xxState *soc) 198 { 199 /* lm75 temperature sensor on SVB, tmp105 is compatible */ 200 i2c_slave_create_simple(npcm7xx_i2c_get_bus(soc, 0), "tmp105", 0x48); 201 /* lm75 temperature sensor on EB, tmp105 is compatible */ 202 i2c_slave_create_simple(npcm7xx_i2c_get_bus(soc, 1), "tmp105", 0x48); 203 /* tmp100 temperature sensor on EB, tmp105 is compatible */ 204 i2c_slave_create_simple(npcm7xx_i2c_get_bus(soc, 2), "tmp105", 0x48); 205 /* tmp100 temperature sensor on SVB, tmp105 is compatible */ 206 i2c_slave_create_simple(npcm7xx_i2c_get_bus(soc, 6), "tmp105", 0x48); 207 } 208 209 static void npcm750_evb_fan_init(NPCM7xxMachine *machine, NPCM7xxState *soc) 210 { 211 SplitIRQ *splitter = machine->fan_splitter; 212 static const int fan_counts[] = {2, 2, 2, 2, 2, 2, 2, 2}; 213 214 npcm7xx_init_pwm_splitter(machine, soc, fan_counts); 215 npcm7xx_connect_pwm_fan(soc, &splitter[0], 0x00, 0); 216 npcm7xx_connect_pwm_fan(soc, &splitter[0], 0x01, 1); 217 npcm7xx_connect_pwm_fan(soc, &splitter[1], 0x02, 0); 218 npcm7xx_connect_pwm_fan(soc, &splitter[1], 0x03, 1); 219 npcm7xx_connect_pwm_fan(soc, &splitter[2], 0x04, 0); 220 npcm7xx_connect_pwm_fan(soc, &splitter[2], 0x05, 1); 221 npcm7xx_connect_pwm_fan(soc, &splitter[3], 0x06, 0); 222 npcm7xx_connect_pwm_fan(soc, &splitter[3], 0x07, 1); 223 npcm7xx_connect_pwm_fan(soc, &splitter[4], 0x08, 0); 224 npcm7xx_connect_pwm_fan(soc, &splitter[4], 0x09, 1); 225 npcm7xx_connect_pwm_fan(soc, &splitter[5], 0x0a, 0); 226 npcm7xx_connect_pwm_fan(soc, &splitter[5], 0x0b, 1); 227 npcm7xx_connect_pwm_fan(soc, &splitter[6], 0x0c, 0); 228 npcm7xx_connect_pwm_fan(soc, &splitter[6], 0x0d, 1); 229 npcm7xx_connect_pwm_fan(soc, &splitter[7], 0x0e, 0); 230 npcm7xx_connect_pwm_fan(soc, &splitter[7], 0x0f, 1); 231 } 232 233 static void quanta_gsj_i2c_init(NPCM7xxState *soc) 234 { 235 /* GSJ machine have 4 max31725 temperature sensors, tmp105 is compatible. */ 236 i2c_slave_create_simple(npcm7xx_i2c_get_bus(soc, 1), "tmp105", 0x5c); 237 i2c_slave_create_simple(npcm7xx_i2c_get_bus(soc, 2), "tmp105", 0x5c); 238 i2c_slave_create_simple(npcm7xx_i2c_get_bus(soc, 3), "tmp105", 0x5c); 239 i2c_slave_create_simple(npcm7xx_i2c_get_bus(soc, 4), "tmp105", 0x5c); 240 241 at24c_eeprom_init(soc, 9, 0x55, 8192); 242 at24c_eeprom_init(soc, 10, 0x55, 8192); 243 244 /* 245 * i2c-11: 246 * - power-brick@36: delta,dps800 247 * - hotswap@15: ti,lm5066i 248 */ 249 250 /* 251 * i2c-12: 252 * - ucd90160@6b 253 */ 254 255 i2c_slave_create_simple(npcm7xx_i2c_get_bus(soc, 15), "pca9548", 0x75); 256 } 257 258 static void quanta_gsj_fan_init(NPCM7xxMachine *machine, NPCM7xxState *soc) 259 { 260 SplitIRQ *splitter = machine->fan_splitter; 261 static const int fan_counts[] = {2, 2, 2, 0, 0, 0, 0, 0}; 262 263 npcm7xx_init_pwm_splitter(machine, soc, fan_counts); 264 npcm7xx_connect_pwm_fan(soc, &splitter[0], 0x00, 0); 265 npcm7xx_connect_pwm_fan(soc, &splitter[0], 0x01, 1); 266 npcm7xx_connect_pwm_fan(soc, &splitter[1], 0x02, 0); 267 npcm7xx_connect_pwm_fan(soc, &splitter[1], 0x03, 1); 268 npcm7xx_connect_pwm_fan(soc, &splitter[2], 0x04, 0); 269 npcm7xx_connect_pwm_fan(soc, &splitter[2], 0x05, 1); 270 } 271 272 static void quanta_gbs_i2c_init(NPCM7xxState *soc) 273 { 274 /* 275 * i2c-0: 276 * pca9546@71 277 * 278 * i2c-1: 279 * pca9535@24 280 * pca9535@20 281 * pca9535@21 282 * pca9535@22 283 * pca9535@23 284 * pca9535@25 285 * pca9535@26 286 * 287 * i2c-2: 288 * sbtsi@4c 289 * 290 * i2c-5: 291 * atmel,24c64@50 mb_fru 292 * pca9546@71 293 * - channel 0: max31725@54 294 * - channel 1: max31725@55 295 * - channel 2: max31725@5d 296 * atmel,24c64@51 fan_fru 297 * - channel 3: atmel,24c64@52 hsbp_fru 298 * 299 * i2c-6: 300 * pca9545@73 301 * 302 * i2c-7: 303 * pca9545@72 304 * 305 * i2c-8: 306 * adi,adm1272@10 307 * 308 * i2c-9: 309 * pca9546@71 310 * - channel 0: isil,isl68137@60 311 * - channel 1: isil,isl68137@61 312 * - channel 2: isil,isl68137@63 313 * - channel 3: isil,isl68137@45 314 * 315 * i2c-10: 316 * pca9545@71 317 * 318 * i2c-11: 319 * pca9545@76 320 * 321 * i2c-12: 322 * maxim,max34451@4e 323 * isil,isl68137@5d 324 * isil,isl68137@5e 325 * 326 * i2c-14: 327 * pca9545@70 328 */ 329 } 330 331 static void kudo_bmc_i2c_init(NPCM7xxState *soc) 332 { 333 i2c_slave_create_simple(npcm7xx_i2c_get_bus(soc, 1), TYPE_PCA9548, 0x75); 334 i2c_slave_create_simple(npcm7xx_i2c_get_bus(soc, 1), TYPE_PCA9548, 0x77); 335 336 i2c_slave_create_simple(npcm7xx_i2c_get_bus(soc, 4), TYPE_PCA9548, 0x77); 337 338 at24c_eeprom_init(soc, 4, 0x50, 8192); /* mbfru */ 339 340 i2c_slave_create_simple(npcm7xx_i2c_get_bus(soc, 13), TYPE_PCA9548, 0x77); 341 342 at24c_eeprom_init(soc, 14, 0x55, 8192); /* bmcfru */ 343 344 /* TODO: Add remaining i2c devices. */ 345 } 346 347 static void npcm750_evb_init(MachineState *machine) 348 { 349 NPCM7xxState *soc; 350 351 soc = npcm7xx_create_soc(machine, NPCM750_EVB_POWER_ON_STRAPS); 352 npcm7xx_connect_dram(soc, machine->ram); 353 qdev_realize(DEVICE(soc), NULL, &error_fatal); 354 355 npcm7xx_load_bootrom(machine, soc); 356 npcm7xx_connect_flash(&soc->fiu[0], 0, "w25q256", drive_get(IF_MTD, 0, 0)); 357 npcm750_evb_i2c_init(soc); 358 npcm750_evb_fan_init(NPCM7XX_MACHINE(machine), soc); 359 npcm7xx_load_kernel(machine, soc); 360 } 361 362 static void quanta_gsj_init(MachineState *machine) 363 { 364 NPCM7xxState *soc; 365 366 soc = npcm7xx_create_soc(machine, QUANTA_GSJ_POWER_ON_STRAPS); 367 npcm7xx_connect_dram(soc, machine->ram); 368 qdev_realize(DEVICE(soc), NULL, &error_fatal); 369 370 npcm7xx_load_bootrom(machine, soc); 371 npcm7xx_connect_flash(&soc->fiu[0], 0, "mx25l25635e", 372 drive_get(IF_MTD, 0, 0)); 373 quanta_gsj_i2c_init(soc); 374 quanta_gsj_fan_init(NPCM7XX_MACHINE(machine), soc); 375 npcm7xx_load_kernel(machine, soc); 376 } 377 378 static void quanta_gbs_init(MachineState *machine) 379 { 380 NPCM7xxState *soc; 381 382 soc = npcm7xx_create_soc(machine, QUANTA_GBS_POWER_ON_STRAPS); 383 npcm7xx_connect_dram(soc, machine->ram); 384 qdev_realize(DEVICE(soc), NULL, &error_fatal); 385 386 npcm7xx_load_bootrom(machine, soc); 387 388 npcm7xx_connect_flash(&soc->fiu[0], 0, "mx66u51235f", 389 drive_get(IF_MTD, 0, 0)); 390 391 quanta_gbs_i2c_init(soc); 392 sdhci_attach_drive(&soc->mmc.sdhci, 0); 393 npcm7xx_load_kernel(machine, soc); 394 } 395 396 static void kudo_bmc_init(MachineState *machine) 397 { 398 NPCM7xxState *soc; 399 400 soc = npcm7xx_create_soc(machine, KUDO_BMC_POWER_ON_STRAPS); 401 npcm7xx_connect_dram(soc, machine->ram); 402 qdev_realize(DEVICE(soc), NULL, &error_fatal); 403 404 npcm7xx_load_bootrom(machine, soc); 405 npcm7xx_connect_flash(&soc->fiu[0], 0, "mx66u51235f", 406 drive_get(IF_MTD, 0, 0)); 407 npcm7xx_connect_flash(&soc->fiu[1], 0, "mx66u51235f", 408 drive_get(IF_MTD, 3, 0)); 409 410 kudo_bmc_i2c_init(soc); 411 sdhci_attach_drive(&soc->mmc.sdhci, 0); 412 npcm7xx_load_kernel(machine, soc); 413 } 414 415 static void npcm7xx_set_soc_type(NPCM7xxMachineClass *nmc, const char *type) 416 { 417 NPCM7xxClass *sc = NPCM7XX_CLASS(object_class_by_name(type)); 418 MachineClass *mc = MACHINE_CLASS(nmc); 419 420 nmc->soc_type = type; 421 mc->default_cpus = mc->min_cpus = mc->max_cpus = sc->num_cpus; 422 } 423 424 static void npcm7xx_machine_class_init(ObjectClass *oc, void *data) 425 { 426 MachineClass *mc = MACHINE_CLASS(oc); 427 428 mc->no_floppy = 1; 429 mc->no_cdrom = 1; 430 mc->no_parallel = 1; 431 mc->default_ram_id = "ram"; 432 mc->default_cpu_type = ARM_CPU_TYPE_NAME("cortex-a9"); 433 } 434 435 /* 436 * Schematics: 437 * https://github.com/Nuvoton-Israel/nuvoton-info/blob/master/npcm7xx-poleg/evaluation-board/board_deliverables/NPCM750x_EB_ver.A1.1_COMPLETE.pdf 438 */ 439 static void npcm750_evb_machine_class_init(ObjectClass *oc, void *data) 440 { 441 NPCM7xxMachineClass *nmc = NPCM7XX_MACHINE_CLASS(oc); 442 MachineClass *mc = MACHINE_CLASS(oc); 443 444 npcm7xx_set_soc_type(nmc, TYPE_NPCM750); 445 446 mc->desc = "Nuvoton NPCM750 Evaluation Board (Cortex-A9)"; 447 mc->init = npcm750_evb_init; 448 mc->default_ram_size = 512 * MiB; 449 }; 450 451 static void gsj_machine_class_init(ObjectClass *oc, void *data) 452 { 453 NPCM7xxMachineClass *nmc = NPCM7XX_MACHINE_CLASS(oc); 454 MachineClass *mc = MACHINE_CLASS(oc); 455 456 npcm7xx_set_soc_type(nmc, TYPE_NPCM730); 457 458 mc->desc = "Quanta GSJ (Cortex-A9)"; 459 mc->init = quanta_gsj_init; 460 mc->default_ram_size = 512 * MiB; 461 }; 462 463 static void gbs_bmc_machine_class_init(ObjectClass *oc, void *data) 464 { 465 NPCM7xxMachineClass *nmc = NPCM7XX_MACHINE_CLASS(oc); 466 MachineClass *mc = MACHINE_CLASS(oc); 467 468 npcm7xx_set_soc_type(nmc, TYPE_NPCM730); 469 470 mc->desc = "Quanta GBS (Cortex-A9)"; 471 mc->init = quanta_gbs_init; 472 mc->default_ram_size = 1 * GiB; 473 } 474 475 static void kudo_bmc_machine_class_init(ObjectClass *oc, void *data) 476 { 477 NPCM7xxMachineClass *nmc = NPCM7XX_MACHINE_CLASS(oc); 478 MachineClass *mc = MACHINE_CLASS(oc); 479 480 npcm7xx_set_soc_type(nmc, TYPE_NPCM730); 481 482 mc->desc = "Kudo BMC (Cortex-A9)"; 483 mc->init = kudo_bmc_init; 484 mc->default_ram_size = 1 * GiB; 485 }; 486 487 static const TypeInfo npcm7xx_machine_types[] = { 488 { 489 .name = TYPE_NPCM7XX_MACHINE, 490 .parent = TYPE_MACHINE, 491 .instance_size = sizeof(NPCM7xxMachine), 492 .class_size = sizeof(NPCM7xxMachineClass), 493 .class_init = npcm7xx_machine_class_init, 494 .abstract = true, 495 }, { 496 .name = MACHINE_TYPE_NAME("npcm750-evb"), 497 .parent = TYPE_NPCM7XX_MACHINE, 498 .class_init = npcm750_evb_machine_class_init, 499 }, { 500 .name = MACHINE_TYPE_NAME("quanta-gsj"), 501 .parent = TYPE_NPCM7XX_MACHINE, 502 .class_init = gsj_machine_class_init, 503 }, { 504 .name = MACHINE_TYPE_NAME("quanta-gbs-bmc"), 505 .parent = TYPE_NPCM7XX_MACHINE, 506 .class_init = gbs_bmc_machine_class_init, 507 }, { 508 .name = MACHINE_TYPE_NAME("kudo-bmc"), 509 .parent = TYPE_NPCM7XX_MACHINE, 510 .class_init = kudo_bmc_machine_class_init, 511 }, 512 }; 513 514 DEFINE_TYPES(npcm7xx_machine_types) 515