1 /* 2 * TI OMAP processors emulation. 3 * 4 * Copyright (C) 2006-2008 Andrzej Zaborowski <balrog@zabor.org> 5 * 6 * This program is free software; you can redistribute it and/or 7 * modify it under the terms of the GNU General Public License as 8 * published by the Free Software Foundation; either version 2 or 9 * (at your option) version 3 of the License. 10 * 11 * This program is distributed in the hope that it will be useful, 12 * but WITHOUT ANY WARRANTY; without even the implied warranty of 13 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the 14 * GNU General Public License for more details. 15 * 16 * You should have received a copy of the GNU General Public License along 17 * with this program; if not, see <http://www.gnu.org/licenses/>. 18 */ 19 #include "hw/hw.h" 20 #include "hw/arm/arm.h" 21 #include "hw/arm/omap.h" 22 #include "sysemu/sysemu.h" 23 #include "hw/arm/soc_dma.h" 24 #include "sysemu/blockdev.h" 25 #include "qemu/range.h" 26 #include "hw/sysbus.h" 27 28 /* Should signal the TCMI/GPMC */ 29 uint32_t omap_badwidth_read8(void *opaque, hwaddr addr) 30 { 31 uint8_t ret; 32 33 OMAP_8B_REG(addr); 34 cpu_physical_memory_read(addr, &ret, 1); 35 return ret; 36 } 37 38 void omap_badwidth_write8(void *opaque, hwaddr addr, 39 uint32_t value) 40 { 41 uint8_t val8 = value; 42 43 OMAP_8B_REG(addr); 44 cpu_physical_memory_write(addr, &val8, 1); 45 } 46 47 uint32_t omap_badwidth_read16(void *opaque, hwaddr addr) 48 { 49 uint16_t ret; 50 51 OMAP_16B_REG(addr); 52 cpu_physical_memory_read(addr, &ret, 2); 53 return ret; 54 } 55 56 void omap_badwidth_write16(void *opaque, hwaddr addr, 57 uint32_t value) 58 { 59 uint16_t val16 = value; 60 61 OMAP_16B_REG(addr); 62 cpu_physical_memory_write(addr, &val16, 2); 63 } 64 65 uint32_t omap_badwidth_read32(void *opaque, hwaddr addr) 66 { 67 uint32_t ret; 68 69 OMAP_32B_REG(addr); 70 cpu_physical_memory_read(addr, &ret, 4); 71 return ret; 72 } 73 74 void omap_badwidth_write32(void *opaque, hwaddr addr, 75 uint32_t value) 76 { 77 OMAP_32B_REG(addr); 78 cpu_physical_memory_write(addr, &value, 4); 79 } 80 81 /* MPU OS timers */ 82 struct omap_mpu_timer_s { 83 MemoryRegion iomem; 84 qemu_irq irq; 85 omap_clk clk; 86 uint32_t val; 87 int64_t time; 88 QEMUTimer *timer; 89 QEMUBH *tick; 90 int64_t rate; 91 int it_ena; 92 93 int enable; 94 int ptv; 95 int ar; 96 int st; 97 uint32_t reset_val; 98 }; 99 100 static inline uint32_t omap_timer_read(struct omap_mpu_timer_s *timer) 101 { 102 uint64_t distance = qemu_clock_get_ns(QEMU_CLOCK_VIRTUAL) - timer->time; 103 104 if (timer->st && timer->enable && timer->rate) 105 return timer->val - muldiv64(distance >> (timer->ptv + 1), 106 timer->rate, get_ticks_per_sec()); 107 else 108 return timer->val; 109 } 110 111 static inline void omap_timer_sync(struct omap_mpu_timer_s *timer) 112 { 113 timer->val = omap_timer_read(timer); 114 timer->time = qemu_clock_get_ns(QEMU_CLOCK_VIRTUAL); 115 } 116 117 static inline void omap_timer_update(struct omap_mpu_timer_s *timer) 118 { 119 int64_t expires; 120 121 if (timer->enable && timer->st && timer->rate) { 122 timer->val = timer->reset_val; /* Should skip this on clk enable */ 123 expires = muldiv64((uint64_t) timer->val << (timer->ptv + 1), 124 get_ticks_per_sec(), timer->rate); 125 126 /* If timer expiry would be sooner than in about 1 ms and 127 * auto-reload isn't set, then fire immediately. This is a hack 128 * to make systems like PalmOS run in acceptable time. PalmOS 129 * sets the interval to a very low value and polls the status bit 130 * in a busy loop when it wants to sleep just a couple of CPU 131 * ticks. */ 132 if (expires > (get_ticks_per_sec() >> 10) || timer->ar) 133 timer_mod(timer->timer, timer->time + expires); 134 else 135 qemu_bh_schedule(timer->tick); 136 } else 137 timer_del(timer->timer); 138 } 139 140 static void omap_timer_fire(void *opaque) 141 { 142 struct omap_mpu_timer_s *timer = opaque; 143 144 if (!timer->ar) { 145 timer->val = 0; 146 timer->st = 0; 147 } 148 149 if (timer->it_ena) 150 /* Edge-triggered irq */ 151 qemu_irq_pulse(timer->irq); 152 } 153 154 static void omap_timer_tick(void *opaque) 155 { 156 struct omap_mpu_timer_s *timer = (struct omap_mpu_timer_s *) opaque; 157 158 omap_timer_sync(timer); 159 omap_timer_fire(timer); 160 omap_timer_update(timer); 161 } 162 163 static void omap_timer_clk_update(void *opaque, int line, int on) 164 { 165 struct omap_mpu_timer_s *timer = (struct omap_mpu_timer_s *) opaque; 166 167 omap_timer_sync(timer); 168 timer->rate = on ? omap_clk_getrate(timer->clk) : 0; 169 omap_timer_update(timer); 170 } 171 172 static void omap_timer_clk_setup(struct omap_mpu_timer_s *timer) 173 { 174 omap_clk_adduser(timer->clk, 175 qemu_allocate_irqs(omap_timer_clk_update, timer, 1)[0]); 176 timer->rate = omap_clk_getrate(timer->clk); 177 } 178 179 static uint64_t omap_mpu_timer_read(void *opaque, hwaddr addr, 180 unsigned size) 181 { 182 struct omap_mpu_timer_s *s = (struct omap_mpu_timer_s *) opaque; 183 184 if (size != 4) { 185 return omap_badwidth_read32(opaque, addr); 186 } 187 188 switch (addr) { 189 case 0x00: /* CNTL_TIMER */ 190 return (s->enable << 5) | (s->ptv << 2) | (s->ar << 1) | s->st; 191 192 case 0x04: /* LOAD_TIM */ 193 break; 194 195 case 0x08: /* READ_TIM */ 196 return omap_timer_read(s); 197 } 198 199 OMAP_BAD_REG(addr); 200 return 0; 201 } 202 203 static void omap_mpu_timer_write(void *opaque, hwaddr addr, 204 uint64_t value, unsigned size) 205 { 206 struct omap_mpu_timer_s *s = (struct omap_mpu_timer_s *) opaque; 207 208 if (size != 4) { 209 return omap_badwidth_write32(opaque, addr, value); 210 } 211 212 switch (addr) { 213 case 0x00: /* CNTL_TIMER */ 214 omap_timer_sync(s); 215 s->enable = (value >> 5) & 1; 216 s->ptv = (value >> 2) & 7; 217 s->ar = (value >> 1) & 1; 218 s->st = value & 1; 219 omap_timer_update(s); 220 return; 221 222 case 0x04: /* LOAD_TIM */ 223 s->reset_val = value; 224 return; 225 226 case 0x08: /* READ_TIM */ 227 OMAP_RO_REG(addr); 228 break; 229 230 default: 231 OMAP_BAD_REG(addr); 232 } 233 } 234 235 static const MemoryRegionOps omap_mpu_timer_ops = { 236 .read = omap_mpu_timer_read, 237 .write = omap_mpu_timer_write, 238 .endianness = DEVICE_LITTLE_ENDIAN, 239 }; 240 241 static void omap_mpu_timer_reset(struct omap_mpu_timer_s *s) 242 { 243 timer_del(s->timer); 244 s->enable = 0; 245 s->reset_val = 31337; 246 s->val = 0; 247 s->ptv = 0; 248 s->ar = 0; 249 s->st = 0; 250 s->it_ena = 1; 251 } 252 253 static struct omap_mpu_timer_s *omap_mpu_timer_init(MemoryRegion *system_memory, 254 hwaddr base, 255 qemu_irq irq, omap_clk clk) 256 { 257 struct omap_mpu_timer_s *s = (struct omap_mpu_timer_s *) 258 g_malloc0(sizeof(struct omap_mpu_timer_s)); 259 260 s->irq = irq; 261 s->clk = clk; 262 s->timer = timer_new_ns(QEMU_CLOCK_VIRTUAL, omap_timer_tick, s); 263 s->tick = qemu_bh_new(omap_timer_fire, s); 264 omap_mpu_timer_reset(s); 265 omap_timer_clk_setup(s); 266 267 memory_region_init_io(&s->iomem, NULL, &omap_mpu_timer_ops, s, 268 "omap-mpu-timer", 0x100); 269 270 memory_region_add_subregion(system_memory, base, &s->iomem); 271 272 return s; 273 } 274 275 /* Watchdog timer */ 276 struct omap_watchdog_timer_s { 277 struct omap_mpu_timer_s timer; 278 MemoryRegion iomem; 279 uint8_t last_wr; 280 int mode; 281 int free; 282 int reset; 283 }; 284 285 static uint64_t omap_wd_timer_read(void *opaque, hwaddr addr, 286 unsigned size) 287 { 288 struct omap_watchdog_timer_s *s = (struct omap_watchdog_timer_s *) opaque; 289 290 if (size != 2) { 291 return omap_badwidth_read16(opaque, addr); 292 } 293 294 switch (addr) { 295 case 0x00: /* CNTL_TIMER */ 296 return (s->timer.ptv << 9) | (s->timer.ar << 8) | 297 (s->timer.st << 7) | (s->free << 1); 298 299 case 0x04: /* READ_TIMER */ 300 return omap_timer_read(&s->timer); 301 302 case 0x08: /* TIMER_MODE */ 303 return s->mode << 15; 304 } 305 306 OMAP_BAD_REG(addr); 307 return 0; 308 } 309 310 static void omap_wd_timer_write(void *opaque, hwaddr addr, 311 uint64_t value, unsigned size) 312 { 313 struct omap_watchdog_timer_s *s = (struct omap_watchdog_timer_s *) opaque; 314 315 if (size != 2) { 316 return omap_badwidth_write16(opaque, addr, value); 317 } 318 319 switch (addr) { 320 case 0x00: /* CNTL_TIMER */ 321 omap_timer_sync(&s->timer); 322 s->timer.ptv = (value >> 9) & 7; 323 s->timer.ar = (value >> 8) & 1; 324 s->timer.st = (value >> 7) & 1; 325 s->free = (value >> 1) & 1; 326 omap_timer_update(&s->timer); 327 break; 328 329 case 0x04: /* LOAD_TIMER */ 330 s->timer.reset_val = value & 0xffff; 331 break; 332 333 case 0x08: /* TIMER_MODE */ 334 if (!s->mode && ((value >> 15) & 1)) 335 omap_clk_get(s->timer.clk); 336 s->mode |= (value >> 15) & 1; 337 if (s->last_wr == 0xf5) { 338 if ((value & 0xff) == 0xa0) { 339 if (s->mode) { 340 s->mode = 0; 341 omap_clk_put(s->timer.clk); 342 } 343 } else { 344 /* XXX: on T|E hardware somehow this has no effect, 345 * on Zire 71 it works as specified. */ 346 s->reset = 1; 347 qemu_system_reset_request(); 348 } 349 } 350 s->last_wr = value & 0xff; 351 break; 352 353 default: 354 OMAP_BAD_REG(addr); 355 } 356 } 357 358 static const MemoryRegionOps omap_wd_timer_ops = { 359 .read = omap_wd_timer_read, 360 .write = omap_wd_timer_write, 361 .endianness = DEVICE_NATIVE_ENDIAN, 362 }; 363 364 static void omap_wd_timer_reset(struct omap_watchdog_timer_s *s) 365 { 366 timer_del(s->timer.timer); 367 if (!s->mode) 368 omap_clk_get(s->timer.clk); 369 s->mode = 1; 370 s->free = 1; 371 s->reset = 0; 372 s->timer.enable = 1; 373 s->timer.it_ena = 1; 374 s->timer.reset_val = 0xffff; 375 s->timer.val = 0; 376 s->timer.st = 0; 377 s->timer.ptv = 0; 378 s->timer.ar = 0; 379 omap_timer_update(&s->timer); 380 } 381 382 static struct omap_watchdog_timer_s *omap_wd_timer_init(MemoryRegion *memory, 383 hwaddr base, 384 qemu_irq irq, omap_clk clk) 385 { 386 struct omap_watchdog_timer_s *s = (struct omap_watchdog_timer_s *) 387 g_malloc0(sizeof(struct omap_watchdog_timer_s)); 388 389 s->timer.irq = irq; 390 s->timer.clk = clk; 391 s->timer.timer = timer_new_ns(QEMU_CLOCK_VIRTUAL, omap_timer_tick, &s->timer); 392 omap_wd_timer_reset(s); 393 omap_timer_clk_setup(&s->timer); 394 395 memory_region_init_io(&s->iomem, NULL, &omap_wd_timer_ops, s, 396 "omap-wd-timer", 0x100); 397 memory_region_add_subregion(memory, base, &s->iomem); 398 399 return s; 400 } 401 402 /* 32-kHz timer */ 403 struct omap_32khz_timer_s { 404 struct omap_mpu_timer_s timer; 405 MemoryRegion iomem; 406 }; 407 408 static uint64_t omap_os_timer_read(void *opaque, hwaddr addr, 409 unsigned size) 410 { 411 struct omap_32khz_timer_s *s = (struct omap_32khz_timer_s *) opaque; 412 int offset = addr & OMAP_MPUI_REG_MASK; 413 414 if (size != 4) { 415 return omap_badwidth_read32(opaque, addr); 416 } 417 418 switch (offset) { 419 case 0x00: /* TVR */ 420 return s->timer.reset_val; 421 422 case 0x04: /* TCR */ 423 return omap_timer_read(&s->timer); 424 425 case 0x08: /* CR */ 426 return (s->timer.ar << 3) | (s->timer.it_ena << 2) | s->timer.st; 427 428 default: 429 break; 430 } 431 OMAP_BAD_REG(addr); 432 return 0; 433 } 434 435 static void omap_os_timer_write(void *opaque, hwaddr addr, 436 uint64_t value, unsigned size) 437 { 438 struct omap_32khz_timer_s *s = (struct omap_32khz_timer_s *) opaque; 439 int offset = addr & OMAP_MPUI_REG_MASK; 440 441 if (size != 4) { 442 return omap_badwidth_write32(opaque, addr, value); 443 } 444 445 switch (offset) { 446 case 0x00: /* TVR */ 447 s->timer.reset_val = value & 0x00ffffff; 448 break; 449 450 case 0x04: /* TCR */ 451 OMAP_RO_REG(addr); 452 break; 453 454 case 0x08: /* CR */ 455 s->timer.ar = (value >> 3) & 1; 456 s->timer.it_ena = (value >> 2) & 1; 457 if (s->timer.st != (value & 1) || (value & 2)) { 458 omap_timer_sync(&s->timer); 459 s->timer.enable = value & 1; 460 s->timer.st = value & 1; 461 omap_timer_update(&s->timer); 462 } 463 break; 464 465 default: 466 OMAP_BAD_REG(addr); 467 } 468 } 469 470 static const MemoryRegionOps omap_os_timer_ops = { 471 .read = omap_os_timer_read, 472 .write = omap_os_timer_write, 473 .endianness = DEVICE_NATIVE_ENDIAN, 474 }; 475 476 static void omap_os_timer_reset(struct omap_32khz_timer_s *s) 477 { 478 timer_del(s->timer.timer); 479 s->timer.enable = 0; 480 s->timer.it_ena = 0; 481 s->timer.reset_val = 0x00ffffff; 482 s->timer.val = 0; 483 s->timer.st = 0; 484 s->timer.ptv = 0; 485 s->timer.ar = 1; 486 } 487 488 static struct omap_32khz_timer_s *omap_os_timer_init(MemoryRegion *memory, 489 hwaddr base, 490 qemu_irq irq, omap_clk clk) 491 { 492 struct omap_32khz_timer_s *s = (struct omap_32khz_timer_s *) 493 g_malloc0(sizeof(struct omap_32khz_timer_s)); 494 495 s->timer.irq = irq; 496 s->timer.clk = clk; 497 s->timer.timer = timer_new_ns(QEMU_CLOCK_VIRTUAL, omap_timer_tick, &s->timer); 498 omap_os_timer_reset(s); 499 omap_timer_clk_setup(&s->timer); 500 501 memory_region_init_io(&s->iomem, NULL, &omap_os_timer_ops, s, 502 "omap-os-timer", 0x800); 503 memory_region_add_subregion(memory, base, &s->iomem); 504 505 return s; 506 } 507 508 /* Ultra Low-Power Device Module */ 509 static uint64_t omap_ulpd_pm_read(void *opaque, hwaddr addr, 510 unsigned size) 511 { 512 struct omap_mpu_state_s *s = (struct omap_mpu_state_s *) opaque; 513 uint16_t ret; 514 515 if (size != 2) { 516 return omap_badwidth_read16(opaque, addr); 517 } 518 519 switch (addr) { 520 case 0x14: /* IT_STATUS */ 521 ret = s->ulpd_pm_regs[addr >> 2]; 522 s->ulpd_pm_regs[addr >> 2] = 0; 523 qemu_irq_lower(qdev_get_gpio_in(s->ih[1], OMAP_INT_GAUGE_32K)); 524 return ret; 525 526 case 0x18: /* Reserved */ 527 case 0x1c: /* Reserved */ 528 case 0x20: /* Reserved */ 529 case 0x28: /* Reserved */ 530 case 0x2c: /* Reserved */ 531 OMAP_BAD_REG(addr); 532 /* fall through */ 533 case 0x00: /* COUNTER_32_LSB */ 534 case 0x04: /* COUNTER_32_MSB */ 535 case 0x08: /* COUNTER_HIGH_FREQ_LSB */ 536 case 0x0c: /* COUNTER_HIGH_FREQ_MSB */ 537 case 0x10: /* GAUGING_CTRL */ 538 case 0x24: /* SETUP_ANALOG_CELL3_ULPD1 */ 539 case 0x30: /* CLOCK_CTRL */ 540 case 0x34: /* SOFT_REQ */ 541 case 0x38: /* COUNTER_32_FIQ */ 542 case 0x3c: /* DPLL_CTRL */ 543 case 0x40: /* STATUS_REQ */ 544 /* XXX: check clk::usecount state for every clock */ 545 case 0x48: /* LOCL_TIME */ 546 case 0x4c: /* APLL_CTRL */ 547 case 0x50: /* POWER_CTRL */ 548 return s->ulpd_pm_regs[addr >> 2]; 549 } 550 551 OMAP_BAD_REG(addr); 552 return 0; 553 } 554 555 static inline void omap_ulpd_clk_update(struct omap_mpu_state_s *s, 556 uint16_t diff, uint16_t value) 557 { 558 if (diff & (1 << 4)) /* USB_MCLK_EN */ 559 omap_clk_onoff(omap_findclk(s, "usb_clk0"), (value >> 4) & 1); 560 if (diff & (1 << 5)) /* DIS_USB_PVCI_CLK */ 561 omap_clk_onoff(omap_findclk(s, "usb_w2fc_ck"), (~value >> 5) & 1); 562 } 563 564 static inline void omap_ulpd_req_update(struct omap_mpu_state_s *s, 565 uint16_t diff, uint16_t value) 566 { 567 if (diff & (1 << 0)) /* SOFT_DPLL_REQ */ 568 omap_clk_canidle(omap_findclk(s, "dpll4"), (~value >> 0) & 1); 569 if (diff & (1 << 1)) /* SOFT_COM_REQ */ 570 omap_clk_canidle(omap_findclk(s, "com_mclk_out"), (~value >> 1) & 1); 571 if (diff & (1 << 2)) /* SOFT_SDW_REQ */ 572 omap_clk_canidle(omap_findclk(s, "bt_mclk_out"), (~value >> 2) & 1); 573 if (diff & (1 << 3)) /* SOFT_USB_REQ */ 574 omap_clk_canidle(omap_findclk(s, "usb_clk0"), (~value >> 3) & 1); 575 } 576 577 static void omap_ulpd_pm_write(void *opaque, hwaddr addr, 578 uint64_t value, unsigned size) 579 { 580 struct omap_mpu_state_s *s = (struct omap_mpu_state_s *) opaque; 581 int64_t now, ticks; 582 int div, mult; 583 static const int bypass_div[4] = { 1, 2, 4, 4 }; 584 uint16_t diff; 585 586 if (size != 2) { 587 return omap_badwidth_write16(opaque, addr, value); 588 } 589 590 switch (addr) { 591 case 0x00: /* COUNTER_32_LSB */ 592 case 0x04: /* COUNTER_32_MSB */ 593 case 0x08: /* COUNTER_HIGH_FREQ_LSB */ 594 case 0x0c: /* COUNTER_HIGH_FREQ_MSB */ 595 case 0x14: /* IT_STATUS */ 596 case 0x40: /* STATUS_REQ */ 597 OMAP_RO_REG(addr); 598 break; 599 600 case 0x10: /* GAUGING_CTRL */ 601 /* Bits 0 and 1 seem to be confused in the OMAP 310 TRM */ 602 if ((s->ulpd_pm_regs[addr >> 2] ^ value) & 1) { 603 now = qemu_clock_get_ns(QEMU_CLOCK_VIRTUAL); 604 605 if (value & 1) 606 s->ulpd_gauge_start = now; 607 else { 608 now -= s->ulpd_gauge_start; 609 610 /* 32-kHz ticks */ 611 ticks = muldiv64(now, 32768, get_ticks_per_sec()); 612 s->ulpd_pm_regs[0x00 >> 2] = (ticks >> 0) & 0xffff; 613 s->ulpd_pm_regs[0x04 >> 2] = (ticks >> 16) & 0xffff; 614 if (ticks >> 32) /* OVERFLOW_32K */ 615 s->ulpd_pm_regs[0x14 >> 2] |= 1 << 2; 616 617 /* High frequency ticks */ 618 ticks = muldiv64(now, 12000000, get_ticks_per_sec()); 619 s->ulpd_pm_regs[0x08 >> 2] = (ticks >> 0) & 0xffff; 620 s->ulpd_pm_regs[0x0c >> 2] = (ticks >> 16) & 0xffff; 621 if (ticks >> 32) /* OVERFLOW_HI_FREQ */ 622 s->ulpd_pm_regs[0x14 >> 2] |= 1 << 1; 623 624 s->ulpd_pm_regs[0x14 >> 2] |= 1 << 0; /* IT_GAUGING */ 625 qemu_irq_raise(qdev_get_gpio_in(s->ih[1], OMAP_INT_GAUGE_32K)); 626 } 627 } 628 s->ulpd_pm_regs[addr >> 2] = value; 629 break; 630 631 case 0x18: /* Reserved */ 632 case 0x1c: /* Reserved */ 633 case 0x20: /* Reserved */ 634 case 0x28: /* Reserved */ 635 case 0x2c: /* Reserved */ 636 OMAP_BAD_REG(addr); 637 /* fall through */ 638 case 0x24: /* SETUP_ANALOG_CELL3_ULPD1 */ 639 case 0x38: /* COUNTER_32_FIQ */ 640 case 0x48: /* LOCL_TIME */ 641 case 0x50: /* POWER_CTRL */ 642 s->ulpd_pm_regs[addr >> 2] = value; 643 break; 644 645 case 0x30: /* CLOCK_CTRL */ 646 diff = s->ulpd_pm_regs[addr >> 2] ^ value; 647 s->ulpd_pm_regs[addr >> 2] = value & 0x3f; 648 omap_ulpd_clk_update(s, diff, value); 649 break; 650 651 case 0x34: /* SOFT_REQ */ 652 diff = s->ulpd_pm_regs[addr >> 2] ^ value; 653 s->ulpd_pm_regs[addr >> 2] = value & 0x1f; 654 omap_ulpd_req_update(s, diff, value); 655 break; 656 657 case 0x3c: /* DPLL_CTRL */ 658 /* XXX: OMAP310 TRM claims bit 3 is PLL_ENABLE, and bit 4 is 659 * omitted altogether, probably a typo. */ 660 /* This register has identical semantics with DPLL(1:3) control 661 * registers, see omap_dpll_write() */ 662 diff = s->ulpd_pm_regs[addr >> 2] & value; 663 s->ulpd_pm_regs[addr >> 2] = value & 0x2fff; 664 if (diff & (0x3ff << 2)) { 665 if (value & (1 << 4)) { /* PLL_ENABLE */ 666 div = ((value >> 5) & 3) + 1; /* PLL_DIV */ 667 mult = MIN((value >> 7) & 0x1f, 1); /* PLL_MULT */ 668 } else { 669 div = bypass_div[((value >> 2) & 3)]; /* BYPASS_DIV */ 670 mult = 1; 671 } 672 omap_clk_setrate(omap_findclk(s, "dpll4"), div, mult); 673 } 674 675 /* Enter the desired mode. */ 676 s->ulpd_pm_regs[addr >> 2] = 677 (s->ulpd_pm_regs[addr >> 2] & 0xfffe) | 678 ((s->ulpd_pm_regs[addr >> 2] >> 4) & 1); 679 680 /* Act as if the lock is restored. */ 681 s->ulpd_pm_regs[addr >> 2] |= 2; 682 break; 683 684 case 0x4c: /* APLL_CTRL */ 685 diff = s->ulpd_pm_regs[addr >> 2] & value; 686 s->ulpd_pm_regs[addr >> 2] = value & 0xf; 687 if (diff & (1 << 0)) /* APLL_NDPLL_SWITCH */ 688 omap_clk_reparent(omap_findclk(s, "ck_48m"), omap_findclk(s, 689 (value & (1 << 0)) ? "apll" : "dpll4")); 690 break; 691 692 default: 693 OMAP_BAD_REG(addr); 694 } 695 } 696 697 static const MemoryRegionOps omap_ulpd_pm_ops = { 698 .read = omap_ulpd_pm_read, 699 .write = omap_ulpd_pm_write, 700 .endianness = DEVICE_NATIVE_ENDIAN, 701 }; 702 703 static void omap_ulpd_pm_reset(struct omap_mpu_state_s *mpu) 704 { 705 mpu->ulpd_pm_regs[0x00 >> 2] = 0x0001; 706 mpu->ulpd_pm_regs[0x04 >> 2] = 0x0000; 707 mpu->ulpd_pm_regs[0x08 >> 2] = 0x0001; 708 mpu->ulpd_pm_regs[0x0c >> 2] = 0x0000; 709 mpu->ulpd_pm_regs[0x10 >> 2] = 0x0000; 710 mpu->ulpd_pm_regs[0x18 >> 2] = 0x01; 711 mpu->ulpd_pm_regs[0x1c >> 2] = 0x01; 712 mpu->ulpd_pm_regs[0x20 >> 2] = 0x01; 713 mpu->ulpd_pm_regs[0x24 >> 2] = 0x03ff; 714 mpu->ulpd_pm_regs[0x28 >> 2] = 0x01; 715 mpu->ulpd_pm_regs[0x2c >> 2] = 0x01; 716 omap_ulpd_clk_update(mpu, mpu->ulpd_pm_regs[0x30 >> 2], 0x0000); 717 mpu->ulpd_pm_regs[0x30 >> 2] = 0x0000; 718 omap_ulpd_req_update(mpu, mpu->ulpd_pm_regs[0x34 >> 2], 0x0000); 719 mpu->ulpd_pm_regs[0x34 >> 2] = 0x0000; 720 mpu->ulpd_pm_regs[0x38 >> 2] = 0x0001; 721 mpu->ulpd_pm_regs[0x3c >> 2] = 0x2211; 722 mpu->ulpd_pm_regs[0x40 >> 2] = 0x0000; /* FIXME: dump a real STATUS_REQ */ 723 mpu->ulpd_pm_regs[0x48 >> 2] = 0x960; 724 mpu->ulpd_pm_regs[0x4c >> 2] = 0x08; 725 mpu->ulpd_pm_regs[0x50 >> 2] = 0x08; 726 omap_clk_setrate(omap_findclk(mpu, "dpll4"), 1, 4); 727 omap_clk_reparent(omap_findclk(mpu, "ck_48m"), omap_findclk(mpu, "dpll4")); 728 } 729 730 static void omap_ulpd_pm_init(MemoryRegion *system_memory, 731 hwaddr base, 732 struct omap_mpu_state_s *mpu) 733 { 734 memory_region_init_io(&mpu->ulpd_pm_iomem, NULL, &omap_ulpd_pm_ops, mpu, 735 "omap-ulpd-pm", 0x800); 736 memory_region_add_subregion(system_memory, base, &mpu->ulpd_pm_iomem); 737 omap_ulpd_pm_reset(mpu); 738 } 739 740 /* OMAP Pin Configuration */ 741 static uint64_t omap_pin_cfg_read(void *opaque, hwaddr addr, 742 unsigned size) 743 { 744 struct omap_mpu_state_s *s = (struct omap_mpu_state_s *) opaque; 745 746 if (size != 4) { 747 return omap_badwidth_read32(opaque, addr); 748 } 749 750 switch (addr) { 751 case 0x00: /* FUNC_MUX_CTRL_0 */ 752 case 0x04: /* FUNC_MUX_CTRL_1 */ 753 case 0x08: /* FUNC_MUX_CTRL_2 */ 754 return s->func_mux_ctrl[addr >> 2]; 755 756 case 0x0c: /* COMP_MODE_CTRL_0 */ 757 return s->comp_mode_ctrl[0]; 758 759 case 0x10: /* FUNC_MUX_CTRL_3 */ 760 case 0x14: /* FUNC_MUX_CTRL_4 */ 761 case 0x18: /* FUNC_MUX_CTRL_5 */ 762 case 0x1c: /* FUNC_MUX_CTRL_6 */ 763 case 0x20: /* FUNC_MUX_CTRL_7 */ 764 case 0x24: /* FUNC_MUX_CTRL_8 */ 765 case 0x28: /* FUNC_MUX_CTRL_9 */ 766 case 0x2c: /* FUNC_MUX_CTRL_A */ 767 case 0x30: /* FUNC_MUX_CTRL_B */ 768 case 0x34: /* FUNC_MUX_CTRL_C */ 769 case 0x38: /* FUNC_MUX_CTRL_D */ 770 return s->func_mux_ctrl[(addr >> 2) - 1]; 771 772 case 0x40: /* PULL_DWN_CTRL_0 */ 773 case 0x44: /* PULL_DWN_CTRL_1 */ 774 case 0x48: /* PULL_DWN_CTRL_2 */ 775 case 0x4c: /* PULL_DWN_CTRL_3 */ 776 return s->pull_dwn_ctrl[(addr & 0xf) >> 2]; 777 778 case 0x50: /* GATE_INH_CTRL_0 */ 779 return s->gate_inh_ctrl[0]; 780 781 case 0x60: /* VOLTAGE_CTRL_0 */ 782 return s->voltage_ctrl[0]; 783 784 case 0x70: /* TEST_DBG_CTRL_0 */ 785 return s->test_dbg_ctrl[0]; 786 787 case 0x80: /* MOD_CONF_CTRL_0 */ 788 return s->mod_conf_ctrl[0]; 789 } 790 791 OMAP_BAD_REG(addr); 792 return 0; 793 } 794 795 static inline void omap_pin_funcmux0_update(struct omap_mpu_state_s *s, 796 uint32_t diff, uint32_t value) 797 { 798 if (s->compat1509) { 799 if (diff & (1 << 9)) /* BLUETOOTH */ 800 omap_clk_onoff(omap_findclk(s, "bt_mclk_out"), 801 (~value >> 9) & 1); 802 if (diff & (1 << 7)) /* USB.CLKO */ 803 omap_clk_onoff(omap_findclk(s, "usb.clko"), 804 (value >> 7) & 1); 805 } 806 } 807 808 static inline void omap_pin_funcmux1_update(struct omap_mpu_state_s *s, 809 uint32_t diff, uint32_t value) 810 { 811 if (s->compat1509) { 812 if (diff & (1U << 31)) { 813 /* MCBSP3_CLK_HIZ_DI */ 814 omap_clk_onoff(omap_findclk(s, "mcbsp3.clkx"), (value >> 31) & 1); 815 } 816 if (diff & (1 << 1)) { 817 /* CLK32K */ 818 omap_clk_onoff(omap_findclk(s, "clk32k_out"), (~value >> 1) & 1); 819 } 820 } 821 } 822 823 static inline void omap_pin_modconf1_update(struct omap_mpu_state_s *s, 824 uint32_t diff, uint32_t value) 825 { 826 if (diff & (1U << 31)) { 827 /* CONF_MOD_UART3_CLK_MODE_R */ 828 omap_clk_reparent(omap_findclk(s, "uart3_ck"), 829 omap_findclk(s, ((value >> 31) & 1) ? 830 "ck_48m" : "armper_ck")); 831 } 832 if (diff & (1 << 30)) /* CONF_MOD_UART2_CLK_MODE_R */ 833 omap_clk_reparent(omap_findclk(s, "uart2_ck"), 834 omap_findclk(s, ((value >> 30) & 1) ? 835 "ck_48m" : "armper_ck")); 836 if (diff & (1 << 29)) /* CONF_MOD_UART1_CLK_MODE_R */ 837 omap_clk_reparent(omap_findclk(s, "uart1_ck"), 838 omap_findclk(s, ((value >> 29) & 1) ? 839 "ck_48m" : "armper_ck")); 840 if (diff & (1 << 23)) /* CONF_MOD_MMC_SD_CLK_REQ_R */ 841 omap_clk_reparent(omap_findclk(s, "mmc_ck"), 842 omap_findclk(s, ((value >> 23) & 1) ? 843 "ck_48m" : "armper_ck")); 844 if (diff & (1 << 12)) /* CONF_MOD_COM_MCLK_12_48_S */ 845 omap_clk_reparent(omap_findclk(s, "com_mclk_out"), 846 omap_findclk(s, ((value >> 12) & 1) ? 847 "ck_48m" : "armper_ck")); 848 if (diff & (1 << 9)) /* CONF_MOD_USB_HOST_HHC_UHO */ 849 omap_clk_onoff(omap_findclk(s, "usb_hhc_ck"), (value >> 9) & 1); 850 } 851 852 static void omap_pin_cfg_write(void *opaque, hwaddr addr, 853 uint64_t value, unsigned size) 854 { 855 struct omap_mpu_state_s *s = (struct omap_mpu_state_s *) opaque; 856 uint32_t diff; 857 858 if (size != 4) { 859 return omap_badwidth_write32(opaque, addr, value); 860 } 861 862 switch (addr) { 863 case 0x00: /* FUNC_MUX_CTRL_0 */ 864 diff = s->func_mux_ctrl[addr >> 2] ^ value; 865 s->func_mux_ctrl[addr >> 2] = value; 866 omap_pin_funcmux0_update(s, diff, value); 867 return; 868 869 case 0x04: /* FUNC_MUX_CTRL_1 */ 870 diff = s->func_mux_ctrl[addr >> 2] ^ value; 871 s->func_mux_ctrl[addr >> 2] = value; 872 omap_pin_funcmux1_update(s, diff, value); 873 return; 874 875 case 0x08: /* FUNC_MUX_CTRL_2 */ 876 s->func_mux_ctrl[addr >> 2] = value; 877 return; 878 879 case 0x0c: /* COMP_MODE_CTRL_0 */ 880 s->comp_mode_ctrl[0] = value; 881 s->compat1509 = (value != 0x0000eaef); 882 omap_pin_funcmux0_update(s, ~0, s->func_mux_ctrl[0]); 883 omap_pin_funcmux1_update(s, ~0, s->func_mux_ctrl[1]); 884 return; 885 886 case 0x10: /* FUNC_MUX_CTRL_3 */ 887 case 0x14: /* FUNC_MUX_CTRL_4 */ 888 case 0x18: /* FUNC_MUX_CTRL_5 */ 889 case 0x1c: /* FUNC_MUX_CTRL_6 */ 890 case 0x20: /* FUNC_MUX_CTRL_7 */ 891 case 0x24: /* FUNC_MUX_CTRL_8 */ 892 case 0x28: /* FUNC_MUX_CTRL_9 */ 893 case 0x2c: /* FUNC_MUX_CTRL_A */ 894 case 0x30: /* FUNC_MUX_CTRL_B */ 895 case 0x34: /* FUNC_MUX_CTRL_C */ 896 case 0x38: /* FUNC_MUX_CTRL_D */ 897 s->func_mux_ctrl[(addr >> 2) - 1] = value; 898 return; 899 900 case 0x40: /* PULL_DWN_CTRL_0 */ 901 case 0x44: /* PULL_DWN_CTRL_1 */ 902 case 0x48: /* PULL_DWN_CTRL_2 */ 903 case 0x4c: /* PULL_DWN_CTRL_3 */ 904 s->pull_dwn_ctrl[(addr & 0xf) >> 2] = value; 905 return; 906 907 case 0x50: /* GATE_INH_CTRL_0 */ 908 s->gate_inh_ctrl[0] = value; 909 return; 910 911 case 0x60: /* VOLTAGE_CTRL_0 */ 912 s->voltage_ctrl[0] = value; 913 return; 914 915 case 0x70: /* TEST_DBG_CTRL_0 */ 916 s->test_dbg_ctrl[0] = value; 917 return; 918 919 case 0x80: /* MOD_CONF_CTRL_0 */ 920 diff = s->mod_conf_ctrl[0] ^ value; 921 s->mod_conf_ctrl[0] = value; 922 omap_pin_modconf1_update(s, diff, value); 923 return; 924 925 default: 926 OMAP_BAD_REG(addr); 927 } 928 } 929 930 static const MemoryRegionOps omap_pin_cfg_ops = { 931 .read = omap_pin_cfg_read, 932 .write = omap_pin_cfg_write, 933 .endianness = DEVICE_NATIVE_ENDIAN, 934 }; 935 936 static void omap_pin_cfg_reset(struct omap_mpu_state_s *mpu) 937 { 938 /* Start in Compatibility Mode. */ 939 mpu->compat1509 = 1; 940 omap_pin_funcmux0_update(mpu, mpu->func_mux_ctrl[0], 0); 941 omap_pin_funcmux1_update(mpu, mpu->func_mux_ctrl[1], 0); 942 omap_pin_modconf1_update(mpu, mpu->mod_conf_ctrl[0], 0); 943 memset(mpu->func_mux_ctrl, 0, sizeof(mpu->func_mux_ctrl)); 944 memset(mpu->comp_mode_ctrl, 0, sizeof(mpu->comp_mode_ctrl)); 945 memset(mpu->pull_dwn_ctrl, 0, sizeof(mpu->pull_dwn_ctrl)); 946 memset(mpu->gate_inh_ctrl, 0, sizeof(mpu->gate_inh_ctrl)); 947 memset(mpu->voltage_ctrl, 0, sizeof(mpu->voltage_ctrl)); 948 memset(mpu->test_dbg_ctrl, 0, sizeof(mpu->test_dbg_ctrl)); 949 memset(mpu->mod_conf_ctrl, 0, sizeof(mpu->mod_conf_ctrl)); 950 } 951 952 static void omap_pin_cfg_init(MemoryRegion *system_memory, 953 hwaddr base, 954 struct omap_mpu_state_s *mpu) 955 { 956 memory_region_init_io(&mpu->pin_cfg_iomem, NULL, &omap_pin_cfg_ops, mpu, 957 "omap-pin-cfg", 0x800); 958 memory_region_add_subregion(system_memory, base, &mpu->pin_cfg_iomem); 959 omap_pin_cfg_reset(mpu); 960 } 961 962 /* Device Identification, Die Identification */ 963 static uint64_t omap_id_read(void *opaque, hwaddr addr, 964 unsigned size) 965 { 966 struct omap_mpu_state_s *s = (struct omap_mpu_state_s *) opaque; 967 968 if (size != 4) { 969 return omap_badwidth_read32(opaque, addr); 970 } 971 972 switch (addr) { 973 case 0xfffe1800: /* DIE_ID_LSB */ 974 return 0xc9581f0e; 975 case 0xfffe1804: /* DIE_ID_MSB */ 976 return 0xa8858bfa; 977 978 case 0xfffe2000: /* PRODUCT_ID_LSB */ 979 return 0x00aaaafc; 980 case 0xfffe2004: /* PRODUCT_ID_MSB */ 981 return 0xcafeb574; 982 983 case 0xfffed400: /* JTAG_ID_LSB */ 984 switch (s->mpu_model) { 985 case omap310: 986 return 0x03310315; 987 case omap1510: 988 return 0x03310115; 989 default: 990 hw_error("%s: bad mpu model\n", __FUNCTION__); 991 } 992 break; 993 994 case 0xfffed404: /* JTAG_ID_MSB */ 995 switch (s->mpu_model) { 996 case omap310: 997 return 0xfb57402f; 998 case omap1510: 999 return 0xfb47002f; 1000 default: 1001 hw_error("%s: bad mpu model\n", __FUNCTION__); 1002 } 1003 break; 1004 } 1005 1006 OMAP_BAD_REG(addr); 1007 return 0; 1008 } 1009 1010 static void omap_id_write(void *opaque, hwaddr addr, 1011 uint64_t value, unsigned size) 1012 { 1013 if (size != 4) { 1014 return omap_badwidth_write32(opaque, addr, value); 1015 } 1016 1017 OMAP_BAD_REG(addr); 1018 } 1019 1020 static const MemoryRegionOps omap_id_ops = { 1021 .read = omap_id_read, 1022 .write = omap_id_write, 1023 .endianness = DEVICE_NATIVE_ENDIAN, 1024 }; 1025 1026 static void omap_id_init(MemoryRegion *memory, struct omap_mpu_state_s *mpu) 1027 { 1028 memory_region_init_io(&mpu->id_iomem, NULL, &omap_id_ops, mpu, 1029 "omap-id", 0x100000000ULL); 1030 memory_region_init_alias(&mpu->id_iomem_e18, NULL, "omap-id-e18", &mpu->id_iomem, 1031 0xfffe1800, 0x800); 1032 memory_region_add_subregion(memory, 0xfffe1800, &mpu->id_iomem_e18); 1033 memory_region_init_alias(&mpu->id_iomem_ed4, NULL, "omap-id-ed4", &mpu->id_iomem, 1034 0xfffed400, 0x100); 1035 memory_region_add_subregion(memory, 0xfffed400, &mpu->id_iomem_ed4); 1036 if (!cpu_is_omap15xx(mpu)) { 1037 memory_region_init_alias(&mpu->id_iomem_ed4, NULL, "omap-id-e20", 1038 &mpu->id_iomem, 0xfffe2000, 0x800); 1039 memory_region_add_subregion(memory, 0xfffe2000, &mpu->id_iomem_e20); 1040 } 1041 } 1042 1043 /* MPUI Control (Dummy) */ 1044 static uint64_t omap_mpui_read(void *opaque, hwaddr addr, 1045 unsigned size) 1046 { 1047 struct omap_mpu_state_s *s = (struct omap_mpu_state_s *) opaque; 1048 1049 if (size != 4) { 1050 return omap_badwidth_read32(opaque, addr); 1051 } 1052 1053 switch (addr) { 1054 case 0x00: /* CTRL */ 1055 return s->mpui_ctrl; 1056 case 0x04: /* DEBUG_ADDR */ 1057 return 0x01ffffff; 1058 case 0x08: /* DEBUG_DATA */ 1059 return 0xffffffff; 1060 case 0x0c: /* DEBUG_FLAG */ 1061 return 0x00000800; 1062 case 0x10: /* STATUS */ 1063 return 0x00000000; 1064 1065 /* Not in OMAP310 */ 1066 case 0x14: /* DSP_STATUS */ 1067 case 0x18: /* DSP_BOOT_CONFIG */ 1068 return 0x00000000; 1069 case 0x1c: /* DSP_MPUI_CONFIG */ 1070 return 0x0000ffff; 1071 } 1072 1073 OMAP_BAD_REG(addr); 1074 return 0; 1075 } 1076 1077 static void omap_mpui_write(void *opaque, hwaddr addr, 1078 uint64_t value, unsigned size) 1079 { 1080 struct omap_mpu_state_s *s = (struct omap_mpu_state_s *) opaque; 1081 1082 if (size != 4) { 1083 return omap_badwidth_write32(opaque, addr, value); 1084 } 1085 1086 switch (addr) { 1087 case 0x00: /* CTRL */ 1088 s->mpui_ctrl = value & 0x007fffff; 1089 break; 1090 1091 case 0x04: /* DEBUG_ADDR */ 1092 case 0x08: /* DEBUG_DATA */ 1093 case 0x0c: /* DEBUG_FLAG */ 1094 case 0x10: /* STATUS */ 1095 /* Not in OMAP310 */ 1096 case 0x14: /* DSP_STATUS */ 1097 OMAP_RO_REG(addr); 1098 break; 1099 case 0x18: /* DSP_BOOT_CONFIG */ 1100 case 0x1c: /* DSP_MPUI_CONFIG */ 1101 break; 1102 1103 default: 1104 OMAP_BAD_REG(addr); 1105 } 1106 } 1107 1108 static const MemoryRegionOps omap_mpui_ops = { 1109 .read = omap_mpui_read, 1110 .write = omap_mpui_write, 1111 .endianness = DEVICE_NATIVE_ENDIAN, 1112 }; 1113 1114 static void omap_mpui_reset(struct omap_mpu_state_s *s) 1115 { 1116 s->mpui_ctrl = 0x0003ff1b; 1117 } 1118 1119 static void omap_mpui_init(MemoryRegion *memory, hwaddr base, 1120 struct omap_mpu_state_s *mpu) 1121 { 1122 memory_region_init_io(&mpu->mpui_iomem, NULL, &omap_mpui_ops, mpu, 1123 "omap-mpui", 0x100); 1124 memory_region_add_subregion(memory, base, &mpu->mpui_iomem); 1125 1126 omap_mpui_reset(mpu); 1127 } 1128 1129 /* TIPB Bridges */ 1130 struct omap_tipb_bridge_s { 1131 qemu_irq abort; 1132 MemoryRegion iomem; 1133 1134 int width_intr; 1135 uint16_t control; 1136 uint16_t alloc; 1137 uint16_t buffer; 1138 uint16_t enh_control; 1139 }; 1140 1141 static uint64_t omap_tipb_bridge_read(void *opaque, hwaddr addr, 1142 unsigned size) 1143 { 1144 struct omap_tipb_bridge_s *s = (struct omap_tipb_bridge_s *) opaque; 1145 1146 if (size < 2) { 1147 return omap_badwidth_read16(opaque, addr); 1148 } 1149 1150 switch (addr) { 1151 case 0x00: /* TIPB_CNTL */ 1152 return s->control; 1153 case 0x04: /* TIPB_BUS_ALLOC */ 1154 return s->alloc; 1155 case 0x08: /* MPU_TIPB_CNTL */ 1156 return s->buffer; 1157 case 0x0c: /* ENHANCED_TIPB_CNTL */ 1158 return s->enh_control; 1159 case 0x10: /* ADDRESS_DBG */ 1160 case 0x14: /* DATA_DEBUG_LOW */ 1161 case 0x18: /* DATA_DEBUG_HIGH */ 1162 return 0xffff; 1163 case 0x1c: /* DEBUG_CNTR_SIG */ 1164 return 0x00f8; 1165 } 1166 1167 OMAP_BAD_REG(addr); 1168 return 0; 1169 } 1170 1171 static void omap_tipb_bridge_write(void *opaque, hwaddr addr, 1172 uint64_t value, unsigned size) 1173 { 1174 struct omap_tipb_bridge_s *s = (struct omap_tipb_bridge_s *) opaque; 1175 1176 if (size < 2) { 1177 return omap_badwidth_write16(opaque, addr, value); 1178 } 1179 1180 switch (addr) { 1181 case 0x00: /* TIPB_CNTL */ 1182 s->control = value & 0xffff; 1183 break; 1184 1185 case 0x04: /* TIPB_BUS_ALLOC */ 1186 s->alloc = value & 0x003f; 1187 break; 1188 1189 case 0x08: /* MPU_TIPB_CNTL */ 1190 s->buffer = value & 0x0003; 1191 break; 1192 1193 case 0x0c: /* ENHANCED_TIPB_CNTL */ 1194 s->width_intr = !(value & 2); 1195 s->enh_control = value & 0x000f; 1196 break; 1197 1198 case 0x10: /* ADDRESS_DBG */ 1199 case 0x14: /* DATA_DEBUG_LOW */ 1200 case 0x18: /* DATA_DEBUG_HIGH */ 1201 case 0x1c: /* DEBUG_CNTR_SIG */ 1202 OMAP_RO_REG(addr); 1203 break; 1204 1205 default: 1206 OMAP_BAD_REG(addr); 1207 } 1208 } 1209 1210 static const MemoryRegionOps omap_tipb_bridge_ops = { 1211 .read = omap_tipb_bridge_read, 1212 .write = omap_tipb_bridge_write, 1213 .endianness = DEVICE_NATIVE_ENDIAN, 1214 }; 1215 1216 static void omap_tipb_bridge_reset(struct omap_tipb_bridge_s *s) 1217 { 1218 s->control = 0xffff; 1219 s->alloc = 0x0009; 1220 s->buffer = 0x0000; 1221 s->enh_control = 0x000f; 1222 } 1223 1224 static struct omap_tipb_bridge_s *omap_tipb_bridge_init( 1225 MemoryRegion *memory, hwaddr base, 1226 qemu_irq abort_irq, omap_clk clk) 1227 { 1228 struct omap_tipb_bridge_s *s = (struct omap_tipb_bridge_s *) 1229 g_malloc0(sizeof(struct omap_tipb_bridge_s)); 1230 1231 s->abort = abort_irq; 1232 omap_tipb_bridge_reset(s); 1233 1234 memory_region_init_io(&s->iomem, NULL, &omap_tipb_bridge_ops, s, 1235 "omap-tipb-bridge", 0x100); 1236 memory_region_add_subregion(memory, base, &s->iomem); 1237 1238 return s; 1239 } 1240 1241 /* Dummy Traffic Controller's Memory Interface */ 1242 static uint64_t omap_tcmi_read(void *opaque, hwaddr addr, 1243 unsigned size) 1244 { 1245 struct omap_mpu_state_s *s = (struct omap_mpu_state_s *) opaque; 1246 uint32_t ret; 1247 1248 if (size != 4) { 1249 return omap_badwidth_read32(opaque, addr); 1250 } 1251 1252 switch (addr) { 1253 case 0x00: /* IMIF_PRIO */ 1254 case 0x04: /* EMIFS_PRIO */ 1255 case 0x08: /* EMIFF_PRIO */ 1256 case 0x0c: /* EMIFS_CONFIG */ 1257 case 0x10: /* EMIFS_CS0_CONFIG */ 1258 case 0x14: /* EMIFS_CS1_CONFIG */ 1259 case 0x18: /* EMIFS_CS2_CONFIG */ 1260 case 0x1c: /* EMIFS_CS3_CONFIG */ 1261 case 0x24: /* EMIFF_MRS */ 1262 case 0x28: /* TIMEOUT1 */ 1263 case 0x2c: /* TIMEOUT2 */ 1264 case 0x30: /* TIMEOUT3 */ 1265 case 0x3c: /* EMIFF_SDRAM_CONFIG_2 */ 1266 case 0x40: /* EMIFS_CFG_DYN_WAIT */ 1267 return s->tcmi_regs[addr >> 2]; 1268 1269 case 0x20: /* EMIFF_SDRAM_CONFIG */ 1270 ret = s->tcmi_regs[addr >> 2]; 1271 s->tcmi_regs[addr >> 2] &= ~1; /* XXX: Clear SLRF on SDRAM access */ 1272 /* XXX: We can try using the VGA_DIRTY flag for this */ 1273 return ret; 1274 } 1275 1276 OMAP_BAD_REG(addr); 1277 return 0; 1278 } 1279 1280 static void omap_tcmi_write(void *opaque, hwaddr addr, 1281 uint64_t value, unsigned size) 1282 { 1283 struct omap_mpu_state_s *s = (struct omap_mpu_state_s *) opaque; 1284 1285 if (size != 4) { 1286 return omap_badwidth_write32(opaque, addr, value); 1287 } 1288 1289 switch (addr) { 1290 case 0x00: /* IMIF_PRIO */ 1291 case 0x04: /* EMIFS_PRIO */ 1292 case 0x08: /* EMIFF_PRIO */ 1293 case 0x10: /* EMIFS_CS0_CONFIG */ 1294 case 0x14: /* EMIFS_CS1_CONFIG */ 1295 case 0x18: /* EMIFS_CS2_CONFIG */ 1296 case 0x1c: /* EMIFS_CS3_CONFIG */ 1297 case 0x20: /* EMIFF_SDRAM_CONFIG */ 1298 case 0x24: /* EMIFF_MRS */ 1299 case 0x28: /* TIMEOUT1 */ 1300 case 0x2c: /* TIMEOUT2 */ 1301 case 0x30: /* TIMEOUT3 */ 1302 case 0x3c: /* EMIFF_SDRAM_CONFIG_2 */ 1303 case 0x40: /* EMIFS_CFG_DYN_WAIT */ 1304 s->tcmi_regs[addr >> 2] = value; 1305 break; 1306 case 0x0c: /* EMIFS_CONFIG */ 1307 s->tcmi_regs[addr >> 2] = (value & 0xf) | (1 << 4); 1308 break; 1309 1310 default: 1311 OMAP_BAD_REG(addr); 1312 } 1313 } 1314 1315 static const MemoryRegionOps omap_tcmi_ops = { 1316 .read = omap_tcmi_read, 1317 .write = omap_tcmi_write, 1318 .endianness = DEVICE_NATIVE_ENDIAN, 1319 }; 1320 1321 static void omap_tcmi_reset(struct omap_mpu_state_s *mpu) 1322 { 1323 mpu->tcmi_regs[0x00 >> 2] = 0x00000000; 1324 mpu->tcmi_regs[0x04 >> 2] = 0x00000000; 1325 mpu->tcmi_regs[0x08 >> 2] = 0x00000000; 1326 mpu->tcmi_regs[0x0c >> 2] = 0x00000010; 1327 mpu->tcmi_regs[0x10 >> 2] = 0x0010fffb; 1328 mpu->tcmi_regs[0x14 >> 2] = 0x0010fffb; 1329 mpu->tcmi_regs[0x18 >> 2] = 0x0010fffb; 1330 mpu->tcmi_regs[0x1c >> 2] = 0x0010fffb; 1331 mpu->tcmi_regs[0x20 >> 2] = 0x00618800; 1332 mpu->tcmi_regs[0x24 >> 2] = 0x00000037; 1333 mpu->tcmi_regs[0x28 >> 2] = 0x00000000; 1334 mpu->tcmi_regs[0x2c >> 2] = 0x00000000; 1335 mpu->tcmi_regs[0x30 >> 2] = 0x00000000; 1336 mpu->tcmi_regs[0x3c >> 2] = 0x00000003; 1337 mpu->tcmi_regs[0x40 >> 2] = 0x00000000; 1338 } 1339 1340 static void omap_tcmi_init(MemoryRegion *memory, hwaddr base, 1341 struct omap_mpu_state_s *mpu) 1342 { 1343 memory_region_init_io(&mpu->tcmi_iomem, NULL, &omap_tcmi_ops, mpu, 1344 "omap-tcmi", 0x100); 1345 memory_region_add_subregion(memory, base, &mpu->tcmi_iomem); 1346 omap_tcmi_reset(mpu); 1347 } 1348 1349 /* Digital phase-locked loops control */ 1350 struct dpll_ctl_s { 1351 MemoryRegion iomem; 1352 uint16_t mode; 1353 omap_clk dpll; 1354 }; 1355 1356 static uint64_t omap_dpll_read(void *opaque, hwaddr addr, 1357 unsigned size) 1358 { 1359 struct dpll_ctl_s *s = (struct dpll_ctl_s *) opaque; 1360 1361 if (size != 2) { 1362 return omap_badwidth_read16(opaque, addr); 1363 } 1364 1365 if (addr == 0x00) /* CTL_REG */ 1366 return s->mode; 1367 1368 OMAP_BAD_REG(addr); 1369 return 0; 1370 } 1371 1372 static void omap_dpll_write(void *opaque, hwaddr addr, 1373 uint64_t value, unsigned size) 1374 { 1375 struct dpll_ctl_s *s = (struct dpll_ctl_s *) opaque; 1376 uint16_t diff; 1377 static const int bypass_div[4] = { 1, 2, 4, 4 }; 1378 int div, mult; 1379 1380 if (size != 2) { 1381 return omap_badwidth_write16(opaque, addr, value); 1382 } 1383 1384 if (addr == 0x00) { /* CTL_REG */ 1385 /* See omap_ulpd_pm_write() too */ 1386 diff = s->mode & value; 1387 s->mode = value & 0x2fff; 1388 if (diff & (0x3ff << 2)) { 1389 if (value & (1 << 4)) { /* PLL_ENABLE */ 1390 div = ((value >> 5) & 3) + 1; /* PLL_DIV */ 1391 mult = MIN((value >> 7) & 0x1f, 1); /* PLL_MULT */ 1392 } else { 1393 div = bypass_div[((value >> 2) & 3)]; /* BYPASS_DIV */ 1394 mult = 1; 1395 } 1396 omap_clk_setrate(s->dpll, div, mult); 1397 } 1398 1399 /* Enter the desired mode. */ 1400 s->mode = (s->mode & 0xfffe) | ((s->mode >> 4) & 1); 1401 1402 /* Act as if the lock is restored. */ 1403 s->mode |= 2; 1404 } else { 1405 OMAP_BAD_REG(addr); 1406 } 1407 } 1408 1409 static const MemoryRegionOps omap_dpll_ops = { 1410 .read = omap_dpll_read, 1411 .write = omap_dpll_write, 1412 .endianness = DEVICE_NATIVE_ENDIAN, 1413 }; 1414 1415 static void omap_dpll_reset(struct dpll_ctl_s *s) 1416 { 1417 s->mode = 0x2002; 1418 omap_clk_setrate(s->dpll, 1, 1); 1419 } 1420 1421 static struct dpll_ctl_s *omap_dpll_init(MemoryRegion *memory, 1422 hwaddr base, omap_clk clk) 1423 { 1424 struct dpll_ctl_s *s = g_malloc0(sizeof(*s)); 1425 memory_region_init_io(&s->iomem, NULL, &omap_dpll_ops, s, "omap-dpll", 0x100); 1426 1427 s->dpll = clk; 1428 omap_dpll_reset(s); 1429 1430 memory_region_add_subregion(memory, base, &s->iomem); 1431 return s; 1432 } 1433 1434 /* MPU Clock/Reset/Power Mode Control */ 1435 static uint64_t omap_clkm_read(void *opaque, hwaddr addr, 1436 unsigned size) 1437 { 1438 struct omap_mpu_state_s *s = (struct omap_mpu_state_s *) opaque; 1439 1440 if (size != 2) { 1441 return omap_badwidth_read16(opaque, addr); 1442 } 1443 1444 switch (addr) { 1445 case 0x00: /* ARM_CKCTL */ 1446 return s->clkm.arm_ckctl; 1447 1448 case 0x04: /* ARM_IDLECT1 */ 1449 return s->clkm.arm_idlect1; 1450 1451 case 0x08: /* ARM_IDLECT2 */ 1452 return s->clkm.arm_idlect2; 1453 1454 case 0x0c: /* ARM_EWUPCT */ 1455 return s->clkm.arm_ewupct; 1456 1457 case 0x10: /* ARM_RSTCT1 */ 1458 return s->clkm.arm_rstct1; 1459 1460 case 0x14: /* ARM_RSTCT2 */ 1461 return s->clkm.arm_rstct2; 1462 1463 case 0x18: /* ARM_SYSST */ 1464 return (s->clkm.clocking_scheme << 11) | s->clkm.cold_start; 1465 1466 case 0x1c: /* ARM_CKOUT1 */ 1467 return s->clkm.arm_ckout1; 1468 1469 case 0x20: /* ARM_CKOUT2 */ 1470 break; 1471 } 1472 1473 OMAP_BAD_REG(addr); 1474 return 0; 1475 } 1476 1477 static inline void omap_clkm_ckctl_update(struct omap_mpu_state_s *s, 1478 uint16_t diff, uint16_t value) 1479 { 1480 omap_clk clk; 1481 1482 if (diff & (1 << 14)) { /* ARM_INTHCK_SEL */ 1483 if (value & (1 << 14)) 1484 /* Reserved */; 1485 else { 1486 clk = omap_findclk(s, "arminth_ck"); 1487 omap_clk_reparent(clk, omap_findclk(s, "tc_ck")); 1488 } 1489 } 1490 if (diff & (1 << 12)) { /* ARM_TIMXO */ 1491 clk = omap_findclk(s, "armtim_ck"); 1492 if (value & (1 << 12)) 1493 omap_clk_reparent(clk, omap_findclk(s, "clkin")); 1494 else 1495 omap_clk_reparent(clk, omap_findclk(s, "ck_gen1")); 1496 } 1497 /* XXX: en_dspck */ 1498 if (diff & (3 << 10)) { /* DSPMMUDIV */ 1499 clk = omap_findclk(s, "dspmmu_ck"); 1500 omap_clk_setrate(clk, 1 << ((value >> 10) & 3), 1); 1501 } 1502 if (diff & (3 << 8)) { /* TCDIV */ 1503 clk = omap_findclk(s, "tc_ck"); 1504 omap_clk_setrate(clk, 1 << ((value >> 8) & 3), 1); 1505 } 1506 if (diff & (3 << 6)) { /* DSPDIV */ 1507 clk = omap_findclk(s, "dsp_ck"); 1508 omap_clk_setrate(clk, 1 << ((value >> 6) & 3), 1); 1509 } 1510 if (diff & (3 << 4)) { /* ARMDIV */ 1511 clk = omap_findclk(s, "arm_ck"); 1512 omap_clk_setrate(clk, 1 << ((value >> 4) & 3), 1); 1513 } 1514 if (diff & (3 << 2)) { /* LCDDIV */ 1515 clk = omap_findclk(s, "lcd_ck"); 1516 omap_clk_setrate(clk, 1 << ((value >> 2) & 3), 1); 1517 } 1518 if (diff & (3 << 0)) { /* PERDIV */ 1519 clk = omap_findclk(s, "armper_ck"); 1520 omap_clk_setrate(clk, 1 << ((value >> 0) & 3), 1); 1521 } 1522 } 1523 1524 static inline void omap_clkm_idlect1_update(struct omap_mpu_state_s *s, 1525 uint16_t diff, uint16_t value) 1526 { 1527 omap_clk clk; 1528 1529 if (value & (1 << 11)) { /* SETARM_IDLE */ 1530 cpu_interrupt(CPU(s->cpu), CPU_INTERRUPT_HALT); 1531 } 1532 if (!(value & (1 << 10))) /* WKUP_MODE */ 1533 qemu_system_shutdown_request(); /* XXX: disable wakeup from IRQ */ 1534 1535 #define SET_CANIDLE(clock, bit) \ 1536 if (diff & (1 << bit)) { \ 1537 clk = omap_findclk(s, clock); \ 1538 omap_clk_canidle(clk, (value >> bit) & 1); \ 1539 } 1540 SET_CANIDLE("mpuwd_ck", 0) /* IDLWDT_ARM */ 1541 SET_CANIDLE("armxor_ck", 1) /* IDLXORP_ARM */ 1542 SET_CANIDLE("mpuper_ck", 2) /* IDLPER_ARM */ 1543 SET_CANIDLE("lcd_ck", 3) /* IDLLCD_ARM */ 1544 SET_CANIDLE("lb_ck", 4) /* IDLLB_ARM */ 1545 SET_CANIDLE("hsab_ck", 5) /* IDLHSAB_ARM */ 1546 SET_CANIDLE("tipb_ck", 6) /* IDLIF_ARM */ 1547 SET_CANIDLE("dma_ck", 6) /* IDLIF_ARM */ 1548 SET_CANIDLE("tc_ck", 6) /* IDLIF_ARM */ 1549 SET_CANIDLE("dpll1", 7) /* IDLDPLL_ARM */ 1550 SET_CANIDLE("dpll2", 7) /* IDLDPLL_ARM */ 1551 SET_CANIDLE("dpll3", 7) /* IDLDPLL_ARM */ 1552 SET_CANIDLE("mpui_ck", 8) /* IDLAPI_ARM */ 1553 SET_CANIDLE("armtim_ck", 9) /* IDLTIM_ARM */ 1554 } 1555 1556 static inline void omap_clkm_idlect2_update(struct omap_mpu_state_s *s, 1557 uint16_t diff, uint16_t value) 1558 { 1559 omap_clk clk; 1560 1561 #define SET_ONOFF(clock, bit) \ 1562 if (diff & (1 << bit)) { \ 1563 clk = omap_findclk(s, clock); \ 1564 omap_clk_onoff(clk, (value >> bit) & 1); \ 1565 } 1566 SET_ONOFF("mpuwd_ck", 0) /* EN_WDTCK */ 1567 SET_ONOFF("armxor_ck", 1) /* EN_XORPCK */ 1568 SET_ONOFF("mpuper_ck", 2) /* EN_PERCK */ 1569 SET_ONOFF("lcd_ck", 3) /* EN_LCDCK */ 1570 SET_ONOFF("lb_ck", 4) /* EN_LBCK */ 1571 SET_ONOFF("hsab_ck", 5) /* EN_HSABCK */ 1572 SET_ONOFF("mpui_ck", 6) /* EN_APICK */ 1573 SET_ONOFF("armtim_ck", 7) /* EN_TIMCK */ 1574 SET_CANIDLE("dma_ck", 8) /* DMACK_REQ */ 1575 SET_ONOFF("arm_gpio_ck", 9) /* EN_GPIOCK */ 1576 SET_ONOFF("lbfree_ck", 10) /* EN_LBFREECK */ 1577 } 1578 1579 static inline void omap_clkm_ckout1_update(struct omap_mpu_state_s *s, 1580 uint16_t diff, uint16_t value) 1581 { 1582 omap_clk clk; 1583 1584 if (diff & (3 << 4)) { /* TCLKOUT */ 1585 clk = omap_findclk(s, "tclk_out"); 1586 switch ((value >> 4) & 3) { 1587 case 1: 1588 omap_clk_reparent(clk, omap_findclk(s, "ck_gen3")); 1589 omap_clk_onoff(clk, 1); 1590 break; 1591 case 2: 1592 omap_clk_reparent(clk, omap_findclk(s, "tc_ck")); 1593 omap_clk_onoff(clk, 1); 1594 break; 1595 default: 1596 omap_clk_onoff(clk, 0); 1597 } 1598 } 1599 if (diff & (3 << 2)) { /* DCLKOUT */ 1600 clk = omap_findclk(s, "dclk_out"); 1601 switch ((value >> 2) & 3) { 1602 case 0: 1603 omap_clk_reparent(clk, omap_findclk(s, "dspmmu_ck")); 1604 break; 1605 case 1: 1606 omap_clk_reparent(clk, omap_findclk(s, "ck_gen2")); 1607 break; 1608 case 2: 1609 omap_clk_reparent(clk, omap_findclk(s, "dsp_ck")); 1610 break; 1611 case 3: 1612 omap_clk_reparent(clk, omap_findclk(s, "ck_ref14")); 1613 break; 1614 } 1615 } 1616 if (diff & (3 << 0)) { /* ACLKOUT */ 1617 clk = omap_findclk(s, "aclk_out"); 1618 switch ((value >> 0) & 3) { 1619 case 1: 1620 omap_clk_reparent(clk, omap_findclk(s, "ck_gen1")); 1621 omap_clk_onoff(clk, 1); 1622 break; 1623 case 2: 1624 omap_clk_reparent(clk, omap_findclk(s, "arm_ck")); 1625 omap_clk_onoff(clk, 1); 1626 break; 1627 case 3: 1628 omap_clk_reparent(clk, omap_findclk(s, "ck_ref14")); 1629 omap_clk_onoff(clk, 1); 1630 break; 1631 default: 1632 omap_clk_onoff(clk, 0); 1633 } 1634 } 1635 } 1636 1637 static void omap_clkm_write(void *opaque, hwaddr addr, 1638 uint64_t value, unsigned size) 1639 { 1640 struct omap_mpu_state_s *s = (struct omap_mpu_state_s *) opaque; 1641 uint16_t diff; 1642 omap_clk clk; 1643 static const char *clkschemename[8] = { 1644 "fully synchronous", "fully asynchronous", "synchronous scalable", 1645 "mix mode 1", "mix mode 2", "bypass mode", "mix mode 3", "mix mode 4", 1646 }; 1647 1648 if (size != 2) { 1649 return omap_badwidth_write16(opaque, addr, value); 1650 } 1651 1652 switch (addr) { 1653 case 0x00: /* ARM_CKCTL */ 1654 diff = s->clkm.arm_ckctl ^ value; 1655 s->clkm.arm_ckctl = value & 0x7fff; 1656 omap_clkm_ckctl_update(s, diff, value); 1657 return; 1658 1659 case 0x04: /* ARM_IDLECT1 */ 1660 diff = s->clkm.arm_idlect1 ^ value; 1661 s->clkm.arm_idlect1 = value & 0x0fff; 1662 omap_clkm_idlect1_update(s, diff, value); 1663 return; 1664 1665 case 0x08: /* ARM_IDLECT2 */ 1666 diff = s->clkm.arm_idlect2 ^ value; 1667 s->clkm.arm_idlect2 = value & 0x07ff; 1668 omap_clkm_idlect2_update(s, diff, value); 1669 return; 1670 1671 case 0x0c: /* ARM_EWUPCT */ 1672 s->clkm.arm_ewupct = value & 0x003f; 1673 return; 1674 1675 case 0x10: /* ARM_RSTCT1 */ 1676 diff = s->clkm.arm_rstct1 ^ value; 1677 s->clkm.arm_rstct1 = value & 0x0007; 1678 if (value & 9) { 1679 qemu_system_reset_request(); 1680 s->clkm.cold_start = 0xa; 1681 } 1682 if (diff & ~value & 4) { /* DSP_RST */ 1683 omap_mpui_reset(s); 1684 omap_tipb_bridge_reset(s->private_tipb); 1685 omap_tipb_bridge_reset(s->public_tipb); 1686 } 1687 if (diff & 2) { /* DSP_EN */ 1688 clk = omap_findclk(s, "dsp_ck"); 1689 omap_clk_canidle(clk, (~value >> 1) & 1); 1690 } 1691 return; 1692 1693 case 0x14: /* ARM_RSTCT2 */ 1694 s->clkm.arm_rstct2 = value & 0x0001; 1695 return; 1696 1697 case 0x18: /* ARM_SYSST */ 1698 if ((s->clkm.clocking_scheme ^ (value >> 11)) & 7) { 1699 s->clkm.clocking_scheme = (value >> 11) & 7; 1700 printf("%s: clocking scheme set to %s\n", __FUNCTION__, 1701 clkschemename[s->clkm.clocking_scheme]); 1702 } 1703 s->clkm.cold_start &= value & 0x3f; 1704 return; 1705 1706 case 0x1c: /* ARM_CKOUT1 */ 1707 diff = s->clkm.arm_ckout1 ^ value; 1708 s->clkm.arm_ckout1 = value & 0x003f; 1709 omap_clkm_ckout1_update(s, diff, value); 1710 return; 1711 1712 case 0x20: /* ARM_CKOUT2 */ 1713 default: 1714 OMAP_BAD_REG(addr); 1715 } 1716 } 1717 1718 static const MemoryRegionOps omap_clkm_ops = { 1719 .read = omap_clkm_read, 1720 .write = omap_clkm_write, 1721 .endianness = DEVICE_NATIVE_ENDIAN, 1722 }; 1723 1724 static uint64_t omap_clkdsp_read(void *opaque, hwaddr addr, 1725 unsigned size) 1726 { 1727 struct omap_mpu_state_s *s = (struct omap_mpu_state_s *) opaque; 1728 CPUState *cpu = CPU(s->cpu); 1729 1730 if (size != 2) { 1731 return omap_badwidth_read16(opaque, addr); 1732 } 1733 1734 switch (addr) { 1735 case 0x04: /* DSP_IDLECT1 */ 1736 return s->clkm.dsp_idlect1; 1737 1738 case 0x08: /* DSP_IDLECT2 */ 1739 return s->clkm.dsp_idlect2; 1740 1741 case 0x14: /* DSP_RSTCT2 */ 1742 return s->clkm.dsp_rstct2; 1743 1744 case 0x18: /* DSP_SYSST */ 1745 cpu = CPU(s->cpu); 1746 return (s->clkm.clocking_scheme << 11) | s->clkm.cold_start | 1747 (cpu->halted << 6); /* Quite useless... */ 1748 } 1749 1750 OMAP_BAD_REG(addr); 1751 return 0; 1752 } 1753 1754 static inline void omap_clkdsp_idlect1_update(struct omap_mpu_state_s *s, 1755 uint16_t diff, uint16_t value) 1756 { 1757 omap_clk clk; 1758 1759 SET_CANIDLE("dspxor_ck", 1); /* IDLXORP_DSP */ 1760 } 1761 1762 static inline void omap_clkdsp_idlect2_update(struct omap_mpu_state_s *s, 1763 uint16_t diff, uint16_t value) 1764 { 1765 omap_clk clk; 1766 1767 SET_ONOFF("dspxor_ck", 1); /* EN_XORPCK */ 1768 } 1769 1770 static void omap_clkdsp_write(void *opaque, hwaddr addr, 1771 uint64_t value, unsigned size) 1772 { 1773 struct omap_mpu_state_s *s = (struct omap_mpu_state_s *) opaque; 1774 uint16_t diff; 1775 1776 if (size != 2) { 1777 return omap_badwidth_write16(opaque, addr, value); 1778 } 1779 1780 switch (addr) { 1781 case 0x04: /* DSP_IDLECT1 */ 1782 diff = s->clkm.dsp_idlect1 ^ value; 1783 s->clkm.dsp_idlect1 = value & 0x01f7; 1784 omap_clkdsp_idlect1_update(s, diff, value); 1785 break; 1786 1787 case 0x08: /* DSP_IDLECT2 */ 1788 s->clkm.dsp_idlect2 = value & 0x0037; 1789 diff = s->clkm.dsp_idlect1 ^ value; 1790 omap_clkdsp_idlect2_update(s, diff, value); 1791 break; 1792 1793 case 0x14: /* DSP_RSTCT2 */ 1794 s->clkm.dsp_rstct2 = value & 0x0001; 1795 break; 1796 1797 case 0x18: /* DSP_SYSST */ 1798 s->clkm.cold_start &= value & 0x3f; 1799 break; 1800 1801 default: 1802 OMAP_BAD_REG(addr); 1803 } 1804 } 1805 1806 static const MemoryRegionOps omap_clkdsp_ops = { 1807 .read = omap_clkdsp_read, 1808 .write = omap_clkdsp_write, 1809 .endianness = DEVICE_NATIVE_ENDIAN, 1810 }; 1811 1812 static void omap_clkm_reset(struct omap_mpu_state_s *s) 1813 { 1814 if (s->wdt && s->wdt->reset) 1815 s->clkm.cold_start = 0x6; 1816 s->clkm.clocking_scheme = 0; 1817 omap_clkm_ckctl_update(s, ~0, 0x3000); 1818 s->clkm.arm_ckctl = 0x3000; 1819 omap_clkm_idlect1_update(s, s->clkm.arm_idlect1 ^ 0x0400, 0x0400); 1820 s->clkm.arm_idlect1 = 0x0400; 1821 omap_clkm_idlect2_update(s, s->clkm.arm_idlect2 ^ 0x0100, 0x0100); 1822 s->clkm.arm_idlect2 = 0x0100; 1823 s->clkm.arm_ewupct = 0x003f; 1824 s->clkm.arm_rstct1 = 0x0000; 1825 s->clkm.arm_rstct2 = 0x0000; 1826 s->clkm.arm_ckout1 = 0x0015; 1827 s->clkm.dpll1_mode = 0x2002; 1828 omap_clkdsp_idlect1_update(s, s->clkm.dsp_idlect1 ^ 0x0040, 0x0040); 1829 s->clkm.dsp_idlect1 = 0x0040; 1830 omap_clkdsp_idlect2_update(s, ~0, 0x0000); 1831 s->clkm.dsp_idlect2 = 0x0000; 1832 s->clkm.dsp_rstct2 = 0x0000; 1833 } 1834 1835 static void omap_clkm_init(MemoryRegion *memory, hwaddr mpu_base, 1836 hwaddr dsp_base, struct omap_mpu_state_s *s) 1837 { 1838 memory_region_init_io(&s->clkm_iomem, NULL, &omap_clkm_ops, s, 1839 "omap-clkm", 0x100); 1840 memory_region_init_io(&s->clkdsp_iomem, NULL, &omap_clkdsp_ops, s, 1841 "omap-clkdsp", 0x1000); 1842 1843 s->clkm.arm_idlect1 = 0x03ff; 1844 s->clkm.arm_idlect2 = 0x0100; 1845 s->clkm.dsp_idlect1 = 0x0002; 1846 omap_clkm_reset(s); 1847 s->clkm.cold_start = 0x3a; 1848 1849 memory_region_add_subregion(memory, mpu_base, &s->clkm_iomem); 1850 memory_region_add_subregion(memory, dsp_base, &s->clkdsp_iomem); 1851 } 1852 1853 /* MPU I/O */ 1854 struct omap_mpuio_s { 1855 qemu_irq irq; 1856 qemu_irq kbd_irq; 1857 qemu_irq *in; 1858 qemu_irq handler[16]; 1859 qemu_irq wakeup; 1860 MemoryRegion iomem; 1861 1862 uint16_t inputs; 1863 uint16_t outputs; 1864 uint16_t dir; 1865 uint16_t edge; 1866 uint16_t mask; 1867 uint16_t ints; 1868 1869 uint16_t debounce; 1870 uint16_t latch; 1871 uint8_t event; 1872 1873 uint8_t buttons[5]; 1874 uint8_t row_latch; 1875 uint8_t cols; 1876 int kbd_mask; 1877 int clk; 1878 }; 1879 1880 static void omap_mpuio_set(void *opaque, int line, int level) 1881 { 1882 struct omap_mpuio_s *s = (struct omap_mpuio_s *) opaque; 1883 uint16_t prev = s->inputs; 1884 1885 if (level) 1886 s->inputs |= 1 << line; 1887 else 1888 s->inputs &= ~(1 << line); 1889 1890 if (((1 << line) & s->dir & ~s->mask) && s->clk) { 1891 if ((s->edge & s->inputs & ~prev) | (~s->edge & ~s->inputs & prev)) { 1892 s->ints |= 1 << line; 1893 qemu_irq_raise(s->irq); 1894 /* TODO: wakeup */ 1895 } 1896 if ((s->event & (1 << 0)) && /* SET_GPIO_EVENT_MODE */ 1897 (s->event >> 1) == line) /* PIN_SELECT */ 1898 s->latch = s->inputs; 1899 } 1900 } 1901 1902 static void omap_mpuio_kbd_update(struct omap_mpuio_s *s) 1903 { 1904 int i; 1905 uint8_t *row, rows = 0, cols = ~s->cols; 1906 1907 for (row = s->buttons + 4, i = 1 << 4; i; row --, i >>= 1) 1908 if (*row & cols) 1909 rows |= i; 1910 1911 qemu_set_irq(s->kbd_irq, rows && !s->kbd_mask && s->clk); 1912 s->row_latch = ~rows; 1913 } 1914 1915 static uint64_t omap_mpuio_read(void *opaque, hwaddr addr, 1916 unsigned size) 1917 { 1918 struct omap_mpuio_s *s = (struct omap_mpuio_s *) opaque; 1919 int offset = addr & OMAP_MPUI_REG_MASK; 1920 uint16_t ret; 1921 1922 if (size != 2) { 1923 return omap_badwidth_read16(opaque, addr); 1924 } 1925 1926 switch (offset) { 1927 case 0x00: /* INPUT_LATCH */ 1928 return s->inputs; 1929 1930 case 0x04: /* OUTPUT_REG */ 1931 return s->outputs; 1932 1933 case 0x08: /* IO_CNTL */ 1934 return s->dir; 1935 1936 case 0x10: /* KBR_LATCH */ 1937 return s->row_latch; 1938 1939 case 0x14: /* KBC_REG */ 1940 return s->cols; 1941 1942 case 0x18: /* GPIO_EVENT_MODE_REG */ 1943 return s->event; 1944 1945 case 0x1c: /* GPIO_INT_EDGE_REG */ 1946 return s->edge; 1947 1948 case 0x20: /* KBD_INT */ 1949 return (~s->row_latch & 0x1f) && !s->kbd_mask; 1950 1951 case 0x24: /* GPIO_INT */ 1952 ret = s->ints; 1953 s->ints &= s->mask; 1954 if (ret) 1955 qemu_irq_lower(s->irq); 1956 return ret; 1957 1958 case 0x28: /* KBD_MASKIT */ 1959 return s->kbd_mask; 1960 1961 case 0x2c: /* GPIO_MASKIT */ 1962 return s->mask; 1963 1964 case 0x30: /* GPIO_DEBOUNCING_REG */ 1965 return s->debounce; 1966 1967 case 0x34: /* GPIO_LATCH_REG */ 1968 return s->latch; 1969 } 1970 1971 OMAP_BAD_REG(addr); 1972 return 0; 1973 } 1974 1975 static void omap_mpuio_write(void *opaque, hwaddr addr, 1976 uint64_t value, unsigned size) 1977 { 1978 struct omap_mpuio_s *s = (struct omap_mpuio_s *) opaque; 1979 int offset = addr & OMAP_MPUI_REG_MASK; 1980 uint16_t diff; 1981 int ln; 1982 1983 if (size != 2) { 1984 return omap_badwidth_write16(opaque, addr, value); 1985 } 1986 1987 switch (offset) { 1988 case 0x04: /* OUTPUT_REG */ 1989 diff = (s->outputs ^ value) & ~s->dir; 1990 s->outputs = value; 1991 while ((ln = ffs(diff))) { 1992 ln --; 1993 if (s->handler[ln]) 1994 qemu_set_irq(s->handler[ln], (value >> ln) & 1); 1995 diff &= ~(1 << ln); 1996 } 1997 break; 1998 1999 case 0x08: /* IO_CNTL */ 2000 diff = s->outputs & (s->dir ^ value); 2001 s->dir = value; 2002 2003 value = s->outputs & ~s->dir; 2004 while ((ln = ffs(diff))) { 2005 ln --; 2006 if (s->handler[ln]) 2007 qemu_set_irq(s->handler[ln], (value >> ln) & 1); 2008 diff &= ~(1 << ln); 2009 } 2010 break; 2011 2012 case 0x14: /* KBC_REG */ 2013 s->cols = value; 2014 omap_mpuio_kbd_update(s); 2015 break; 2016 2017 case 0x18: /* GPIO_EVENT_MODE_REG */ 2018 s->event = value & 0x1f; 2019 break; 2020 2021 case 0x1c: /* GPIO_INT_EDGE_REG */ 2022 s->edge = value; 2023 break; 2024 2025 case 0x28: /* KBD_MASKIT */ 2026 s->kbd_mask = value & 1; 2027 omap_mpuio_kbd_update(s); 2028 break; 2029 2030 case 0x2c: /* GPIO_MASKIT */ 2031 s->mask = value; 2032 break; 2033 2034 case 0x30: /* GPIO_DEBOUNCING_REG */ 2035 s->debounce = value & 0x1ff; 2036 break; 2037 2038 case 0x00: /* INPUT_LATCH */ 2039 case 0x10: /* KBR_LATCH */ 2040 case 0x20: /* KBD_INT */ 2041 case 0x24: /* GPIO_INT */ 2042 case 0x34: /* GPIO_LATCH_REG */ 2043 OMAP_RO_REG(addr); 2044 return; 2045 2046 default: 2047 OMAP_BAD_REG(addr); 2048 return; 2049 } 2050 } 2051 2052 static const MemoryRegionOps omap_mpuio_ops = { 2053 .read = omap_mpuio_read, 2054 .write = omap_mpuio_write, 2055 .endianness = DEVICE_NATIVE_ENDIAN, 2056 }; 2057 2058 static void omap_mpuio_reset(struct omap_mpuio_s *s) 2059 { 2060 s->inputs = 0; 2061 s->outputs = 0; 2062 s->dir = ~0; 2063 s->event = 0; 2064 s->edge = 0; 2065 s->kbd_mask = 0; 2066 s->mask = 0; 2067 s->debounce = 0; 2068 s->latch = 0; 2069 s->ints = 0; 2070 s->row_latch = 0x1f; 2071 s->clk = 1; 2072 } 2073 2074 static void omap_mpuio_onoff(void *opaque, int line, int on) 2075 { 2076 struct omap_mpuio_s *s = (struct omap_mpuio_s *) opaque; 2077 2078 s->clk = on; 2079 if (on) 2080 omap_mpuio_kbd_update(s); 2081 } 2082 2083 static struct omap_mpuio_s *omap_mpuio_init(MemoryRegion *memory, 2084 hwaddr base, 2085 qemu_irq kbd_int, qemu_irq gpio_int, qemu_irq wakeup, 2086 omap_clk clk) 2087 { 2088 struct omap_mpuio_s *s = (struct omap_mpuio_s *) 2089 g_malloc0(sizeof(struct omap_mpuio_s)); 2090 2091 s->irq = gpio_int; 2092 s->kbd_irq = kbd_int; 2093 s->wakeup = wakeup; 2094 s->in = qemu_allocate_irqs(omap_mpuio_set, s, 16); 2095 omap_mpuio_reset(s); 2096 2097 memory_region_init_io(&s->iomem, NULL, &omap_mpuio_ops, s, 2098 "omap-mpuio", 0x800); 2099 memory_region_add_subregion(memory, base, &s->iomem); 2100 2101 omap_clk_adduser(clk, qemu_allocate_irqs(omap_mpuio_onoff, s, 1)[0]); 2102 2103 return s; 2104 } 2105 2106 qemu_irq *omap_mpuio_in_get(struct omap_mpuio_s *s) 2107 { 2108 return s->in; 2109 } 2110 2111 void omap_mpuio_out_set(struct omap_mpuio_s *s, int line, qemu_irq handler) 2112 { 2113 if (line >= 16 || line < 0) 2114 hw_error("%s: No GPIO line %i\n", __FUNCTION__, line); 2115 s->handler[line] = handler; 2116 } 2117 2118 void omap_mpuio_key(struct omap_mpuio_s *s, int row, int col, int down) 2119 { 2120 if (row >= 5 || row < 0) 2121 hw_error("%s: No key %i-%i\n", __FUNCTION__, col, row); 2122 2123 if (down) 2124 s->buttons[row] |= 1 << col; 2125 else 2126 s->buttons[row] &= ~(1 << col); 2127 2128 omap_mpuio_kbd_update(s); 2129 } 2130 2131 /* MicroWire Interface */ 2132 struct omap_uwire_s { 2133 MemoryRegion iomem; 2134 qemu_irq txirq; 2135 qemu_irq rxirq; 2136 qemu_irq txdrq; 2137 2138 uint16_t txbuf; 2139 uint16_t rxbuf; 2140 uint16_t control; 2141 uint16_t setup[5]; 2142 2143 uWireSlave *chip[4]; 2144 }; 2145 2146 static void omap_uwire_transfer_start(struct omap_uwire_s *s) 2147 { 2148 int chipselect = (s->control >> 10) & 3; /* INDEX */ 2149 uWireSlave *slave = s->chip[chipselect]; 2150 2151 if ((s->control >> 5) & 0x1f) { /* NB_BITS_WR */ 2152 if (s->control & (1 << 12)) /* CS_CMD */ 2153 if (slave && slave->send) 2154 slave->send(slave->opaque, 2155 s->txbuf >> (16 - ((s->control >> 5) & 0x1f))); 2156 s->control &= ~(1 << 14); /* CSRB */ 2157 /* TODO: depending on s->setup[4] bits [1:0] assert an IRQ or 2158 * a DRQ. When is the level IRQ supposed to be reset? */ 2159 } 2160 2161 if ((s->control >> 0) & 0x1f) { /* NB_BITS_RD */ 2162 if (s->control & (1 << 12)) /* CS_CMD */ 2163 if (slave && slave->receive) 2164 s->rxbuf = slave->receive(slave->opaque); 2165 s->control |= 1 << 15; /* RDRB */ 2166 /* TODO: depending on s->setup[4] bits [1:0] assert an IRQ or 2167 * a DRQ. When is the level IRQ supposed to be reset? */ 2168 } 2169 } 2170 2171 static uint64_t omap_uwire_read(void *opaque, hwaddr addr, 2172 unsigned size) 2173 { 2174 struct omap_uwire_s *s = (struct omap_uwire_s *) opaque; 2175 int offset = addr & OMAP_MPUI_REG_MASK; 2176 2177 if (size != 2) { 2178 return omap_badwidth_read16(opaque, addr); 2179 } 2180 2181 switch (offset) { 2182 case 0x00: /* RDR */ 2183 s->control &= ~(1 << 15); /* RDRB */ 2184 return s->rxbuf; 2185 2186 case 0x04: /* CSR */ 2187 return s->control; 2188 2189 case 0x08: /* SR1 */ 2190 return s->setup[0]; 2191 case 0x0c: /* SR2 */ 2192 return s->setup[1]; 2193 case 0x10: /* SR3 */ 2194 return s->setup[2]; 2195 case 0x14: /* SR4 */ 2196 return s->setup[3]; 2197 case 0x18: /* SR5 */ 2198 return s->setup[4]; 2199 } 2200 2201 OMAP_BAD_REG(addr); 2202 return 0; 2203 } 2204 2205 static void omap_uwire_write(void *opaque, hwaddr addr, 2206 uint64_t value, unsigned size) 2207 { 2208 struct omap_uwire_s *s = (struct omap_uwire_s *) opaque; 2209 int offset = addr & OMAP_MPUI_REG_MASK; 2210 2211 if (size != 2) { 2212 return omap_badwidth_write16(opaque, addr, value); 2213 } 2214 2215 switch (offset) { 2216 case 0x00: /* TDR */ 2217 s->txbuf = value; /* TD */ 2218 if ((s->setup[4] & (1 << 2)) && /* AUTO_TX_EN */ 2219 ((s->setup[4] & (1 << 3)) || /* CS_TOGGLE_TX_EN */ 2220 (s->control & (1 << 12)))) { /* CS_CMD */ 2221 s->control |= 1 << 14; /* CSRB */ 2222 omap_uwire_transfer_start(s); 2223 } 2224 break; 2225 2226 case 0x04: /* CSR */ 2227 s->control = value & 0x1fff; 2228 if (value & (1 << 13)) /* START */ 2229 omap_uwire_transfer_start(s); 2230 break; 2231 2232 case 0x08: /* SR1 */ 2233 s->setup[0] = value & 0x003f; 2234 break; 2235 2236 case 0x0c: /* SR2 */ 2237 s->setup[1] = value & 0x0fc0; 2238 break; 2239 2240 case 0x10: /* SR3 */ 2241 s->setup[2] = value & 0x0003; 2242 break; 2243 2244 case 0x14: /* SR4 */ 2245 s->setup[3] = value & 0x0001; 2246 break; 2247 2248 case 0x18: /* SR5 */ 2249 s->setup[4] = value & 0x000f; 2250 break; 2251 2252 default: 2253 OMAP_BAD_REG(addr); 2254 return; 2255 } 2256 } 2257 2258 static const MemoryRegionOps omap_uwire_ops = { 2259 .read = omap_uwire_read, 2260 .write = omap_uwire_write, 2261 .endianness = DEVICE_NATIVE_ENDIAN, 2262 }; 2263 2264 static void omap_uwire_reset(struct omap_uwire_s *s) 2265 { 2266 s->control = 0; 2267 s->setup[0] = 0; 2268 s->setup[1] = 0; 2269 s->setup[2] = 0; 2270 s->setup[3] = 0; 2271 s->setup[4] = 0; 2272 } 2273 2274 static struct omap_uwire_s *omap_uwire_init(MemoryRegion *system_memory, 2275 hwaddr base, 2276 qemu_irq txirq, qemu_irq rxirq, 2277 qemu_irq dma, 2278 omap_clk clk) 2279 { 2280 struct omap_uwire_s *s = (struct omap_uwire_s *) 2281 g_malloc0(sizeof(struct omap_uwire_s)); 2282 2283 s->txirq = txirq; 2284 s->rxirq = rxirq; 2285 s->txdrq = dma; 2286 omap_uwire_reset(s); 2287 2288 memory_region_init_io(&s->iomem, NULL, &omap_uwire_ops, s, "omap-uwire", 0x800); 2289 memory_region_add_subregion(system_memory, base, &s->iomem); 2290 2291 return s; 2292 } 2293 2294 void omap_uwire_attach(struct omap_uwire_s *s, 2295 uWireSlave *slave, int chipselect) 2296 { 2297 if (chipselect < 0 || chipselect > 3) { 2298 fprintf(stderr, "%s: Bad chipselect %i\n", __FUNCTION__, chipselect); 2299 exit(-1); 2300 } 2301 2302 s->chip[chipselect] = slave; 2303 } 2304 2305 /* Pseudonoise Pulse-Width Light Modulator */ 2306 struct omap_pwl_s { 2307 MemoryRegion iomem; 2308 uint8_t output; 2309 uint8_t level; 2310 uint8_t enable; 2311 int clk; 2312 }; 2313 2314 static void omap_pwl_update(struct omap_pwl_s *s) 2315 { 2316 int output = (s->clk && s->enable) ? s->level : 0; 2317 2318 if (output != s->output) { 2319 s->output = output; 2320 printf("%s: Backlight now at %i/256\n", __FUNCTION__, output); 2321 } 2322 } 2323 2324 static uint64_t omap_pwl_read(void *opaque, hwaddr addr, 2325 unsigned size) 2326 { 2327 struct omap_pwl_s *s = (struct omap_pwl_s *) opaque; 2328 int offset = addr & OMAP_MPUI_REG_MASK; 2329 2330 if (size != 1) { 2331 return omap_badwidth_read8(opaque, addr); 2332 } 2333 2334 switch (offset) { 2335 case 0x00: /* PWL_LEVEL */ 2336 return s->level; 2337 case 0x04: /* PWL_CTRL */ 2338 return s->enable; 2339 } 2340 OMAP_BAD_REG(addr); 2341 return 0; 2342 } 2343 2344 static void omap_pwl_write(void *opaque, hwaddr addr, 2345 uint64_t value, unsigned size) 2346 { 2347 struct omap_pwl_s *s = (struct omap_pwl_s *) opaque; 2348 int offset = addr & OMAP_MPUI_REG_MASK; 2349 2350 if (size != 1) { 2351 return omap_badwidth_write8(opaque, addr, value); 2352 } 2353 2354 switch (offset) { 2355 case 0x00: /* PWL_LEVEL */ 2356 s->level = value; 2357 omap_pwl_update(s); 2358 break; 2359 case 0x04: /* PWL_CTRL */ 2360 s->enable = value & 1; 2361 omap_pwl_update(s); 2362 break; 2363 default: 2364 OMAP_BAD_REG(addr); 2365 return; 2366 } 2367 } 2368 2369 static const MemoryRegionOps omap_pwl_ops = { 2370 .read = omap_pwl_read, 2371 .write = omap_pwl_write, 2372 .endianness = DEVICE_NATIVE_ENDIAN, 2373 }; 2374 2375 static void omap_pwl_reset(struct omap_pwl_s *s) 2376 { 2377 s->output = 0; 2378 s->level = 0; 2379 s->enable = 0; 2380 s->clk = 1; 2381 omap_pwl_update(s); 2382 } 2383 2384 static void omap_pwl_clk_update(void *opaque, int line, int on) 2385 { 2386 struct omap_pwl_s *s = (struct omap_pwl_s *) opaque; 2387 2388 s->clk = on; 2389 omap_pwl_update(s); 2390 } 2391 2392 static struct omap_pwl_s *omap_pwl_init(MemoryRegion *system_memory, 2393 hwaddr base, 2394 omap_clk clk) 2395 { 2396 struct omap_pwl_s *s = g_malloc0(sizeof(*s)); 2397 2398 omap_pwl_reset(s); 2399 2400 memory_region_init_io(&s->iomem, NULL, &omap_pwl_ops, s, 2401 "omap-pwl", 0x800); 2402 memory_region_add_subregion(system_memory, base, &s->iomem); 2403 2404 omap_clk_adduser(clk, qemu_allocate_irqs(omap_pwl_clk_update, s, 1)[0]); 2405 return s; 2406 } 2407 2408 /* Pulse-Width Tone module */ 2409 struct omap_pwt_s { 2410 MemoryRegion iomem; 2411 uint8_t frc; 2412 uint8_t vrc; 2413 uint8_t gcr; 2414 omap_clk clk; 2415 }; 2416 2417 static uint64_t omap_pwt_read(void *opaque, hwaddr addr, 2418 unsigned size) 2419 { 2420 struct omap_pwt_s *s = (struct omap_pwt_s *) opaque; 2421 int offset = addr & OMAP_MPUI_REG_MASK; 2422 2423 if (size != 1) { 2424 return omap_badwidth_read8(opaque, addr); 2425 } 2426 2427 switch (offset) { 2428 case 0x00: /* FRC */ 2429 return s->frc; 2430 case 0x04: /* VCR */ 2431 return s->vrc; 2432 case 0x08: /* GCR */ 2433 return s->gcr; 2434 } 2435 OMAP_BAD_REG(addr); 2436 return 0; 2437 } 2438 2439 static void omap_pwt_write(void *opaque, hwaddr addr, 2440 uint64_t value, unsigned size) 2441 { 2442 struct omap_pwt_s *s = (struct omap_pwt_s *) opaque; 2443 int offset = addr & OMAP_MPUI_REG_MASK; 2444 2445 if (size != 1) { 2446 return omap_badwidth_write8(opaque, addr, value); 2447 } 2448 2449 switch (offset) { 2450 case 0x00: /* FRC */ 2451 s->frc = value & 0x3f; 2452 break; 2453 case 0x04: /* VRC */ 2454 if ((value ^ s->vrc) & 1) { 2455 if (value & 1) 2456 printf("%s: %iHz buzz on\n", __FUNCTION__, (int) 2457 /* 1.5 MHz from a 12-MHz or 13-MHz PWT_CLK */ 2458 ((omap_clk_getrate(s->clk) >> 3) / 2459 /* Pre-multiplexer divider */ 2460 ((s->gcr & 2) ? 1 : 154) / 2461 /* Octave multiplexer */ 2462 (2 << (value & 3)) * 2463 /* 101/107 divider */ 2464 ((value & (1 << 2)) ? 101 : 107) * 2465 /* 49/55 divider */ 2466 ((value & (1 << 3)) ? 49 : 55) * 2467 /* 50/63 divider */ 2468 ((value & (1 << 4)) ? 50 : 63) * 2469 /* 80/127 divider */ 2470 ((value & (1 << 5)) ? 80 : 127) / 2471 (107 * 55 * 63 * 127))); 2472 else 2473 printf("%s: silence!\n", __FUNCTION__); 2474 } 2475 s->vrc = value & 0x7f; 2476 break; 2477 case 0x08: /* GCR */ 2478 s->gcr = value & 3; 2479 break; 2480 default: 2481 OMAP_BAD_REG(addr); 2482 return; 2483 } 2484 } 2485 2486 static const MemoryRegionOps omap_pwt_ops = { 2487 .read =omap_pwt_read, 2488 .write = omap_pwt_write, 2489 .endianness = DEVICE_NATIVE_ENDIAN, 2490 }; 2491 2492 static void omap_pwt_reset(struct omap_pwt_s *s) 2493 { 2494 s->frc = 0; 2495 s->vrc = 0; 2496 s->gcr = 0; 2497 } 2498 2499 static struct omap_pwt_s *omap_pwt_init(MemoryRegion *system_memory, 2500 hwaddr base, 2501 omap_clk clk) 2502 { 2503 struct omap_pwt_s *s = g_malloc0(sizeof(*s)); 2504 s->clk = clk; 2505 omap_pwt_reset(s); 2506 2507 memory_region_init_io(&s->iomem, NULL, &omap_pwt_ops, s, 2508 "omap-pwt", 0x800); 2509 memory_region_add_subregion(system_memory, base, &s->iomem); 2510 return s; 2511 } 2512 2513 /* Real-time Clock module */ 2514 struct omap_rtc_s { 2515 MemoryRegion iomem; 2516 qemu_irq irq; 2517 qemu_irq alarm; 2518 QEMUTimer *clk; 2519 2520 uint8_t interrupts; 2521 uint8_t status; 2522 int16_t comp_reg; 2523 int running; 2524 int pm_am; 2525 int auto_comp; 2526 int round; 2527 struct tm alarm_tm; 2528 time_t alarm_ti; 2529 2530 struct tm current_tm; 2531 time_t ti; 2532 uint64_t tick; 2533 }; 2534 2535 static void omap_rtc_interrupts_update(struct omap_rtc_s *s) 2536 { 2537 /* s->alarm is level-triggered */ 2538 qemu_set_irq(s->alarm, (s->status >> 6) & 1); 2539 } 2540 2541 static void omap_rtc_alarm_update(struct omap_rtc_s *s) 2542 { 2543 s->alarm_ti = mktimegm(&s->alarm_tm); 2544 if (s->alarm_ti == -1) 2545 printf("%s: conversion failed\n", __FUNCTION__); 2546 } 2547 2548 static uint64_t omap_rtc_read(void *opaque, hwaddr addr, 2549 unsigned size) 2550 { 2551 struct omap_rtc_s *s = (struct omap_rtc_s *) opaque; 2552 int offset = addr & OMAP_MPUI_REG_MASK; 2553 uint8_t i; 2554 2555 if (size != 1) { 2556 return omap_badwidth_read8(opaque, addr); 2557 } 2558 2559 switch (offset) { 2560 case 0x00: /* SECONDS_REG */ 2561 return to_bcd(s->current_tm.tm_sec); 2562 2563 case 0x04: /* MINUTES_REG */ 2564 return to_bcd(s->current_tm.tm_min); 2565 2566 case 0x08: /* HOURS_REG */ 2567 if (s->pm_am) 2568 return ((s->current_tm.tm_hour > 11) << 7) | 2569 to_bcd(((s->current_tm.tm_hour - 1) % 12) + 1); 2570 else 2571 return to_bcd(s->current_tm.tm_hour); 2572 2573 case 0x0c: /* DAYS_REG */ 2574 return to_bcd(s->current_tm.tm_mday); 2575 2576 case 0x10: /* MONTHS_REG */ 2577 return to_bcd(s->current_tm.tm_mon + 1); 2578 2579 case 0x14: /* YEARS_REG */ 2580 return to_bcd(s->current_tm.tm_year % 100); 2581 2582 case 0x18: /* WEEK_REG */ 2583 return s->current_tm.tm_wday; 2584 2585 case 0x20: /* ALARM_SECONDS_REG */ 2586 return to_bcd(s->alarm_tm.tm_sec); 2587 2588 case 0x24: /* ALARM_MINUTES_REG */ 2589 return to_bcd(s->alarm_tm.tm_min); 2590 2591 case 0x28: /* ALARM_HOURS_REG */ 2592 if (s->pm_am) 2593 return ((s->alarm_tm.tm_hour > 11) << 7) | 2594 to_bcd(((s->alarm_tm.tm_hour - 1) % 12) + 1); 2595 else 2596 return to_bcd(s->alarm_tm.tm_hour); 2597 2598 case 0x2c: /* ALARM_DAYS_REG */ 2599 return to_bcd(s->alarm_tm.tm_mday); 2600 2601 case 0x30: /* ALARM_MONTHS_REG */ 2602 return to_bcd(s->alarm_tm.tm_mon + 1); 2603 2604 case 0x34: /* ALARM_YEARS_REG */ 2605 return to_bcd(s->alarm_tm.tm_year % 100); 2606 2607 case 0x40: /* RTC_CTRL_REG */ 2608 return (s->pm_am << 3) | (s->auto_comp << 2) | 2609 (s->round << 1) | s->running; 2610 2611 case 0x44: /* RTC_STATUS_REG */ 2612 i = s->status; 2613 s->status &= ~0x3d; 2614 return i; 2615 2616 case 0x48: /* RTC_INTERRUPTS_REG */ 2617 return s->interrupts; 2618 2619 case 0x4c: /* RTC_COMP_LSB_REG */ 2620 return ((uint16_t) s->comp_reg) & 0xff; 2621 2622 case 0x50: /* RTC_COMP_MSB_REG */ 2623 return ((uint16_t) s->comp_reg) >> 8; 2624 } 2625 2626 OMAP_BAD_REG(addr); 2627 return 0; 2628 } 2629 2630 static void omap_rtc_write(void *opaque, hwaddr addr, 2631 uint64_t value, unsigned size) 2632 { 2633 struct omap_rtc_s *s = (struct omap_rtc_s *) opaque; 2634 int offset = addr & OMAP_MPUI_REG_MASK; 2635 struct tm new_tm; 2636 time_t ti[2]; 2637 2638 if (size != 1) { 2639 return omap_badwidth_write8(opaque, addr, value); 2640 } 2641 2642 switch (offset) { 2643 case 0x00: /* SECONDS_REG */ 2644 #ifdef ALMDEBUG 2645 printf("RTC SEC_REG <-- %02x\n", value); 2646 #endif 2647 s->ti -= s->current_tm.tm_sec; 2648 s->ti += from_bcd(value); 2649 return; 2650 2651 case 0x04: /* MINUTES_REG */ 2652 #ifdef ALMDEBUG 2653 printf("RTC MIN_REG <-- %02x\n", value); 2654 #endif 2655 s->ti -= s->current_tm.tm_min * 60; 2656 s->ti += from_bcd(value) * 60; 2657 return; 2658 2659 case 0x08: /* HOURS_REG */ 2660 #ifdef ALMDEBUG 2661 printf("RTC HRS_REG <-- %02x\n", value); 2662 #endif 2663 s->ti -= s->current_tm.tm_hour * 3600; 2664 if (s->pm_am) { 2665 s->ti += (from_bcd(value & 0x3f) & 12) * 3600; 2666 s->ti += ((value >> 7) & 1) * 43200; 2667 } else 2668 s->ti += from_bcd(value & 0x3f) * 3600; 2669 return; 2670 2671 case 0x0c: /* DAYS_REG */ 2672 #ifdef ALMDEBUG 2673 printf("RTC DAY_REG <-- %02x\n", value); 2674 #endif 2675 s->ti -= s->current_tm.tm_mday * 86400; 2676 s->ti += from_bcd(value) * 86400; 2677 return; 2678 2679 case 0x10: /* MONTHS_REG */ 2680 #ifdef ALMDEBUG 2681 printf("RTC MTH_REG <-- %02x\n", value); 2682 #endif 2683 memcpy(&new_tm, &s->current_tm, sizeof(new_tm)); 2684 new_tm.tm_mon = from_bcd(value); 2685 ti[0] = mktimegm(&s->current_tm); 2686 ti[1] = mktimegm(&new_tm); 2687 2688 if (ti[0] != -1 && ti[1] != -1) { 2689 s->ti -= ti[0]; 2690 s->ti += ti[1]; 2691 } else { 2692 /* A less accurate version */ 2693 s->ti -= s->current_tm.tm_mon * 2592000; 2694 s->ti += from_bcd(value) * 2592000; 2695 } 2696 return; 2697 2698 case 0x14: /* YEARS_REG */ 2699 #ifdef ALMDEBUG 2700 printf("RTC YRS_REG <-- %02x\n", value); 2701 #endif 2702 memcpy(&new_tm, &s->current_tm, sizeof(new_tm)); 2703 new_tm.tm_year += from_bcd(value) - (new_tm.tm_year % 100); 2704 ti[0] = mktimegm(&s->current_tm); 2705 ti[1] = mktimegm(&new_tm); 2706 2707 if (ti[0] != -1 && ti[1] != -1) { 2708 s->ti -= ti[0]; 2709 s->ti += ti[1]; 2710 } else { 2711 /* A less accurate version */ 2712 s->ti -= (time_t)(s->current_tm.tm_year % 100) * 31536000; 2713 s->ti += (time_t)from_bcd(value) * 31536000; 2714 } 2715 return; 2716 2717 case 0x18: /* WEEK_REG */ 2718 return; /* Ignored */ 2719 2720 case 0x20: /* ALARM_SECONDS_REG */ 2721 #ifdef ALMDEBUG 2722 printf("ALM SEC_REG <-- %02x\n", value); 2723 #endif 2724 s->alarm_tm.tm_sec = from_bcd(value); 2725 omap_rtc_alarm_update(s); 2726 return; 2727 2728 case 0x24: /* ALARM_MINUTES_REG */ 2729 #ifdef ALMDEBUG 2730 printf("ALM MIN_REG <-- %02x\n", value); 2731 #endif 2732 s->alarm_tm.tm_min = from_bcd(value); 2733 omap_rtc_alarm_update(s); 2734 return; 2735 2736 case 0x28: /* ALARM_HOURS_REG */ 2737 #ifdef ALMDEBUG 2738 printf("ALM HRS_REG <-- %02x\n", value); 2739 #endif 2740 if (s->pm_am) 2741 s->alarm_tm.tm_hour = 2742 ((from_bcd(value & 0x3f)) % 12) + 2743 ((value >> 7) & 1) * 12; 2744 else 2745 s->alarm_tm.tm_hour = from_bcd(value); 2746 omap_rtc_alarm_update(s); 2747 return; 2748 2749 case 0x2c: /* ALARM_DAYS_REG */ 2750 #ifdef ALMDEBUG 2751 printf("ALM DAY_REG <-- %02x\n", value); 2752 #endif 2753 s->alarm_tm.tm_mday = from_bcd(value); 2754 omap_rtc_alarm_update(s); 2755 return; 2756 2757 case 0x30: /* ALARM_MONTHS_REG */ 2758 #ifdef ALMDEBUG 2759 printf("ALM MON_REG <-- %02x\n", value); 2760 #endif 2761 s->alarm_tm.tm_mon = from_bcd(value); 2762 omap_rtc_alarm_update(s); 2763 return; 2764 2765 case 0x34: /* ALARM_YEARS_REG */ 2766 #ifdef ALMDEBUG 2767 printf("ALM YRS_REG <-- %02x\n", value); 2768 #endif 2769 s->alarm_tm.tm_year = from_bcd(value); 2770 omap_rtc_alarm_update(s); 2771 return; 2772 2773 case 0x40: /* RTC_CTRL_REG */ 2774 #ifdef ALMDEBUG 2775 printf("RTC CONTROL <-- %02x\n", value); 2776 #endif 2777 s->pm_am = (value >> 3) & 1; 2778 s->auto_comp = (value >> 2) & 1; 2779 s->round = (value >> 1) & 1; 2780 s->running = value & 1; 2781 s->status &= 0xfd; 2782 s->status |= s->running << 1; 2783 return; 2784 2785 case 0x44: /* RTC_STATUS_REG */ 2786 #ifdef ALMDEBUG 2787 printf("RTC STATUSL <-- %02x\n", value); 2788 #endif 2789 s->status &= ~((value & 0xc0) ^ 0x80); 2790 omap_rtc_interrupts_update(s); 2791 return; 2792 2793 case 0x48: /* RTC_INTERRUPTS_REG */ 2794 #ifdef ALMDEBUG 2795 printf("RTC INTRS <-- %02x\n", value); 2796 #endif 2797 s->interrupts = value; 2798 return; 2799 2800 case 0x4c: /* RTC_COMP_LSB_REG */ 2801 #ifdef ALMDEBUG 2802 printf("RTC COMPLSB <-- %02x\n", value); 2803 #endif 2804 s->comp_reg &= 0xff00; 2805 s->comp_reg |= 0x00ff & value; 2806 return; 2807 2808 case 0x50: /* RTC_COMP_MSB_REG */ 2809 #ifdef ALMDEBUG 2810 printf("RTC COMPMSB <-- %02x\n", value); 2811 #endif 2812 s->comp_reg &= 0x00ff; 2813 s->comp_reg |= 0xff00 & (value << 8); 2814 return; 2815 2816 default: 2817 OMAP_BAD_REG(addr); 2818 return; 2819 } 2820 } 2821 2822 static const MemoryRegionOps omap_rtc_ops = { 2823 .read = omap_rtc_read, 2824 .write = omap_rtc_write, 2825 .endianness = DEVICE_NATIVE_ENDIAN, 2826 }; 2827 2828 static void omap_rtc_tick(void *opaque) 2829 { 2830 struct omap_rtc_s *s = opaque; 2831 2832 if (s->round) { 2833 /* Round to nearest full minute. */ 2834 if (s->current_tm.tm_sec < 30) 2835 s->ti -= s->current_tm.tm_sec; 2836 else 2837 s->ti += 60 - s->current_tm.tm_sec; 2838 2839 s->round = 0; 2840 } 2841 2842 localtime_r(&s->ti, &s->current_tm); 2843 2844 if ((s->interrupts & 0x08) && s->ti == s->alarm_ti) { 2845 s->status |= 0x40; 2846 omap_rtc_interrupts_update(s); 2847 } 2848 2849 if (s->interrupts & 0x04) 2850 switch (s->interrupts & 3) { 2851 case 0: 2852 s->status |= 0x04; 2853 qemu_irq_pulse(s->irq); 2854 break; 2855 case 1: 2856 if (s->current_tm.tm_sec) 2857 break; 2858 s->status |= 0x08; 2859 qemu_irq_pulse(s->irq); 2860 break; 2861 case 2: 2862 if (s->current_tm.tm_sec || s->current_tm.tm_min) 2863 break; 2864 s->status |= 0x10; 2865 qemu_irq_pulse(s->irq); 2866 break; 2867 case 3: 2868 if (s->current_tm.tm_sec || 2869 s->current_tm.tm_min || s->current_tm.tm_hour) 2870 break; 2871 s->status |= 0x20; 2872 qemu_irq_pulse(s->irq); 2873 break; 2874 } 2875 2876 /* Move on */ 2877 if (s->running) 2878 s->ti ++; 2879 s->tick += 1000; 2880 2881 /* 2882 * Every full hour add a rough approximation of the compensation 2883 * register to the 32kHz Timer (which drives the RTC) value. 2884 */ 2885 if (s->auto_comp && !s->current_tm.tm_sec && !s->current_tm.tm_min) 2886 s->tick += s->comp_reg * 1000 / 32768; 2887 2888 timer_mod(s->clk, s->tick); 2889 } 2890 2891 static void omap_rtc_reset(struct omap_rtc_s *s) 2892 { 2893 struct tm tm; 2894 2895 s->interrupts = 0; 2896 s->comp_reg = 0; 2897 s->running = 0; 2898 s->pm_am = 0; 2899 s->auto_comp = 0; 2900 s->round = 0; 2901 s->tick = qemu_clock_get_ms(rtc_clock); 2902 memset(&s->alarm_tm, 0, sizeof(s->alarm_tm)); 2903 s->alarm_tm.tm_mday = 0x01; 2904 s->status = 1 << 7; 2905 qemu_get_timedate(&tm, 0); 2906 s->ti = mktimegm(&tm); 2907 2908 omap_rtc_alarm_update(s); 2909 omap_rtc_tick(s); 2910 } 2911 2912 static struct omap_rtc_s *omap_rtc_init(MemoryRegion *system_memory, 2913 hwaddr base, 2914 qemu_irq timerirq, qemu_irq alarmirq, 2915 omap_clk clk) 2916 { 2917 struct omap_rtc_s *s = (struct omap_rtc_s *) 2918 g_malloc0(sizeof(struct omap_rtc_s)); 2919 2920 s->irq = timerirq; 2921 s->alarm = alarmirq; 2922 s->clk = timer_new_ms(rtc_clock, omap_rtc_tick, s); 2923 2924 omap_rtc_reset(s); 2925 2926 memory_region_init_io(&s->iomem, NULL, &omap_rtc_ops, s, 2927 "omap-rtc", 0x800); 2928 memory_region_add_subregion(system_memory, base, &s->iomem); 2929 2930 return s; 2931 } 2932 2933 /* Multi-channel Buffered Serial Port interfaces */ 2934 struct omap_mcbsp_s { 2935 MemoryRegion iomem; 2936 qemu_irq txirq; 2937 qemu_irq rxirq; 2938 qemu_irq txdrq; 2939 qemu_irq rxdrq; 2940 2941 uint16_t spcr[2]; 2942 uint16_t rcr[2]; 2943 uint16_t xcr[2]; 2944 uint16_t srgr[2]; 2945 uint16_t mcr[2]; 2946 uint16_t pcr; 2947 uint16_t rcer[8]; 2948 uint16_t xcer[8]; 2949 int tx_rate; 2950 int rx_rate; 2951 int tx_req; 2952 int rx_req; 2953 2954 I2SCodec *codec; 2955 QEMUTimer *source_timer; 2956 QEMUTimer *sink_timer; 2957 }; 2958 2959 static void omap_mcbsp_intr_update(struct omap_mcbsp_s *s) 2960 { 2961 int irq; 2962 2963 switch ((s->spcr[0] >> 4) & 3) { /* RINTM */ 2964 case 0: 2965 irq = (s->spcr[0] >> 1) & 1; /* RRDY */ 2966 break; 2967 case 3: 2968 irq = (s->spcr[0] >> 3) & 1; /* RSYNCERR */ 2969 break; 2970 default: 2971 irq = 0; 2972 break; 2973 } 2974 2975 if (irq) 2976 qemu_irq_pulse(s->rxirq); 2977 2978 switch ((s->spcr[1] >> 4) & 3) { /* XINTM */ 2979 case 0: 2980 irq = (s->spcr[1] >> 1) & 1; /* XRDY */ 2981 break; 2982 case 3: 2983 irq = (s->spcr[1] >> 3) & 1; /* XSYNCERR */ 2984 break; 2985 default: 2986 irq = 0; 2987 break; 2988 } 2989 2990 if (irq) 2991 qemu_irq_pulse(s->txirq); 2992 } 2993 2994 static void omap_mcbsp_rx_newdata(struct omap_mcbsp_s *s) 2995 { 2996 if ((s->spcr[0] >> 1) & 1) /* RRDY */ 2997 s->spcr[0] |= 1 << 2; /* RFULL */ 2998 s->spcr[0] |= 1 << 1; /* RRDY */ 2999 qemu_irq_raise(s->rxdrq); 3000 omap_mcbsp_intr_update(s); 3001 } 3002 3003 static void omap_mcbsp_source_tick(void *opaque) 3004 { 3005 struct omap_mcbsp_s *s = (struct omap_mcbsp_s *) opaque; 3006 static const int bps[8] = { 0, 1, 1, 2, 2, 2, -255, -255 }; 3007 3008 if (!s->rx_rate) 3009 return; 3010 if (s->rx_req) 3011 printf("%s: Rx FIFO overrun\n", __FUNCTION__); 3012 3013 s->rx_req = s->rx_rate << bps[(s->rcr[0] >> 5) & 7]; 3014 3015 omap_mcbsp_rx_newdata(s); 3016 timer_mod(s->source_timer, qemu_clock_get_ns(QEMU_CLOCK_VIRTUAL) + 3017 get_ticks_per_sec()); 3018 } 3019 3020 static void omap_mcbsp_rx_start(struct omap_mcbsp_s *s) 3021 { 3022 if (!s->codec || !s->codec->rts) 3023 omap_mcbsp_source_tick(s); 3024 else if (s->codec->in.len) { 3025 s->rx_req = s->codec->in.len; 3026 omap_mcbsp_rx_newdata(s); 3027 } 3028 } 3029 3030 static void omap_mcbsp_rx_stop(struct omap_mcbsp_s *s) 3031 { 3032 timer_del(s->source_timer); 3033 } 3034 3035 static void omap_mcbsp_rx_done(struct omap_mcbsp_s *s) 3036 { 3037 s->spcr[0] &= ~(1 << 1); /* RRDY */ 3038 qemu_irq_lower(s->rxdrq); 3039 omap_mcbsp_intr_update(s); 3040 } 3041 3042 static void omap_mcbsp_tx_newdata(struct omap_mcbsp_s *s) 3043 { 3044 s->spcr[1] |= 1 << 1; /* XRDY */ 3045 qemu_irq_raise(s->txdrq); 3046 omap_mcbsp_intr_update(s); 3047 } 3048 3049 static void omap_mcbsp_sink_tick(void *opaque) 3050 { 3051 struct omap_mcbsp_s *s = (struct omap_mcbsp_s *) opaque; 3052 static const int bps[8] = { 0, 1, 1, 2, 2, 2, -255, -255 }; 3053 3054 if (!s->tx_rate) 3055 return; 3056 if (s->tx_req) 3057 printf("%s: Tx FIFO underrun\n", __FUNCTION__); 3058 3059 s->tx_req = s->tx_rate << bps[(s->xcr[0] >> 5) & 7]; 3060 3061 omap_mcbsp_tx_newdata(s); 3062 timer_mod(s->sink_timer, qemu_clock_get_ns(QEMU_CLOCK_VIRTUAL) + 3063 get_ticks_per_sec()); 3064 } 3065 3066 static void omap_mcbsp_tx_start(struct omap_mcbsp_s *s) 3067 { 3068 if (!s->codec || !s->codec->cts) 3069 omap_mcbsp_sink_tick(s); 3070 else if (s->codec->out.size) { 3071 s->tx_req = s->codec->out.size; 3072 omap_mcbsp_tx_newdata(s); 3073 } 3074 } 3075 3076 static void omap_mcbsp_tx_done(struct omap_mcbsp_s *s) 3077 { 3078 s->spcr[1] &= ~(1 << 1); /* XRDY */ 3079 qemu_irq_lower(s->txdrq); 3080 omap_mcbsp_intr_update(s); 3081 if (s->codec && s->codec->cts) 3082 s->codec->tx_swallow(s->codec->opaque); 3083 } 3084 3085 static void omap_mcbsp_tx_stop(struct omap_mcbsp_s *s) 3086 { 3087 s->tx_req = 0; 3088 omap_mcbsp_tx_done(s); 3089 timer_del(s->sink_timer); 3090 } 3091 3092 static void omap_mcbsp_req_update(struct omap_mcbsp_s *s) 3093 { 3094 int prev_rx_rate, prev_tx_rate; 3095 int rx_rate = 0, tx_rate = 0; 3096 int cpu_rate = 1500000; /* XXX */ 3097 3098 /* TODO: check CLKSTP bit */ 3099 if (s->spcr[1] & (1 << 6)) { /* GRST */ 3100 if (s->spcr[0] & (1 << 0)) { /* RRST */ 3101 if ((s->srgr[1] & (1 << 13)) && /* CLKSM */ 3102 (s->pcr & (1 << 8))) { /* CLKRM */ 3103 if (~s->pcr & (1 << 7)) /* SCLKME */ 3104 rx_rate = cpu_rate / 3105 ((s->srgr[0] & 0xff) + 1); /* CLKGDV */ 3106 } else 3107 if (s->codec) 3108 rx_rate = s->codec->rx_rate; 3109 } 3110 3111 if (s->spcr[1] & (1 << 0)) { /* XRST */ 3112 if ((s->srgr[1] & (1 << 13)) && /* CLKSM */ 3113 (s->pcr & (1 << 9))) { /* CLKXM */ 3114 if (~s->pcr & (1 << 7)) /* SCLKME */ 3115 tx_rate = cpu_rate / 3116 ((s->srgr[0] & 0xff) + 1); /* CLKGDV */ 3117 } else 3118 if (s->codec) 3119 tx_rate = s->codec->tx_rate; 3120 } 3121 } 3122 prev_tx_rate = s->tx_rate; 3123 prev_rx_rate = s->rx_rate; 3124 s->tx_rate = tx_rate; 3125 s->rx_rate = rx_rate; 3126 3127 if (s->codec) 3128 s->codec->set_rate(s->codec->opaque, rx_rate, tx_rate); 3129 3130 if (!prev_tx_rate && tx_rate) 3131 omap_mcbsp_tx_start(s); 3132 else if (s->tx_rate && !tx_rate) 3133 omap_mcbsp_tx_stop(s); 3134 3135 if (!prev_rx_rate && rx_rate) 3136 omap_mcbsp_rx_start(s); 3137 else if (prev_tx_rate && !tx_rate) 3138 omap_mcbsp_rx_stop(s); 3139 } 3140 3141 static uint64_t omap_mcbsp_read(void *opaque, hwaddr addr, 3142 unsigned size) 3143 { 3144 struct omap_mcbsp_s *s = (struct omap_mcbsp_s *) opaque; 3145 int offset = addr & OMAP_MPUI_REG_MASK; 3146 uint16_t ret; 3147 3148 if (size != 2) { 3149 return omap_badwidth_read16(opaque, addr); 3150 } 3151 3152 switch (offset) { 3153 case 0x00: /* DRR2 */ 3154 if (((s->rcr[0] >> 5) & 7) < 3) /* RWDLEN1 */ 3155 return 0x0000; 3156 /* Fall through. */ 3157 case 0x02: /* DRR1 */ 3158 if (s->rx_req < 2) { 3159 printf("%s: Rx FIFO underrun\n", __FUNCTION__); 3160 omap_mcbsp_rx_done(s); 3161 } else { 3162 s->tx_req -= 2; 3163 if (s->codec && s->codec->in.len >= 2) { 3164 ret = s->codec->in.fifo[s->codec->in.start ++] << 8; 3165 ret |= s->codec->in.fifo[s->codec->in.start ++]; 3166 s->codec->in.len -= 2; 3167 } else 3168 ret = 0x0000; 3169 if (!s->tx_req) 3170 omap_mcbsp_rx_done(s); 3171 return ret; 3172 } 3173 return 0x0000; 3174 3175 case 0x04: /* DXR2 */ 3176 case 0x06: /* DXR1 */ 3177 return 0x0000; 3178 3179 case 0x08: /* SPCR2 */ 3180 return s->spcr[1]; 3181 case 0x0a: /* SPCR1 */ 3182 return s->spcr[0]; 3183 case 0x0c: /* RCR2 */ 3184 return s->rcr[1]; 3185 case 0x0e: /* RCR1 */ 3186 return s->rcr[0]; 3187 case 0x10: /* XCR2 */ 3188 return s->xcr[1]; 3189 case 0x12: /* XCR1 */ 3190 return s->xcr[0]; 3191 case 0x14: /* SRGR2 */ 3192 return s->srgr[1]; 3193 case 0x16: /* SRGR1 */ 3194 return s->srgr[0]; 3195 case 0x18: /* MCR2 */ 3196 return s->mcr[1]; 3197 case 0x1a: /* MCR1 */ 3198 return s->mcr[0]; 3199 case 0x1c: /* RCERA */ 3200 return s->rcer[0]; 3201 case 0x1e: /* RCERB */ 3202 return s->rcer[1]; 3203 case 0x20: /* XCERA */ 3204 return s->xcer[0]; 3205 case 0x22: /* XCERB */ 3206 return s->xcer[1]; 3207 case 0x24: /* PCR0 */ 3208 return s->pcr; 3209 case 0x26: /* RCERC */ 3210 return s->rcer[2]; 3211 case 0x28: /* RCERD */ 3212 return s->rcer[3]; 3213 case 0x2a: /* XCERC */ 3214 return s->xcer[2]; 3215 case 0x2c: /* XCERD */ 3216 return s->xcer[3]; 3217 case 0x2e: /* RCERE */ 3218 return s->rcer[4]; 3219 case 0x30: /* RCERF */ 3220 return s->rcer[5]; 3221 case 0x32: /* XCERE */ 3222 return s->xcer[4]; 3223 case 0x34: /* XCERF */ 3224 return s->xcer[5]; 3225 case 0x36: /* RCERG */ 3226 return s->rcer[6]; 3227 case 0x38: /* RCERH */ 3228 return s->rcer[7]; 3229 case 0x3a: /* XCERG */ 3230 return s->xcer[6]; 3231 case 0x3c: /* XCERH */ 3232 return s->xcer[7]; 3233 } 3234 3235 OMAP_BAD_REG(addr); 3236 return 0; 3237 } 3238 3239 static void omap_mcbsp_writeh(void *opaque, hwaddr addr, 3240 uint32_t value) 3241 { 3242 struct omap_mcbsp_s *s = (struct omap_mcbsp_s *) opaque; 3243 int offset = addr & OMAP_MPUI_REG_MASK; 3244 3245 switch (offset) { 3246 case 0x00: /* DRR2 */ 3247 case 0x02: /* DRR1 */ 3248 OMAP_RO_REG(addr); 3249 return; 3250 3251 case 0x04: /* DXR2 */ 3252 if (((s->xcr[0] >> 5) & 7) < 3) /* XWDLEN1 */ 3253 return; 3254 /* Fall through. */ 3255 case 0x06: /* DXR1 */ 3256 if (s->tx_req > 1) { 3257 s->tx_req -= 2; 3258 if (s->codec && s->codec->cts) { 3259 s->codec->out.fifo[s->codec->out.len ++] = (value >> 8) & 0xff; 3260 s->codec->out.fifo[s->codec->out.len ++] = (value >> 0) & 0xff; 3261 } 3262 if (s->tx_req < 2) 3263 omap_mcbsp_tx_done(s); 3264 } else 3265 printf("%s: Tx FIFO overrun\n", __FUNCTION__); 3266 return; 3267 3268 case 0x08: /* SPCR2 */ 3269 s->spcr[1] &= 0x0002; 3270 s->spcr[1] |= 0x03f9 & value; 3271 s->spcr[1] |= 0x0004 & (value << 2); /* XEMPTY := XRST */ 3272 if (~value & 1) /* XRST */ 3273 s->spcr[1] &= ~6; 3274 omap_mcbsp_req_update(s); 3275 return; 3276 case 0x0a: /* SPCR1 */ 3277 s->spcr[0] &= 0x0006; 3278 s->spcr[0] |= 0xf8f9 & value; 3279 if (value & (1 << 15)) /* DLB */ 3280 printf("%s: Digital Loopback mode enable attempt\n", __FUNCTION__); 3281 if (~value & 1) { /* RRST */ 3282 s->spcr[0] &= ~6; 3283 s->rx_req = 0; 3284 omap_mcbsp_rx_done(s); 3285 } 3286 omap_mcbsp_req_update(s); 3287 return; 3288 3289 case 0x0c: /* RCR2 */ 3290 s->rcr[1] = value & 0xffff; 3291 return; 3292 case 0x0e: /* RCR1 */ 3293 s->rcr[0] = value & 0x7fe0; 3294 return; 3295 case 0x10: /* XCR2 */ 3296 s->xcr[1] = value & 0xffff; 3297 return; 3298 case 0x12: /* XCR1 */ 3299 s->xcr[0] = value & 0x7fe0; 3300 return; 3301 case 0x14: /* SRGR2 */ 3302 s->srgr[1] = value & 0xffff; 3303 omap_mcbsp_req_update(s); 3304 return; 3305 case 0x16: /* SRGR1 */ 3306 s->srgr[0] = value & 0xffff; 3307 omap_mcbsp_req_update(s); 3308 return; 3309 case 0x18: /* MCR2 */ 3310 s->mcr[1] = value & 0x03e3; 3311 if (value & 3) /* XMCM */ 3312 printf("%s: Tx channel selection mode enable attempt\n", 3313 __FUNCTION__); 3314 return; 3315 case 0x1a: /* MCR1 */ 3316 s->mcr[0] = value & 0x03e1; 3317 if (value & 1) /* RMCM */ 3318 printf("%s: Rx channel selection mode enable attempt\n", 3319 __FUNCTION__); 3320 return; 3321 case 0x1c: /* RCERA */ 3322 s->rcer[0] = value & 0xffff; 3323 return; 3324 case 0x1e: /* RCERB */ 3325 s->rcer[1] = value & 0xffff; 3326 return; 3327 case 0x20: /* XCERA */ 3328 s->xcer[0] = value & 0xffff; 3329 return; 3330 case 0x22: /* XCERB */ 3331 s->xcer[1] = value & 0xffff; 3332 return; 3333 case 0x24: /* PCR0 */ 3334 s->pcr = value & 0x7faf; 3335 return; 3336 case 0x26: /* RCERC */ 3337 s->rcer[2] = value & 0xffff; 3338 return; 3339 case 0x28: /* RCERD */ 3340 s->rcer[3] = value & 0xffff; 3341 return; 3342 case 0x2a: /* XCERC */ 3343 s->xcer[2] = value & 0xffff; 3344 return; 3345 case 0x2c: /* XCERD */ 3346 s->xcer[3] = value & 0xffff; 3347 return; 3348 case 0x2e: /* RCERE */ 3349 s->rcer[4] = value & 0xffff; 3350 return; 3351 case 0x30: /* RCERF */ 3352 s->rcer[5] = value & 0xffff; 3353 return; 3354 case 0x32: /* XCERE */ 3355 s->xcer[4] = value & 0xffff; 3356 return; 3357 case 0x34: /* XCERF */ 3358 s->xcer[5] = value & 0xffff; 3359 return; 3360 case 0x36: /* RCERG */ 3361 s->rcer[6] = value & 0xffff; 3362 return; 3363 case 0x38: /* RCERH */ 3364 s->rcer[7] = value & 0xffff; 3365 return; 3366 case 0x3a: /* XCERG */ 3367 s->xcer[6] = value & 0xffff; 3368 return; 3369 case 0x3c: /* XCERH */ 3370 s->xcer[7] = value & 0xffff; 3371 return; 3372 } 3373 3374 OMAP_BAD_REG(addr); 3375 } 3376 3377 static void omap_mcbsp_writew(void *opaque, hwaddr addr, 3378 uint32_t value) 3379 { 3380 struct omap_mcbsp_s *s = (struct omap_mcbsp_s *) opaque; 3381 int offset = addr & OMAP_MPUI_REG_MASK; 3382 3383 if (offset == 0x04) { /* DXR */ 3384 if (((s->xcr[0] >> 5) & 7) < 3) /* XWDLEN1 */ 3385 return; 3386 if (s->tx_req > 3) { 3387 s->tx_req -= 4; 3388 if (s->codec && s->codec->cts) { 3389 s->codec->out.fifo[s->codec->out.len ++] = 3390 (value >> 24) & 0xff; 3391 s->codec->out.fifo[s->codec->out.len ++] = 3392 (value >> 16) & 0xff; 3393 s->codec->out.fifo[s->codec->out.len ++] = 3394 (value >> 8) & 0xff; 3395 s->codec->out.fifo[s->codec->out.len ++] = 3396 (value >> 0) & 0xff; 3397 } 3398 if (s->tx_req < 4) 3399 omap_mcbsp_tx_done(s); 3400 } else 3401 printf("%s: Tx FIFO overrun\n", __FUNCTION__); 3402 return; 3403 } 3404 3405 omap_badwidth_write16(opaque, addr, value); 3406 } 3407 3408 static void omap_mcbsp_write(void *opaque, hwaddr addr, 3409 uint64_t value, unsigned size) 3410 { 3411 switch (size) { 3412 case 2: return omap_mcbsp_writeh(opaque, addr, value); 3413 case 4: return omap_mcbsp_writew(opaque, addr, value); 3414 default: return omap_badwidth_write16(opaque, addr, value); 3415 } 3416 } 3417 3418 static const MemoryRegionOps omap_mcbsp_ops = { 3419 .read = omap_mcbsp_read, 3420 .write = omap_mcbsp_write, 3421 .endianness = DEVICE_NATIVE_ENDIAN, 3422 }; 3423 3424 static void omap_mcbsp_reset(struct omap_mcbsp_s *s) 3425 { 3426 memset(&s->spcr, 0, sizeof(s->spcr)); 3427 memset(&s->rcr, 0, sizeof(s->rcr)); 3428 memset(&s->xcr, 0, sizeof(s->xcr)); 3429 s->srgr[0] = 0x0001; 3430 s->srgr[1] = 0x2000; 3431 memset(&s->mcr, 0, sizeof(s->mcr)); 3432 memset(&s->pcr, 0, sizeof(s->pcr)); 3433 memset(&s->rcer, 0, sizeof(s->rcer)); 3434 memset(&s->xcer, 0, sizeof(s->xcer)); 3435 s->tx_req = 0; 3436 s->rx_req = 0; 3437 s->tx_rate = 0; 3438 s->rx_rate = 0; 3439 timer_del(s->source_timer); 3440 timer_del(s->sink_timer); 3441 } 3442 3443 static struct omap_mcbsp_s *omap_mcbsp_init(MemoryRegion *system_memory, 3444 hwaddr base, 3445 qemu_irq txirq, qemu_irq rxirq, 3446 qemu_irq *dma, omap_clk clk) 3447 { 3448 struct omap_mcbsp_s *s = (struct omap_mcbsp_s *) 3449 g_malloc0(sizeof(struct omap_mcbsp_s)); 3450 3451 s->txirq = txirq; 3452 s->rxirq = rxirq; 3453 s->txdrq = dma[0]; 3454 s->rxdrq = dma[1]; 3455 s->sink_timer = timer_new_ns(QEMU_CLOCK_VIRTUAL, omap_mcbsp_sink_tick, s); 3456 s->source_timer = timer_new_ns(QEMU_CLOCK_VIRTUAL, omap_mcbsp_source_tick, s); 3457 omap_mcbsp_reset(s); 3458 3459 memory_region_init_io(&s->iomem, NULL, &omap_mcbsp_ops, s, "omap-mcbsp", 0x800); 3460 memory_region_add_subregion(system_memory, base, &s->iomem); 3461 3462 return s; 3463 } 3464 3465 static void omap_mcbsp_i2s_swallow(void *opaque, int line, int level) 3466 { 3467 struct omap_mcbsp_s *s = (struct omap_mcbsp_s *) opaque; 3468 3469 if (s->rx_rate) { 3470 s->rx_req = s->codec->in.len; 3471 omap_mcbsp_rx_newdata(s); 3472 } 3473 } 3474 3475 static void omap_mcbsp_i2s_start(void *opaque, int line, int level) 3476 { 3477 struct omap_mcbsp_s *s = (struct omap_mcbsp_s *) opaque; 3478 3479 if (s->tx_rate) { 3480 s->tx_req = s->codec->out.size; 3481 omap_mcbsp_tx_newdata(s); 3482 } 3483 } 3484 3485 void omap_mcbsp_i2s_attach(struct omap_mcbsp_s *s, I2SCodec *slave) 3486 { 3487 s->codec = slave; 3488 slave->rx_swallow = qemu_allocate_irqs(omap_mcbsp_i2s_swallow, s, 1)[0]; 3489 slave->tx_start = qemu_allocate_irqs(omap_mcbsp_i2s_start, s, 1)[0]; 3490 } 3491 3492 /* LED Pulse Generators */ 3493 struct omap_lpg_s { 3494 MemoryRegion iomem; 3495 QEMUTimer *tm; 3496 3497 uint8_t control; 3498 uint8_t power; 3499 int64_t on; 3500 int64_t period; 3501 int clk; 3502 int cycle; 3503 }; 3504 3505 static void omap_lpg_tick(void *opaque) 3506 { 3507 struct omap_lpg_s *s = opaque; 3508 3509 if (s->cycle) 3510 timer_mod(s->tm, qemu_clock_get_ms(QEMU_CLOCK_VIRTUAL) + s->period - s->on); 3511 else 3512 timer_mod(s->tm, qemu_clock_get_ms(QEMU_CLOCK_VIRTUAL) + s->on); 3513 3514 s->cycle = !s->cycle; 3515 printf("%s: LED is %s\n", __FUNCTION__, s->cycle ? "on" : "off"); 3516 } 3517 3518 static void omap_lpg_update(struct omap_lpg_s *s) 3519 { 3520 int64_t on, period = 1, ticks = 1000; 3521 static const int per[8] = { 1, 2, 4, 8, 12, 16, 20, 24 }; 3522 3523 if (~s->control & (1 << 6)) /* LPGRES */ 3524 on = 0; 3525 else if (s->control & (1 << 7)) /* PERM_ON */ 3526 on = period; 3527 else { 3528 period = muldiv64(ticks, per[s->control & 7], /* PERCTRL */ 3529 256 / 32); 3530 on = (s->clk && s->power) ? muldiv64(ticks, 3531 per[(s->control >> 3) & 7], 256) : 0; /* ONCTRL */ 3532 } 3533 3534 timer_del(s->tm); 3535 if (on == period && s->on < s->period) 3536 printf("%s: LED is on\n", __FUNCTION__); 3537 else if (on == 0 && s->on) 3538 printf("%s: LED is off\n", __FUNCTION__); 3539 else if (on && (on != s->on || period != s->period)) { 3540 s->cycle = 0; 3541 s->on = on; 3542 s->period = period; 3543 omap_lpg_tick(s); 3544 return; 3545 } 3546 3547 s->on = on; 3548 s->period = period; 3549 } 3550 3551 static void omap_lpg_reset(struct omap_lpg_s *s) 3552 { 3553 s->control = 0x00; 3554 s->power = 0x00; 3555 s->clk = 1; 3556 omap_lpg_update(s); 3557 } 3558 3559 static uint64_t omap_lpg_read(void *opaque, hwaddr addr, 3560 unsigned size) 3561 { 3562 struct omap_lpg_s *s = (struct omap_lpg_s *) opaque; 3563 int offset = addr & OMAP_MPUI_REG_MASK; 3564 3565 if (size != 1) { 3566 return omap_badwidth_read8(opaque, addr); 3567 } 3568 3569 switch (offset) { 3570 case 0x00: /* LCR */ 3571 return s->control; 3572 3573 case 0x04: /* PMR */ 3574 return s->power; 3575 } 3576 3577 OMAP_BAD_REG(addr); 3578 return 0; 3579 } 3580 3581 static void omap_lpg_write(void *opaque, hwaddr addr, 3582 uint64_t value, unsigned size) 3583 { 3584 struct omap_lpg_s *s = (struct omap_lpg_s *) opaque; 3585 int offset = addr & OMAP_MPUI_REG_MASK; 3586 3587 if (size != 1) { 3588 return omap_badwidth_write8(opaque, addr, value); 3589 } 3590 3591 switch (offset) { 3592 case 0x00: /* LCR */ 3593 if (~value & (1 << 6)) /* LPGRES */ 3594 omap_lpg_reset(s); 3595 s->control = value & 0xff; 3596 omap_lpg_update(s); 3597 return; 3598 3599 case 0x04: /* PMR */ 3600 s->power = value & 0x01; 3601 omap_lpg_update(s); 3602 return; 3603 3604 default: 3605 OMAP_BAD_REG(addr); 3606 return; 3607 } 3608 } 3609 3610 static const MemoryRegionOps omap_lpg_ops = { 3611 .read = omap_lpg_read, 3612 .write = omap_lpg_write, 3613 .endianness = DEVICE_NATIVE_ENDIAN, 3614 }; 3615 3616 static void omap_lpg_clk_update(void *opaque, int line, int on) 3617 { 3618 struct omap_lpg_s *s = (struct omap_lpg_s *) opaque; 3619 3620 s->clk = on; 3621 omap_lpg_update(s); 3622 } 3623 3624 static struct omap_lpg_s *omap_lpg_init(MemoryRegion *system_memory, 3625 hwaddr base, omap_clk clk) 3626 { 3627 struct omap_lpg_s *s = (struct omap_lpg_s *) 3628 g_malloc0(sizeof(struct omap_lpg_s)); 3629 3630 s->tm = timer_new_ms(QEMU_CLOCK_VIRTUAL, omap_lpg_tick, s); 3631 3632 omap_lpg_reset(s); 3633 3634 memory_region_init_io(&s->iomem, NULL, &omap_lpg_ops, s, "omap-lpg", 0x800); 3635 memory_region_add_subregion(system_memory, base, &s->iomem); 3636 3637 omap_clk_adduser(clk, qemu_allocate_irqs(omap_lpg_clk_update, s, 1)[0]); 3638 3639 return s; 3640 } 3641 3642 /* MPUI Peripheral Bridge configuration */ 3643 static uint64_t omap_mpui_io_read(void *opaque, hwaddr addr, 3644 unsigned size) 3645 { 3646 if (size != 2) { 3647 return omap_badwidth_read16(opaque, addr); 3648 } 3649 3650 if (addr == OMAP_MPUI_BASE) /* CMR */ 3651 return 0xfe4d; 3652 3653 OMAP_BAD_REG(addr); 3654 return 0; 3655 } 3656 3657 static void omap_mpui_io_write(void *opaque, hwaddr addr, 3658 uint64_t value, unsigned size) 3659 { 3660 /* FIXME: infinite loop */ 3661 omap_badwidth_write16(opaque, addr, value); 3662 } 3663 3664 static const MemoryRegionOps omap_mpui_io_ops = { 3665 .read = omap_mpui_io_read, 3666 .write = omap_mpui_io_write, 3667 .endianness = DEVICE_NATIVE_ENDIAN, 3668 }; 3669 3670 static void omap_setup_mpui_io(MemoryRegion *system_memory, 3671 struct omap_mpu_state_s *mpu) 3672 { 3673 memory_region_init_io(&mpu->mpui_io_iomem, NULL, &omap_mpui_io_ops, mpu, 3674 "omap-mpui-io", 0x7fff); 3675 memory_region_add_subregion(system_memory, OMAP_MPUI_BASE, 3676 &mpu->mpui_io_iomem); 3677 } 3678 3679 /* General chip reset */ 3680 static void omap1_mpu_reset(void *opaque) 3681 { 3682 struct omap_mpu_state_s *mpu = (struct omap_mpu_state_s *) opaque; 3683 3684 omap_dma_reset(mpu->dma); 3685 omap_mpu_timer_reset(mpu->timer[0]); 3686 omap_mpu_timer_reset(mpu->timer[1]); 3687 omap_mpu_timer_reset(mpu->timer[2]); 3688 omap_wd_timer_reset(mpu->wdt); 3689 omap_os_timer_reset(mpu->os_timer); 3690 omap_lcdc_reset(mpu->lcd); 3691 omap_ulpd_pm_reset(mpu); 3692 omap_pin_cfg_reset(mpu); 3693 omap_mpui_reset(mpu); 3694 omap_tipb_bridge_reset(mpu->private_tipb); 3695 omap_tipb_bridge_reset(mpu->public_tipb); 3696 omap_dpll_reset(mpu->dpll[0]); 3697 omap_dpll_reset(mpu->dpll[1]); 3698 omap_dpll_reset(mpu->dpll[2]); 3699 omap_uart_reset(mpu->uart[0]); 3700 omap_uart_reset(mpu->uart[1]); 3701 omap_uart_reset(mpu->uart[2]); 3702 omap_mmc_reset(mpu->mmc); 3703 omap_mpuio_reset(mpu->mpuio); 3704 omap_uwire_reset(mpu->microwire); 3705 omap_pwl_reset(mpu->pwl); 3706 omap_pwt_reset(mpu->pwt); 3707 omap_rtc_reset(mpu->rtc); 3708 omap_mcbsp_reset(mpu->mcbsp1); 3709 omap_mcbsp_reset(mpu->mcbsp2); 3710 omap_mcbsp_reset(mpu->mcbsp3); 3711 omap_lpg_reset(mpu->led[0]); 3712 omap_lpg_reset(mpu->led[1]); 3713 omap_clkm_reset(mpu); 3714 cpu_reset(CPU(mpu->cpu)); 3715 } 3716 3717 static const struct omap_map_s { 3718 hwaddr phys_dsp; 3719 hwaddr phys_mpu; 3720 uint32_t size; 3721 const char *name; 3722 } omap15xx_dsp_mm[] = { 3723 /* Strobe 0 */ 3724 { 0xe1010000, 0xfffb0000, 0x800, "UART1 BT" }, /* CS0 */ 3725 { 0xe1010800, 0xfffb0800, 0x800, "UART2 COM" }, /* CS1 */ 3726 { 0xe1011800, 0xfffb1800, 0x800, "McBSP1 audio" }, /* CS3 */ 3727 { 0xe1012000, 0xfffb2000, 0x800, "MCSI2 communication" }, /* CS4 */ 3728 { 0xe1012800, 0xfffb2800, 0x800, "MCSI1 BT u-Law" }, /* CS5 */ 3729 { 0xe1013000, 0xfffb3000, 0x800, "uWire" }, /* CS6 */ 3730 { 0xe1013800, 0xfffb3800, 0x800, "I^2C" }, /* CS7 */ 3731 { 0xe1014000, 0xfffb4000, 0x800, "USB W2FC" }, /* CS8 */ 3732 { 0xe1014800, 0xfffb4800, 0x800, "RTC" }, /* CS9 */ 3733 { 0xe1015000, 0xfffb5000, 0x800, "MPUIO" }, /* CS10 */ 3734 { 0xe1015800, 0xfffb5800, 0x800, "PWL" }, /* CS11 */ 3735 { 0xe1016000, 0xfffb6000, 0x800, "PWT" }, /* CS12 */ 3736 { 0xe1017000, 0xfffb7000, 0x800, "McBSP3" }, /* CS14 */ 3737 { 0xe1017800, 0xfffb7800, 0x800, "MMC" }, /* CS15 */ 3738 { 0xe1019000, 0xfffb9000, 0x800, "32-kHz timer" }, /* CS18 */ 3739 { 0xe1019800, 0xfffb9800, 0x800, "UART3" }, /* CS19 */ 3740 { 0xe101c800, 0xfffbc800, 0x800, "TIPB switches" }, /* CS25 */ 3741 /* Strobe 1 */ 3742 { 0xe101e000, 0xfffce000, 0x800, "GPIOs" }, /* CS28 */ 3743 3744 { 0 } 3745 }; 3746 3747 static void omap_setup_dsp_mapping(MemoryRegion *system_memory, 3748 const struct omap_map_s *map) 3749 { 3750 MemoryRegion *io; 3751 3752 for (; map->phys_dsp; map ++) { 3753 io = g_new(MemoryRegion, 1); 3754 memory_region_init_alias(io, NULL, map->name, 3755 system_memory, map->phys_mpu, map->size); 3756 memory_region_add_subregion(system_memory, map->phys_dsp, io); 3757 } 3758 } 3759 3760 void omap_mpu_wakeup(void *opaque, int irq, int req) 3761 { 3762 struct omap_mpu_state_s *mpu = (struct omap_mpu_state_s *) opaque; 3763 CPUState *cpu = CPU(mpu->cpu); 3764 3765 if (cpu->halted) { 3766 cpu_interrupt(cpu, CPU_INTERRUPT_EXITTB); 3767 } 3768 } 3769 3770 static const struct dma_irq_map omap1_dma_irq_map[] = { 3771 { 0, OMAP_INT_DMA_CH0_6 }, 3772 { 0, OMAP_INT_DMA_CH1_7 }, 3773 { 0, OMAP_INT_DMA_CH2_8 }, 3774 { 0, OMAP_INT_DMA_CH3 }, 3775 { 0, OMAP_INT_DMA_CH4 }, 3776 { 0, OMAP_INT_DMA_CH5 }, 3777 { 1, OMAP_INT_1610_DMA_CH6 }, 3778 { 1, OMAP_INT_1610_DMA_CH7 }, 3779 { 1, OMAP_INT_1610_DMA_CH8 }, 3780 { 1, OMAP_INT_1610_DMA_CH9 }, 3781 { 1, OMAP_INT_1610_DMA_CH10 }, 3782 { 1, OMAP_INT_1610_DMA_CH11 }, 3783 { 1, OMAP_INT_1610_DMA_CH12 }, 3784 { 1, OMAP_INT_1610_DMA_CH13 }, 3785 { 1, OMAP_INT_1610_DMA_CH14 }, 3786 { 1, OMAP_INT_1610_DMA_CH15 } 3787 }; 3788 3789 /* DMA ports for OMAP1 */ 3790 static int omap_validate_emiff_addr(struct omap_mpu_state_s *s, 3791 hwaddr addr) 3792 { 3793 return range_covers_byte(OMAP_EMIFF_BASE, s->sdram_size, addr); 3794 } 3795 3796 static int omap_validate_emifs_addr(struct omap_mpu_state_s *s, 3797 hwaddr addr) 3798 { 3799 return range_covers_byte(OMAP_EMIFS_BASE, OMAP_EMIFF_BASE - OMAP_EMIFS_BASE, 3800 addr); 3801 } 3802 3803 static int omap_validate_imif_addr(struct omap_mpu_state_s *s, 3804 hwaddr addr) 3805 { 3806 return range_covers_byte(OMAP_IMIF_BASE, s->sram_size, addr); 3807 } 3808 3809 static int omap_validate_tipb_addr(struct omap_mpu_state_s *s, 3810 hwaddr addr) 3811 { 3812 return range_covers_byte(0xfffb0000, 0xffff0000 - 0xfffb0000, addr); 3813 } 3814 3815 static int omap_validate_local_addr(struct omap_mpu_state_s *s, 3816 hwaddr addr) 3817 { 3818 return range_covers_byte(OMAP_LOCALBUS_BASE, 0x1000000, addr); 3819 } 3820 3821 static int omap_validate_tipb_mpui_addr(struct omap_mpu_state_s *s, 3822 hwaddr addr) 3823 { 3824 return range_covers_byte(0xe1010000, 0xe1020004 - 0xe1010000, addr); 3825 } 3826 3827 struct omap_mpu_state_s *omap310_mpu_init(MemoryRegion *system_memory, 3828 unsigned long sdram_size, 3829 const char *core) 3830 { 3831 int i; 3832 struct omap_mpu_state_s *s = (struct omap_mpu_state_s *) 3833 g_malloc0(sizeof(struct omap_mpu_state_s)); 3834 qemu_irq dma_irqs[6]; 3835 DriveInfo *dinfo; 3836 SysBusDevice *busdev; 3837 3838 if (!core) 3839 core = "ti925t"; 3840 3841 /* Core */ 3842 s->mpu_model = omap310; 3843 s->cpu = cpu_arm_init(core); 3844 if (s->cpu == NULL) { 3845 fprintf(stderr, "Unable to find CPU definition\n"); 3846 exit(1); 3847 } 3848 s->sdram_size = sdram_size; 3849 s->sram_size = OMAP15XX_SRAM_SIZE; 3850 3851 s->wakeup = qemu_allocate_irqs(omap_mpu_wakeup, s, 1)[0]; 3852 3853 /* Clocks */ 3854 omap_clk_init(s); 3855 3856 /* Memory-mapped stuff */ 3857 memory_region_init_ram(&s->emiff_ram, NULL, "omap1.dram", s->sdram_size); 3858 vmstate_register_ram_global(&s->emiff_ram); 3859 memory_region_add_subregion(system_memory, OMAP_EMIFF_BASE, &s->emiff_ram); 3860 memory_region_init_ram(&s->imif_ram, NULL, "omap1.sram", s->sram_size); 3861 vmstate_register_ram_global(&s->imif_ram); 3862 memory_region_add_subregion(system_memory, OMAP_IMIF_BASE, &s->imif_ram); 3863 3864 omap_clkm_init(system_memory, 0xfffece00, 0xe1008000, s); 3865 3866 s->ih[0] = qdev_create(NULL, "omap-intc"); 3867 qdev_prop_set_uint32(s->ih[0], "size", 0x100); 3868 qdev_prop_set_ptr(s->ih[0], "clk", omap_findclk(s, "arminth_ck")); 3869 qdev_init_nofail(s->ih[0]); 3870 busdev = SYS_BUS_DEVICE(s->ih[0]); 3871 sysbus_connect_irq(busdev, 0, 3872 qdev_get_gpio_in(DEVICE(s->cpu), ARM_CPU_IRQ)); 3873 sysbus_connect_irq(busdev, 1, 3874 qdev_get_gpio_in(DEVICE(s->cpu), ARM_CPU_FIQ)); 3875 sysbus_mmio_map(busdev, 0, 0xfffecb00); 3876 s->ih[1] = qdev_create(NULL, "omap-intc"); 3877 qdev_prop_set_uint32(s->ih[1], "size", 0x800); 3878 qdev_prop_set_ptr(s->ih[1], "clk", omap_findclk(s, "arminth_ck")); 3879 qdev_init_nofail(s->ih[1]); 3880 busdev = SYS_BUS_DEVICE(s->ih[1]); 3881 sysbus_connect_irq(busdev, 0, 3882 qdev_get_gpio_in(s->ih[0], OMAP_INT_15XX_IH2_IRQ)); 3883 /* The second interrupt controller's FIQ output is not wired up */ 3884 sysbus_mmio_map(busdev, 0, 0xfffe0000); 3885 3886 for (i = 0; i < 6; i++) { 3887 dma_irqs[i] = qdev_get_gpio_in(s->ih[omap1_dma_irq_map[i].ih], 3888 omap1_dma_irq_map[i].intr); 3889 } 3890 s->dma = omap_dma_init(0xfffed800, dma_irqs, system_memory, 3891 qdev_get_gpio_in(s->ih[0], OMAP_INT_DMA_LCD), 3892 s, omap_findclk(s, "dma_ck"), omap_dma_3_1); 3893 3894 s->port[emiff ].addr_valid = omap_validate_emiff_addr; 3895 s->port[emifs ].addr_valid = omap_validate_emifs_addr; 3896 s->port[imif ].addr_valid = omap_validate_imif_addr; 3897 s->port[tipb ].addr_valid = omap_validate_tipb_addr; 3898 s->port[local ].addr_valid = omap_validate_local_addr; 3899 s->port[tipb_mpui].addr_valid = omap_validate_tipb_mpui_addr; 3900 3901 /* Register SDRAM and SRAM DMA ports for fast transfers. */ 3902 soc_dma_port_add_mem(s->dma, memory_region_get_ram_ptr(&s->emiff_ram), 3903 OMAP_EMIFF_BASE, s->sdram_size); 3904 soc_dma_port_add_mem(s->dma, memory_region_get_ram_ptr(&s->imif_ram), 3905 OMAP_IMIF_BASE, s->sram_size); 3906 3907 s->timer[0] = omap_mpu_timer_init(system_memory, 0xfffec500, 3908 qdev_get_gpio_in(s->ih[0], OMAP_INT_TIMER1), 3909 omap_findclk(s, "mputim_ck")); 3910 s->timer[1] = omap_mpu_timer_init(system_memory, 0xfffec600, 3911 qdev_get_gpio_in(s->ih[0], OMAP_INT_TIMER2), 3912 omap_findclk(s, "mputim_ck")); 3913 s->timer[2] = omap_mpu_timer_init(system_memory, 0xfffec700, 3914 qdev_get_gpio_in(s->ih[0], OMAP_INT_TIMER3), 3915 omap_findclk(s, "mputim_ck")); 3916 3917 s->wdt = omap_wd_timer_init(system_memory, 0xfffec800, 3918 qdev_get_gpio_in(s->ih[0], OMAP_INT_WD_TIMER), 3919 omap_findclk(s, "armwdt_ck")); 3920 3921 s->os_timer = omap_os_timer_init(system_memory, 0xfffb9000, 3922 qdev_get_gpio_in(s->ih[1], OMAP_INT_OS_TIMER), 3923 omap_findclk(s, "clk32-kHz")); 3924 3925 s->lcd = omap_lcdc_init(system_memory, 0xfffec000, 3926 qdev_get_gpio_in(s->ih[0], OMAP_INT_LCD_CTRL), 3927 omap_dma_get_lcdch(s->dma), 3928 omap_findclk(s, "lcd_ck")); 3929 3930 omap_ulpd_pm_init(system_memory, 0xfffe0800, s); 3931 omap_pin_cfg_init(system_memory, 0xfffe1000, s); 3932 omap_id_init(system_memory, s); 3933 3934 omap_mpui_init(system_memory, 0xfffec900, s); 3935 3936 s->private_tipb = omap_tipb_bridge_init(system_memory, 0xfffeca00, 3937 qdev_get_gpio_in(s->ih[0], OMAP_INT_BRIDGE_PRIV), 3938 omap_findclk(s, "tipb_ck")); 3939 s->public_tipb = omap_tipb_bridge_init(system_memory, 0xfffed300, 3940 qdev_get_gpio_in(s->ih[0], OMAP_INT_BRIDGE_PUB), 3941 omap_findclk(s, "tipb_ck")); 3942 3943 omap_tcmi_init(system_memory, 0xfffecc00, s); 3944 3945 s->uart[0] = omap_uart_init(0xfffb0000, 3946 qdev_get_gpio_in(s->ih[1], OMAP_INT_UART1), 3947 omap_findclk(s, "uart1_ck"), 3948 omap_findclk(s, "uart1_ck"), 3949 s->drq[OMAP_DMA_UART1_TX], s->drq[OMAP_DMA_UART1_RX], 3950 "uart1", 3951 serial_hds[0]); 3952 s->uart[1] = omap_uart_init(0xfffb0800, 3953 qdev_get_gpio_in(s->ih[1], OMAP_INT_UART2), 3954 omap_findclk(s, "uart2_ck"), 3955 omap_findclk(s, "uart2_ck"), 3956 s->drq[OMAP_DMA_UART2_TX], s->drq[OMAP_DMA_UART2_RX], 3957 "uart2", 3958 serial_hds[0] ? serial_hds[1] : NULL); 3959 s->uart[2] = omap_uart_init(0xfffb9800, 3960 qdev_get_gpio_in(s->ih[0], OMAP_INT_UART3), 3961 omap_findclk(s, "uart3_ck"), 3962 omap_findclk(s, "uart3_ck"), 3963 s->drq[OMAP_DMA_UART3_TX], s->drq[OMAP_DMA_UART3_RX], 3964 "uart3", 3965 serial_hds[0] && serial_hds[1] ? serial_hds[2] : NULL); 3966 3967 s->dpll[0] = omap_dpll_init(system_memory, 0xfffecf00, 3968 omap_findclk(s, "dpll1")); 3969 s->dpll[1] = omap_dpll_init(system_memory, 0xfffed000, 3970 omap_findclk(s, "dpll2")); 3971 s->dpll[2] = omap_dpll_init(system_memory, 0xfffed100, 3972 omap_findclk(s, "dpll3")); 3973 3974 dinfo = drive_get(IF_SD, 0, 0); 3975 if (!dinfo) { 3976 fprintf(stderr, "qemu: missing SecureDigital device\n"); 3977 exit(1); 3978 } 3979 s->mmc = omap_mmc_init(0xfffb7800, system_memory, dinfo->bdrv, 3980 qdev_get_gpio_in(s->ih[1], OMAP_INT_OQN), 3981 &s->drq[OMAP_DMA_MMC_TX], 3982 omap_findclk(s, "mmc_ck")); 3983 3984 s->mpuio = omap_mpuio_init(system_memory, 0xfffb5000, 3985 qdev_get_gpio_in(s->ih[1], OMAP_INT_KEYBOARD), 3986 qdev_get_gpio_in(s->ih[1], OMAP_INT_MPUIO), 3987 s->wakeup, omap_findclk(s, "clk32-kHz")); 3988 3989 s->gpio = qdev_create(NULL, "omap-gpio"); 3990 qdev_prop_set_int32(s->gpio, "mpu_model", s->mpu_model); 3991 qdev_prop_set_ptr(s->gpio, "clk", omap_findclk(s, "arm_gpio_ck")); 3992 qdev_init_nofail(s->gpio); 3993 sysbus_connect_irq(SYS_BUS_DEVICE(s->gpio), 0, 3994 qdev_get_gpio_in(s->ih[0], OMAP_INT_GPIO_BANK1)); 3995 sysbus_mmio_map(SYS_BUS_DEVICE(s->gpio), 0, 0xfffce000); 3996 3997 s->microwire = omap_uwire_init(system_memory, 0xfffb3000, 3998 qdev_get_gpio_in(s->ih[1], OMAP_INT_uWireTX), 3999 qdev_get_gpio_in(s->ih[1], OMAP_INT_uWireRX), 4000 s->drq[OMAP_DMA_UWIRE_TX], omap_findclk(s, "mpuper_ck")); 4001 4002 s->pwl = omap_pwl_init(system_memory, 0xfffb5800, 4003 omap_findclk(s, "armxor_ck")); 4004 s->pwt = omap_pwt_init(system_memory, 0xfffb6000, 4005 omap_findclk(s, "armxor_ck")); 4006 4007 s->i2c[0] = qdev_create(NULL, "omap_i2c"); 4008 qdev_prop_set_uint8(s->i2c[0], "revision", 0x11); 4009 qdev_prop_set_ptr(s->i2c[0], "fclk", omap_findclk(s, "mpuper_ck")); 4010 qdev_init_nofail(s->i2c[0]); 4011 busdev = SYS_BUS_DEVICE(s->i2c[0]); 4012 sysbus_connect_irq(busdev, 0, qdev_get_gpio_in(s->ih[1], OMAP_INT_I2C)); 4013 sysbus_connect_irq(busdev, 1, s->drq[OMAP_DMA_I2C_TX]); 4014 sysbus_connect_irq(busdev, 2, s->drq[OMAP_DMA_I2C_RX]); 4015 sysbus_mmio_map(busdev, 0, 0xfffb3800); 4016 4017 s->rtc = omap_rtc_init(system_memory, 0xfffb4800, 4018 qdev_get_gpio_in(s->ih[1], OMAP_INT_RTC_TIMER), 4019 qdev_get_gpio_in(s->ih[1], OMAP_INT_RTC_ALARM), 4020 omap_findclk(s, "clk32-kHz")); 4021 4022 s->mcbsp1 = omap_mcbsp_init(system_memory, 0xfffb1800, 4023 qdev_get_gpio_in(s->ih[1], OMAP_INT_McBSP1TX), 4024 qdev_get_gpio_in(s->ih[1], OMAP_INT_McBSP1RX), 4025 &s->drq[OMAP_DMA_MCBSP1_TX], omap_findclk(s, "dspxor_ck")); 4026 s->mcbsp2 = omap_mcbsp_init(system_memory, 0xfffb1000, 4027 qdev_get_gpio_in(s->ih[0], 4028 OMAP_INT_310_McBSP2_TX), 4029 qdev_get_gpio_in(s->ih[0], 4030 OMAP_INT_310_McBSP2_RX), 4031 &s->drq[OMAP_DMA_MCBSP2_TX], omap_findclk(s, "mpuper_ck")); 4032 s->mcbsp3 = omap_mcbsp_init(system_memory, 0xfffb7000, 4033 qdev_get_gpio_in(s->ih[1], OMAP_INT_McBSP3TX), 4034 qdev_get_gpio_in(s->ih[1], OMAP_INT_McBSP3RX), 4035 &s->drq[OMAP_DMA_MCBSP3_TX], omap_findclk(s, "dspxor_ck")); 4036 4037 s->led[0] = omap_lpg_init(system_memory, 4038 0xfffbd000, omap_findclk(s, "clk32-kHz")); 4039 s->led[1] = omap_lpg_init(system_memory, 4040 0xfffbd800, omap_findclk(s, "clk32-kHz")); 4041 4042 /* Register mappings not currenlty implemented: 4043 * MCSI2 Comm fffb2000 - fffb27ff (not mapped on OMAP310) 4044 * MCSI1 Bluetooth fffb2800 - fffb2fff (not mapped on OMAP310) 4045 * USB W2FC fffb4000 - fffb47ff 4046 * Camera Interface fffb6800 - fffb6fff 4047 * USB Host fffba000 - fffba7ff 4048 * FAC fffba800 - fffbafff 4049 * HDQ/1-Wire fffbc000 - fffbc7ff 4050 * TIPB switches fffbc800 - fffbcfff 4051 * Mailbox fffcf000 - fffcf7ff 4052 * Local bus IF fffec100 - fffec1ff 4053 * Local bus MMU fffec200 - fffec2ff 4054 * DSP MMU fffed200 - fffed2ff 4055 */ 4056 4057 omap_setup_dsp_mapping(system_memory, omap15xx_dsp_mm); 4058 omap_setup_mpui_io(system_memory, s); 4059 4060 qemu_register_reset(omap1_mpu_reset, s); 4061 4062 return s; 4063 } 4064