1 /* 2 * TI OMAP processors emulation. 3 * 4 * Copyright (C) 2007-2008 Nokia Corporation 5 * Written by Andrzej Zaborowski <andrew@openedhand.com> 6 * 7 * This program is free software; you can redistribute it and/or 8 * modify it under the terms of the GNU General Public License as 9 * published by the Free Software Foundation; either version 2 or 10 * (at your option) version 3 of the License. 11 * 12 * This program is distributed in the hope that it will be useful, 13 * but WITHOUT ANY WARRANTY; without even the implied warranty of 14 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the 15 * GNU General Public License for more details. 16 * 17 * You should have received a copy of the GNU General Public License along 18 * with this program; if not, see <http://www.gnu.org/licenses/>. 19 */ 20 21 #include "qemu/osdep.h" 22 #include "sysemu/block-backend.h" 23 #include "sysemu/blockdev.h" 24 #include "hw/boards.h" 25 #include "hw/hw.h" 26 #include "hw/arm/arm.h" 27 #include "hw/arm/omap.h" 28 #include "sysemu/sysemu.h" 29 #include "qemu/timer.h" 30 #include "sysemu/char.h" 31 #include "hw/block/flash.h" 32 #include "hw/arm/soc_dma.h" 33 #include "hw/sysbus.h" 34 #include "audio/audio.h" 35 36 /* Enhanced Audio Controller (CODEC only) */ 37 struct omap_eac_s { 38 qemu_irq irq; 39 MemoryRegion iomem; 40 41 uint16_t sysconfig; 42 uint8_t config[4]; 43 uint8_t control; 44 uint8_t address; 45 uint16_t data; 46 uint8_t vtol; 47 uint8_t vtsl; 48 uint16_t mixer; 49 uint16_t gain[4]; 50 uint8_t att; 51 uint16_t max[7]; 52 53 struct { 54 qemu_irq txdrq; 55 qemu_irq rxdrq; 56 uint32_t (*txrx)(void *opaque, uint32_t, int); 57 void *opaque; 58 59 #define EAC_BUF_LEN 1024 60 uint32_t rxbuf[EAC_BUF_LEN]; 61 int rxoff; 62 int rxlen; 63 int rxavail; 64 uint32_t txbuf[EAC_BUF_LEN]; 65 int txlen; 66 int txavail; 67 68 int enable; 69 int rate; 70 71 uint16_t config[4]; 72 73 /* These need to be moved to the actual codec */ 74 QEMUSoundCard card; 75 SWVoiceIn *in_voice; 76 SWVoiceOut *out_voice; 77 int hw_enable; 78 } codec; 79 80 struct { 81 uint8_t control; 82 uint16_t config; 83 } modem, bt; 84 }; 85 86 static inline void omap_eac_interrupt_update(struct omap_eac_s *s) 87 { 88 qemu_set_irq(s->irq, (s->codec.config[1] >> 14) & 1); /* AURDI */ 89 } 90 91 static inline void omap_eac_in_dmarequest_update(struct omap_eac_s *s) 92 { 93 qemu_set_irq(s->codec.rxdrq, (s->codec.rxavail || s->codec.rxlen) && 94 ((s->codec.config[1] >> 12) & 1)); /* DMAREN */ 95 } 96 97 static inline void omap_eac_out_dmarequest_update(struct omap_eac_s *s) 98 { 99 qemu_set_irq(s->codec.txdrq, s->codec.txlen < s->codec.txavail && 100 ((s->codec.config[1] >> 11) & 1)); /* DMAWEN */ 101 } 102 103 static inline void omap_eac_in_refill(struct omap_eac_s *s) 104 { 105 int left = MIN(EAC_BUF_LEN - s->codec.rxlen, s->codec.rxavail) << 2; 106 int start = ((s->codec.rxoff + s->codec.rxlen) & (EAC_BUF_LEN - 1)) << 2; 107 int leftwrap = MIN(left, (EAC_BUF_LEN << 2) - start); 108 int recv = 1; 109 uint8_t *buf = (uint8_t *) s->codec.rxbuf + start; 110 111 left -= leftwrap; 112 start = 0; 113 while (leftwrap && (recv = AUD_read(s->codec.in_voice, buf + start, 114 leftwrap)) > 0) { /* Be defensive */ 115 start += recv; 116 leftwrap -= recv; 117 } 118 if (recv <= 0) 119 s->codec.rxavail = 0; 120 else 121 s->codec.rxavail -= start >> 2; 122 s->codec.rxlen += start >> 2; 123 124 if (recv > 0 && left > 0) { 125 start = 0; 126 while (left && (recv = AUD_read(s->codec.in_voice, 127 (uint8_t *) s->codec.rxbuf + start, 128 left)) > 0) { /* Be defensive */ 129 start += recv; 130 left -= recv; 131 } 132 if (recv <= 0) 133 s->codec.rxavail = 0; 134 else 135 s->codec.rxavail -= start >> 2; 136 s->codec.rxlen += start >> 2; 137 } 138 } 139 140 static inline void omap_eac_out_empty(struct omap_eac_s *s) 141 { 142 int left = s->codec.txlen << 2; 143 int start = 0; 144 int sent = 1; 145 146 while (left && (sent = AUD_write(s->codec.out_voice, 147 (uint8_t *) s->codec.txbuf + start, 148 left)) > 0) { /* Be defensive */ 149 start += sent; 150 left -= sent; 151 } 152 153 if (!sent) { 154 s->codec.txavail = 0; 155 omap_eac_out_dmarequest_update(s); 156 } 157 158 if (start) 159 s->codec.txlen = 0; 160 } 161 162 static void omap_eac_in_cb(void *opaque, int avail_b) 163 { 164 struct omap_eac_s *s = (struct omap_eac_s *) opaque; 165 166 s->codec.rxavail = avail_b >> 2; 167 omap_eac_in_refill(s); 168 /* TODO: possibly discard current buffer if overrun */ 169 omap_eac_in_dmarequest_update(s); 170 } 171 172 static void omap_eac_out_cb(void *opaque, int free_b) 173 { 174 struct omap_eac_s *s = (struct omap_eac_s *) opaque; 175 176 s->codec.txavail = free_b >> 2; 177 if (s->codec.txlen) 178 omap_eac_out_empty(s); 179 else 180 omap_eac_out_dmarequest_update(s); 181 } 182 183 static void omap_eac_enable_update(struct omap_eac_s *s) 184 { 185 s->codec.enable = !(s->codec.config[1] & 1) && /* EACPWD */ 186 (s->codec.config[1] & 2) && /* AUDEN */ 187 s->codec.hw_enable; 188 } 189 190 static const int omap_eac_fsint[4] = { 191 8000, 192 11025, 193 22050, 194 44100, 195 }; 196 197 static const int omap_eac_fsint2[8] = { 198 8000, 199 11025, 200 22050, 201 44100, 202 48000, 203 0, 0, 0, 204 }; 205 206 static const int omap_eac_fsint3[16] = { 207 8000, 208 11025, 209 16000, 210 22050, 211 24000, 212 32000, 213 44100, 214 48000, 215 0, 0, 0, 0, 0, 0, 0, 0, 216 }; 217 218 static void omap_eac_rate_update(struct omap_eac_s *s) 219 { 220 int fsint[3]; 221 222 fsint[2] = (s->codec.config[3] >> 9) & 0xf; 223 fsint[1] = (s->codec.config[2] >> 0) & 0x7; 224 fsint[0] = (s->codec.config[0] >> 6) & 0x3; 225 if (fsint[2] < 0xf) 226 s->codec.rate = omap_eac_fsint3[fsint[2]]; 227 else if (fsint[1] < 0x7) 228 s->codec.rate = omap_eac_fsint2[fsint[1]]; 229 else 230 s->codec.rate = omap_eac_fsint[fsint[0]]; 231 } 232 233 static void omap_eac_volume_update(struct omap_eac_s *s) 234 { 235 /* TODO */ 236 } 237 238 static void omap_eac_format_update(struct omap_eac_s *s) 239 { 240 struct audsettings fmt; 241 242 /* The hardware buffers at most one sample */ 243 if (s->codec.rxlen) 244 s->codec.rxlen = 1; 245 246 if (s->codec.in_voice) { 247 AUD_set_active_in(s->codec.in_voice, 0); 248 AUD_close_in(&s->codec.card, s->codec.in_voice); 249 s->codec.in_voice = NULL; 250 } 251 if (s->codec.out_voice) { 252 omap_eac_out_empty(s); 253 AUD_set_active_out(s->codec.out_voice, 0); 254 AUD_close_out(&s->codec.card, s->codec.out_voice); 255 s->codec.out_voice = NULL; 256 s->codec.txavail = 0; 257 } 258 /* Discard what couldn't be written */ 259 s->codec.txlen = 0; 260 261 omap_eac_enable_update(s); 262 if (!s->codec.enable) 263 return; 264 265 omap_eac_rate_update(s); 266 fmt.endianness = ((s->codec.config[0] >> 8) & 1); /* LI_BI */ 267 fmt.nchannels = ((s->codec.config[0] >> 10) & 1) ? 2 : 1; /* MN_ST */ 268 fmt.freq = s->codec.rate; 269 /* TODO: signedness possibly depends on the CODEC hardware - or 270 * does I2S specify it? */ 271 /* All register writes are 16 bits so we we store 16-bit samples 272 * in the buffers regardless of AGCFR[B8_16] value. */ 273 fmt.fmt = AUD_FMT_U16; 274 275 s->codec.in_voice = AUD_open_in(&s->codec.card, s->codec.in_voice, 276 "eac.codec.in", s, omap_eac_in_cb, &fmt); 277 s->codec.out_voice = AUD_open_out(&s->codec.card, s->codec.out_voice, 278 "eac.codec.out", s, omap_eac_out_cb, &fmt); 279 280 omap_eac_volume_update(s); 281 282 AUD_set_active_in(s->codec.in_voice, 1); 283 AUD_set_active_out(s->codec.out_voice, 1); 284 } 285 286 static void omap_eac_reset(struct omap_eac_s *s) 287 { 288 s->sysconfig = 0; 289 s->config[0] = 0x0c; 290 s->config[1] = 0x09; 291 s->config[2] = 0xab; 292 s->config[3] = 0x03; 293 s->control = 0x00; 294 s->address = 0x00; 295 s->data = 0x0000; 296 s->vtol = 0x00; 297 s->vtsl = 0x00; 298 s->mixer = 0x0000; 299 s->gain[0] = 0xe7e7; 300 s->gain[1] = 0x6767; 301 s->gain[2] = 0x6767; 302 s->gain[3] = 0x6767; 303 s->att = 0xce; 304 s->max[0] = 0; 305 s->max[1] = 0; 306 s->max[2] = 0; 307 s->max[3] = 0; 308 s->max[4] = 0; 309 s->max[5] = 0; 310 s->max[6] = 0; 311 312 s->modem.control = 0x00; 313 s->modem.config = 0x0000; 314 s->bt.control = 0x00; 315 s->bt.config = 0x0000; 316 s->codec.config[0] = 0x0649; 317 s->codec.config[1] = 0x0000; 318 s->codec.config[2] = 0x0007; 319 s->codec.config[3] = 0x1ffc; 320 s->codec.rxoff = 0; 321 s->codec.rxlen = 0; 322 s->codec.txlen = 0; 323 s->codec.rxavail = 0; 324 s->codec.txavail = 0; 325 326 omap_eac_format_update(s); 327 omap_eac_interrupt_update(s); 328 } 329 330 static uint64_t omap_eac_read(void *opaque, hwaddr addr, 331 unsigned size) 332 { 333 struct omap_eac_s *s = (struct omap_eac_s *) opaque; 334 uint32_t ret; 335 336 if (size != 2) { 337 return omap_badwidth_read16(opaque, addr); 338 } 339 340 switch (addr) { 341 case 0x000: /* CPCFR1 */ 342 return s->config[0]; 343 case 0x004: /* CPCFR2 */ 344 return s->config[1]; 345 case 0x008: /* CPCFR3 */ 346 return s->config[2]; 347 case 0x00c: /* CPCFR4 */ 348 return s->config[3]; 349 350 case 0x010: /* CPTCTL */ 351 return s->control | ((s->codec.rxavail + s->codec.rxlen > 0) << 7) | 352 ((s->codec.txlen < s->codec.txavail) << 5); 353 354 case 0x014: /* CPTTADR */ 355 return s->address; 356 case 0x018: /* CPTDATL */ 357 return s->data & 0xff; 358 case 0x01c: /* CPTDATH */ 359 return s->data >> 8; 360 case 0x020: /* CPTVSLL */ 361 return s->vtol; 362 case 0x024: /* CPTVSLH */ 363 return s->vtsl | (3 << 5); /* CRDY1 | CRDY2 */ 364 case 0x040: /* MPCTR */ 365 return s->modem.control; 366 case 0x044: /* MPMCCFR */ 367 return s->modem.config; 368 case 0x060: /* BPCTR */ 369 return s->bt.control; 370 case 0x064: /* BPMCCFR */ 371 return s->bt.config; 372 case 0x080: /* AMSCFR */ 373 return s->mixer; 374 case 0x084: /* AMVCTR */ 375 return s->gain[0]; 376 case 0x088: /* AM1VCTR */ 377 return s->gain[1]; 378 case 0x08c: /* AM2VCTR */ 379 return s->gain[2]; 380 case 0x090: /* AM3VCTR */ 381 return s->gain[3]; 382 case 0x094: /* ASTCTR */ 383 return s->att; 384 case 0x098: /* APD1LCR */ 385 return s->max[0]; 386 case 0x09c: /* APD1RCR */ 387 return s->max[1]; 388 case 0x0a0: /* APD2LCR */ 389 return s->max[2]; 390 case 0x0a4: /* APD2RCR */ 391 return s->max[3]; 392 case 0x0a8: /* APD3LCR */ 393 return s->max[4]; 394 case 0x0ac: /* APD3RCR */ 395 return s->max[5]; 396 case 0x0b0: /* APD4R */ 397 return s->max[6]; 398 case 0x0b4: /* ADWR */ 399 /* This should be write-only? Docs list it as read-only. */ 400 return 0x0000; 401 case 0x0b8: /* ADRDR */ 402 if (likely(s->codec.rxlen > 1)) { 403 ret = s->codec.rxbuf[s->codec.rxoff ++]; 404 s->codec.rxlen --; 405 s->codec.rxoff &= EAC_BUF_LEN - 1; 406 return ret; 407 } else if (s->codec.rxlen) { 408 ret = s->codec.rxbuf[s->codec.rxoff ++]; 409 s->codec.rxlen --; 410 s->codec.rxoff &= EAC_BUF_LEN - 1; 411 if (s->codec.rxavail) 412 omap_eac_in_refill(s); 413 omap_eac_in_dmarequest_update(s); 414 return ret; 415 } 416 return 0x0000; 417 case 0x0bc: /* AGCFR */ 418 return s->codec.config[0]; 419 case 0x0c0: /* AGCTR */ 420 return s->codec.config[1] | ((s->codec.config[1] & 2) << 14); 421 case 0x0c4: /* AGCFR2 */ 422 return s->codec.config[2]; 423 case 0x0c8: /* AGCFR3 */ 424 return s->codec.config[3]; 425 case 0x0cc: /* MBPDMACTR */ 426 case 0x0d0: /* MPDDMARR */ 427 case 0x0d8: /* MPUDMARR */ 428 case 0x0e4: /* BPDDMARR */ 429 case 0x0ec: /* BPUDMARR */ 430 return 0x0000; 431 432 case 0x100: /* VERSION_NUMBER */ 433 return 0x0010; 434 435 case 0x104: /* SYSCONFIG */ 436 return s->sysconfig; 437 438 case 0x108: /* SYSSTATUS */ 439 return 1 | 0xe; /* RESETDONE | stuff */ 440 } 441 442 OMAP_BAD_REG(addr); 443 return 0; 444 } 445 446 static void omap_eac_write(void *opaque, hwaddr addr, 447 uint64_t value, unsigned size) 448 { 449 struct omap_eac_s *s = (struct omap_eac_s *) opaque; 450 451 if (size != 2) { 452 omap_badwidth_write16(opaque, addr, value); 453 return; 454 } 455 456 switch (addr) { 457 case 0x098: /* APD1LCR */ 458 case 0x09c: /* APD1RCR */ 459 case 0x0a0: /* APD2LCR */ 460 case 0x0a4: /* APD2RCR */ 461 case 0x0a8: /* APD3LCR */ 462 case 0x0ac: /* APD3RCR */ 463 case 0x0b0: /* APD4R */ 464 case 0x0b8: /* ADRDR */ 465 case 0x0d0: /* MPDDMARR */ 466 case 0x0d8: /* MPUDMARR */ 467 case 0x0e4: /* BPDDMARR */ 468 case 0x0ec: /* BPUDMARR */ 469 case 0x100: /* VERSION_NUMBER */ 470 case 0x108: /* SYSSTATUS */ 471 OMAP_RO_REG(addr); 472 return; 473 474 case 0x000: /* CPCFR1 */ 475 s->config[0] = value & 0xff; 476 omap_eac_format_update(s); 477 break; 478 case 0x004: /* CPCFR2 */ 479 s->config[1] = value & 0xff; 480 omap_eac_format_update(s); 481 break; 482 case 0x008: /* CPCFR3 */ 483 s->config[2] = value & 0xff; 484 omap_eac_format_update(s); 485 break; 486 case 0x00c: /* CPCFR4 */ 487 s->config[3] = value & 0xff; 488 omap_eac_format_update(s); 489 break; 490 491 case 0x010: /* CPTCTL */ 492 /* Assuming TXF and TXE bits are read-only... */ 493 s->control = value & 0x5f; 494 omap_eac_interrupt_update(s); 495 break; 496 497 case 0x014: /* CPTTADR */ 498 s->address = value & 0xff; 499 break; 500 case 0x018: /* CPTDATL */ 501 s->data &= 0xff00; 502 s->data |= value & 0xff; 503 break; 504 case 0x01c: /* CPTDATH */ 505 s->data &= 0x00ff; 506 s->data |= value << 8; 507 break; 508 case 0x020: /* CPTVSLL */ 509 s->vtol = value & 0xf8; 510 break; 511 case 0x024: /* CPTVSLH */ 512 s->vtsl = value & 0x9f; 513 break; 514 case 0x040: /* MPCTR */ 515 s->modem.control = value & 0x8f; 516 break; 517 case 0x044: /* MPMCCFR */ 518 s->modem.config = value & 0x7fff; 519 break; 520 case 0x060: /* BPCTR */ 521 s->bt.control = value & 0x8f; 522 break; 523 case 0x064: /* BPMCCFR */ 524 s->bt.config = value & 0x7fff; 525 break; 526 case 0x080: /* AMSCFR */ 527 s->mixer = value & 0x0fff; 528 break; 529 case 0x084: /* AMVCTR */ 530 s->gain[0] = value & 0xffff; 531 break; 532 case 0x088: /* AM1VCTR */ 533 s->gain[1] = value & 0xff7f; 534 break; 535 case 0x08c: /* AM2VCTR */ 536 s->gain[2] = value & 0xff7f; 537 break; 538 case 0x090: /* AM3VCTR */ 539 s->gain[3] = value & 0xff7f; 540 break; 541 case 0x094: /* ASTCTR */ 542 s->att = value & 0xff; 543 break; 544 545 case 0x0b4: /* ADWR */ 546 s->codec.txbuf[s->codec.txlen ++] = value; 547 if (unlikely(s->codec.txlen == EAC_BUF_LEN || 548 s->codec.txlen == s->codec.txavail)) { 549 if (s->codec.txavail) 550 omap_eac_out_empty(s); 551 /* Discard what couldn't be written */ 552 s->codec.txlen = 0; 553 } 554 break; 555 556 case 0x0bc: /* AGCFR */ 557 s->codec.config[0] = value & 0x07ff; 558 omap_eac_format_update(s); 559 break; 560 case 0x0c0: /* AGCTR */ 561 s->codec.config[1] = value & 0x780f; 562 omap_eac_format_update(s); 563 break; 564 case 0x0c4: /* AGCFR2 */ 565 s->codec.config[2] = value & 0x003f; 566 omap_eac_format_update(s); 567 break; 568 case 0x0c8: /* AGCFR3 */ 569 s->codec.config[3] = value & 0xffff; 570 omap_eac_format_update(s); 571 break; 572 case 0x0cc: /* MBPDMACTR */ 573 case 0x0d4: /* MPDDMAWR */ 574 case 0x0e0: /* MPUDMAWR */ 575 case 0x0e8: /* BPDDMAWR */ 576 case 0x0f0: /* BPUDMAWR */ 577 break; 578 579 case 0x104: /* SYSCONFIG */ 580 if (value & (1 << 1)) /* SOFTRESET */ 581 omap_eac_reset(s); 582 s->sysconfig = value & 0x31d; 583 break; 584 585 default: 586 OMAP_BAD_REG(addr); 587 return; 588 } 589 } 590 591 static const MemoryRegionOps omap_eac_ops = { 592 .read = omap_eac_read, 593 .write = omap_eac_write, 594 .endianness = DEVICE_NATIVE_ENDIAN, 595 }; 596 597 static struct omap_eac_s *omap_eac_init(struct omap_target_agent_s *ta, 598 qemu_irq irq, qemu_irq *drq, omap_clk fclk, omap_clk iclk) 599 { 600 struct omap_eac_s *s = g_new0(struct omap_eac_s, 1); 601 602 s->irq = irq; 603 s->codec.rxdrq = *drq ++; 604 s->codec.txdrq = *drq; 605 omap_eac_reset(s); 606 607 AUD_register_card("OMAP EAC", &s->codec.card); 608 609 memory_region_init_io(&s->iomem, NULL, &omap_eac_ops, s, "omap.eac", 610 omap_l4_region_size(ta, 0)); 611 omap_l4_attach(ta, 0, &s->iomem); 612 613 return s; 614 } 615 616 /* STI/XTI (emulation interface) console - reverse engineered only */ 617 struct omap_sti_s { 618 qemu_irq irq; 619 MemoryRegion iomem; 620 MemoryRegion iomem_fifo; 621 CharDriverState *chr; 622 623 uint32_t sysconfig; 624 uint32_t systest; 625 uint32_t irqst; 626 uint32_t irqen; 627 uint32_t clkcontrol; 628 uint32_t serial_config; 629 }; 630 631 #define STI_TRACE_CONSOLE_CHANNEL 239 632 #define STI_TRACE_CONTROL_CHANNEL 253 633 634 static inline void omap_sti_interrupt_update(struct omap_sti_s *s) 635 { 636 qemu_set_irq(s->irq, s->irqst & s->irqen); 637 } 638 639 static void omap_sti_reset(struct omap_sti_s *s) 640 { 641 s->sysconfig = 0; 642 s->irqst = 0; 643 s->irqen = 0; 644 s->clkcontrol = 0; 645 s->serial_config = 0; 646 647 omap_sti_interrupt_update(s); 648 } 649 650 static uint64_t omap_sti_read(void *opaque, hwaddr addr, 651 unsigned size) 652 { 653 struct omap_sti_s *s = (struct omap_sti_s *) opaque; 654 655 if (size != 4) { 656 return omap_badwidth_read32(opaque, addr); 657 } 658 659 switch (addr) { 660 case 0x00: /* STI_REVISION */ 661 return 0x10; 662 663 case 0x10: /* STI_SYSCONFIG */ 664 return s->sysconfig; 665 666 case 0x14: /* STI_SYSSTATUS / STI_RX_STATUS / XTI_SYSSTATUS */ 667 return 0x00; 668 669 case 0x18: /* STI_IRQSTATUS */ 670 return s->irqst; 671 672 case 0x1c: /* STI_IRQSETEN / STI_IRQCLREN */ 673 return s->irqen; 674 675 case 0x24: /* STI_ER / STI_DR / XTI_TRACESELECT */ 676 case 0x28: /* STI_RX_DR / XTI_RXDATA */ 677 /* TODO */ 678 return 0; 679 680 case 0x2c: /* STI_CLK_CTRL / XTI_SCLKCRTL */ 681 return s->clkcontrol; 682 683 case 0x30: /* STI_SERIAL_CFG / XTI_SCONFIG */ 684 return s->serial_config; 685 } 686 687 OMAP_BAD_REG(addr); 688 return 0; 689 } 690 691 static void omap_sti_write(void *opaque, hwaddr addr, 692 uint64_t value, unsigned size) 693 { 694 struct omap_sti_s *s = (struct omap_sti_s *) opaque; 695 696 if (size != 4) { 697 omap_badwidth_write32(opaque, addr, value); 698 return; 699 } 700 701 switch (addr) { 702 case 0x00: /* STI_REVISION */ 703 case 0x14: /* STI_SYSSTATUS / STI_RX_STATUS / XTI_SYSSTATUS */ 704 OMAP_RO_REG(addr); 705 return; 706 707 case 0x10: /* STI_SYSCONFIG */ 708 if (value & (1 << 1)) /* SOFTRESET */ 709 omap_sti_reset(s); 710 s->sysconfig = value & 0xfe; 711 break; 712 713 case 0x18: /* STI_IRQSTATUS */ 714 s->irqst &= ~value; 715 omap_sti_interrupt_update(s); 716 break; 717 718 case 0x1c: /* STI_IRQSETEN / STI_IRQCLREN */ 719 s->irqen = value & 0xffff; 720 omap_sti_interrupt_update(s); 721 break; 722 723 case 0x2c: /* STI_CLK_CTRL / XTI_SCLKCRTL */ 724 s->clkcontrol = value & 0xff; 725 break; 726 727 case 0x30: /* STI_SERIAL_CFG / XTI_SCONFIG */ 728 s->serial_config = value & 0xff; 729 break; 730 731 case 0x24: /* STI_ER / STI_DR / XTI_TRACESELECT */ 732 case 0x28: /* STI_RX_DR / XTI_RXDATA */ 733 /* TODO */ 734 return; 735 736 default: 737 OMAP_BAD_REG(addr); 738 return; 739 } 740 } 741 742 static const MemoryRegionOps omap_sti_ops = { 743 .read = omap_sti_read, 744 .write = omap_sti_write, 745 .endianness = DEVICE_NATIVE_ENDIAN, 746 }; 747 748 static uint64_t omap_sti_fifo_read(void *opaque, hwaddr addr, 749 unsigned size) 750 { 751 OMAP_BAD_REG(addr); 752 return 0; 753 } 754 755 static void omap_sti_fifo_write(void *opaque, hwaddr addr, 756 uint64_t value, unsigned size) 757 { 758 struct omap_sti_s *s = (struct omap_sti_s *) opaque; 759 int ch = addr >> 6; 760 uint8_t byte = value; 761 762 if (size != 1) { 763 omap_badwidth_write8(opaque, addr, size); 764 return; 765 } 766 767 if (ch == STI_TRACE_CONTROL_CHANNEL) { 768 /* Flush channel <i>value</i>. */ 769 qemu_chr_fe_write(s->chr, (const uint8_t *) "\r", 1); 770 } else if (ch == STI_TRACE_CONSOLE_CHANNEL || 1) { 771 if (value == 0xc0 || value == 0xc3) { 772 /* Open channel <i>ch</i>. */ 773 } else if (value == 0x00) 774 qemu_chr_fe_write(s->chr, (const uint8_t *) "\n", 1); 775 else 776 qemu_chr_fe_write(s->chr, &byte, 1); 777 } 778 } 779 780 static const MemoryRegionOps omap_sti_fifo_ops = { 781 .read = omap_sti_fifo_read, 782 .write = omap_sti_fifo_write, 783 .endianness = DEVICE_NATIVE_ENDIAN, 784 }; 785 786 static struct omap_sti_s *omap_sti_init(struct omap_target_agent_s *ta, 787 MemoryRegion *sysmem, 788 hwaddr channel_base, qemu_irq irq, omap_clk clk, 789 CharDriverState *chr) 790 { 791 struct omap_sti_s *s = g_new0(struct omap_sti_s, 1); 792 793 s->irq = irq; 794 omap_sti_reset(s); 795 796 s->chr = chr ?: qemu_chr_new("null", "null", NULL); 797 798 memory_region_init_io(&s->iomem, NULL, &omap_sti_ops, s, "omap.sti", 799 omap_l4_region_size(ta, 0)); 800 omap_l4_attach(ta, 0, &s->iomem); 801 802 memory_region_init_io(&s->iomem_fifo, NULL, &omap_sti_fifo_ops, s, 803 "omap.sti.fifo", 0x10000); 804 memory_region_add_subregion(sysmem, channel_base, &s->iomem_fifo); 805 806 return s; 807 } 808 809 /* L4 Interconnect */ 810 #define L4TA(n) (n) 811 #define L4TAO(n) ((n) + 39) 812 813 static const struct omap_l4_region_s omap_l4_region[125] = { 814 [ 1] = { 0x40800, 0x800, 32 }, /* Initiator agent */ 815 [ 2] = { 0x41000, 0x1000, 32 }, /* Link agent */ 816 [ 0] = { 0x40000, 0x800, 32 }, /* Address and protection */ 817 [ 3] = { 0x00000, 0x1000, 32 | 16 | 8 }, /* System Control and Pinout */ 818 [ 4] = { 0x01000, 0x1000, 32 | 16 | 8 }, /* L4TAO1 */ 819 [ 5] = { 0x04000, 0x1000, 32 | 16 }, /* 32K Timer */ 820 [ 6] = { 0x05000, 0x1000, 32 | 16 | 8 }, /* L4TAO2 */ 821 [ 7] = { 0x08000, 0x800, 32 }, /* PRCM Region A */ 822 [ 8] = { 0x08800, 0x800, 32 }, /* PRCM Region B */ 823 [ 9] = { 0x09000, 0x1000, 32 | 16 | 8 }, /* L4TAO */ 824 [ 10] = { 0x12000, 0x1000, 32 | 16 | 8 }, /* Test (BCM) */ 825 [ 11] = { 0x13000, 0x1000, 32 | 16 | 8 }, /* L4TA1 */ 826 [ 12] = { 0x14000, 0x1000, 32 }, /* Test/emulation (TAP) */ 827 [ 13] = { 0x15000, 0x1000, 32 | 16 | 8 }, /* L4TA2 */ 828 [ 14] = { 0x18000, 0x1000, 32 | 16 | 8 }, /* GPIO1 */ 829 [ 16] = { 0x1a000, 0x1000, 32 | 16 | 8 }, /* GPIO2 */ 830 [ 18] = { 0x1c000, 0x1000, 32 | 16 | 8 }, /* GPIO3 */ 831 [ 19] = { 0x1e000, 0x1000, 32 | 16 | 8 }, /* GPIO4 */ 832 [ 15] = { 0x19000, 0x1000, 32 | 16 | 8 }, /* Quad GPIO TOP */ 833 [ 17] = { 0x1b000, 0x1000, 32 | 16 | 8 }, /* L4TA3 */ 834 [ 20] = { 0x20000, 0x1000, 32 | 16 | 8 }, /* WD Timer 1 (Secure) */ 835 [ 22] = { 0x22000, 0x1000, 32 | 16 | 8 }, /* WD Timer 2 (OMAP) */ 836 [ 21] = { 0x21000, 0x1000, 32 | 16 | 8 }, /* Dual WD timer TOP */ 837 [ 23] = { 0x23000, 0x1000, 32 | 16 | 8 }, /* L4TA4 */ 838 [ 24] = { 0x28000, 0x1000, 32 | 16 | 8 }, /* GP Timer 1 */ 839 [ 25] = { 0x29000, 0x1000, 32 | 16 | 8 }, /* L4TA7 */ 840 [ 26] = { 0x48000, 0x2000, 32 | 16 | 8 }, /* Emulation (ARM11ETB) */ 841 [ 27] = { 0x4a000, 0x1000, 32 | 16 | 8 }, /* L4TA9 */ 842 [ 28] = { 0x50000, 0x400, 32 | 16 | 8 }, /* Display top */ 843 [ 29] = { 0x50400, 0x400, 32 | 16 | 8 }, /* Display control */ 844 [ 30] = { 0x50800, 0x400, 32 | 16 | 8 }, /* Display RFBI */ 845 [ 31] = { 0x50c00, 0x400, 32 | 16 | 8 }, /* Display encoder */ 846 [ 32] = { 0x51000, 0x1000, 32 | 16 | 8 }, /* L4TA10 */ 847 [ 33] = { 0x52000, 0x400, 32 | 16 | 8 }, /* Camera top */ 848 [ 34] = { 0x52400, 0x400, 32 | 16 | 8 }, /* Camera core */ 849 [ 35] = { 0x52800, 0x400, 32 | 16 | 8 }, /* Camera DMA */ 850 [ 36] = { 0x52c00, 0x400, 32 | 16 | 8 }, /* Camera MMU */ 851 [ 37] = { 0x53000, 0x1000, 32 | 16 | 8 }, /* L4TA11 */ 852 [ 38] = { 0x56000, 0x1000, 32 | 16 | 8 }, /* sDMA */ 853 [ 39] = { 0x57000, 0x1000, 32 | 16 | 8 }, /* L4TA12 */ 854 [ 40] = { 0x58000, 0x1000, 32 | 16 | 8 }, /* SSI top */ 855 [ 41] = { 0x59000, 0x1000, 32 | 16 | 8 }, /* SSI GDD */ 856 [ 42] = { 0x5a000, 0x1000, 32 | 16 | 8 }, /* SSI Port1 */ 857 [ 43] = { 0x5b000, 0x1000, 32 | 16 | 8 }, /* SSI Port2 */ 858 [ 44] = { 0x5c000, 0x1000, 32 | 16 | 8 }, /* L4TA13 */ 859 [ 45] = { 0x5e000, 0x1000, 32 | 16 | 8 }, /* USB OTG */ 860 [ 46] = { 0x5f000, 0x1000, 32 | 16 | 8 }, /* L4TAO4 */ 861 [ 47] = { 0x60000, 0x1000, 32 | 16 | 8 }, /* Emulation (WIN_TRACER1SDRC) */ 862 [ 48] = { 0x61000, 0x1000, 32 | 16 | 8 }, /* L4TA14 */ 863 [ 49] = { 0x62000, 0x1000, 32 | 16 | 8 }, /* Emulation (WIN_TRACER2GPMC) */ 864 [ 50] = { 0x63000, 0x1000, 32 | 16 | 8 }, /* L4TA15 */ 865 [ 51] = { 0x64000, 0x1000, 32 | 16 | 8 }, /* Emulation (WIN_TRACER3OCM) */ 866 [ 52] = { 0x65000, 0x1000, 32 | 16 | 8 }, /* L4TA16 */ 867 [ 53] = { 0x66000, 0x300, 32 | 16 | 8 }, /* Emulation (WIN_TRACER4L4) */ 868 [ 54] = { 0x67000, 0x1000, 32 | 16 | 8 }, /* L4TA17 */ 869 [ 55] = { 0x68000, 0x1000, 32 | 16 | 8 }, /* Emulation (XTI) */ 870 [ 56] = { 0x69000, 0x1000, 32 | 16 | 8 }, /* L4TA18 */ 871 [ 57] = { 0x6a000, 0x1000, 16 | 8 }, /* UART1 */ 872 [ 58] = { 0x6b000, 0x1000, 32 | 16 | 8 }, /* L4TA19 */ 873 [ 59] = { 0x6c000, 0x1000, 16 | 8 }, /* UART2 */ 874 [ 60] = { 0x6d000, 0x1000, 32 | 16 | 8 }, /* L4TA20 */ 875 [ 61] = { 0x6e000, 0x1000, 16 | 8 }, /* UART3 */ 876 [ 62] = { 0x6f000, 0x1000, 32 | 16 | 8 }, /* L4TA21 */ 877 [ 63] = { 0x70000, 0x1000, 16 }, /* I2C1 */ 878 [ 64] = { 0x71000, 0x1000, 32 | 16 | 8 }, /* L4TAO5 */ 879 [ 65] = { 0x72000, 0x1000, 16 }, /* I2C2 */ 880 [ 66] = { 0x73000, 0x1000, 32 | 16 | 8 }, /* L4TAO6 */ 881 [ 67] = { 0x74000, 0x1000, 16 }, /* McBSP1 */ 882 [ 68] = { 0x75000, 0x1000, 32 | 16 | 8 }, /* L4TAO7 */ 883 [ 69] = { 0x76000, 0x1000, 16 }, /* McBSP2 */ 884 [ 70] = { 0x77000, 0x1000, 32 | 16 | 8 }, /* L4TAO8 */ 885 [ 71] = { 0x24000, 0x1000, 32 | 16 | 8 }, /* WD Timer 3 (DSP) */ 886 [ 72] = { 0x25000, 0x1000, 32 | 16 | 8 }, /* L4TA5 */ 887 [ 73] = { 0x26000, 0x1000, 32 | 16 | 8 }, /* WD Timer 4 (IVA) */ 888 [ 74] = { 0x27000, 0x1000, 32 | 16 | 8 }, /* L4TA6 */ 889 [ 75] = { 0x2a000, 0x1000, 32 | 16 | 8 }, /* GP Timer 2 */ 890 [ 76] = { 0x2b000, 0x1000, 32 | 16 | 8 }, /* L4TA8 */ 891 [ 77] = { 0x78000, 0x1000, 32 | 16 | 8 }, /* GP Timer 3 */ 892 [ 78] = { 0x79000, 0x1000, 32 | 16 | 8 }, /* L4TA22 */ 893 [ 79] = { 0x7a000, 0x1000, 32 | 16 | 8 }, /* GP Timer 4 */ 894 [ 80] = { 0x7b000, 0x1000, 32 | 16 | 8 }, /* L4TA23 */ 895 [ 81] = { 0x7c000, 0x1000, 32 | 16 | 8 }, /* GP Timer 5 */ 896 [ 82] = { 0x7d000, 0x1000, 32 | 16 | 8 }, /* L4TA24 */ 897 [ 83] = { 0x7e000, 0x1000, 32 | 16 | 8 }, /* GP Timer 6 */ 898 [ 84] = { 0x7f000, 0x1000, 32 | 16 | 8 }, /* L4TA25 */ 899 [ 85] = { 0x80000, 0x1000, 32 | 16 | 8 }, /* GP Timer 7 */ 900 [ 86] = { 0x81000, 0x1000, 32 | 16 | 8 }, /* L4TA26 */ 901 [ 87] = { 0x82000, 0x1000, 32 | 16 | 8 }, /* GP Timer 8 */ 902 [ 88] = { 0x83000, 0x1000, 32 | 16 | 8 }, /* L4TA27 */ 903 [ 89] = { 0x84000, 0x1000, 32 | 16 | 8 }, /* GP Timer 9 */ 904 [ 90] = { 0x85000, 0x1000, 32 | 16 | 8 }, /* L4TA28 */ 905 [ 91] = { 0x86000, 0x1000, 32 | 16 | 8 }, /* GP Timer 10 */ 906 [ 92] = { 0x87000, 0x1000, 32 | 16 | 8 }, /* L4TA29 */ 907 [ 93] = { 0x88000, 0x1000, 32 | 16 | 8 }, /* GP Timer 11 */ 908 [ 94] = { 0x89000, 0x1000, 32 | 16 | 8 }, /* L4TA30 */ 909 [ 95] = { 0x8a000, 0x1000, 32 | 16 | 8 }, /* GP Timer 12 */ 910 [ 96] = { 0x8b000, 0x1000, 32 | 16 | 8 }, /* L4TA31 */ 911 [ 97] = { 0x90000, 0x1000, 16 }, /* EAC */ 912 [ 98] = { 0x91000, 0x1000, 32 | 16 | 8 }, /* L4TA32 */ 913 [ 99] = { 0x92000, 0x1000, 16 }, /* FAC */ 914 [100] = { 0x93000, 0x1000, 32 | 16 | 8 }, /* L4TA33 */ 915 [101] = { 0x94000, 0x1000, 32 | 16 | 8 }, /* IPC (MAILBOX) */ 916 [102] = { 0x95000, 0x1000, 32 | 16 | 8 }, /* L4TA34 */ 917 [103] = { 0x98000, 0x1000, 32 | 16 | 8 }, /* SPI1 */ 918 [104] = { 0x99000, 0x1000, 32 | 16 | 8 }, /* L4TA35 */ 919 [105] = { 0x9a000, 0x1000, 32 | 16 | 8 }, /* SPI2 */ 920 [106] = { 0x9b000, 0x1000, 32 | 16 | 8 }, /* L4TA36 */ 921 [107] = { 0x9c000, 0x1000, 16 | 8 }, /* MMC SDIO */ 922 [108] = { 0x9d000, 0x1000, 32 | 16 | 8 }, /* L4TAO9 */ 923 [109] = { 0x9e000, 0x1000, 32 | 16 | 8 }, /* MS_PRO */ 924 [110] = { 0x9f000, 0x1000, 32 | 16 | 8 }, /* L4TAO10 */ 925 [111] = { 0xa0000, 0x1000, 32 }, /* RNG */ 926 [112] = { 0xa1000, 0x1000, 32 | 16 | 8 }, /* L4TAO11 */ 927 [113] = { 0xa2000, 0x1000, 32 }, /* DES3DES */ 928 [114] = { 0xa3000, 0x1000, 32 | 16 | 8 }, /* L4TAO12 */ 929 [115] = { 0xa4000, 0x1000, 32 }, /* SHA1MD5 */ 930 [116] = { 0xa5000, 0x1000, 32 | 16 | 8 }, /* L4TAO13 */ 931 [117] = { 0xa6000, 0x1000, 32 }, /* AES */ 932 [118] = { 0xa7000, 0x1000, 32 | 16 | 8 }, /* L4TA37 */ 933 [119] = { 0xa8000, 0x2000, 32 }, /* PKA */ 934 [120] = { 0xaa000, 0x1000, 32 | 16 | 8 }, /* L4TA38 */ 935 [121] = { 0xb0000, 0x1000, 32 }, /* MG */ 936 [122] = { 0xb1000, 0x1000, 32 | 16 | 8 }, 937 [123] = { 0xb2000, 0x1000, 32 }, /* HDQ/1-Wire */ 938 [124] = { 0xb3000, 0x1000, 32 | 16 | 8 }, /* L4TA39 */ 939 }; 940 941 static const struct omap_l4_agent_info_s omap_l4_agent_info[54] = { 942 { 0, 0, 3, 2 }, /* L4IA initiatior agent */ 943 { L4TAO(1), 3, 2, 1 }, /* Control and pinout module */ 944 { L4TAO(2), 5, 2, 1 }, /* 32K timer */ 945 { L4TAO(3), 7, 3, 2 }, /* PRCM */ 946 { L4TA(1), 10, 2, 1 }, /* BCM */ 947 { L4TA(2), 12, 2, 1 }, /* Test JTAG */ 948 { L4TA(3), 14, 6, 3 }, /* Quad GPIO */ 949 { L4TA(4), 20, 4, 3 }, /* WD timer 1/2 */ 950 { L4TA(7), 24, 2, 1 }, /* GP timer 1 */ 951 { L4TA(9), 26, 2, 1 }, /* ATM11 ETB */ 952 { L4TA(10), 28, 5, 4 }, /* Display subsystem */ 953 { L4TA(11), 33, 5, 4 }, /* Camera subsystem */ 954 { L4TA(12), 38, 2, 1 }, /* sDMA */ 955 { L4TA(13), 40, 5, 4 }, /* SSI */ 956 { L4TAO(4), 45, 2, 1 }, /* USB */ 957 { L4TA(14), 47, 2, 1 }, /* Win Tracer1 */ 958 { L4TA(15), 49, 2, 1 }, /* Win Tracer2 */ 959 { L4TA(16), 51, 2, 1 }, /* Win Tracer3 */ 960 { L4TA(17), 53, 2, 1 }, /* Win Tracer4 */ 961 { L4TA(18), 55, 2, 1 }, /* XTI */ 962 { L4TA(19), 57, 2, 1 }, /* UART1 */ 963 { L4TA(20), 59, 2, 1 }, /* UART2 */ 964 { L4TA(21), 61, 2, 1 }, /* UART3 */ 965 { L4TAO(5), 63, 2, 1 }, /* I2C1 */ 966 { L4TAO(6), 65, 2, 1 }, /* I2C2 */ 967 { L4TAO(7), 67, 2, 1 }, /* McBSP1 */ 968 { L4TAO(8), 69, 2, 1 }, /* McBSP2 */ 969 { L4TA(5), 71, 2, 1 }, /* WD Timer 3 (DSP) */ 970 { L4TA(6), 73, 2, 1 }, /* WD Timer 4 (IVA) */ 971 { L4TA(8), 75, 2, 1 }, /* GP Timer 2 */ 972 { L4TA(22), 77, 2, 1 }, /* GP Timer 3 */ 973 { L4TA(23), 79, 2, 1 }, /* GP Timer 4 */ 974 { L4TA(24), 81, 2, 1 }, /* GP Timer 5 */ 975 { L4TA(25), 83, 2, 1 }, /* GP Timer 6 */ 976 { L4TA(26), 85, 2, 1 }, /* GP Timer 7 */ 977 { L4TA(27), 87, 2, 1 }, /* GP Timer 8 */ 978 { L4TA(28), 89, 2, 1 }, /* GP Timer 9 */ 979 { L4TA(29), 91, 2, 1 }, /* GP Timer 10 */ 980 { L4TA(30), 93, 2, 1 }, /* GP Timer 11 */ 981 { L4TA(31), 95, 2, 1 }, /* GP Timer 12 */ 982 { L4TA(32), 97, 2, 1 }, /* EAC */ 983 { L4TA(33), 99, 2, 1 }, /* FAC */ 984 { L4TA(34), 101, 2, 1 }, /* IPC */ 985 { L4TA(35), 103, 2, 1 }, /* SPI1 */ 986 { L4TA(36), 105, 2, 1 }, /* SPI2 */ 987 { L4TAO(9), 107, 2, 1 }, /* MMC SDIO */ 988 { L4TAO(10), 109, 2, 1 }, 989 { L4TAO(11), 111, 2, 1 }, /* RNG */ 990 { L4TAO(12), 113, 2, 1 }, /* DES3DES */ 991 { L4TAO(13), 115, 2, 1 }, /* SHA1MD5 */ 992 { L4TA(37), 117, 2, 1 }, /* AES */ 993 { L4TA(38), 119, 2, 1 }, /* PKA */ 994 { -1, 121, 2, 1 }, 995 { L4TA(39), 123, 2, 1 }, /* HDQ/1-Wire */ 996 }; 997 998 #define omap_l4ta(bus, cs) \ 999 omap_l4ta_get(bus, omap_l4_region, omap_l4_agent_info, L4TA(cs)) 1000 #define omap_l4tao(bus, cs) \ 1001 omap_l4ta_get(bus, omap_l4_region, omap_l4_agent_info, L4TAO(cs)) 1002 1003 /* Power, Reset, and Clock Management */ 1004 struct omap_prcm_s { 1005 qemu_irq irq[3]; 1006 struct omap_mpu_state_s *mpu; 1007 MemoryRegion iomem0; 1008 MemoryRegion iomem1; 1009 1010 uint32_t irqst[3]; 1011 uint32_t irqen[3]; 1012 1013 uint32_t sysconfig; 1014 uint32_t voltctrl; 1015 uint32_t scratch[20]; 1016 1017 uint32_t clksrc[1]; 1018 uint32_t clkout[1]; 1019 uint32_t clkemul[1]; 1020 uint32_t clkpol[1]; 1021 uint32_t clksel[8]; 1022 uint32_t clken[12]; 1023 uint32_t clkctrl[4]; 1024 uint32_t clkidle[7]; 1025 uint32_t setuptime[2]; 1026 1027 uint32_t wkup[3]; 1028 uint32_t wken[3]; 1029 uint32_t wkst[3]; 1030 uint32_t rst[4]; 1031 uint32_t rstctrl[1]; 1032 uint32_t power[4]; 1033 uint32_t rsttime_wkup; 1034 1035 uint32_t ev; 1036 uint32_t evtime[2]; 1037 1038 int dpll_lock, apll_lock[2]; 1039 }; 1040 1041 static void omap_prcm_int_update(struct omap_prcm_s *s, int dom) 1042 { 1043 qemu_set_irq(s->irq[dom], s->irqst[dom] & s->irqen[dom]); 1044 /* XXX or is the mask applied before PRCM_IRQSTATUS_* ? */ 1045 } 1046 1047 static uint64_t omap_prcm_read(void *opaque, hwaddr addr, 1048 unsigned size) 1049 { 1050 struct omap_prcm_s *s = (struct omap_prcm_s *) opaque; 1051 uint32_t ret; 1052 1053 if (size != 4) { 1054 return omap_badwidth_read32(opaque, addr); 1055 } 1056 1057 switch (addr) { 1058 case 0x000: /* PRCM_REVISION */ 1059 return 0x10; 1060 1061 case 0x010: /* PRCM_SYSCONFIG */ 1062 return s->sysconfig; 1063 1064 case 0x018: /* PRCM_IRQSTATUS_MPU */ 1065 return s->irqst[0]; 1066 1067 case 0x01c: /* PRCM_IRQENABLE_MPU */ 1068 return s->irqen[0]; 1069 1070 case 0x050: /* PRCM_VOLTCTRL */ 1071 return s->voltctrl; 1072 case 0x054: /* PRCM_VOLTST */ 1073 return s->voltctrl & 3; 1074 1075 case 0x060: /* PRCM_CLKSRC_CTRL */ 1076 return s->clksrc[0]; 1077 case 0x070: /* PRCM_CLKOUT_CTRL */ 1078 return s->clkout[0]; 1079 case 0x078: /* PRCM_CLKEMUL_CTRL */ 1080 return s->clkemul[0]; 1081 case 0x080: /* PRCM_CLKCFG_CTRL */ 1082 case 0x084: /* PRCM_CLKCFG_STATUS */ 1083 return 0; 1084 1085 case 0x090: /* PRCM_VOLTSETUP */ 1086 return s->setuptime[0]; 1087 1088 case 0x094: /* PRCM_CLKSSETUP */ 1089 return s->setuptime[1]; 1090 1091 case 0x098: /* PRCM_POLCTRL */ 1092 return s->clkpol[0]; 1093 1094 case 0x0b0: /* GENERAL_PURPOSE1 */ 1095 case 0x0b4: /* GENERAL_PURPOSE2 */ 1096 case 0x0b8: /* GENERAL_PURPOSE3 */ 1097 case 0x0bc: /* GENERAL_PURPOSE4 */ 1098 case 0x0c0: /* GENERAL_PURPOSE5 */ 1099 case 0x0c4: /* GENERAL_PURPOSE6 */ 1100 case 0x0c8: /* GENERAL_PURPOSE7 */ 1101 case 0x0cc: /* GENERAL_PURPOSE8 */ 1102 case 0x0d0: /* GENERAL_PURPOSE9 */ 1103 case 0x0d4: /* GENERAL_PURPOSE10 */ 1104 case 0x0d8: /* GENERAL_PURPOSE11 */ 1105 case 0x0dc: /* GENERAL_PURPOSE12 */ 1106 case 0x0e0: /* GENERAL_PURPOSE13 */ 1107 case 0x0e4: /* GENERAL_PURPOSE14 */ 1108 case 0x0e8: /* GENERAL_PURPOSE15 */ 1109 case 0x0ec: /* GENERAL_PURPOSE16 */ 1110 case 0x0f0: /* GENERAL_PURPOSE17 */ 1111 case 0x0f4: /* GENERAL_PURPOSE18 */ 1112 case 0x0f8: /* GENERAL_PURPOSE19 */ 1113 case 0x0fc: /* GENERAL_PURPOSE20 */ 1114 return s->scratch[(addr - 0xb0) >> 2]; 1115 1116 case 0x140: /* CM_CLKSEL_MPU */ 1117 return s->clksel[0]; 1118 case 0x148: /* CM_CLKSTCTRL_MPU */ 1119 return s->clkctrl[0]; 1120 1121 case 0x158: /* RM_RSTST_MPU */ 1122 return s->rst[0]; 1123 case 0x1c8: /* PM_WKDEP_MPU */ 1124 return s->wkup[0]; 1125 case 0x1d4: /* PM_EVGENCTRL_MPU */ 1126 return s->ev; 1127 case 0x1d8: /* PM_EVEGENONTIM_MPU */ 1128 return s->evtime[0]; 1129 case 0x1dc: /* PM_EVEGENOFFTIM_MPU */ 1130 return s->evtime[1]; 1131 case 0x1e0: /* PM_PWSTCTRL_MPU */ 1132 return s->power[0]; 1133 case 0x1e4: /* PM_PWSTST_MPU */ 1134 return 0; 1135 1136 case 0x200: /* CM_FCLKEN1_CORE */ 1137 return s->clken[0]; 1138 case 0x204: /* CM_FCLKEN2_CORE */ 1139 return s->clken[1]; 1140 case 0x210: /* CM_ICLKEN1_CORE */ 1141 return s->clken[2]; 1142 case 0x214: /* CM_ICLKEN2_CORE */ 1143 return s->clken[3]; 1144 case 0x21c: /* CM_ICLKEN4_CORE */ 1145 return s->clken[4]; 1146 1147 case 0x220: /* CM_IDLEST1_CORE */ 1148 /* TODO: check the actual iclk status */ 1149 return 0x7ffffff9; 1150 case 0x224: /* CM_IDLEST2_CORE */ 1151 /* TODO: check the actual iclk status */ 1152 return 0x00000007; 1153 case 0x22c: /* CM_IDLEST4_CORE */ 1154 /* TODO: check the actual iclk status */ 1155 return 0x0000001f; 1156 1157 case 0x230: /* CM_AUTOIDLE1_CORE */ 1158 return s->clkidle[0]; 1159 case 0x234: /* CM_AUTOIDLE2_CORE */ 1160 return s->clkidle[1]; 1161 case 0x238: /* CM_AUTOIDLE3_CORE */ 1162 return s->clkidle[2]; 1163 case 0x23c: /* CM_AUTOIDLE4_CORE */ 1164 return s->clkidle[3]; 1165 1166 case 0x240: /* CM_CLKSEL1_CORE */ 1167 return s->clksel[1]; 1168 case 0x244: /* CM_CLKSEL2_CORE */ 1169 return s->clksel[2]; 1170 1171 case 0x248: /* CM_CLKSTCTRL_CORE */ 1172 return s->clkctrl[1]; 1173 1174 case 0x2a0: /* PM_WKEN1_CORE */ 1175 return s->wken[0]; 1176 case 0x2a4: /* PM_WKEN2_CORE */ 1177 return s->wken[1]; 1178 1179 case 0x2b0: /* PM_WKST1_CORE */ 1180 return s->wkst[0]; 1181 case 0x2b4: /* PM_WKST2_CORE */ 1182 return s->wkst[1]; 1183 case 0x2c8: /* PM_WKDEP_CORE */ 1184 return 0x1e; 1185 1186 case 0x2e0: /* PM_PWSTCTRL_CORE */ 1187 return s->power[1]; 1188 case 0x2e4: /* PM_PWSTST_CORE */ 1189 return 0x000030 | (s->power[1] & 0xfc00); 1190 1191 case 0x300: /* CM_FCLKEN_GFX */ 1192 return s->clken[5]; 1193 case 0x310: /* CM_ICLKEN_GFX */ 1194 return s->clken[6]; 1195 case 0x320: /* CM_IDLEST_GFX */ 1196 /* TODO: check the actual iclk status */ 1197 return 0x00000001; 1198 case 0x340: /* CM_CLKSEL_GFX */ 1199 return s->clksel[3]; 1200 case 0x348: /* CM_CLKSTCTRL_GFX */ 1201 return s->clkctrl[2]; 1202 case 0x350: /* RM_RSTCTRL_GFX */ 1203 return s->rstctrl[0]; 1204 case 0x358: /* RM_RSTST_GFX */ 1205 return s->rst[1]; 1206 case 0x3c8: /* PM_WKDEP_GFX */ 1207 return s->wkup[1]; 1208 1209 case 0x3e0: /* PM_PWSTCTRL_GFX */ 1210 return s->power[2]; 1211 case 0x3e4: /* PM_PWSTST_GFX */ 1212 return s->power[2] & 3; 1213 1214 case 0x400: /* CM_FCLKEN_WKUP */ 1215 return s->clken[7]; 1216 case 0x410: /* CM_ICLKEN_WKUP */ 1217 return s->clken[8]; 1218 case 0x420: /* CM_IDLEST_WKUP */ 1219 /* TODO: check the actual iclk status */ 1220 return 0x0000003f; 1221 case 0x430: /* CM_AUTOIDLE_WKUP */ 1222 return s->clkidle[4]; 1223 case 0x440: /* CM_CLKSEL_WKUP */ 1224 return s->clksel[4]; 1225 case 0x450: /* RM_RSTCTRL_WKUP */ 1226 return 0; 1227 case 0x454: /* RM_RSTTIME_WKUP */ 1228 return s->rsttime_wkup; 1229 case 0x458: /* RM_RSTST_WKUP */ 1230 return s->rst[2]; 1231 case 0x4a0: /* PM_WKEN_WKUP */ 1232 return s->wken[2]; 1233 case 0x4b0: /* PM_WKST_WKUP */ 1234 return s->wkst[2]; 1235 1236 case 0x500: /* CM_CLKEN_PLL */ 1237 return s->clken[9]; 1238 case 0x520: /* CM_IDLEST_CKGEN */ 1239 ret = 0x0000070 | (s->apll_lock[0] << 9) | (s->apll_lock[1] << 8); 1240 if (!(s->clksel[6] & 3)) 1241 /* Core uses 32-kHz clock */ 1242 ret |= 3 << 0; 1243 else if (!s->dpll_lock) 1244 /* DPLL not locked, core uses ref_clk */ 1245 ret |= 1 << 0; 1246 else 1247 /* Core uses DPLL */ 1248 ret |= 2 << 0; 1249 return ret; 1250 case 0x530: /* CM_AUTOIDLE_PLL */ 1251 return s->clkidle[5]; 1252 case 0x540: /* CM_CLKSEL1_PLL */ 1253 return s->clksel[5]; 1254 case 0x544: /* CM_CLKSEL2_PLL */ 1255 return s->clksel[6]; 1256 1257 case 0x800: /* CM_FCLKEN_DSP */ 1258 return s->clken[10]; 1259 case 0x810: /* CM_ICLKEN_DSP */ 1260 return s->clken[11]; 1261 case 0x820: /* CM_IDLEST_DSP */ 1262 /* TODO: check the actual iclk status */ 1263 return 0x00000103; 1264 case 0x830: /* CM_AUTOIDLE_DSP */ 1265 return s->clkidle[6]; 1266 case 0x840: /* CM_CLKSEL_DSP */ 1267 return s->clksel[7]; 1268 case 0x848: /* CM_CLKSTCTRL_DSP */ 1269 return s->clkctrl[3]; 1270 case 0x850: /* RM_RSTCTRL_DSP */ 1271 return 0; 1272 case 0x858: /* RM_RSTST_DSP */ 1273 return s->rst[3]; 1274 case 0x8c8: /* PM_WKDEP_DSP */ 1275 return s->wkup[2]; 1276 case 0x8e0: /* PM_PWSTCTRL_DSP */ 1277 return s->power[3]; 1278 case 0x8e4: /* PM_PWSTST_DSP */ 1279 return 0x008030 | (s->power[3] & 0x3003); 1280 1281 case 0x8f0: /* PRCM_IRQSTATUS_DSP */ 1282 return s->irqst[1]; 1283 case 0x8f4: /* PRCM_IRQENABLE_DSP */ 1284 return s->irqen[1]; 1285 1286 case 0x8f8: /* PRCM_IRQSTATUS_IVA */ 1287 return s->irqst[2]; 1288 case 0x8fc: /* PRCM_IRQENABLE_IVA */ 1289 return s->irqen[2]; 1290 } 1291 1292 OMAP_BAD_REG(addr); 1293 return 0; 1294 } 1295 1296 static void omap_prcm_apll_update(struct omap_prcm_s *s) 1297 { 1298 int mode[2]; 1299 1300 mode[0] = (s->clken[9] >> 6) & 3; 1301 s->apll_lock[0] = (mode[0] == 3); 1302 mode[1] = (s->clken[9] >> 2) & 3; 1303 s->apll_lock[1] = (mode[1] == 3); 1304 /* TODO: update clocks */ 1305 1306 if (mode[0] == 1 || mode[0] == 2 || mode[1] == 1 || mode[1] == 2) 1307 fprintf(stderr, "%s: bad EN_54M_PLL or bad EN_96M_PLL\n", 1308 __FUNCTION__); 1309 } 1310 1311 static void omap_prcm_dpll_update(struct omap_prcm_s *s) 1312 { 1313 omap_clk dpll = omap_findclk(s->mpu, "dpll"); 1314 omap_clk dpll_x2 = omap_findclk(s->mpu, "dpll"); 1315 omap_clk core = omap_findclk(s->mpu, "core_clk"); 1316 int mode = (s->clken[9] >> 0) & 3; 1317 int mult, div; 1318 1319 mult = (s->clksel[5] >> 12) & 0x3ff; 1320 div = (s->clksel[5] >> 8) & 0xf; 1321 if (mult == 0 || mult == 1) 1322 mode = 1; /* Bypass */ 1323 1324 s->dpll_lock = 0; 1325 switch (mode) { 1326 case 0: 1327 fprintf(stderr, "%s: bad EN_DPLL\n", __FUNCTION__); 1328 break; 1329 case 1: /* Low-power bypass mode (Default) */ 1330 case 2: /* Fast-relock bypass mode */ 1331 omap_clk_setrate(dpll, 1, 1); 1332 omap_clk_setrate(dpll_x2, 1, 1); 1333 break; 1334 case 3: /* Lock mode */ 1335 s->dpll_lock = 1; /* After 20 FINT cycles (ref_clk / (div + 1)). */ 1336 1337 omap_clk_setrate(dpll, div + 1, mult); 1338 omap_clk_setrate(dpll_x2, div + 1, mult * 2); 1339 break; 1340 } 1341 1342 switch ((s->clksel[6] >> 0) & 3) { 1343 case 0: 1344 omap_clk_reparent(core, omap_findclk(s->mpu, "clk32-kHz")); 1345 break; 1346 case 1: 1347 omap_clk_reparent(core, dpll); 1348 break; 1349 case 2: 1350 /* Default */ 1351 omap_clk_reparent(core, dpll_x2); 1352 break; 1353 case 3: 1354 fprintf(stderr, "%s: bad CORE_CLK_SRC\n", __FUNCTION__); 1355 break; 1356 } 1357 } 1358 1359 static void omap_prcm_write(void *opaque, hwaddr addr, 1360 uint64_t value, unsigned size) 1361 { 1362 struct omap_prcm_s *s = (struct omap_prcm_s *) opaque; 1363 1364 if (size != 4) { 1365 omap_badwidth_write32(opaque, addr, value); 1366 return; 1367 } 1368 1369 switch (addr) { 1370 case 0x000: /* PRCM_REVISION */ 1371 case 0x054: /* PRCM_VOLTST */ 1372 case 0x084: /* PRCM_CLKCFG_STATUS */ 1373 case 0x1e4: /* PM_PWSTST_MPU */ 1374 case 0x220: /* CM_IDLEST1_CORE */ 1375 case 0x224: /* CM_IDLEST2_CORE */ 1376 case 0x22c: /* CM_IDLEST4_CORE */ 1377 case 0x2c8: /* PM_WKDEP_CORE */ 1378 case 0x2e4: /* PM_PWSTST_CORE */ 1379 case 0x320: /* CM_IDLEST_GFX */ 1380 case 0x3e4: /* PM_PWSTST_GFX */ 1381 case 0x420: /* CM_IDLEST_WKUP */ 1382 case 0x520: /* CM_IDLEST_CKGEN */ 1383 case 0x820: /* CM_IDLEST_DSP */ 1384 case 0x8e4: /* PM_PWSTST_DSP */ 1385 OMAP_RO_REG(addr); 1386 return; 1387 1388 case 0x010: /* PRCM_SYSCONFIG */ 1389 s->sysconfig = value & 1; 1390 break; 1391 1392 case 0x018: /* PRCM_IRQSTATUS_MPU */ 1393 s->irqst[0] &= ~value; 1394 omap_prcm_int_update(s, 0); 1395 break; 1396 case 0x01c: /* PRCM_IRQENABLE_MPU */ 1397 s->irqen[0] = value & 0x3f; 1398 omap_prcm_int_update(s, 0); 1399 break; 1400 1401 case 0x050: /* PRCM_VOLTCTRL */ 1402 s->voltctrl = value & 0xf1c3; 1403 break; 1404 1405 case 0x060: /* PRCM_CLKSRC_CTRL */ 1406 s->clksrc[0] = value & 0xdb; 1407 /* TODO update clocks */ 1408 break; 1409 1410 case 0x070: /* PRCM_CLKOUT_CTRL */ 1411 s->clkout[0] = value & 0xbbbb; 1412 /* TODO update clocks */ 1413 break; 1414 1415 case 0x078: /* PRCM_CLKEMUL_CTRL */ 1416 s->clkemul[0] = value & 1; 1417 /* TODO update clocks */ 1418 break; 1419 1420 case 0x080: /* PRCM_CLKCFG_CTRL */ 1421 break; 1422 1423 case 0x090: /* PRCM_VOLTSETUP */ 1424 s->setuptime[0] = value & 0xffff; 1425 break; 1426 case 0x094: /* PRCM_CLKSSETUP */ 1427 s->setuptime[1] = value & 0xffff; 1428 break; 1429 1430 case 0x098: /* PRCM_POLCTRL */ 1431 s->clkpol[0] = value & 0x701; 1432 break; 1433 1434 case 0x0b0: /* GENERAL_PURPOSE1 */ 1435 case 0x0b4: /* GENERAL_PURPOSE2 */ 1436 case 0x0b8: /* GENERAL_PURPOSE3 */ 1437 case 0x0bc: /* GENERAL_PURPOSE4 */ 1438 case 0x0c0: /* GENERAL_PURPOSE5 */ 1439 case 0x0c4: /* GENERAL_PURPOSE6 */ 1440 case 0x0c8: /* GENERAL_PURPOSE7 */ 1441 case 0x0cc: /* GENERAL_PURPOSE8 */ 1442 case 0x0d0: /* GENERAL_PURPOSE9 */ 1443 case 0x0d4: /* GENERAL_PURPOSE10 */ 1444 case 0x0d8: /* GENERAL_PURPOSE11 */ 1445 case 0x0dc: /* GENERAL_PURPOSE12 */ 1446 case 0x0e0: /* GENERAL_PURPOSE13 */ 1447 case 0x0e4: /* GENERAL_PURPOSE14 */ 1448 case 0x0e8: /* GENERAL_PURPOSE15 */ 1449 case 0x0ec: /* GENERAL_PURPOSE16 */ 1450 case 0x0f0: /* GENERAL_PURPOSE17 */ 1451 case 0x0f4: /* GENERAL_PURPOSE18 */ 1452 case 0x0f8: /* GENERAL_PURPOSE19 */ 1453 case 0x0fc: /* GENERAL_PURPOSE20 */ 1454 s->scratch[(addr - 0xb0) >> 2] = value; 1455 break; 1456 1457 case 0x140: /* CM_CLKSEL_MPU */ 1458 s->clksel[0] = value & 0x1f; 1459 /* TODO update clocks */ 1460 break; 1461 case 0x148: /* CM_CLKSTCTRL_MPU */ 1462 s->clkctrl[0] = value & 0x1f; 1463 break; 1464 1465 case 0x158: /* RM_RSTST_MPU */ 1466 s->rst[0] &= ~value; 1467 break; 1468 case 0x1c8: /* PM_WKDEP_MPU */ 1469 s->wkup[0] = value & 0x15; 1470 break; 1471 1472 case 0x1d4: /* PM_EVGENCTRL_MPU */ 1473 s->ev = value & 0x1f; 1474 break; 1475 case 0x1d8: /* PM_EVEGENONTIM_MPU */ 1476 s->evtime[0] = value; 1477 break; 1478 case 0x1dc: /* PM_EVEGENOFFTIM_MPU */ 1479 s->evtime[1] = value; 1480 break; 1481 1482 case 0x1e0: /* PM_PWSTCTRL_MPU */ 1483 s->power[0] = value & 0xc0f; 1484 break; 1485 1486 case 0x200: /* CM_FCLKEN1_CORE */ 1487 s->clken[0] = value & 0xbfffffff; 1488 /* TODO update clocks */ 1489 /* The EN_EAC bit only gets/puts func_96m_clk. */ 1490 break; 1491 case 0x204: /* CM_FCLKEN2_CORE */ 1492 s->clken[1] = value & 0x00000007; 1493 /* TODO update clocks */ 1494 break; 1495 case 0x210: /* CM_ICLKEN1_CORE */ 1496 s->clken[2] = value & 0xfffffff9; 1497 /* TODO update clocks */ 1498 /* The EN_EAC bit only gets/puts core_l4_iclk. */ 1499 break; 1500 case 0x214: /* CM_ICLKEN2_CORE */ 1501 s->clken[3] = value & 0x00000007; 1502 /* TODO update clocks */ 1503 break; 1504 case 0x21c: /* CM_ICLKEN4_CORE */ 1505 s->clken[4] = value & 0x0000001f; 1506 /* TODO update clocks */ 1507 break; 1508 1509 case 0x230: /* CM_AUTOIDLE1_CORE */ 1510 s->clkidle[0] = value & 0xfffffff9; 1511 /* TODO update clocks */ 1512 break; 1513 case 0x234: /* CM_AUTOIDLE2_CORE */ 1514 s->clkidle[1] = value & 0x00000007; 1515 /* TODO update clocks */ 1516 break; 1517 case 0x238: /* CM_AUTOIDLE3_CORE */ 1518 s->clkidle[2] = value & 0x00000007; 1519 /* TODO update clocks */ 1520 break; 1521 case 0x23c: /* CM_AUTOIDLE4_CORE */ 1522 s->clkidle[3] = value & 0x0000001f; 1523 /* TODO update clocks */ 1524 break; 1525 1526 case 0x240: /* CM_CLKSEL1_CORE */ 1527 s->clksel[1] = value & 0x0fffbf7f; 1528 /* TODO update clocks */ 1529 break; 1530 1531 case 0x244: /* CM_CLKSEL2_CORE */ 1532 s->clksel[2] = value & 0x00fffffc; 1533 /* TODO update clocks */ 1534 break; 1535 1536 case 0x248: /* CM_CLKSTCTRL_CORE */ 1537 s->clkctrl[1] = value & 0x7; 1538 break; 1539 1540 case 0x2a0: /* PM_WKEN1_CORE */ 1541 s->wken[0] = value & 0x04667ff8; 1542 break; 1543 case 0x2a4: /* PM_WKEN2_CORE */ 1544 s->wken[1] = value & 0x00000005; 1545 break; 1546 1547 case 0x2b0: /* PM_WKST1_CORE */ 1548 s->wkst[0] &= ~value; 1549 break; 1550 case 0x2b4: /* PM_WKST2_CORE */ 1551 s->wkst[1] &= ~value; 1552 break; 1553 1554 case 0x2e0: /* PM_PWSTCTRL_CORE */ 1555 s->power[1] = (value & 0x00fc3f) | (1 << 2); 1556 break; 1557 1558 case 0x300: /* CM_FCLKEN_GFX */ 1559 s->clken[5] = value & 6; 1560 /* TODO update clocks */ 1561 break; 1562 case 0x310: /* CM_ICLKEN_GFX */ 1563 s->clken[6] = value & 1; 1564 /* TODO update clocks */ 1565 break; 1566 case 0x340: /* CM_CLKSEL_GFX */ 1567 s->clksel[3] = value & 7; 1568 /* TODO update clocks */ 1569 break; 1570 case 0x348: /* CM_CLKSTCTRL_GFX */ 1571 s->clkctrl[2] = value & 1; 1572 break; 1573 case 0x350: /* RM_RSTCTRL_GFX */ 1574 s->rstctrl[0] = value & 1; 1575 /* TODO: reset */ 1576 break; 1577 case 0x358: /* RM_RSTST_GFX */ 1578 s->rst[1] &= ~value; 1579 break; 1580 case 0x3c8: /* PM_WKDEP_GFX */ 1581 s->wkup[1] = value & 0x13; 1582 break; 1583 case 0x3e0: /* PM_PWSTCTRL_GFX */ 1584 s->power[2] = (value & 0x00c0f) | (3 << 2); 1585 break; 1586 1587 case 0x400: /* CM_FCLKEN_WKUP */ 1588 s->clken[7] = value & 0xd; 1589 /* TODO update clocks */ 1590 break; 1591 case 0x410: /* CM_ICLKEN_WKUP */ 1592 s->clken[8] = value & 0x3f; 1593 /* TODO update clocks */ 1594 break; 1595 case 0x430: /* CM_AUTOIDLE_WKUP */ 1596 s->clkidle[4] = value & 0x0000003f; 1597 /* TODO update clocks */ 1598 break; 1599 case 0x440: /* CM_CLKSEL_WKUP */ 1600 s->clksel[4] = value & 3; 1601 /* TODO update clocks */ 1602 break; 1603 case 0x450: /* RM_RSTCTRL_WKUP */ 1604 /* TODO: reset */ 1605 if (value & 2) 1606 qemu_system_reset_request(); 1607 break; 1608 case 0x454: /* RM_RSTTIME_WKUP */ 1609 s->rsttime_wkup = value & 0x1fff; 1610 break; 1611 case 0x458: /* RM_RSTST_WKUP */ 1612 s->rst[2] &= ~value; 1613 break; 1614 case 0x4a0: /* PM_WKEN_WKUP */ 1615 s->wken[2] = value & 0x00000005; 1616 break; 1617 case 0x4b0: /* PM_WKST_WKUP */ 1618 s->wkst[2] &= ~value; 1619 break; 1620 1621 case 0x500: /* CM_CLKEN_PLL */ 1622 if (value & 0xffffff30) 1623 fprintf(stderr, "%s: write 0s in CM_CLKEN_PLL for " 1624 "future compatibility\n", __FUNCTION__); 1625 if ((s->clken[9] ^ value) & 0xcc) { 1626 s->clken[9] &= ~0xcc; 1627 s->clken[9] |= value & 0xcc; 1628 omap_prcm_apll_update(s); 1629 } 1630 if ((s->clken[9] ^ value) & 3) { 1631 s->clken[9] &= ~3; 1632 s->clken[9] |= value & 3; 1633 omap_prcm_dpll_update(s); 1634 } 1635 break; 1636 case 0x530: /* CM_AUTOIDLE_PLL */ 1637 s->clkidle[5] = value & 0x000000cf; 1638 /* TODO update clocks */ 1639 break; 1640 case 0x540: /* CM_CLKSEL1_PLL */ 1641 if (value & 0xfc4000d7) 1642 fprintf(stderr, "%s: write 0s in CM_CLKSEL1_PLL for " 1643 "future compatibility\n", __FUNCTION__); 1644 if ((s->clksel[5] ^ value) & 0x003fff00) { 1645 s->clksel[5] = value & 0x03bfff28; 1646 omap_prcm_dpll_update(s); 1647 } 1648 /* TODO update the other clocks */ 1649 1650 s->clksel[5] = value & 0x03bfff28; 1651 break; 1652 case 0x544: /* CM_CLKSEL2_PLL */ 1653 if (value & ~3) 1654 fprintf(stderr, "%s: write 0s in CM_CLKSEL2_PLL[31:2] for " 1655 "future compatibility\n", __FUNCTION__); 1656 if (s->clksel[6] != (value & 3)) { 1657 s->clksel[6] = value & 3; 1658 omap_prcm_dpll_update(s); 1659 } 1660 break; 1661 1662 case 0x800: /* CM_FCLKEN_DSP */ 1663 s->clken[10] = value & 0x501; 1664 /* TODO update clocks */ 1665 break; 1666 case 0x810: /* CM_ICLKEN_DSP */ 1667 s->clken[11] = value & 0x2; 1668 /* TODO update clocks */ 1669 break; 1670 case 0x830: /* CM_AUTOIDLE_DSP */ 1671 s->clkidle[6] = value & 0x2; 1672 /* TODO update clocks */ 1673 break; 1674 case 0x840: /* CM_CLKSEL_DSP */ 1675 s->clksel[7] = value & 0x3fff; 1676 /* TODO update clocks */ 1677 break; 1678 case 0x848: /* CM_CLKSTCTRL_DSP */ 1679 s->clkctrl[3] = value & 0x101; 1680 break; 1681 case 0x850: /* RM_RSTCTRL_DSP */ 1682 /* TODO: reset */ 1683 break; 1684 case 0x858: /* RM_RSTST_DSP */ 1685 s->rst[3] &= ~value; 1686 break; 1687 case 0x8c8: /* PM_WKDEP_DSP */ 1688 s->wkup[2] = value & 0x13; 1689 break; 1690 case 0x8e0: /* PM_PWSTCTRL_DSP */ 1691 s->power[3] = (value & 0x03017) | (3 << 2); 1692 break; 1693 1694 case 0x8f0: /* PRCM_IRQSTATUS_DSP */ 1695 s->irqst[1] &= ~value; 1696 omap_prcm_int_update(s, 1); 1697 break; 1698 case 0x8f4: /* PRCM_IRQENABLE_DSP */ 1699 s->irqen[1] = value & 0x7; 1700 omap_prcm_int_update(s, 1); 1701 break; 1702 1703 case 0x8f8: /* PRCM_IRQSTATUS_IVA */ 1704 s->irqst[2] &= ~value; 1705 omap_prcm_int_update(s, 2); 1706 break; 1707 case 0x8fc: /* PRCM_IRQENABLE_IVA */ 1708 s->irqen[2] = value & 0x7; 1709 omap_prcm_int_update(s, 2); 1710 break; 1711 1712 default: 1713 OMAP_BAD_REG(addr); 1714 return; 1715 } 1716 } 1717 1718 static const MemoryRegionOps omap_prcm_ops = { 1719 .read = omap_prcm_read, 1720 .write = omap_prcm_write, 1721 .endianness = DEVICE_NATIVE_ENDIAN, 1722 }; 1723 1724 static void omap_prcm_reset(struct omap_prcm_s *s) 1725 { 1726 s->sysconfig = 0; 1727 s->irqst[0] = 0; 1728 s->irqst[1] = 0; 1729 s->irqst[2] = 0; 1730 s->irqen[0] = 0; 1731 s->irqen[1] = 0; 1732 s->irqen[2] = 0; 1733 s->voltctrl = 0x1040; 1734 s->ev = 0x14; 1735 s->evtime[0] = 0; 1736 s->evtime[1] = 0; 1737 s->clkctrl[0] = 0; 1738 s->clkctrl[1] = 0; 1739 s->clkctrl[2] = 0; 1740 s->clkctrl[3] = 0; 1741 s->clken[1] = 7; 1742 s->clken[3] = 7; 1743 s->clken[4] = 0; 1744 s->clken[5] = 0; 1745 s->clken[6] = 0; 1746 s->clken[7] = 0xc; 1747 s->clken[8] = 0x3e; 1748 s->clken[9] = 0x0d; 1749 s->clken[10] = 0; 1750 s->clken[11] = 0; 1751 s->clkidle[0] = 0; 1752 s->clkidle[2] = 7; 1753 s->clkidle[3] = 0; 1754 s->clkidle[4] = 0; 1755 s->clkidle[5] = 0x0c; 1756 s->clkidle[6] = 0; 1757 s->clksel[0] = 0x01; 1758 s->clksel[1] = 0x02100121; 1759 s->clksel[2] = 0x00000000; 1760 s->clksel[3] = 0x01; 1761 s->clksel[4] = 0; 1762 s->clksel[7] = 0x0121; 1763 s->wkup[0] = 0x15; 1764 s->wkup[1] = 0x13; 1765 s->wkup[2] = 0x13; 1766 s->wken[0] = 0x04667ff8; 1767 s->wken[1] = 0x00000005; 1768 s->wken[2] = 5; 1769 s->wkst[0] = 0; 1770 s->wkst[1] = 0; 1771 s->wkst[2] = 0; 1772 s->power[0] = 0x00c; 1773 s->power[1] = 4; 1774 s->power[2] = 0x0000c; 1775 s->power[3] = 0x14; 1776 s->rstctrl[0] = 1; 1777 s->rst[3] = 1; 1778 omap_prcm_apll_update(s); 1779 omap_prcm_dpll_update(s); 1780 } 1781 1782 static void omap_prcm_coldreset(struct omap_prcm_s *s) 1783 { 1784 s->setuptime[0] = 0; 1785 s->setuptime[1] = 0; 1786 memset(&s->scratch, 0, sizeof(s->scratch)); 1787 s->rst[0] = 0x01; 1788 s->rst[1] = 0x00; 1789 s->rst[2] = 0x01; 1790 s->clken[0] = 0; 1791 s->clken[2] = 0; 1792 s->clkidle[1] = 0; 1793 s->clksel[5] = 0; 1794 s->clksel[6] = 2; 1795 s->clksrc[0] = 0x43; 1796 s->clkout[0] = 0x0303; 1797 s->clkemul[0] = 0; 1798 s->clkpol[0] = 0x100; 1799 s->rsttime_wkup = 0x1002; 1800 1801 omap_prcm_reset(s); 1802 } 1803 1804 static struct omap_prcm_s *omap_prcm_init(struct omap_target_agent_s *ta, 1805 qemu_irq mpu_int, qemu_irq dsp_int, qemu_irq iva_int, 1806 struct omap_mpu_state_s *mpu) 1807 { 1808 struct omap_prcm_s *s = g_new0(struct omap_prcm_s, 1); 1809 1810 s->irq[0] = mpu_int; 1811 s->irq[1] = dsp_int; 1812 s->irq[2] = iva_int; 1813 s->mpu = mpu; 1814 omap_prcm_coldreset(s); 1815 1816 memory_region_init_io(&s->iomem0, NULL, &omap_prcm_ops, s, "omap.pcrm0", 1817 omap_l4_region_size(ta, 0)); 1818 memory_region_init_io(&s->iomem1, NULL, &omap_prcm_ops, s, "omap.pcrm1", 1819 omap_l4_region_size(ta, 1)); 1820 omap_l4_attach(ta, 0, &s->iomem0); 1821 omap_l4_attach(ta, 1, &s->iomem1); 1822 1823 return s; 1824 } 1825 1826 /* System and Pinout control */ 1827 struct omap_sysctl_s { 1828 struct omap_mpu_state_s *mpu; 1829 MemoryRegion iomem; 1830 1831 uint32_t sysconfig; 1832 uint32_t devconfig; 1833 uint32_t psaconfig; 1834 uint32_t padconf[0x45]; 1835 uint8_t obs; 1836 uint32_t msuspendmux[5]; 1837 }; 1838 1839 static uint32_t omap_sysctl_read8(void *opaque, hwaddr addr) 1840 { 1841 1842 struct omap_sysctl_s *s = (struct omap_sysctl_s *) opaque; 1843 int pad_offset, byte_offset; 1844 int value; 1845 1846 switch (addr) { 1847 case 0x030 ... 0x140: /* CONTROL_PADCONF - only used in the POP */ 1848 pad_offset = (addr - 0x30) >> 2; 1849 byte_offset = (addr - 0x30) & (4 - 1); 1850 1851 value = s->padconf[pad_offset]; 1852 value = (value >> (byte_offset * 8)) & 0xff; 1853 1854 return value; 1855 1856 default: 1857 break; 1858 } 1859 1860 OMAP_BAD_REG(addr); 1861 return 0; 1862 } 1863 1864 static uint32_t omap_sysctl_read(void *opaque, hwaddr addr) 1865 { 1866 struct omap_sysctl_s *s = (struct omap_sysctl_s *) opaque; 1867 1868 switch (addr) { 1869 case 0x000: /* CONTROL_REVISION */ 1870 return 0x20; 1871 1872 case 0x010: /* CONTROL_SYSCONFIG */ 1873 return s->sysconfig; 1874 1875 case 0x030 ... 0x140: /* CONTROL_PADCONF - only used in the POP */ 1876 return s->padconf[(addr - 0x30) >> 2]; 1877 1878 case 0x270: /* CONTROL_DEBOBS */ 1879 return s->obs; 1880 1881 case 0x274: /* CONTROL_DEVCONF */ 1882 return s->devconfig; 1883 1884 case 0x28c: /* CONTROL_EMU_SUPPORT */ 1885 return 0; 1886 1887 case 0x290: /* CONTROL_MSUSPENDMUX_0 */ 1888 return s->msuspendmux[0]; 1889 case 0x294: /* CONTROL_MSUSPENDMUX_1 */ 1890 return s->msuspendmux[1]; 1891 case 0x298: /* CONTROL_MSUSPENDMUX_2 */ 1892 return s->msuspendmux[2]; 1893 case 0x29c: /* CONTROL_MSUSPENDMUX_3 */ 1894 return s->msuspendmux[3]; 1895 case 0x2a0: /* CONTROL_MSUSPENDMUX_4 */ 1896 return s->msuspendmux[4]; 1897 case 0x2a4: /* CONTROL_MSUSPENDMUX_5 */ 1898 return 0; 1899 1900 case 0x2b8: /* CONTROL_PSA_CTRL */ 1901 return s->psaconfig; 1902 case 0x2bc: /* CONTROL_PSA_CMD */ 1903 case 0x2c0: /* CONTROL_PSA_VALUE */ 1904 return 0; 1905 1906 case 0x2b0: /* CONTROL_SEC_CTRL */ 1907 return 0x800000f1; 1908 case 0x2d0: /* CONTROL_SEC_EMU */ 1909 return 0x80000015; 1910 case 0x2d4: /* CONTROL_SEC_TAP */ 1911 return 0x8000007f; 1912 case 0x2b4: /* CONTROL_SEC_TEST */ 1913 case 0x2f0: /* CONTROL_SEC_STATUS */ 1914 case 0x2f4: /* CONTROL_SEC_ERR_STATUS */ 1915 /* Secure mode is not present on general-pusrpose device. Outside 1916 * secure mode these values cannot be read or written. */ 1917 return 0; 1918 1919 case 0x2d8: /* CONTROL_OCM_RAM_PERM */ 1920 return 0xff; 1921 case 0x2dc: /* CONTROL_OCM_PUB_RAM_ADD */ 1922 case 0x2e0: /* CONTROL_EXT_SEC_RAM_START_ADD */ 1923 case 0x2e4: /* CONTROL_EXT_SEC_RAM_STOP_ADD */ 1924 /* No secure mode so no Extended Secure RAM present. */ 1925 return 0; 1926 1927 case 0x2f8: /* CONTROL_STATUS */ 1928 /* Device Type => General-purpose */ 1929 return 0x0300; 1930 case 0x2fc: /* CONTROL_GENERAL_PURPOSE_STATUS */ 1931 1932 case 0x300: /* CONTROL_RPUB_KEY_H_0 */ 1933 case 0x304: /* CONTROL_RPUB_KEY_H_1 */ 1934 case 0x308: /* CONTROL_RPUB_KEY_H_2 */ 1935 case 0x30c: /* CONTROL_RPUB_KEY_H_3 */ 1936 return 0xdecafbad; 1937 1938 case 0x310: /* CONTROL_RAND_KEY_0 */ 1939 case 0x314: /* CONTROL_RAND_KEY_1 */ 1940 case 0x318: /* CONTROL_RAND_KEY_2 */ 1941 case 0x31c: /* CONTROL_RAND_KEY_3 */ 1942 case 0x320: /* CONTROL_CUST_KEY_0 */ 1943 case 0x324: /* CONTROL_CUST_KEY_1 */ 1944 case 0x330: /* CONTROL_TEST_KEY_0 */ 1945 case 0x334: /* CONTROL_TEST_KEY_1 */ 1946 case 0x338: /* CONTROL_TEST_KEY_2 */ 1947 case 0x33c: /* CONTROL_TEST_KEY_3 */ 1948 case 0x340: /* CONTROL_TEST_KEY_4 */ 1949 case 0x344: /* CONTROL_TEST_KEY_5 */ 1950 case 0x348: /* CONTROL_TEST_KEY_6 */ 1951 case 0x34c: /* CONTROL_TEST_KEY_7 */ 1952 case 0x350: /* CONTROL_TEST_KEY_8 */ 1953 case 0x354: /* CONTROL_TEST_KEY_9 */ 1954 /* Can only be accessed in secure mode and when C_FieldAccEnable 1955 * bit is set in CONTROL_SEC_CTRL. 1956 * TODO: otherwise an interconnect access error is generated. */ 1957 return 0; 1958 } 1959 1960 OMAP_BAD_REG(addr); 1961 return 0; 1962 } 1963 1964 static void omap_sysctl_write8(void *opaque, hwaddr addr, 1965 uint32_t value) 1966 { 1967 struct omap_sysctl_s *s = (struct omap_sysctl_s *) opaque; 1968 int pad_offset, byte_offset; 1969 int prev_value; 1970 1971 switch (addr) { 1972 case 0x030 ... 0x140: /* CONTROL_PADCONF - only used in the POP */ 1973 pad_offset = (addr - 0x30) >> 2; 1974 byte_offset = (addr - 0x30) & (4 - 1); 1975 1976 prev_value = s->padconf[pad_offset]; 1977 prev_value &= ~(0xff << (byte_offset * 8)); 1978 prev_value |= ((value & 0x1f1f1f1f) << (byte_offset * 8)) & 0x1f1f1f1f; 1979 s->padconf[pad_offset] = prev_value; 1980 break; 1981 1982 default: 1983 OMAP_BAD_REG(addr); 1984 break; 1985 } 1986 } 1987 1988 static void omap_sysctl_write(void *opaque, hwaddr addr, 1989 uint32_t value) 1990 { 1991 struct omap_sysctl_s *s = (struct omap_sysctl_s *) opaque; 1992 1993 switch (addr) { 1994 case 0x000: /* CONTROL_REVISION */ 1995 case 0x2a4: /* CONTROL_MSUSPENDMUX_5 */ 1996 case 0x2c0: /* CONTROL_PSA_VALUE */ 1997 case 0x2f8: /* CONTROL_STATUS */ 1998 case 0x2fc: /* CONTROL_GENERAL_PURPOSE_STATUS */ 1999 case 0x300: /* CONTROL_RPUB_KEY_H_0 */ 2000 case 0x304: /* CONTROL_RPUB_KEY_H_1 */ 2001 case 0x308: /* CONTROL_RPUB_KEY_H_2 */ 2002 case 0x30c: /* CONTROL_RPUB_KEY_H_3 */ 2003 case 0x310: /* CONTROL_RAND_KEY_0 */ 2004 case 0x314: /* CONTROL_RAND_KEY_1 */ 2005 case 0x318: /* CONTROL_RAND_KEY_2 */ 2006 case 0x31c: /* CONTROL_RAND_KEY_3 */ 2007 case 0x320: /* CONTROL_CUST_KEY_0 */ 2008 case 0x324: /* CONTROL_CUST_KEY_1 */ 2009 case 0x330: /* CONTROL_TEST_KEY_0 */ 2010 case 0x334: /* CONTROL_TEST_KEY_1 */ 2011 case 0x338: /* CONTROL_TEST_KEY_2 */ 2012 case 0x33c: /* CONTROL_TEST_KEY_3 */ 2013 case 0x340: /* CONTROL_TEST_KEY_4 */ 2014 case 0x344: /* CONTROL_TEST_KEY_5 */ 2015 case 0x348: /* CONTROL_TEST_KEY_6 */ 2016 case 0x34c: /* CONTROL_TEST_KEY_7 */ 2017 case 0x350: /* CONTROL_TEST_KEY_8 */ 2018 case 0x354: /* CONTROL_TEST_KEY_9 */ 2019 OMAP_RO_REG(addr); 2020 return; 2021 2022 case 0x010: /* CONTROL_SYSCONFIG */ 2023 s->sysconfig = value & 0x1e; 2024 break; 2025 2026 case 0x030 ... 0x140: /* CONTROL_PADCONF - only used in the POP */ 2027 /* XXX: should check constant bits */ 2028 s->padconf[(addr - 0x30) >> 2] = value & 0x1f1f1f1f; 2029 break; 2030 2031 case 0x270: /* CONTROL_DEBOBS */ 2032 s->obs = value & 0xff; 2033 break; 2034 2035 case 0x274: /* CONTROL_DEVCONF */ 2036 s->devconfig = value & 0xffffc7ff; 2037 break; 2038 2039 case 0x28c: /* CONTROL_EMU_SUPPORT */ 2040 break; 2041 2042 case 0x290: /* CONTROL_MSUSPENDMUX_0 */ 2043 s->msuspendmux[0] = value & 0x3fffffff; 2044 break; 2045 case 0x294: /* CONTROL_MSUSPENDMUX_1 */ 2046 s->msuspendmux[1] = value & 0x3fffffff; 2047 break; 2048 case 0x298: /* CONTROL_MSUSPENDMUX_2 */ 2049 s->msuspendmux[2] = value & 0x3fffffff; 2050 break; 2051 case 0x29c: /* CONTROL_MSUSPENDMUX_3 */ 2052 s->msuspendmux[3] = value & 0x3fffffff; 2053 break; 2054 case 0x2a0: /* CONTROL_MSUSPENDMUX_4 */ 2055 s->msuspendmux[4] = value & 0x3fffffff; 2056 break; 2057 2058 case 0x2b8: /* CONTROL_PSA_CTRL */ 2059 s->psaconfig = value & 0x1c; 2060 s->psaconfig |= (value & 0x20) ? 2 : 1; 2061 break; 2062 case 0x2bc: /* CONTROL_PSA_CMD */ 2063 break; 2064 2065 case 0x2b0: /* CONTROL_SEC_CTRL */ 2066 case 0x2b4: /* CONTROL_SEC_TEST */ 2067 case 0x2d0: /* CONTROL_SEC_EMU */ 2068 case 0x2d4: /* CONTROL_SEC_TAP */ 2069 case 0x2d8: /* CONTROL_OCM_RAM_PERM */ 2070 case 0x2dc: /* CONTROL_OCM_PUB_RAM_ADD */ 2071 case 0x2e0: /* CONTROL_EXT_SEC_RAM_START_ADD */ 2072 case 0x2e4: /* CONTROL_EXT_SEC_RAM_STOP_ADD */ 2073 case 0x2f0: /* CONTROL_SEC_STATUS */ 2074 case 0x2f4: /* CONTROL_SEC_ERR_STATUS */ 2075 break; 2076 2077 default: 2078 OMAP_BAD_REG(addr); 2079 return; 2080 } 2081 } 2082 2083 static const MemoryRegionOps omap_sysctl_ops = { 2084 .old_mmio = { 2085 .read = { 2086 omap_sysctl_read8, 2087 omap_badwidth_read32, /* TODO */ 2088 omap_sysctl_read, 2089 }, 2090 .write = { 2091 omap_sysctl_write8, 2092 omap_badwidth_write32, /* TODO */ 2093 omap_sysctl_write, 2094 }, 2095 }, 2096 .endianness = DEVICE_NATIVE_ENDIAN, 2097 }; 2098 2099 static void omap_sysctl_reset(struct omap_sysctl_s *s) 2100 { 2101 /* (power-on reset) */ 2102 s->sysconfig = 0; 2103 s->obs = 0; 2104 s->devconfig = 0x0c000000; 2105 s->msuspendmux[0] = 0x00000000; 2106 s->msuspendmux[1] = 0x00000000; 2107 s->msuspendmux[2] = 0x00000000; 2108 s->msuspendmux[3] = 0x00000000; 2109 s->msuspendmux[4] = 0x00000000; 2110 s->psaconfig = 1; 2111 2112 s->padconf[0x00] = 0x000f0f0f; 2113 s->padconf[0x01] = 0x00000000; 2114 s->padconf[0x02] = 0x00000000; 2115 s->padconf[0x03] = 0x00000000; 2116 s->padconf[0x04] = 0x00000000; 2117 s->padconf[0x05] = 0x00000000; 2118 s->padconf[0x06] = 0x00000000; 2119 s->padconf[0x07] = 0x00000000; 2120 s->padconf[0x08] = 0x08080800; 2121 s->padconf[0x09] = 0x08080808; 2122 s->padconf[0x0a] = 0x08080808; 2123 s->padconf[0x0b] = 0x08080808; 2124 s->padconf[0x0c] = 0x08080808; 2125 s->padconf[0x0d] = 0x08080800; 2126 s->padconf[0x0e] = 0x08080808; 2127 s->padconf[0x0f] = 0x08080808; 2128 s->padconf[0x10] = 0x18181808; /* | 0x07070700 if SBoot3 */ 2129 s->padconf[0x11] = 0x18181818; /* | 0x07070707 if SBoot3 */ 2130 s->padconf[0x12] = 0x18181818; /* | 0x07070707 if SBoot3 */ 2131 s->padconf[0x13] = 0x18181818; /* | 0x07070707 if SBoot3 */ 2132 s->padconf[0x14] = 0x18181818; /* | 0x00070707 if SBoot3 */ 2133 s->padconf[0x15] = 0x18181818; 2134 s->padconf[0x16] = 0x18181818; /* | 0x07000000 if SBoot3 */ 2135 s->padconf[0x17] = 0x1f001f00; 2136 s->padconf[0x18] = 0x1f1f1f1f; 2137 s->padconf[0x19] = 0x00000000; 2138 s->padconf[0x1a] = 0x1f180000; 2139 s->padconf[0x1b] = 0x00001f1f; 2140 s->padconf[0x1c] = 0x1f001f00; 2141 s->padconf[0x1d] = 0x00000000; 2142 s->padconf[0x1e] = 0x00000000; 2143 s->padconf[0x1f] = 0x08000000; 2144 s->padconf[0x20] = 0x08080808; 2145 s->padconf[0x21] = 0x08080808; 2146 s->padconf[0x22] = 0x0f080808; 2147 s->padconf[0x23] = 0x0f0f0f0f; 2148 s->padconf[0x24] = 0x000f0f0f; 2149 s->padconf[0x25] = 0x1f1f1f0f; 2150 s->padconf[0x26] = 0x080f0f1f; 2151 s->padconf[0x27] = 0x070f1808; 2152 s->padconf[0x28] = 0x0f070707; 2153 s->padconf[0x29] = 0x000f0f1f; 2154 s->padconf[0x2a] = 0x0f0f0f1f; 2155 s->padconf[0x2b] = 0x08000000; 2156 s->padconf[0x2c] = 0x0000001f; 2157 s->padconf[0x2d] = 0x0f0f1f00; 2158 s->padconf[0x2e] = 0x1f1f0f0f; 2159 s->padconf[0x2f] = 0x0f1f1f1f; 2160 s->padconf[0x30] = 0x0f0f0f0f; 2161 s->padconf[0x31] = 0x0f1f0f1f; 2162 s->padconf[0x32] = 0x0f0f0f0f; 2163 s->padconf[0x33] = 0x0f1f0f1f; 2164 s->padconf[0x34] = 0x1f1f0f0f; 2165 s->padconf[0x35] = 0x0f0f1f1f; 2166 s->padconf[0x36] = 0x0f0f1f0f; 2167 s->padconf[0x37] = 0x0f0f0f0f; 2168 s->padconf[0x38] = 0x1f18180f; 2169 s->padconf[0x39] = 0x1f1f1f1f; 2170 s->padconf[0x3a] = 0x00001f1f; 2171 s->padconf[0x3b] = 0x00000000; 2172 s->padconf[0x3c] = 0x00000000; 2173 s->padconf[0x3d] = 0x0f0f0f0f; 2174 s->padconf[0x3e] = 0x18000f0f; 2175 s->padconf[0x3f] = 0x00070000; 2176 s->padconf[0x40] = 0x00000707; 2177 s->padconf[0x41] = 0x0f1f0700; 2178 s->padconf[0x42] = 0x1f1f070f; 2179 s->padconf[0x43] = 0x0008081f; 2180 s->padconf[0x44] = 0x00000800; 2181 } 2182 2183 static struct omap_sysctl_s *omap_sysctl_init(struct omap_target_agent_s *ta, 2184 omap_clk iclk, struct omap_mpu_state_s *mpu) 2185 { 2186 struct omap_sysctl_s *s = g_new0(struct omap_sysctl_s, 1); 2187 2188 s->mpu = mpu; 2189 omap_sysctl_reset(s); 2190 2191 memory_region_init_io(&s->iomem, NULL, &omap_sysctl_ops, s, "omap.sysctl", 2192 omap_l4_region_size(ta, 0)); 2193 omap_l4_attach(ta, 0, &s->iomem); 2194 2195 return s; 2196 } 2197 2198 /* General chip reset */ 2199 static void omap2_mpu_reset(void *opaque) 2200 { 2201 struct omap_mpu_state_s *mpu = (struct omap_mpu_state_s *) opaque; 2202 2203 omap_dma_reset(mpu->dma); 2204 omap_prcm_reset(mpu->prcm); 2205 omap_sysctl_reset(mpu->sysc); 2206 omap_gp_timer_reset(mpu->gptimer[0]); 2207 omap_gp_timer_reset(mpu->gptimer[1]); 2208 omap_gp_timer_reset(mpu->gptimer[2]); 2209 omap_gp_timer_reset(mpu->gptimer[3]); 2210 omap_gp_timer_reset(mpu->gptimer[4]); 2211 omap_gp_timer_reset(mpu->gptimer[5]); 2212 omap_gp_timer_reset(mpu->gptimer[6]); 2213 omap_gp_timer_reset(mpu->gptimer[7]); 2214 omap_gp_timer_reset(mpu->gptimer[8]); 2215 omap_gp_timer_reset(mpu->gptimer[9]); 2216 omap_gp_timer_reset(mpu->gptimer[10]); 2217 omap_gp_timer_reset(mpu->gptimer[11]); 2218 omap_synctimer_reset(mpu->synctimer); 2219 omap_sdrc_reset(mpu->sdrc); 2220 omap_gpmc_reset(mpu->gpmc); 2221 omap_dss_reset(mpu->dss); 2222 omap_uart_reset(mpu->uart[0]); 2223 omap_uart_reset(mpu->uart[1]); 2224 omap_uart_reset(mpu->uart[2]); 2225 omap_mmc_reset(mpu->mmc); 2226 omap_mcspi_reset(mpu->mcspi[0]); 2227 omap_mcspi_reset(mpu->mcspi[1]); 2228 cpu_reset(CPU(mpu->cpu)); 2229 } 2230 2231 static int omap2_validate_addr(struct omap_mpu_state_s *s, 2232 hwaddr addr) 2233 { 2234 return 1; 2235 } 2236 2237 static const struct dma_irq_map omap2_dma_irq_map[] = { 2238 { 0, OMAP_INT_24XX_SDMA_IRQ0 }, 2239 { 0, OMAP_INT_24XX_SDMA_IRQ1 }, 2240 { 0, OMAP_INT_24XX_SDMA_IRQ2 }, 2241 { 0, OMAP_INT_24XX_SDMA_IRQ3 }, 2242 }; 2243 2244 struct omap_mpu_state_s *omap2420_mpu_init(MemoryRegion *sysmem, 2245 unsigned long sdram_size, 2246 const char *core) 2247 { 2248 struct omap_mpu_state_s *s = g_new0(struct omap_mpu_state_s, 1); 2249 qemu_irq dma_irqs[4]; 2250 DriveInfo *dinfo; 2251 int i; 2252 SysBusDevice *busdev; 2253 struct omap_target_agent_s *ta; 2254 2255 /* Core */ 2256 s->mpu_model = omap2420; 2257 s->cpu = cpu_arm_init(core ?: "arm1136-r2"); 2258 if (s->cpu == NULL) { 2259 fprintf(stderr, "Unable to find CPU definition\n"); 2260 exit(1); 2261 } 2262 s->sdram_size = sdram_size; 2263 s->sram_size = OMAP242X_SRAM_SIZE; 2264 2265 s->wakeup = qemu_allocate_irq(omap_mpu_wakeup, s, 0); 2266 2267 /* Clocks */ 2268 omap_clk_init(s); 2269 2270 /* Memory-mapped stuff */ 2271 memory_region_allocate_system_memory(&s->sdram, NULL, "omap2.dram", 2272 s->sdram_size); 2273 memory_region_add_subregion(sysmem, OMAP2_Q2_BASE, &s->sdram); 2274 memory_region_init_ram(&s->sram, NULL, "omap2.sram", s->sram_size, 2275 &error_fatal); 2276 vmstate_register_ram_global(&s->sram); 2277 memory_region_add_subregion(sysmem, OMAP2_SRAM_BASE, &s->sram); 2278 2279 s->l4 = omap_l4_init(sysmem, OMAP2_L4_BASE, 54); 2280 2281 /* Actually mapped at any 2K boundary in the ARM11 private-peripheral if */ 2282 s->ih[0] = qdev_create(NULL, "omap2-intc"); 2283 qdev_prop_set_uint8(s->ih[0], "revision", 0x21); 2284 qdev_prop_set_ptr(s->ih[0], "fclk", omap_findclk(s, "mpu_intc_fclk")); 2285 qdev_prop_set_ptr(s->ih[0], "iclk", omap_findclk(s, "mpu_intc_iclk")); 2286 qdev_init_nofail(s->ih[0]); 2287 busdev = SYS_BUS_DEVICE(s->ih[0]); 2288 sysbus_connect_irq(busdev, 0, 2289 qdev_get_gpio_in(DEVICE(s->cpu), ARM_CPU_IRQ)); 2290 sysbus_connect_irq(busdev, 1, 2291 qdev_get_gpio_in(DEVICE(s->cpu), ARM_CPU_FIQ)); 2292 sysbus_mmio_map(busdev, 0, 0x480fe000); 2293 s->prcm = omap_prcm_init(omap_l4tao(s->l4, 3), 2294 qdev_get_gpio_in(s->ih[0], 2295 OMAP_INT_24XX_PRCM_MPU_IRQ), 2296 NULL, NULL, s); 2297 2298 s->sysc = omap_sysctl_init(omap_l4tao(s->l4, 1), 2299 omap_findclk(s, "omapctrl_iclk"), s); 2300 2301 for (i = 0; i < 4; i++) { 2302 dma_irqs[i] = qdev_get_gpio_in(s->ih[omap2_dma_irq_map[i].ih], 2303 omap2_dma_irq_map[i].intr); 2304 } 2305 s->dma = omap_dma4_init(0x48056000, dma_irqs, sysmem, s, 256, 32, 2306 omap_findclk(s, "sdma_iclk"), 2307 omap_findclk(s, "sdma_fclk")); 2308 s->port->addr_valid = omap2_validate_addr; 2309 2310 /* Register SDRAM and SRAM ports for fast DMA transfers. */ 2311 soc_dma_port_add_mem(s->dma, memory_region_get_ram_ptr(&s->sdram), 2312 OMAP2_Q2_BASE, s->sdram_size); 2313 soc_dma_port_add_mem(s->dma, memory_region_get_ram_ptr(&s->sram), 2314 OMAP2_SRAM_BASE, s->sram_size); 2315 2316 s->uart[0] = omap2_uart_init(sysmem, omap_l4ta(s->l4, 19), 2317 qdev_get_gpio_in(s->ih[0], 2318 OMAP_INT_24XX_UART1_IRQ), 2319 omap_findclk(s, "uart1_fclk"), 2320 omap_findclk(s, "uart1_iclk"), 2321 s->drq[OMAP24XX_DMA_UART1_TX], 2322 s->drq[OMAP24XX_DMA_UART1_RX], 2323 "uart1", 2324 serial_hds[0]); 2325 s->uart[1] = omap2_uart_init(sysmem, omap_l4ta(s->l4, 20), 2326 qdev_get_gpio_in(s->ih[0], 2327 OMAP_INT_24XX_UART2_IRQ), 2328 omap_findclk(s, "uart2_fclk"), 2329 omap_findclk(s, "uart2_iclk"), 2330 s->drq[OMAP24XX_DMA_UART2_TX], 2331 s->drq[OMAP24XX_DMA_UART2_RX], 2332 "uart2", 2333 serial_hds[0] ? serial_hds[1] : NULL); 2334 s->uart[2] = omap2_uart_init(sysmem, omap_l4ta(s->l4, 21), 2335 qdev_get_gpio_in(s->ih[0], 2336 OMAP_INT_24XX_UART3_IRQ), 2337 omap_findclk(s, "uart3_fclk"), 2338 omap_findclk(s, "uart3_iclk"), 2339 s->drq[OMAP24XX_DMA_UART3_TX], 2340 s->drq[OMAP24XX_DMA_UART3_RX], 2341 "uart3", 2342 serial_hds[0] && serial_hds[1] ? serial_hds[2] : NULL); 2343 2344 s->gptimer[0] = omap_gp_timer_init(omap_l4ta(s->l4, 7), 2345 qdev_get_gpio_in(s->ih[0], OMAP_INT_24XX_GPTIMER1), 2346 omap_findclk(s, "wu_gpt1_clk"), 2347 omap_findclk(s, "wu_l4_iclk")); 2348 s->gptimer[1] = omap_gp_timer_init(omap_l4ta(s->l4, 8), 2349 qdev_get_gpio_in(s->ih[0], OMAP_INT_24XX_GPTIMER2), 2350 omap_findclk(s, "core_gpt2_clk"), 2351 omap_findclk(s, "core_l4_iclk")); 2352 s->gptimer[2] = omap_gp_timer_init(omap_l4ta(s->l4, 22), 2353 qdev_get_gpio_in(s->ih[0], OMAP_INT_24XX_GPTIMER3), 2354 omap_findclk(s, "core_gpt3_clk"), 2355 omap_findclk(s, "core_l4_iclk")); 2356 s->gptimer[3] = omap_gp_timer_init(omap_l4ta(s->l4, 23), 2357 qdev_get_gpio_in(s->ih[0], OMAP_INT_24XX_GPTIMER4), 2358 omap_findclk(s, "core_gpt4_clk"), 2359 omap_findclk(s, "core_l4_iclk")); 2360 s->gptimer[4] = omap_gp_timer_init(omap_l4ta(s->l4, 24), 2361 qdev_get_gpio_in(s->ih[0], OMAP_INT_24XX_GPTIMER5), 2362 omap_findclk(s, "core_gpt5_clk"), 2363 omap_findclk(s, "core_l4_iclk")); 2364 s->gptimer[5] = omap_gp_timer_init(omap_l4ta(s->l4, 25), 2365 qdev_get_gpio_in(s->ih[0], OMAP_INT_24XX_GPTIMER6), 2366 omap_findclk(s, "core_gpt6_clk"), 2367 omap_findclk(s, "core_l4_iclk")); 2368 s->gptimer[6] = omap_gp_timer_init(omap_l4ta(s->l4, 26), 2369 qdev_get_gpio_in(s->ih[0], OMAP_INT_24XX_GPTIMER7), 2370 omap_findclk(s, "core_gpt7_clk"), 2371 omap_findclk(s, "core_l4_iclk")); 2372 s->gptimer[7] = omap_gp_timer_init(omap_l4ta(s->l4, 27), 2373 qdev_get_gpio_in(s->ih[0], OMAP_INT_24XX_GPTIMER8), 2374 omap_findclk(s, "core_gpt8_clk"), 2375 omap_findclk(s, "core_l4_iclk")); 2376 s->gptimer[8] = omap_gp_timer_init(omap_l4ta(s->l4, 28), 2377 qdev_get_gpio_in(s->ih[0], OMAP_INT_24XX_GPTIMER9), 2378 omap_findclk(s, "core_gpt9_clk"), 2379 omap_findclk(s, "core_l4_iclk")); 2380 s->gptimer[9] = omap_gp_timer_init(omap_l4ta(s->l4, 29), 2381 qdev_get_gpio_in(s->ih[0], OMAP_INT_24XX_GPTIMER10), 2382 omap_findclk(s, "core_gpt10_clk"), 2383 omap_findclk(s, "core_l4_iclk")); 2384 s->gptimer[10] = omap_gp_timer_init(omap_l4ta(s->l4, 30), 2385 qdev_get_gpio_in(s->ih[0], OMAP_INT_24XX_GPTIMER11), 2386 omap_findclk(s, "core_gpt11_clk"), 2387 omap_findclk(s, "core_l4_iclk")); 2388 s->gptimer[11] = omap_gp_timer_init(omap_l4ta(s->l4, 31), 2389 qdev_get_gpio_in(s->ih[0], OMAP_INT_24XX_GPTIMER12), 2390 omap_findclk(s, "core_gpt12_clk"), 2391 omap_findclk(s, "core_l4_iclk")); 2392 2393 omap_tap_init(omap_l4ta(s->l4, 2), s); 2394 2395 s->synctimer = omap_synctimer_init(omap_l4tao(s->l4, 2), s, 2396 omap_findclk(s, "clk32-kHz"), 2397 omap_findclk(s, "core_l4_iclk")); 2398 2399 s->i2c[0] = qdev_create(NULL, "omap_i2c"); 2400 qdev_prop_set_uint8(s->i2c[0], "revision", 0x34); 2401 qdev_prop_set_ptr(s->i2c[0], "iclk", omap_findclk(s, "i2c1.iclk")); 2402 qdev_prop_set_ptr(s->i2c[0], "fclk", omap_findclk(s, "i2c1.fclk")); 2403 qdev_init_nofail(s->i2c[0]); 2404 busdev = SYS_BUS_DEVICE(s->i2c[0]); 2405 sysbus_connect_irq(busdev, 0, 2406 qdev_get_gpio_in(s->ih[0], OMAP_INT_24XX_I2C1_IRQ)); 2407 sysbus_connect_irq(busdev, 1, s->drq[OMAP24XX_DMA_I2C1_TX]); 2408 sysbus_connect_irq(busdev, 2, s->drq[OMAP24XX_DMA_I2C1_RX]); 2409 sysbus_mmio_map(busdev, 0, omap_l4_region_base(omap_l4tao(s->l4, 5), 0)); 2410 2411 s->i2c[1] = qdev_create(NULL, "omap_i2c"); 2412 qdev_prop_set_uint8(s->i2c[1], "revision", 0x34); 2413 qdev_prop_set_ptr(s->i2c[1], "iclk", omap_findclk(s, "i2c2.iclk")); 2414 qdev_prop_set_ptr(s->i2c[1], "fclk", omap_findclk(s, "i2c2.fclk")); 2415 qdev_init_nofail(s->i2c[1]); 2416 busdev = SYS_BUS_DEVICE(s->i2c[1]); 2417 sysbus_connect_irq(busdev, 0, 2418 qdev_get_gpio_in(s->ih[0], OMAP_INT_24XX_I2C2_IRQ)); 2419 sysbus_connect_irq(busdev, 1, s->drq[OMAP24XX_DMA_I2C2_TX]); 2420 sysbus_connect_irq(busdev, 2, s->drq[OMAP24XX_DMA_I2C2_RX]); 2421 sysbus_mmio_map(busdev, 0, omap_l4_region_base(omap_l4tao(s->l4, 6), 0)); 2422 2423 s->gpio = qdev_create(NULL, "omap2-gpio"); 2424 qdev_prop_set_int32(s->gpio, "mpu_model", s->mpu_model); 2425 qdev_prop_set_ptr(s->gpio, "iclk", omap_findclk(s, "gpio_iclk")); 2426 qdev_prop_set_ptr(s->gpio, "fclk0", omap_findclk(s, "gpio1_dbclk")); 2427 qdev_prop_set_ptr(s->gpio, "fclk1", omap_findclk(s, "gpio2_dbclk")); 2428 qdev_prop_set_ptr(s->gpio, "fclk2", omap_findclk(s, "gpio3_dbclk")); 2429 qdev_prop_set_ptr(s->gpio, "fclk3", omap_findclk(s, "gpio4_dbclk")); 2430 if (s->mpu_model == omap2430) { 2431 qdev_prop_set_ptr(s->gpio, "fclk4", omap_findclk(s, "gpio5_dbclk")); 2432 } 2433 qdev_init_nofail(s->gpio); 2434 busdev = SYS_BUS_DEVICE(s->gpio); 2435 sysbus_connect_irq(busdev, 0, 2436 qdev_get_gpio_in(s->ih[0], OMAP_INT_24XX_GPIO_BANK1)); 2437 sysbus_connect_irq(busdev, 3, 2438 qdev_get_gpio_in(s->ih[0], OMAP_INT_24XX_GPIO_BANK2)); 2439 sysbus_connect_irq(busdev, 6, 2440 qdev_get_gpio_in(s->ih[0], OMAP_INT_24XX_GPIO_BANK3)); 2441 sysbus_connect_irq(busdev, 9, 2442 qdev_get_gpio_in(s->ih[0], OMAP_INT_24XX_GPIO_BANK4)); 2443 if (s->mpu_model == omap2430) { 2444 sysbus_connect_irq(busdev, 12, 2445 qdev_get_gpio_in(s->ih[0], 2446 OMAP_INT_243X_GPIO_BANK5)); 2447 } 2448 ta = omap_l4ta(s->l4, 3); 2449 sysbus_mmio_map(busdev, 0, omap_l4_region_base(ta, 1)); 2450 sysbus_mmio_map(busdev, 1, omap_l4_region_base(ta, 0)); 2451 sysbus_mmio_map(busdev, 2, omap_l4_region_base(ta, 2)); 2452 sysbus_mmio_map(busdev, 3, omap_l4_region_base(ta, 4)); 2453 sysbus_mmio_map(busdev, 4, omap_l4_region_base(ta, 5)); 2454 2455 s->sdrc = omap_sdrc_init(sysmem, 0x68009000); 2456 s->gpmc = omap_gpmc_init(s, 0x6800a000, 2457 qdev_get_gpio_in(s->ih[0], OMAP_INT_24XX_GPMC_IRQ), 2458 s->drq[OMAP24XX_DMA_GPMC]); 2459 2460 dinfo = drive_get(IF_SD, 0, 0); 2461 if (!dinfo) { 2462 fprintf(stderr, "qemu: missing SecureDigital device\n"); 2463 exit(1); 2464 } 2465 s->mmc = omap2_mmc_init(omap_l4tao(s->l4, 9), 2466 blk_by_legacy_dinfo(dinfo), 2467 qdev_get_gpio_in(s->ih[0], OMAP_INT_24XX_MMC_IRQ), 2468 &s->drq[OMAP24XX_DMA_MMC1_TX], 2469 omap_findclk(s, "mmc_fclk"), omap_findclk(s, "mmc_iclk")); 2470 2471 s->mcspi[0] = omap_mcspi_init(omap_l4ta(s->l4, 35), 4, 2472 qdev_get_gpio_in(s->ih[0], OMAP_INT_24XX_MCSPI1_IRQ), 2473 &s->drq[OMAP24XX_DMA_SPI1_TX0], 2474 omap_findclk(s, "spi1_fclk"), 2475 omap_findclk(s, "spi1_iclk")); 2476 s->mcspi[1] = omap_mcspi_init(omap_l4ta(s->l4, 36), 2, 2477 qdev_get_gpio_in(s->ih[0], OMAP_INT_24XX_MCSPI2_IRQ), 2478 &s->drq[OMAP24XX_DMA_SPI2_TX0], 2479 omap_findclk(s, "spi2_fclk"), 2480 omap_findclk(s, "spi2_iclk")); 2481 2482 s->dss = omap_dss_init(omap_l4ta(s->l4, 10), sysmem, 0x68000800, 2483 /* XXX wire M_IRQ_25, D_L2_IRQ_30 and I_IRQ_13 together */ 2484 qdev_get_gpio_in(s->ih[0], OMAP_INT_24XX_DSS_IRQ), 2485 s->drq[OMAP24XX_DMA_DSS], 2486 omap_findclk(s, "dss_clk1"), omap_findclk(s, "dss_clk2"), 2487 omap_findclk(s, "dss_54m_clk"), 2488 omap_findclk(s, "dss_l3_iclk"), 2489 omap_findclk(s, "dss_l4_iclk")); 2490 2491 omap_sti_init(omap_l4ta(s->l4, 18), sysmem, 0x54000000, 2492 qdev_get_gpio_in(s->ih[0], OMAP_INT_24XX_STI), 2493 omap_findclk(s, "emul_ck"), 2494 serial_hds[0] && serial_hds[1] && serial_hds[2] ? 2495 serial_hds[3] : NULL); 2496 2497 s->eac = omap_eac_init(omap_l4ta(s->l4, 32), 2498 qdev_get_gpio_in(s->ih[0], OMAP_INT_24XX_EAC_IRQ), 2499 /* Ten consecutive lines */ 2500 &s->drq[OMAP24XX_DMA_EAC_AC_RD], 2501 omap_findclk(s, "func_96m_clk"), 2502 omap_findclk(s, "core_l4_iclk")); 2503 2504 /* All register mappings (includin those not currenlty implemented): 2505 * SystemControlMod 48000000 - 48000fff 2506 * SystemControlL4 48001000 - 48001fff 2507 * 32kHz Timer Mod 48004000 - 48004fff 2508 * 32kHz Timer L4 48005000 - 48005fff 2509 * PRCM ModA 48008000 - 480087ff 2510 * PRCM ModB 48008800 - 48008fff 2511 * PRCM L4 48009000 - 48009fff 2512 * TEST-BCM Mod 48012000 - 48012fff 2513 * TEST-BCM L4 48013000 - 48013fff 2514 * TEST-TAP Mod 48014000 - 48014fff 2515 * TEST-TAP L4 48015000 - 48015fff 2516 * GPIO1 Mod 48018000 - 48018fff 2517 * GPIO Top 48019000 - 48019fff 2518 * GPIO2 Mod 4801a000 - 4801afff 2519 * GPIO L4 4801b000 - 4801bfff 2520 * GPIO3 Mod 4801c000 - 4801cfff 2521 * GPIO4 Mod 4801e000 - 4801efff 2522 * WDTIMER1 Mod 48020000 - 48010fff 2523 * WDTIMER Top 48021000 - 48011fff 2524 * WDTIMER2 Mod 48022000 - 48012fff 2525 * WDTIMER L4 48023000 - 48013fff 2526 * WDTIMER3 Mod 48024000 - 48014fff 2527 * WDTIMER3 L4 48025000 - 48015fff 2528 * WDTIMER4 Mod 48026000 - 48016fff 2529 * WDTIMER4 L4 48027000 - 48017fff 2530 * GPTIMER1 Mod 48028000 - 48018fff 2531 * GPTIMER1 L4 48029000 - 48019fff 2532 * GPTIMER2 Mod 4802a000 - 4801afff 2533 * GPTIMER2 L4 4802b000 - 4801bfff 2534 * L4-Config AP 48040000 - 480407ff 2535 * L4-Config IP 48040800 - 48040fff 2536 * L4-Config LA 48041000 - 48041fff 2537 * ARM11ETB Mod 48048000 - 48049fff 2538 * ARM11ETB L4 4804a000 - 4804afff 2539 * DISPLAY Top 48050000 - 480503ff 2540 * DISPLAY DISPC 48050400 - 480507ff 2541 * DISPLAY RFBI 48050800 - 48050bff 2542 * DISPLAY VENC 48050c00 - 48050fff 2543 * DISPLAY L4 48051000 - 48051fff 2544 * CAMERA Top 48052000 - 480523ff 2545 * CAMERA core 48052400 - 480527ff 2546 * CAMERA DMA 48052800 - 48052bff 2547 * CAMERA MMU 48052c00 - 48052fff 2548 * CAMERA L4 48053000 - 48053fff 2549 * SDMA Mod 48056000 - 48056fff 2550 * SDMA L4 48057000 - 48057fff 2551 * SSI Top 48058000 - 48058fff 2552 * SSI GDD 48059000 - 48059fff 2553 * SSI Port1 4805a000 - 4805afff 2554 * SSI Port2 4805b000 - 4805bfff 2555 * SSI L4 4805c000 - 4805cfff 2556 * USB Mod 4805e000 - 480fefff 2557 * USB L4 4805f000 - 480fffff 2558 * WIN_TRACER1 Mod 48060000 - 48060fff 2559 * WIN_TRACER1 L4 48061000 - 48061fff 2560 * WIN_TRACER2 Mod 48062000 - 48062fff 2561 * WIN_TRACER2 L4 48063000 - 48063fff 2562 * WIN_TRACER3 Mod 48064000 - 48064fff 2563 * WIN_TRACER3 L4 48065000 - 48065fff 2564 * WIN_TRACER4 Top 48066000 - 480660ff 2565 * WIN_TRACER4 ETT 48066100 - 480661ff 2566 * WIN_TRACER4 WT 48066200 - 480662ff 2567 * WIN_TRACER4 L4 48067000 - 48067fff 2568 * XTI Mod 48068000 - 48068fff 2569 * XTI L4 48069000 - 48069fff 2570 * UART1 Mod 4806a000 - 4806afff 2571 * UART1 L4 4806b000 - 4806bfff 2572 * UART2 Mod 4806c000 - 4806cfff 2573 * UART2 L4 4806d000 - 4806dfff 2574 * UART3 Mod 4806e000 - 4806efff 2575 * UART3 L4 4806f000 - 4806ffff 2576 * I2C1 Mod 48070000 - 48070fff 2577 * I2C1 L4 48071000 - 48071fff 2578 * I2C2 Mod 48072000 - 48072fff 2579 * I2C2 L4 48073000 - 48073fff 2580 * McBSP1 Mod 48074000 - 48074fff 2581 * McBSP1 L4 48075000 - 48075fff 2582 * McBSP2 Mod 48076000 - 48076fff 2583 * McBSP2 L4 48077000 - 48077fff 2584 * GPTIMER3 Mod 48078000 - 48078fff 2585 * GPTIMER3 L4 48079000 - 48079fff 2586 * GPTIMER4 Mod 4807a000 - 4807afff 2587 * GPTIMER4 L4 4807b000 - 4807bfff 2588 * GPTIMER5 Mod 4807c000 - 4807cfff 2589 * GPTIMER5 L4 4807d000 - 4807dfff 2590 * GPTIMER6 Mod 4807e000 - 4807efff 2591 * GPTIMER6 L4 4807f000 - 4807ffff 2592 * GPTIMER7 Mod 48080000 - 48080fff 2593 * GPTIMER7 L4 48081000 - 48081fff 2594 * GPTIMER8 Mod 48082000 - 48082fff 2595 * GPTIMER8 L4 48083000 - 48083fff 2596 * GPTIMER9 Mod 48084000 - 48084fff 2597 * GPTIMER9 L4 48085000 - 48085fff 2598 * GPTIMER10 Mod 48086000 - 48086fff 2599 * GPTIMER10 L4 48087000 - 48087fff 2600 * GPTIMER11 Mod 48088000 - 48088fff 2601 * GPTIMER11 L4 48089000 - 48089fff 2602 * GPTIMER12 Mod 4808a000 - 4808afff 2603 * GPTIMER12 L4 4808b000 - 4808bfff 2604 * EAC Mod 48090000 - 48090fff 2605 * EAC L4 48091000 - 48091fff 2606 * FAC Mod 48092000 - 48092fff 2607 * FAC L4 48093000 - 48093fff 2608 * MAILBOX Mod 48094000 - 48094fff 2609 * MAILBOX L4 48095000 - 48095fff 2610 * SPI1 Mod 48098000 - 48098fff 2611 * SPI1 L4 48099000 - 48099fff 2612 * SPI2 Mod 4809a000 - 4809afff 2613 * SPI2 L4 4809b000 - 4809bfff 2614 * MMC/SDIO Mod 4809c000 - 4809cfff 2615 * MMC/SDIO L4 4809d000 - 4809dfff 2616 * MS_PRO Mod 4809e000 - 4809efff 2617 * MS_PRO L4 4809f000 - 4809ffff 2618 * RNG Mod 480a0000 - 480a0fff 2619 * RNG L4 480a1000 - 480a1fff 2620 * DES3DES Mod 480a2000 - 480a2fff 2621 * DES3DES L4 480a3000 - 480a3fff 2622 * SHA1MD5 Mod 480a4000 - 480a4fff 2623 * SHA1MD5 L4 480a5000 - 480a5fff 2624 * AES Mod 480a6000 - 480a6fff 2625 * AES L4 480a7000 - 480a7fff 2626 * PKA Mod 480a8000 - 480a9fff 2627 * PKA L4 480aa000 - 480aafff 2628 * MG Mod 480b0000 - 480b0fff 2629 * MG L4 480b1000 - 480b1fff 2630 * HDQ/1-wire Mod 480b2000 - 480b2fff 2631 * HDQ/1-wire L4 480b3000 - 480b3fff 2632 * MPU interrupt 480fe000 - 480fefff 2633 * STI channel base 54000000 - 5400ffff 2634 * IVA RAM 5c000000 - 5c01ffff 2635 * IVA ROM 5c020000 - 5c027fff 2636 * IMG_BUF_A 5c040000 - 5c040fff 2637 * IMG_BUF_B 5c042000 - 5c042fff 2638 * VLCDS 5c048000 - 5c0487ff 2639 * IMX_COEF 5c049000 - 5c04afff 2640 * IMX_CMD 5c051000 - 5c051fff 2641 * VLCDQ 5c053000 - 5c0533ff 2642 * VLCDH 5c054000 - 5c054fff 2643 * SEQ_CMD 5c055000 - 5c055fff 2644 * IMX_REG 5c056000 - 5c0560ff 2645 * VLCD_REG 5c056100 - 5c0561ff 2646 * SEQ_REG 5c056200 - 5c0562ff 2647 * IMG_BUF_REG 5c056300 - 5c0563ff 2648 * SEQIRQ_REG 5c056400 - 5c0564ff 2649 * OCP_REG 5c060000 - 5c060fff 2650 * SYSC_REG 5c070000 - 5c070fff 2651 * MMU_REG 5d000000 - 5d000fff 2652 * sDMA R 68000400 - 680005ff 2653 * sDMA W 68000600 - 680007ff 2654 * Display Control 68000800 - 680009ff 2655 * DSP subsystem 68000a00 - 68000bff 2656 * MPU subsystem 68000c00 - 68000dff 2657 * IVA subsystem 68001000 - 680011ff 2658 * USB 68001200 - 680013ff 2659 * Camera 68001400 - 680015ff 2660 * VLYNQ (firewall) 68001800 - 68001bff 2661 * VLYNQ 68001e00 - 68001fff 2662 * SSI 68002000 - 680021ff 2663 * L4 68002400 - 680025ff 2664 * DSP (firewall) 68002800 - 68002bff 2665 * DSP subsystem 68002e00 - 68002fff 2666 * IVA (firewall) 68003000 - 680033ff 2667 * IVA 68003600 - 680037ff 2668 * GFX 68003a00 - 68003bff 2669 * CMDWR emulation 68003c00 - 68003dff 2670 * SMS 68004000 - 680041ff 2671 * OCM 68004200 - 680043ff 2672 * GPMC 68004400 - 680045ff 2673 * RAM (firewall) 68005000 - 680053ff 2674 * RAM (err login) 68005400 - 680057ff 2675 * ROM (firewall) 68005800 - 68005bff 2676 * ROM (err login) 68005c00 - 68005fff 2677 * GPMC (firewall) 68006000 - 680063ff 2678 * GPMC (err login) 68006400 - 680067ff 2679 * SMS (err login) 68006c00 - 68006fff 2680 * SMS registers 68008000 - 68008fff 2681 * SDRC registers 68009000 - 68009fff 2682 * GPMC registers 6800a000 6800afff 2683 */ 2684 2685 qemu_register_reset(omap2_mpu_reset, s); 2686 2687 return s; 2688 } 2689