1*b0c96666SNiek Linnenbank /* 2*b0c96666SNiek Linnenbank * Orange Pi emulation 3*b0c96666SNiek Linnenbank * 4*b0c96666SNiek Linnenbank * Copyright (C) 2019 Niek Linnenbank <nieklinnenbank@gmail.com> 5*b0c96666SNiek Linnenbank * 6*b0c96666SNiek Linnenbank * This program is free software: you can redistribute it and/or modify 7*b0c96666SNiek Linnenbank * it under the terms of the GNU General Public License as published by 8*b0c96666SNiek Linnenbank * the Free Software Foundation, either version 2 of the License, or 9*b0c96666SNiek Linnenbank * (at your option) any later version. 10*b0c96666SNiek Linnenbank * 11*b0c96666SNiek Linnenbank * This program is distributed in the hope that it will be useful, 12*b0c96666SNiek Linnenbank * but WITHOUT ANY WARRANTY; without even the implied warranty of 13*b0c96666SNiek Linnenbank * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the 14*b0c96666SNiek Linnenbank * GNU General Public License for more details. 15*b0c96666SNiek Linnenbank * 16*b0c96666SNiek Linnenbank * You should have received a copy of the GNU General Public License 17*b0c96666SNiek Linnenbank * along with this program. If not, see <http://www.gnu.org/licenses/>. 18*b0c96666SNiek Linnenbank */ 19*b0c96666SNiek Linnenbank 20*b0c96666SNiek Linnenbank #include "qemu/osdep.h" 21*b0c96666SNiek Linnenbank #include "qemu/units.h" 22*b0c96666SNiek Linnenbank #include "exec/address-spaces.h" 23*b0c96666SNiek Linnenbank #include "qapi/error.h" 24*b0c96666SNiek Linnenbank #include "cpu.h" 25*b0c96666SNiek Linnenbank #include "hw/sysbus.h" 26*b0c96666SNiek Linnenbank #include "hw/boards.h" 27*b0c96666SNiek Linnenbank #include "hw/qdev-properties.h" 28*b0c96666SNiek Linnenbank #include "hw/arm/allwinner-h3.h" 29*b0c96666SNiek Linnenbank #include "sysemu/sysemu.h" 30*b0c96666SNiek Linnenbank 31*b0c96666SNiek Linnenbank static struct arm_boot_info orangepi_binfo = { 32*b0c96666SNiek Linnenbank .nb_cpus = AW_H3_NUM_CPUS, 33*b0c96666SNiek Linnenbank }; 34*b0c96666SNiek Linnenbank 35*b0c96666SNiek Linnenbank static void orangepi_init(MachineState *machine) 36*b0c96666SNiek Linnenbank { 37*b0c96666SNiek Linnenbank AwH3State *h3; 38*b0c96666SNiek Linnenbank 39*b0c96666SNiek Linnenbank /* BIOS is not supported by this board */ 40*b0c96666SNiek Linnenbank if (bios_name) { 41*b0c96666SNiek Linnenbank error_report("BIOS not supported for this machine"); 42*b0c96666SNiek Linnenbank exit(1); 43*b0c96666SNiek Linnenbank } 44*b0c96666SNiek Linnenbank 45*b0c96666SNiek Linnenbank /* This board has fixed size RAM */ 46*b0c96666SNiek Linnenbank if (machine->ram_size != 1 * GiB) { 47*b0c96666SNiek Linnenbank error_report("This machine can only be used with 1GiB of RAM"); 48*b0c96666SNiek Linnenbank exit(1); 49*b0c96666SNiek Linnenbank } 50*b0c96666SNiek Linnenbank 51*b0c96666SNiek Linnenbank /* Only allow Cortex-A7 for this board */ 52*b0c96666SNiek Linnenbank if (strcmp(machine->cpu_type, ARM_CPU_TYPE_NAME("cortex-a7")) != 0) { 53*b0c96666SNiek Linnenbank error_report("This board can only be used with cortex-a7 CPU"); 54*b0c96666SNiek Linnenbank exit(1); 55*b0c96666SNiek Linnenbank } 56*b0c96666SNiek Linnenbank 57*b0c96666SNiek Linnenbank h3 = AW_H3(object_new(TYPE_AW_H3)); 58*b0c96666SNiek Linnenbank object_property_add_child(OBJECT(machine), "soc", OBJECT(h3), 59*b0c96666SNiek Linnenbank &error_abort); 60*b0c96666SNiek Linnenbank object_unref(OBJECT(h3)); 61*b0c96666SNiek Linnenbank 62*b0c96666SNiek Linnenbank /* Setup timer properties */ 63*b0c96666SNiek Linnenbank object_property_set_int(OBJECT(h3), 32768, "clk0-freq", 64*b0c96666SNiek Linnenbank &error_abort); 65*b0c96666SNiek Linnenbank object_property_set_int(OBJECT(h3), 24 * 1000 * 1000, "clk1-freq", 66*b0c96666SNiek Linnenbank &error_abort); 67*b0c96666SNiek Linnenbank 68*b0c96666SNiek Linnenbank /* Mark H3 object realized */ 69*b0c96666SNiek Linnenbank object_property_set_bool(OBJECT(h3), true, "realized", &error_abort); 70*b0c96666SNiek Linnenbank 71*b0c96666SNiek Linnenbank /* SDRAM */ 72*b0c96666SNiek Linnenbank memory_region_add_subregion(get_system_memory(), h3->memmap[AW_H3_SDRAM], 73*b0c96666SNiek Linnenbank machine->ram); 74*b0c96666SNiek Linnenbank 75*b0c96666SNiek Linnenbank orangepi_binfo.loader_start = h3->memmap[AW_H3_SDRAM]; 76*b0c96666SNiek Linnenbank orangepi_binfo.ram_size = machine->ram_size; 77*b0c96666SNiek Linnenbank arm_load_kernel(ARM_CPU(first_cpu), machine, &orangepi_binfo); 78*b0c96666SNiek Linnenbank } 79*b0c96666SNiek Linnenbank 80*b0c96666SNiek Linnenbank static void orangepi_machine_init(MachineClass *mc) 81*b0c96666SNiek Linnenbank { 82*b0c96666SNiek Linnenbank mc->desc = "Orange Pi PC"; 83*b0c96666SNiek Linnenbank mc->init = orangepi_init; 84*b0c96666SNiek Linnenbank mc->min_cpus = AW_H3_NUM_CPUS; 85*b0c96666SNiek Linnenbank mc->max_cpus = AW_H3_NUM_CPUS; 86*b0c96666SNiek Linnenbank mc->default_cpus = AW_H3_NUM_CPUS; 87*b0c96666SNiek Linnenbank mc->default_cpu_type = ARM_CPU_TYPE_NAME("cortex-a7"); 88*b0c96666SNiek Linnenbank mc->default_ram_size = 1 * GiB; 89*b0c96666SNiek Linnenbank mc->default_ram_id = "orangepi.ram"; 90*b0c96666SNiek Linnenbank } 91*b0c96666SNiek Linnenbank 92*b0c96666SNiek Linnenbank DEFINE_MACHINE("orangepi-pc", orangepi_machine_init) 93