1 /* 2 * Intel XScale PXA255/270 processor support. 3 * 4 * Copyright (c) 2006 Openedhand Ltd. 5 * Written by Andrzej Zaborowski <balrog@zabor.org> 6 * 7 * This code is licensed under the GPL. 8 */ 9 10 #include "qemu/osdep.h" 11 #include "qapi/error.h" 12 #include "qemu-common.h" 13 #include "cpu.h" 14 #include "hw/sysbus.h" 15 #include "hw/arm/pxa.h" 16 #include "sysemu/sysemu.h" 17 #include "hw/char/serial.h" 18 #include "hw/i2c/i2c.h" 19 #include "hw/ssi/ssi.h" 20 #include "sysemu/char.h" 21 #include "sysemu/block-backend.h" 22 #include "sysemu/blockdev.h" 23 #include "qemu/cutils.h" 24 25 static struct { 26 hwaddr io_base; 27 int irqn; 28 } pxa255_serial[] = { 29 { 0x40100000, PXA2XX_PIC_FFUART }, 30 { 0x40200000, PXA2XX_PIC_BTUART }, 31 { 0x40700000, PXA2XX_PIC_STUART }, 32 { 0x41600000, PXA25X_PIC_HWUART }, 33 { 0, 0 } 34 }, pxa270_serial[] = { 35 { 0x40100000, PXA2XX_PIC_FFUART }, 36 { 0x40200000, PXA2XX_PIC_BTUART }, 37 { 0x40700000, PXA2XX_PIC_STUART }, 38 { 0, 0 } 39 }; 40 41 typedef struct PXASSPDef { 42 hwaddr io_base; 43 int irqn; 44 } PXASSPDef; 45 46 #if 0 47 static PXASSPDef pxa250_ssp[] = { 48 { 0x41000000, PXA2XX_PIC_SSP }, 49 { 0, 0 } 50 }; 51 #endif 52 53 static PXASSPDef pxa255_ssp[] = { 54 { 0x41000000, PXA2XX_PIC_SSP }, 55 { 0x41400000, PXA25X_PIC_NSSP }, 56 { 0, 0 } 57 }; 58 59 #if 0 60 static PXASSPDef pxa26x_ssp[] = { 61 { 0x41000000, PXA2XX_PIC_SSP }, 62 { 0x41400000, PXA25X_PIC_NSSP }, 63 { 0x41500000, PXA26X_PIC_ASSP }, 64 { 0, 0 } 65 }; 66 #endif 67 68 static PXASSPDef pxa27x_ssp[] = { 69 { 0x41000000, PXA2XX_PIC_SSP }, 70 { 0x41700000, PXA27X_PIC_SSP2 }, 71 { 0x41900000, PXA2XX_PIC_SSP3 }, 72 { 0, 0 } 73 }; 74 75 #define PMCR 0x00 /* Power Manager Control register */ 76 #define PSSR 0x04 /* Power Manager Sleep Status register */ 77 #define PSPR 0x08 /* Power Manager Scratch-Pad register */ 78 #define PWER 0x0c /* Power Manager Wake-Up Enable register */ 79 #define PRER 0x10 /* Power Manager Rising-Edge Detect Enable register */ 80 #define PFER 0x14 /* Power Manager Falling-Edge Detect Enable register */ 81 #define PEDR 0x18 /* Power Manager Edge-Detect Status register */ 82 #define PCFR 0x1c /* Power Manager General Configuration register */ 83 #define PGSR0 0x20 /* Power Manager GPIO Sleep-State register 0 */ 84 #define PGSR1 0x24 /* Power Manager GPIO Sleep-State register 1 */ 85 #define PGSR2 0x28 /* Power Manager GPIO Sleep-State register 2 */ 86 #define PGSR3 0x2c /* Power Manager GPIO Sleep-State register 3 */ 87 #define RCSR 0x30 /* Reset Controller Status register */ 88 #define PSLR 0x34 /* Power Manager Sleep Configuration register */ 89 #define PTSR 0x38 /* Power Manager Standby Configuration register */ 90 #define PVCR 0x40 /* Power Manager Voltage Change Control register */ 91 #define PUCR 0x4c /* Power Manager USIM Card Control/Status register */ 92 #define PKWR 0x50 /* Power Manager Keyboard Wake-Up Enable register */ 93 #define PKSR 0x54 /* Power Manager Keyboard Level-Detect Status */ 94 #define PCMD0 0x80 /* Power Manager I2C Command register File 0 */ 95 #define PCMD31 0xfc /* Power Manager I2C Command register File 31 */ 96 97 static uint64_t pxa2xx_pm_read(void *opaque, hwaddr addr, 98 unsigned size) 99 { 100 PXA2xxState *s = (PXA2xxState *) opaque; 101 102 switch (addr) { 103 case PMCR ... PCMD31: 104 if (addr & 3) 105 goto fail; 106 107 return s->pm_regs[addr >> 2]; 108 default: 109 fail: 110 printf("%s: Bad register " REG_FMT "\n", __FUNCTION__, addr); 111 break; 112 } 113 return 0; 114 } 115 116 static void pxa2xx_pm_write(void *opaque, hwaddr addr, 117 uint64_t value, unsigned size) 118 { 119 PXA2xxState *s = (PXA2xxState *) opaque; 120 121 switch (addr) { 122 case PMCR: 123 /* Clear the write-one-to-clear bits... */ 124 s->pm_regs[addr >> 2] &= ~(value & 0x2a); 125 /* ...and set the plain r/w bits */ 126 s->pm_regs[addr >> 2] &= ~0x15; 127 s->pm_regs[addr >> 2] |= value & 0x15; 128 break; 129 130 case PSSR: /* Read-clean registers */ 131 case RCSR: 132 case PKSR: 133 s->pm_regs[addr >> 2] &= ~value; 134 break; 135 136 default: /* Read-write registers */ 137 if (!(addr & 3)) { 138 s->pm_regs[addr >> 2] = value; 139 break; 140 } 141 142 printf("%s: Bad register " REG_FMT "\n", __FUNCTION__, addr); 143 break; 144 } 145 } 146 147 static const MemoryRegionOps pxa2xx_pm_ops = { 148 .read = pxa2xx_pm_read, 149 .write = pxa2xx_pm_write, 150 .endianness = DEVICE_NATIVE_ENDIAN, 151 }; 152 153 static const VMStateDescription vmstate_pxa2xx_pm = { 154 .name = "pxa2xx_pm", 155 .version_id = 0, 156 .minimum_version_id = 0, 157 .fields = (VMStateField[]) { 158 VMSTATE_UINT32_ARRAY(pm_regs, PXA2xxState, 0x40), 159 VMSTATE_END_OF_LIST() 160 } 161 }; 162 163 #define CCCR 0x00 /* Core Clock Configuration register */ 164 #define CKEN 0x04 /* Clock Enable register */ 165 #define OSCC 0x08 /* Oscillator Configuration register */ 166 #define CCSR 0x0c /* Core Clock Status register */ 167 168 static uint64_t pxa2xx_cm_read(void *opaque, hwaddr addr, 169 unsigned size) 170 { 171 PXA2xxState *s = (PXA2xxState *) opaque; 172 173 switch (addr) { 174 case CCCR: 175 case CKEN: 176 case OSCC: 177 return s->cm_regs[addr >> 2]; 178 179 case CCSR: 180 return s->cm_regs[CCCR >> 2] | (3 << 28); 181 182 default: 183 printf("%s: Bad register " REG_FMT "\n", __FUNCTION__, addr); 184 break; 185 } 186 return 0; 187 } 188 189 static void pxa2xx_cm_write(void *opaque, hwaddr addr, 190 uint64_t value, unsigned size) 191 { 192 PXA2xxState *s = (PXA2xxState *) opaque; 193 194 switch (addr) { 195 case CCCR: 196 case CKEN: 197 s->cm_regs[addr >> 2] = value; 198 break; 199 200 case OSCC: 201 s->cm_regs[addr >> 2] &= ~0x6c; 202 s->cm_regs[addr >> 2] |= value & 0x6e; 203 if ((value >> 1) & 1) /* OON */ 204 s->cm_regs[addr >> 2] |= 1 << 0; /* Oscillator is now stable */ 205 break; 206 207 default: 208 printf("%s: Bad register " REG_FMT "\n", __FUNCTION__, addr); 209 break; 210 } 211 } 212 213 static const MemoryRegionOps pxa2xx_cm_ops = { 214 .read = pxa2xx_cm_read, 215 .write = pxa2xx_cm_write, 216 .endianness = DEVICE_NATIVE_ENDIAN, 217 }; 218 219 static const VMStateDescription vmstate_pxa2xx_cm = { 220 .name = "pxa2xx_cm", 221 .version_id = 0, 222 .minimum_version_id = 0, 223 .fields = (VMStateField[]) { 224 VMSTATE_UINT32_ARRAY(cm_regs, PXA2xxState, 4), 225 VMSTATE_UINT32(clkcfg, PXA2xxState), 226 VMSTATE_UINT32(pmnc, PXA2xxState), 227 VMSTATE_END_OF_LIST() 228 } 229 }; 230 231 static uint64_t pxa2xx_clkcfg_read(CPUARMState *env, const ARMCPRegInfo *ri) 232 { 233 PXA2xxState *s = (PXA2xxState *)ri->opaque; 234 return s->clkcfg; 235 } 236 237 static void pxa2xx_clkcfg_write(CPUARMState *env, const ARMCPRegInfo *ri, 238 uint64_t value) 239 { 240 PXA2xxState *s = (PXA2xxState *)ri->opaque; 241 s->clkcfg = value & 0xf; 242 if (value & 2) { 243 printf("%s: CPU frequency change attempt\n", __func__); 244 } 245 } 246 247 static void pxa2xx_pwrmode_write(CPUARMState *env, const ARMCPRegInfo *ri, 248 uint64_t value) 249 { 250 PXA2xxState *s = (PXA2xxState *)ri->opaque; 251 static const char *pwrmode[8] = { 252 "Normal", "Idle", "Deep-idle", "Standby", 253 "Sleep", "reserved (!)", "reserved (!)", "Deep-sleep", 254 }; 255 256 if (value & 8) { 257 printf("%s: CPU voltage change attempt\n", __func__); 258 } 259 switch (value & 7) { 260 case 0: 261 /* Do nothing */ 262 break; 263 264 case 1: 265 /* Idle */ 266 if (!(s->cm_regs[CCCR >> 2] & (1U << 31))) { /* CPDIS */ 267 cpu_interrupt(CPU(s->cpu), CPU_INTERRUPT_HALT); 268 break; 269 } 270 /* Fall through. */ 271 272 case 2: 273 /* Deep-Idle */ 274 cpu_interrupt(CPU(s->cpu), CPU_INTERRUPT_HALT); 275 s->pm_regs[RCSR >> 2] |= 0x8; /* Set GPR */ 276 goto message; 277 278 case 3: 279 s->cpu->env.uncached_cpsr = ARM_CPU_MODE_SVC; 280 s->cpu->env.daif = PSTATE_A | PSTATE_F | PSTATE_I; 281 s->cpu->env.cp15.sctlr_ns = 0; 282 s->cpu->env.cp15.cpacr_el1 = 0; 283 s->cpu->env.cp15.ttbr0_el[1] = 0; 284 s->cpu->env.cp15.dacr_ns = 0; 285 s->pm_regs[PSSR >> 2] |= 0x8; /* Set STS */ 286 s->pm_regs[RCSR >> 2] |= 0x8; /* Set GPR */ 287 288 /* 289 * The scratch-pad register is almost universally used 290 * for storing the return address on suspend. For the 291 * lack of a resuming bootloader, perform a jump 292 * directly to that address. 293 */ 294 memset(s->cpu->env.regs, 0, 4 * 15); 295 s->cpu->env.regs[15] = s->pm_regs[PSPR >> 2]; 296 297 #if 0 298 buffer = 0xe59ff000; /* ldr pc, [pc, #0] */ 299 cpu_physical_memory_write(0, &buffer, 4); 300 buffer = s->pm_regs[PSPR >> 2]; 301 cpu_physical_memory_write(8, &buffer, 4); 302 #endif 303 304 /* Suspend */ 305 cpu_interrupt(current_cpu, CPU_INTERRUPT_HALT); 306 307 goto message; 308 309 default: 310 message: 311 printf("%s: machine entered %s mode\n", __func__, 312 pwrmode[value & 7]); 313 } 314 } 315 316 static uint64_t pxa2xx_cppmnc_read(CPUARMState *env, const ARMCPRegInfo *ri) 317 { 318 PXA2xxState *s = (PXA2xxState *)ri->opaque; 319 return s->pmnc; 320 } 321 322 static void pxa2xx_cppmnc_write(CPUARMState *env, const ARMCPRegInfo *ri, 323 uint64_t value) 324 { 325 PXA2xxState *s = (PXA2xxState *)ri->opaque; 326 s->pmnc = value; 327 } 328 329 static uint64_t pxa2xx_cpccnt_read(CPUARMState *env, const ARMCPRegInfo *ri) 330 { 331 PXA2xxState *s = (PXA2xxState *)ri->opaque; 332 if (s->pmnc & 1) { 333 return qemu_clock_get_ns(QEMU_CLOCK_VIRTUAL); 334 } else { 335 return 0; 336 } 337 } 338 339 static const ARMCPRegInfo pxa_cp_reginfo[] = { 340 /* cp14 crm==1: perf registers */ 341 { .name = "CPPMNC", .cp = 14, .crn = 0, .crm = 1, .opc1 = 0, .opc2 = 0, 342 .access = PL1_RW, .type = ARM_CP_IO, 343 .readfn = pxa2xx_cppmnc_read, .writefn = pxa2xx_cppmnc_write }, 344 { .name = "CPCCNT", .cp = 14, .crn = 1, .crm = 1, .opc1 = 0, .opc2 = 0, 345 .access = PL1_RW, .type = ARM_CP_IO, 346 .readfn = pxa2xx_cpccnt_read, .writefn = arm_cp_write_ignore }, 347 { .name = "CPINTEN", .cp = 14, .crn = 4, .crm = 1, .opc1 = 0, .opc2 = 0, 348 .access = PL1_RW, .type = ARM_CP_CONST, .resetvalue = 0 }, 349 { .name = "CPFLAG", .cp = 14, .crn = 5, .crm = 1, .opc1 = 0, .opc2 = 0, 350 .access = PL1_RW, .type = ARM_CP_CONST, .resetvalue = 0 }, 351 { .name = "CPEVTSEL", .cp = 14, .crn = 8, .crm = 1, .opc1 = 0, .opc2 = 0, 352 .access = PL1_RW, .type = ARM_CP_CONST, .resetvalue = 0 }, 353 /* cp14 crm==2: performance count registers */ 354 { .name = "CPPMN0", .cp = 14, .crn = 0, .crm = 2, .opc1 = 0, .opc2 = 0, 355 .access = PL1_RW, .type = ARM_CP_CONST, .resetvalue = 0 }, 356 { .name = "CPPMN1", .cp = 14, .crn = 1, .crm = 2, .opc1 = 0, .opc2 = 0, 357 .access = PL1_RW, .type = ARM_CP_CONST, .resetvalue = 0 }, 358 { .name = "CPPMN2", .cp = 14, .crn = 2, .crm = 2, .opc1 = 0, .opc2 = 0, 359 .access = PL1_RW, .type = ARM_CP_CONST, .resetvalue = 0 }, 360 { .name = "CPPMN3", .cp = 14, .crn = 2, .crm = 3, .opc1 = 0, .opc2 = 0, 361 .access = PL1_RW, .type = ARM_CP_CONST, .resetvalue = 0 }, 362 /* cp14 crn==6: CLKCFG */ 363 { .name = "CLKCFG", .cp = 14, .crn = 6, .crm = 0, .opc1 = 0, .opc2 = 0, 364 .access = PL1_RW, .type = ARM_CP_IO, 365 .readfn = pxa2xx_clkcfg_read, .writefn = pxa2xx_clkcfg_write }, 366 /* cp14 crn==7: PWRMODE */ 367 { .name = "PWRMODE", .cp = 14, .crn = 7, .crm = 0, .opc1 = 0, .opc2 = 0, 368 .access = PL1_RW, .type = ARM_CP_IO, 369 .readfn = arm_cp_read_zero, .writefn = pxa2xx_pwrmode_write }, 370 REGINFO_SENTINEL 371 }; 372 373 static void pxa2xx_setup_cp14(PXA2xxState *s) 374 { 375 define_arm_cp_regs_with_opaque(s->cpu, pxa_cp_reginfo, s); 376 } 377 378 #define MDCNFG 0x00 /* SDRAM Configuration register */ 379 #define MDREFR 0x04 /* SDRAM Refresh Control register */ 380 #define MSC0 0x08 /* Static Memory Control register 0 */ 381 #define MSC1 0x0c /* Static Memory Control register 1 */ 382 #define MSC2 0x10 /* Static Memory Control register 2 */ 383 #define MECR 0x14 /* Expansion Memory Bus Config register */ 384 #define SXCNFG 0x1c /* Synchronous Static Memory Config register */ 385 #define MCMEM0 0x28 /* PC Card Memory Socket 0 Timing register */ 386 #define MCMEM1 0x2c /* PC Card Memory Socket 1 Timing register */ 387 #define MCATT0 0x30 /* PC Card Attribute Socket 0 register */ 388 #define MCATT1 0x34 /* PC Card Attribute Socket 1 register */ 389 #define MCIO0 0x38 /* PC Card I/O Socket 0 Timing register */ 390 #define MCIO1 0x3c /* PC Card I/O Socket 1 Timing register */ 391 #define MDMRS 0x40 /* SDRAM Mode Register Set Config register */ 392 #define BOOT_DEF 0x44 /* Boot-time Default Configuration register */ 393 #define ARB_CNTL 0x48 /* Arbiter Control register */ 394 #define BSCNTR0 0x4c /* Memory Buffer Strength Control register 0 */ 395 #define BSCNTR1 0x50 /* Memory Buffer Strength Control register 1 */ 396 #define LCDBSCNTR 0x54 /* LCD Buffer Strength Control register */ 397 #define MDMRSLP 0x58 /* Low Power SDRAM Mode Set Config register */ 398 #define BSCNTR2 0x5c /* Memory Buffer Strength Control register 2 */ 399 #define BSCNTR3 0x60 /* Memory Buffer Strength Control register 3 */ 400 #define SA1110 0x64 /* SA-1110 Memory Compatibility register */ 401 402 static uint64_t pxa2xx_mm_read(void *opaque, hwaddr addr, 403 unsigned size) 404 { 405 PXA2xxState *s = (PXA2xxState *) opaque; 406 407 switch (addr) { 408 case MDCNFG ... SA1110: 409 if ((addr & 3) == 0) 410 return s->mm_regs[addr >> 2]; 411 412 default: 413 printf("%s: Bad register " REG_FMT "\n", __FUNCTION__, addr); 414 break; 415 } 416 return 0; 417 } 418 419 static void pxa2xx_mm_write(void *opaque, hwaddr addr, 420 uint64_t value, unsigned size) 421 { 422 PXA2xxState *s = (PXA2xxState *) opaque; 423 424 switch (addr) { 425 case MDCNFG ... SA1110: 426 if ((addr & 3) == 0) { 427 s->mm_regs[addr >> 2] = value; 428 break; 429 } 430 431 default: 432 printf("%s: Bad register " REG_FMT "\n", __FUNCTION__, addr); 433 break; 434 } 435 } 436 437 static const MemoryRegionOps pxa2xx_mm_ops = { 438 .read = pxa2xx_mm_read, 439 .write = pxa2xx_mm_write, 440 .endianness = DEVICE_NATIVE_ENDIAN, 441 }; 442 443 static const VMStateDescription vmstate_pxa2xx_mm = { 444 .name = "pxa2xx_mm", 445 .version_id = 0, 446 .minimum_version_id = 0, 447 .fields = (VMStateField[]) { 448 VMSTATE_UINT32_ARRAY(mm_regs, PXA2xxState, 0x1a), 449 VMSTATE_END_OF_LIST() 450 } 451 }; 452 453 #define TYPE_PXA2XX_SSP "pxa2xx-ssp" 454 #define PXA2XX_SSP(obj) \ 455 OBJECT_CHECK(PXA2xxSSPState, (obj), TYPE_PXA2XX_SSP) 456 457 /* Synchronous Serial Ports */ 458 typedef struct { 459 /*< private >*/ 460 SysBusDevice parent_obj; 461 /*< public >*/ 462 463 MemoryRegion iomem; 464 qemu_irq irq; 465 uint32_t enable; 466 SSIBus *bus; 467 468 uint32_t sscr[2]; 469 uint32_t sspsp; 470 uint32_t ssto; 471 uint32_t ssitr; 472 uint32_t sssr; 473 uint8_t sstsa; 474 uint8_t ssrsa; 475 uint8_t ssacd; 476 477 uint32_t rx_fifo[16]; 478 uint32_t rx_level; 479 uint32_t rx_start; 480 } PXA2xxSSPState; 481 482 static bool pxa2xx_ssp_vmstate_validate(void *opaque, int version_id) 483 { 484 PXA2xxSSPState *s = opaque; 485 486 return s->rx_start < sizeof(s->rx_fifo); 487 } 488 489 static const VMStateDescription vmstate_pxa2xx_ssp = { 490 .name = "pxa2xx-ssp", 491 .version_id = 1, 492 .minimum_version_id = 1, 493 .fields = (VMStateField[]) { 494 VMSTATE_UINT32(enable, PXA2xxSSPState), 495 VMSTATE_UINT32_ARRAY(sscr, PXA2xxSSPState, 2), 496 VMSTATE_UINT32(sspsp, PXA2xxSSPState), 497 VMSTATE_UINT32(ssto, PXA2xxSSPState), 498 VMSTATE_UINT32(ssitr, PXA2xxSSPState), 499 VMSTATE_UINT32(sssr, PXA2xxSSPState), 500 VMSTATE_UINT8(sstsa, PXA2xxSSPState), 501 VMSTATE_UINT8(ssrsa, PXA2xxSSPState), 502 VMSTATE_UINT8(ssacd, PXA2xxSSPState), 503 VMSTATE_UINT32(rx_level, PXA2xxSSPState), 504 VMSTATE_UINT32(rx_start, PXA2xxSSPState), 505 VMSTATE_VALIDATE("fifo is 16 bytes", pxa2xx_ssp_vmstate_validate), 506 VMSTATE_UINT32_ARRAY(rx_fifo, PXA2xxSSPState, 16), 507 VMSTATE_END_OF_LIST() 508 } 509 }; 510 511 #define SSCR0 0x00 /* SSP Control register 0 */ 512 #define SSCR1 0x04 /* SSP Control register 1 */ 513 #define SSSR 0x08 /* SSP Status register */ 514 #define SSITR 0x0c /* SSP Interrupt Test register */ 515 #define SSDR 0x10 /* SSP Data register */ 516 #define SSTO 0x28 /* SSP Time-Out register */ 517 #define SSPSP 0x2c /* SSP Programmable Serial Protocol register */ 518 #define SSTSA 0x30 /* SSP TX Time Slot Active register */ 519 #define SSRSA 0x34 /* SSP RX Time Slot Active register */ 520 #define SSTSS 0x38 /* SSP Time Slot Status register */ 521 #define SSACD 0x3c /* SSP Audio Clock Divider register */ 522 523 /* Bitfields for above registers */ 524 #define SSCR0_SPI(x) (((x) & 0x30) == 0x00) 525 #define SSCR0_SSP(x) (((x) & 0x30) == 0x10) 526 #define SSCR0_UWIRE(x) (((x) & 0x30) == 0x20) 527 #define SSCR0_PSP(x) (((x) & 0x30) == 0x30) 528 #define SSCR0_SSE (1 << 7) 529 #define SSCR0_RIM (1 << 22) 530 #define SSCR0_TIM (1 << 23) 531 #define SSCR0_MOD (1U << 31) 532 #define SSCR0_DSS(x) (((((x) >> 16) & 0x10) | ((x) & 0xf)) + 1) 533 #define SSCR1_RIE (1 << 0) 534 #define SSCR1_TIE (1 << 1) 535 #define SSCR1_LBM (1 << 2) 536 #define SSCR1_MWDS (1 << 5) 537 #define SSCR1_TFT(x) ((((x) >> 6) & 0xf) + 1) 538 #define SSCR1_RFT(x) ((((x) >> 10) & 0xf) + 1) 539 #define SSCR1_EFWR (1 << 14) 540 #define SSCR1_PINTE (1 << 18) 541 #define SSCR1_TINTE (1 << 19) 542 #define SSCR1_RSRE (1 << 20) 543 #define SSCR1_TSRE (1 << 21) 544 #define SSCR1_EBCEI (1 << 29) 545 #define SSITR_INT (7 << 5) 546 #define SSSR_TNF (1 << 2) 547 #define SSSR_RNE (1 << 3) 548 #define SSSR_TFS (1 << 5) 549 #define SSSR_RFS (1 << 6) 550 #define SSSR_ROR (1 << 7) 551 #define SSSR_PINT (1 << 18) 552 #define SSSR_TINT (1 << 19) 553 #define SSSR_EOC (1 << 20) 554 #define SSSR_TUR (1 << 21) 555 #define SSSR_BCE (1 << 23) 556 #define SSSR_RW 0x00bc0080 557 558 static void pxa2xx_ssp_int_update(PXA2xxSSPState *s) 559 { 560 int level = 0; 561 562 level |= s->ssitr & SSITR_INT; 563 level |= (s->sssr & SSSR_BCE) && (s->sscr[1] & SSCR1_EBCEI); 564 level |= (s->sssr & SSSR_TUR) && !(s->sscr[0] & SSCR0_TIM); 565 level |= (s->sssr & SSSR_EOC) && (s->sssr & (SSSR_TINT | SSSR_PINT)); 566 level |= (s->sssr & SSSR_TINT) && (s->sscr[1] & SSCR1_TINTE); 567 level |= (s->sssr & SSSR_PINT) && (s->sscr[1] & SSCR1_PINTE); 568 level |= (s->sssr & SSSR_ROR) && !(s->sscr[0] & SSCR0_RIM); 569 level |= (s->sssr & SSSR_RFS) && (s->sscr[1] & SSCR1_RIE); 570 level |= (s->sssr & SSSR_TFS) && (s->sscr[1] & SSCR1_TIE); 571 qemu_set_irq(s->irq, !!level); 572 } 573 574 static void pxa2xx_ssp_fifo_update(PXA2xxSSPState *s) 575 { 576 s->sssr &= ~(0xf << 12); /* Clear RFL */ 577 s->sssr &= ~(0xf << 8); /* Clear TFL */ 578 s->sssr &= ~SSSR_TFS; 579 s->sssr &= ~SSSR_TNF; 580 if (s->enable) { 581 s->sssr |= ((s->rx_level - 1) & 0xf) << 12; 582 if (s->rx_level >= SSCR1_RFT(s->sscr[1])) 583 s->sssr |= SSSR_RFS; 584 else 585 s->sssr &= ~SSSR_RFS; 586 if (s->rx_level) 587 s->sssr |= SSSR_RNE; 588 else 589 s->sssr &= ~SSSR_RNE; 590 /* TX FIFO is never filled, so it is always in underrun 591 condition if SSP is enabled */ 592 s->sssr |= SSSR_TFS; 593 s->sssr |= SSSR_TNF; 594 } 595 596 pxa2xx_ssp_int_update(s); 597 } 598 599 static uint64_t pxa2xx_ssp_read(void *opaque, hwaddr addr, 600 unsigned size) 601 { 602 PXA2xxSSPState *s = (PXA2xxSSPState *) opaque; 603 uint32_t retval; 604 605 switch (addr) { 606 case SSCR0: 607 return s->sscr[0]; 608 case SSCR1: 609 return s->sscr[1]; 610 case SSPSP: 611 return s->sspsp; 612 case SSTO: 613 return s->ssto; 614 case SSITR: 615 return s->ssitr; 616 case SSSR: 617 return s->sssr | s->ssitr; 618 case SSDR: 619 if (!s->enable) 620 return 0xffffffff; 621 if (s->rx_level < 1) { 622 printf("%s: SSP Rx Underrun\n", __FUNCTION__); 623 return 0xffffffff; 624 } 625 s->rx_level --; 626 retval = s->rx_fifo[s->rx_start ++]; 627 s->rx_start &= 0xf; 628 pxa2xx_ssp_fifo_update(s); 629 return retval; 630 case SSTSA: 631 return s->sstsa; 632 case SSRSA: 633 return s->ssrsa; 634 case SSTSS: 635 return 0; 636 case SSACD: 637 return s->ssacd; 638 default: 639 printf("%s: Bad register " REG_FMT "\n", __FUNCTION__, addr); 640 break; 641 } 642 return 0; 643 } 644 645 static void pxa2xx_ssp_write(void *opaque, hwaddr addr, 646 uint64_t value64, unsigned size) 647 { 648 PXA2xxSSPState *s = (PXA2xxSSPState *) opaque; 649 uint32_t value = value64; 650 651 switch (addr) { 652 case SSCR0: 653 s->sscr[0] = value & 0xc7ffffff; 654 s->enable = value & SSCR0_SSE; 655 if (value & SSCR0_MOD) 656 printf("%s: Attempt to use network mode\n", __FUNCTION__); 657 if (s->enable && SSCR0_DSS(value) < 4) 658 printf("%s: Wrong data size: %i bits\n", __FUNCTION__, 659 SSCR0_DSS(value)); 660 if (!(value & SSCR0_SSE)) { 661 s->sssr = 0; 662 s->ssitr = 0; 663 s->rx_level = 0; 664 } 665 pxa2xx_ssp_fifo_update(s); 666 break; 667 668 case SSCR1: 669 s->sscr[1] = value; 670 if (value & (SSCR1_LBM | SSCR1_EFWR)) 671 printf("%s: Attempt to use SSP test mode\n", __FUNCTION__); 672 pxa2xx_ssp_fifo_update(s); 673 break; 674 675 case SSPSP: 676 s->sspsp = value; 677 break; 678 679 case SSTO: 680 s->ssto = value; 681 break; 682 683 case SSITR: 684 s->ssitr = value & SSITR_INT; 685 pxa2xx_ssp_int_update(s); 686 break; 687 688 case SSSR: 689 s->sssr &= ~(value & SSSR_RW); 690 pxa2xx_ssp_int_update(s); 691 break; 692 693 case SSDR: 694 if (SSCR0_UWIRE(s->sscr[0])) { 695 if (s->sscr[1] & SSCR1_MWDS) 696 value &= 0xffff; 697 else 698 value &= 0xff; 699 } else 700 /* Note how 32bits overflow does no harm here */ 701 value &= (1 << SSCR0_DSS(s->sscr[0])) - 1; 702 703 /* Data goes from here to the Tx FIFO and is shifted out from 704 * there directly to the slave, no need to buffer it. 705 */ 706 if (s->enable) { 707 uint32_t readval; 708 readval = ssi_transfer(s->bus, value); 709 if (s->rx_level < 0x10) { 710 s->rx_fifo[(s->rx_start + s->rx_level ++) & 0xf] = readval; 711 } else { 712 s->sssr |= SSSR_ROR; 713 } 714 } 715 pxa2xx_ssp_fifo_update(s); 716 break; 717 718 case SSTSA: 719 s->sstsa = value; 720 break; 721 722 case SSRSA: 723 s->ssrsa = value; 724 break; 725 726 case SSACD: 727 s->ssacd = value; 728 break; 729 730 default: 731 printf("%s: Bad register " REG_FMT "\n", __FUNCTION__, addr); 732 break; 733 } 734 } 735 736 static const MemoryRegionOps pxa2xx_ssp_ops = { 737 .read = pxa2xx_ssp_read, 738 .write = pxa2xx_ssp_write, 739 .endianness = DEVICE_NATIVE_ENDIAN, 740 }; 741 742 static void pxa2xx_ssp_reset(DeviceState *d) 743 { 744 PXA2xxSSPState *s = PXA2XX_SSP(d); 745 746 s->enable = 0; 747 s->sscr[0] = s->sscr[1] = 0; 748 s->sspsp = 0; 749 s->ssto = 0; 750 s->ssitr = 0; 751 s->sssr = 0; 752 s->sstsa = 0; 753 s->ssrsa = 0; 754 s->ssacd = 0; 755 s->rx_start = s->rx_level = 0; 756 } 757 758 static int pxa2xx_ssp_init(SysBusDevice *sbd) 759 { 760 DeviceState *dev = DEVICE(sbd); 761 PXA2xxSSPState *s = PXA2XX_SSP(dev); 762 763 sysbus_init_irq(sbd, &s->irq); 764 765 memory_region_init_io(&s->iomem, OBJECT(s), &pxa2xx_ssp_ops, s, 766 "pxa2xx-ssp", 0x1000); 767 sysbus_init_mmio(sbd, &s->iomem); 768 769 s->bus = ssi_create_bus(dev, "ssi"); 770 return 0; 771 } 772 773 /* Real-Time Clock */ 774 #define RCNR 0x00 /* RTC Counter register */ 775 #define RTAR 0x04 /* RTC Alarm register */ 776 #define RTSR 0x08 /* RTC Status register */ 777 #define RTTR 0x0c /* RTC Timer Trim register */ 778 #define RDCR 0x10 /* RTC Day Counter register */ 779 #define RYCR 0x14 /* RTC Year Counter register */ 780 #define RDAR1 0x18 /* RTC Wristwatch Day Alarm register 1 */ 781 #define RYAR1 0x1c /* RTC Wristwatch Year Alarm register 1 */ 782 #define RDAR2 0x20 /* RTC Wristwatch Day Alarm register 2 */ 783 #define RYAR2 0x24 /* RTC Wristwatch Year Alarm register 2 */ 784 #define SWCR 0x28 /* RTC Stopwatch Counter register */ 785 #define SWAR1 0x2c /* RTC Stopwatch Alarm register 1 */ 786 #define SWAR2 0x30 /* RTC Stopwatch Alarm register 2 */ 787 #define RTCPICR 0x34 /* RTC Periodic Interrupt Counter register */ 788 #define PIAR 0x38 /* RTC Periodic Interrupt Alarm register */ 789 790 #define TYPE_PXA2XX_RTC "pxa2xx_rtc" 791 #define PXA2XX_RTC(obj) \ 792 OBJECT_CHECK(PXA2xxRTCState, (obj), TYPE_PXA2XX_RTC) 793 794 typedef struct { 795 /*< private >*/ 796 SysBusDevice parent_obj; 797 /*< public >*/ 798 799 MemoryRegion iomem; 800 uint32_t rttr; 801 uint32_t rtsr; 802 uint32_t rtar; 803 uint32_t rdar1; 804 uint32_t rdar2; 805 uint32_t ryar1; 806 uint32_t ryar2; 807 uint32_t swar1; 808 uint32_t swar2; 809 uint32_t piar; 810 uint32_t last_rcnr; 811 uint32_t last_rdcr; 812 uint32_t last_rycr; 813 uint32_t last_swcr; 814 uint32_t last_rtcpicr; 815 int64_t last_hz; 816 int64_t last_sw; 817 int64_t last_pi; 818 QEMUTimer *rtc_hz; 819 QEMUTimer *rtc_rdal1; 820 QEMUTimer *rtc_rdal2; 821 QEMUTimer *rtc_swal1; 822 QEMUTimer *rtc_swal2; 823 QEMUTimer *rtc_pi; 824 qemu_irq rtc_irq; 825 } PXA2xxRTCState; 826 827 static inline void pxa2xx_rtc_int_update(PXA2xxRTCState *s) 828 { 829 qemu_set_irq(s->rtc_irq, !!(s->rtsr & 0x2553)); 830 } 831 832 static void pxa2xx_rtc_hzupdate(PXA2xxRTCState *s) 833 { 834 int64_t rt = qemu_clock_get_ms(rtc_clock); 835 s->last_rcnr += ((rt - s->last_hz) << 15) / 836 (1000 * ((s->rttr & 0xffff) + 1)); 837 s->last_rdcr += ((rt - s->last_hz) << 15) / 838 (1000 * ((s->rttr & 0xffff) + 1)); 839 s->last_hz = rt; 840 } 841 842 static void pxa2xx_rtc_swupdate(PXA2xxRTCState *s) 843 { 844 int64_t rt = qemu_clock_get_ms(rtc_clock); 845 if (s->rtsr & (1 << 12)) 846 s->last_swcr += (rt - s->last_sw) / 10; 847 s->last_sw = rt; 848 } 849 850 static void pxa2xx_rtc_piupdate(PXA2xxRTCState *s) 851 { 852 int64_t rt = qemu_clock_get_ms(rtc_clock); 853 if (s->rtsr & (1 << 15)) 854 s->last_swcr += rt - s->last_pi; 855 s->last_pi = rt; 856 } 857 858 static inline void pxa2xx_rtc_alarm_update(PXA2xxRTCState *s, 859 uint32_t rtsr) 860 { 861 if ((rtsr & (1 << 2)) && !(rtsr & (1 << 0))) 862 timer_mod(s->rtc_hz, s->last_hz + 863 (((s->rtar - s->last_rcnr) * 1000 * 864 ((s->rttr & 0xffff) + 1)) >> 15)); 865 else 866 timer_del(s->rtc_hz); 867 868 if ((rtsr & (1 << 5)) && !(rtsr & (1 << 4))) 869 timer_mod(s->rtc_rdal1, s->last_hz + 870 (((s->rdar1 - s->last_rdcr) * 1000 * 871 ((s->rttr & 0xffff) + 1)) >> 15)); /* TODO: fixup */ 872 else 873 timer_del(s->rtc_rdal1); 874 875 if ((rtsr & (1 << 7)) && !(rtsr & (1 << 6))) 876 timer_mod(s->rtc_rdal2, s->last_hz + 877 (((s->rdar2 - s->last_rdcr) * 1000 * 878 ((s->rttr & 0xffff) + 1)) >> 15)); /* TODO: fixup */ 879 else 880 timer_del(s->rtc_rdal2); 881 882 if ((rtsr & 0x1200) == 0x1200 && !(rtsr & (1 << 8))) 883 timer_mod(s->rtc_swal1, s->last_sw + 884 (s->swar1 - s->last_swcr) * 10); /* TODO: fixup */ 885 else 886 timer_del(s->rtc_swal1); 887 888 if ((rtsr & 0x1800) == 0x1800 && !(rtsr & (1 << 10))) 889 timer_mod(s->rtc_swal2, s->last_sw + 890 (s->swar2 - s->last_swcr) * 10); /* TODO: fixup */ 891 else 892 timer_del(s->rtc_swal2); 893 894 if ((rtsr & 0xc000) == 0xc000 && !(rtsr & (1 << 13))) 895 timer_mod(s->rtc_pi, s->last_pi + 896 (s->piar & 0xffff) - s->last_rtcpicr); 897 else 898 timer_del(s->rtc_pi); 899 } 900 901 static inline void pxa2xx_rtc_hz_tick(void *opaque) 902 { 903 PXA2xxRTCState *s = (PXA2xxRTCState *) opaque; 904 s->rtsr |= (1 << 0); 905 pxa2xx_rtc_alarm_update(s, s->rtsr); 906 pxa2xx_rtc_int_update(s); 907 } 908 909 static inline void pxa2xx_rtc_rdal1_tick(void *opaque) 910 { 911 PXA2xxRTCState *s = (PXA2xxRTCState *) opaque; 912 s->rtsr |= (1 << 4); 913 pxa2xx_rtc_alarm_update(s, s->rtsr); 914 pxa2xx_rtc_int_update(s); 915 } 916 917 static inline void pxa2xx_rtc_rdal2_tick(void *opaque) 918 { 919 PXA2xxRTCState *s = (PXA2xxRTCState *) opaque; 920 s->rtsr |= (1 << 6); 921 pxa2xx_rtc_alarm_update(s, s->rtsr); 922 pxa2xx_rtc_int_update(s); 923 } 924 925 static inline void pxa2xx_rtc_swal1_tick(void *opaque) 926 { 927 PXA2xxRTCState *s = (PXA2xxRTCState *) opaque; 928 s->rtsr |= (1 << 8); 929 pxa2xx_rtc_alarm_update(s, s->rtsr); 930 pxa2xx_rtc_int_update(s); 931 } 932 933 static inline void pxa2xx_rtc_swal2_tick(void *opaque) 934 { 935 PXA2xxRTCState *s = (PXA2xxRTCState *) opaque; 936 s->rtsr |= (1 << 10); 937 pxa2xx_rtc_alarm_update(s, s->rtsr); 938 pxa2xx_rtc_int_update(s); 939 } 940 941 static inline void pxa2xx_rtc_pi_tick(void *opaque) 942 { 943 PXA2xxRTCState *s = (PXA2xxRTCState *) opaque; 944 s->rtsr |= (1 << 13); 945 pxa2xx_rtc_piupdate(s); 946 s->last_rtcpicr = 0; 947 pxa2xx_rtc_alarm_update(s, s->rtsr); 948 pxa2xx_rtc_int_update(s); 949 } 950 951 static uint64_t pxa2xx_rtc_read(void *opaque, hwaddr addr, 952 unsigned size) 953 { 954 PXA2xxRTCState *s = (PXA2xxRTCState *) opaque; 955 956 switch (addr) { 957 case RTTR: 958 return s->rttr; 959 case RTSR: 960 return s->rtsr; 961 case RTAR: 962 return s->rtar; 963 case RDAR1: 964 return s->rdar1; 965 case RDAR2: 966 return s->rdar2; 967 case RYAR1: 968 return s->ryar1; 969 case RYAR2: 970 return s->ryar2; 971 case SWAR1: 972 return s->swar1; 973 case SWAR2: 974 return s->swar2; 975 case PIAR: 976 return s->piar; 977 case RCNR: 978 return s->last_rcnr + 979 ((qemu_clock_get_ms(rtc_clock) - s->last_hz) << 15) / 980 (1000 * ((s->rttr & 0xffff) + 1)); 981 case RDCR: 982 return s->last_rdcr + 983 ((qemu_clock_get_ms(rtc_clock) - s->last_hz) << 15) / 984 (1000 * ((s->rttr & 0xffff) + 1)); 985 case RYCR: 986 return s->last_rycr; 987 case SWCR: 988 if (s->rtsr & (1 << 12)) 989 return s->last_swcr + 990 (qemu_clock_get_ms(rtc_clock) - s->last_sw) / 10; 991 else 992 return s->last_swcr; 993 default: 994 printf("%s: Bad register " REG_FMT "\n", __FUNCTION__, addr); 995 break; 996 } 997 return 0; 998 } 999 1000 static void pxa2xx_rtc_write(void *opaque, hwaddr addr, 1001 uint64_t value64, unsigned size) 1002 { 1003 PXA2xxRTCState *s = (PXA2xxRTCState *) opaque; 1004 uint32_t value = value64; 1005 1006 switch (addr) { 1007 case RTTR: 1008 if (!(s->rttr & (1U << 31))) { 1009 pxa2xx_rtc_hzupdate(s); 1010 s->rttr = value; 1011 pxa2xx_rtc_alarm_update(s, s->rtsr); 1012 } 1013 break; 1014 1015 case RTSR: 1016 if ((s->rtsr ^ value) & (1 << 15)) 1017 pxa2xx_rtc_piupdate(s); 1018 1019 if ((s->rtsr ^ value) & (1 << 12)) 1020 pxa2xx_rtc_swupdate(s); 1021 1022 if (((s->rtsr ^ value) & 0x4aac) | (value & ~0xdaac)) 1023 pxa2xx_rtc_alarm_update(s, value); 1024 1025 s->rtsr = (value & 0xdaac) | (s->rtsr & ~(value & ~0xdaac)); 1026 pxa2xx_rtc_int_update(s); 1027 break; 1028 1029 case RTAR: 1030 s->rtar = value; 1031 pxa2xx_rtc_alarm_update(s, s->rtsr); 1032 break; 1033 1034 case RDAR1: 1035 s->rdar1 = value; 1036 pxa2xx_rtc_alarm_update(s, s->rtsr); 1037 break; 1038 1039 case RDAR2: 1040 s->rdar2 = value; 1041 pxa2xx_rtc_alarm_update(s, s->rtsr); 1042 break; 1043 1044 case RYAR1: 1045 s->ryar1 = value; 1046 pxa2xx_rtc_alarm_update(s, s->rtsr); 1047 break; 1048 1049 case RYAR2: 1050 s->ryar2 = value; 1051 pxa2xx_rtc_alarm_update(s, s->rtsr); 1052 break; 1053 1054 case SWAR1: 1055 pxa2xx_rtc_swupdate(s); 1056 s->swar1 = value; 1057 s->last_swcr = 0; 1058 pxa2xx_rtc_alarm_update(s, s->rtsr); 1059 break; 1060 1061 case SWAR2: 1062 s->swar2 = value; 1063 pxa2xx_rtc_alarm_update(s, s->rtsr); 1064 break; 1065 1066 case PIAR: 1067 s->piar = value; 1068 pxa2xx_rtc_alarm_update(s, s->rtsr); 1069 break; 1070 1071 case RCNR: 1072 pxa2xx_rtc_hzupdate(s); 1073 s->last_rcnr = value; 1074 pxa2xx_rtc_alarm_update(s, s->rtsr); 1075 break; 1076 1077 case RDCR: 1078 pxa2xx_rtc_hzupdate(s); 1079 s->last_rdcr = value; 1080 pxa2xx_rtc_alarm_update(s, s->rtsr); 1081 break; 1082 1083 case RYCR: 1084 s->last_rycr = value; 1085 break; 1086 1087 case SWCR: 1088 pxa2xx_rtc_swupdate(s); 1089 s->last_swcr = value; 1090 pxa2xx_rtc_alarm_update(s, s->rtsr); 1091 break; 1092 1093 case RTCPICR: 1094 pxa2xx_rtc_piupdate(s); 1095 s->last_rtcpicr = value & 0xffff; 1096 pxa2xx_rtc_alarm_update(s, s->rtsr); 1097 break; 1098 1099 default: 1100 printf("%s: Bad register " REG_FMT "\n", __FUNCTION__, addr); 1101 } 1102 } 1103 1104 static const MemoryRegionOps pxa2xx_rtc_ops = { 1105 .read = pxa2xx_rtc_read, 1106 .write = pxa2xx_rtc_write, 1107 .endianness = DEVICE_NATIVE_ENDIAN, 1108 }; 1109 1110 static int pxa2xx_rtc_init(SysBusDevice *dev) 1111 { 1112 PXA2xxRTCState *s = PXA2XX_RTC(dev); 1113 struct tm tm; 1114 int wom; 1115 1116 s->rttr = 0x7fff; 1117 s->rtsr = 0; 1118 1119 qemu_get_timedate(&tm, 0); 1120 wom = ((tm.tm_mday - 1) / 7) + 1; 1121 1122 s->last_rcnr = (uint32_t) mktimegm(&tm); 1123 s->last_rdcr = (wom << 20) | ((tm.tm_wday + 1) << 17) | 1124 (tm.tm_hour << 12) | (tm.tm_min << 6) | tm.tm_sec; 1125 s->last_rycr = ((tm.tm_year + 1900) << 9) | 1126 ((tm.tm_mon + 1) << 5) | tm.tm_mday; 1127 s->last_swcr = (tm.tm_hour << 19) | 1128 (tm.tm_min << 13) | (tm.tm_sec << 7); 1129 s->last_rtcpicr = 0; 1130 s->last_hz = s->last_sw = s->last_pi = qemu_clock_get_ms(rtc_clock); 1131 1132 s->rtc_hz = timer_new_ms(rtc_clock, pxa2xx_rtc_hz_tick, s); 1133 s->rtc_rdal1 = timer_new_ms(rtc_clock, pxa2xx_rtc_rdal1_tick, s); 1134 s->rtc_rdal2 = timer_new_ms(rtc_clock, pxa2xx_rtc_rdal2_tick, s); 1135 s->rtc_swal1 = timer_new_ms(rtc_clock, pxa2xx_rtc_swal1_tick, s); 1136 s->rtc_swal2 = timer_new_ms(rtc_clock, pxa2xx_rtc_swal2_tick, s); 1137 s->rtc_pi = timer_new_ms(rtc_clock, pxa2xx_rtc_pi_tick, s); 1138 1139 sysbus_init_irq(dev, &s->rtc_irq); 1140 1141 memory_region_init_io(&s->iomem, OBJECT(s), &pxa2xx_rtc_ops, s, 1142 "pxa2xx-rtc", 0x10000); 1143 sysbus_init_mmio(dev, &s->iomem); 1144 1145 return 0; 1146 } 1147 1148 static void pxa2xx_rtc_pre_save(void *opaque) 1149 { 1150 PXA2xxRTCState *s = (PXA2xxRTCState *) opaque; 1151 1152 pxa2xx_rtc_hzupdate(s); 1153 pxa2xx_rtc_piupdate(s); 1154 pxa2xx_rtc_swupdate(s); 1155 } 1156 1157 static int pxa2xx_rtc_post_load(void *opaque, int version_id) 1158 { 1159 PXA2xxRTCState *s = (PXA2xxRTCState *) opaque; 1160 1161 pxa2xx_rtc_alarm_update(s, s->rtsr); 1162 1163 return 0; 1164 } 1165 1166 static const VMStateDescription vmstate_pxa2xx_rtc_regs = { 1167 .name = "pxa2xx_rtc", 1168 .version_id = 0, 1169 .minimum_version_id = 0, 1170 .pre_save = pxa2xx_rtc_pre_save, 1171 .post_load = pxa2xx_rtc_post_load, 1172 .fields = (VMStateField[]) { 1173 VMSTATE_UINT32(rttr, PXA2xxRTCState), 1174 VMSTATE_UINT32(rtsr, PXA2xxRTCState), 1175 VMSTATE_UINT32(rtar, PXA2xxRTCState), 1176 VMSTATE_UINT32(rdar1, PXA2xxRTCState), 1177 VMSTATE_UINT32(rdar2, PXA2xxRTCState), 1178 VMSTATE_UINT32(ryar1, PXA2xxRTCState), 1179 VMSTATE_UINT32(ryar2, PXA2xxRTCState), 1180 VMSTATE_UINT32(swar1, PXA2xxRTCState), 1181 VMSTATE_UINT32(swar2, PXA2xxRTCState), 1182 VMSTATE_UINT32(piar, PXA2xxRTCState), 1183 VMSTATE_UINT32(last_rcnr, PXA2xxRTCState), 1184 VMSTATE_UINT32(last_rdcr, PXA2xxRTCState), 1185 VMSTATE_UINT32(last_rycr, PXA2xxRTCState), 1186 VMSTATE_UINT32(last_swcr, PXA2xxRTCState), 1187 VMSTATE_UINT32(last_rtcpicr, PXA2xxRTCState), 1188 VMSTATE_INT64(last_hz, PXA2xxRTCState), 1189 VMSTATE_INT64(last_sw, PXA2xxRTCState), 1190 VMSTATE_INT64(last_pi, PXA2xxRTCState), 1191 VMSTATE_END_OF_LIST(), 1192 }, 1193 }; 1194 1195 static void pxa2xx_rtc_sysbus_class_init(ObjectClass *klass, void *data) 1196 { 1197 DeviceClass *dc = DEVICE_CLASS(klass); 1198 SysBusDeviceClass *k = SYS_BUS_DEVICE_CLASS(klass); 1199 1200 k->init = pxa2xx_rtc_init; 1201 dc->desc = "PXA2xx RTC Controller"; 1202 dc->vmsd = &vmstate_pxa2xx_rtc_regs; 1203 } 1204 1205 static const TypeInfo pxa2xx_rtc_sysbus_info = { 1206 .name = TYPE_PXA2XX_RTC, 1207 .parent = TYPE_SYS_BUS_DEVICE, 1208 .instance_size = sizeof(PXA2xxRTCState), 1209 .class_init = pxa2xx_rtc_sysbus_class_init, 1210 }; 1211 1212 /* I2C Interface */ 1213 1214 #define TYPE_PXA2XX_I2C_SLAVE "pxa2xx-i2c-slave" 1215 #define PXA2XX_I2C_SLAVE(obj) \ 1216 OBJECT_CHECK(PXA2xxI2CSlaveState, (obj), TYPE_PXA2XX_I2C_SLAVE) 1217 1218 typedef struct PXA2xxI2CSlaveState { 1219 I2CSlave parent_obj; 1220 1221 PXA2xxI2CState *host; 1222 } PXA2xxI2CSlaveState; 1223 1224 #define TYPE_PXA2XX_I2C "pxa2xx_i2c" 1225 #define PXA2XX_I2C(obj) \ 1226 OBJECT_CHECK(PXA2xxI2CState, (obj), TYPE_PXA2XX_I2C) 1227 1228 struct PXA2xxI2CState { 1229 /*< private >*/ 1230 SysBusDevice parent_obj; 1231 /*< public >*/ 1232 1233 MemoryRegion iomem; 1234 PXA2xxI2CSlaveState *slave; 1235 I2CBus *bus; 1236 qemu_irq irq; 1237 uint32_t offset; 1238 uint32_t region_size; 1239 1240 uint16_t control; 1241 uint16_t status; 1242 uint8_t ibmr; 1243 uint8_t data; 1244 }; 1245 1246 #define IBMR 0x80 /* I2C Bus Monitor register */ 1247 #define IDBR 0x88 /* I2C Data Buffer register */ 1248 #define ICR 0x90 /* I2C Control register */ 1249 #define ISR 0x98 /* I2C Status register */ 1250 #define ISAR 0xa0 /* I2C Slave Address register */ 1251 1252 static void pxa2xx_i2c_update(PXA2xxI2CState *s) 1253 { 1254 uint16_t level = 0; 1255 level |= s->status & s->control & (1 << 10); /* BED */ 1256 level |= (s->status & (1 << 7)) && (s->control & (1 << 9)); /* IRF */ 1257 level |= (s->status & (1 << 6)) && (s->control & (1 << 8)); /* ITE */ 1258 level |= s->status & (1 << 9); /* SAD */ 1259 qemu_set_irq(s->irq, !!level); 1260 } 1261 1262 /* These are only stubs now. */ 1263 static void pxa2xx_i2c_event(I2CSlave *i2c, enum i2c_event event) 1264 { 1265 PXA2xxI2CSlaveState *slave = PXA2XX_I2C_SLAVE(i2c); 1266 PXA2xxI2CState *s = slave->host; 1267 1268 switch (event) { 1269 case I2C_START_SEND: 1270 s->status |= (1 << 9); /* set SAD */ 1271 s->status &= ~(1 << 0); /* clear RWM */ 1272 break; 1273 case I2C_START_RECV: 1274 s->status |= (1 << 9); /* set SAD */ 1275 s->status |= 1 << 0; /* set RWM */ 1276 break; 1277 case I2C_FINISH: 1278 s->status |= (1 << 4); /* set SSD */ 1279 break; 1280 case I2C_NACK: 1281 s->status |= 1 << 1; /* set ACKNAK */ 1282 break; 1283 } 1284 pxa2xx_i2c_update(s); 1285 } 1286 1287 static int pxa2xx_i2c_rx(I2CSlave *i2c) 1288 { 1289 PXA2xxI2CSlaveState *slave = PXA2XX_I2C_SLAVE(i2c); 1290 PXA2xxI2CState *s = slave->host; 1291 1292 if ((s->control & (1 << 14)) || !(s->control & (1 << 6))) { 1293 return 0; 1294 } 1295 1296 if (s->status & (1 << 0)) { /* RWM */ 1297 s->status |= 1 << 6; /* set ITE */ 1298 } 1299 pxa2xx_i2c_update(s); 1300 1301 return s->data; 1302 } 1303 1304 static int pxa2xx_i2c_tx(I2CSlave *i2c, uint8_t data) 1305 { 1306 PXA2xxI2CSlaveState *slave = PXA2XX_I2C_SLAVE(i2c); 1307 PXA2xxI2CState *s = slave->host; 1308 1309 if ((s->control & (1 << 14)) || !(s->control & (1 << 6))) { 1310 return 1; 1311 } 1312 1313 if (!(s->status & (1 << 0))) { /* RWM */ 1314 s->status |= 1 << 7; /* set IRF */ 1315 s->data = data; 1316 } 1317 pxa2xx_i2c_update(s); 1318 1319 return 1; 1320 } 1321 1322 static uint64_t pxa2xx_i2c_read(void *opaque, hwaddr addr, 1323 unsigned size) 1324 { 1325 PXA2xxI2CState *s = (PXA2xxI2CState *) opaque; 1326 I2CSlave *slave; 1327 1328 addr -= s->offset; 1329 switch (addr) { 1330 case ICR: 1331 return s->control; 1332 case ISR: 1333 return s->status | (i2c_bus_busy(s->bus) << 2); 1334 case ISAR: 1335 slave = I2C_SLAVE(s->slave); 1336 return slave->address; 1337 case IDBR: 1338 return s->data; 1339 case IBMR: 1340 if (s->status & (1 << 2)) 1341 s->ibmr ^= 3; /* Fake SCL and SDA pin changes */ 1342 else 1343 s->ibmr = 0; 1344 return s->ibmr; 1345 default: 1346 printf("%s: Bad register " REG_FMT "\n", __FUNCTION__, addr); 1347 break; 1348 } 1349 return 0; 1350 } 1351 1352 static void pxa2xx_i2c_write(void *opaque, hwaddr addr, 1353 uint64_t value64, unsigned size) 1354 { 1355 PXA2xxI2CState *s = (PXA2xxI2CState *) opaque; 1356 uint32_t value = value64; 1357 int ack; 1358 1359 addr -= s->offset; 1360 switch (addr) { 1361 case ICR: 1362 s->control = value & 0xfff7; 1363 if ((value & (1 << 3)) && (value & (1 << 6))) { /* TB and IUE */ 1364 /* TODO: slave mode */ 1365 if (value & (1 << 0)) { /* START condition */ 1366 if (s->data & 1) 1367 s->status |= 1 << 0; /* set RWM */ 1368 else 1369 s->status &= ~(1 << 0); /* clear RWM */ 1370 ack = !i2c_start_transfer(s->bus, s->data >> 1, s->data & 1); 1371 } else { 1372 if (s->status & (1 << 0)) { /* RWM */ 1373 s->data = i2c_recv(s->bus); 1374 if (value & (1 << 2)) /* ACKNAK */ 1375 i2c_nack(s->bus); 1376 ack = 1; 1377 } else 1378 ack = !i2c_send(s->bus, s->data); 1379 } 1380 1381 if (value & (1 << 1)) /* STOP condition */ 1382 i2c_end_transfer(s->bus); 1383 1384 if (ack) { 1385 if (value & (1 << 0)) /* START condition */ 1386 s->status |= 1 << 6; /* set ITE */ 1387 else 1388 if (s->status & (1 << 0)) /* RWM */ 1389 s->status |= 1 << 7; /* set IRF */ 1390 else 1391 s->status |= 1 << 6; /* set ITE */ 1392 s->status &= ~(1 << 1); /* clear ACKNAK */ 1393 } else { 1394 s->status |= 1 << 6; /* set ITE */ 1395 s->status |= 1 << 10; /* set BED */ 1396 s->status |= 1 << 1; /* set ACKNAK */ 1397 } 1398 } 1399 if (!(value & (1 << 3)) && (value & (1 << 6))) /* !TB and IUE */ 1400 if (value & (1 << 4)) /* MA */ 1401 i2c_end_transfer(s->bus); 1402 pxa2xx_i2c_update(s); 1403 break; 1404 1405 case ISR: 1406 s->status &= ~(value & 0x07f0); 1407 pxa2xx_i2c_update(s); 1408 break; 1409 1410 case ISAR: 1411 i2c_set_slave_address(I2C_SLAVE(s->slave), value & 0x7f); 1412 break; 1413 1414 case IDBR: 1415 s->data = value & 0xff; 1416 break; 1417 1418 default: 1419 printf("%s: Bad register " REG_FMT "\n", __FUNCTION__, addr); 1420 } 1421 } 1422 1423 static const MemoryRegionOps pxa2xx_i2c_ops = { 1424 .read = pxa2xx_i2c_read, 1425 .write = pxa2xx_i2c_write, 1426 .endianness = DEVICE_NATIVE_ENDIAN, 1427 }; 1428 1429 static const VMStateDescription vmstate_pxa2xx_i2c_slave = { 1430 .name = "pxa2xx_i2c_slave", 1431 .version_id = 1, 1432 .minimum_version_id = 1, 1433 .fields = (VMStateField[]) { 1434 VMSTATE_I2C_SLAVE(parent_obj, PXA2xxI2CSlaveState), 1435 VMSTATE_END_OF_LIST() 1436 } 1437 }; 1438 1439 static const VMStateDescription vmstate_pxa2xx_i2c = { 1440 .name = "pxa2xx_i2c", 1441 .version_id = 1, 1442 .minimum_version_id = 1, 1443 .fields = (VMStateField[]) { 1444 VMSTATE_UINT16(control, PXA2xxI2CState), 1445 VMSTATE_UINT16(status, PXA2xxI2CState), 1446 VMSTATE_UINT8(ibmr, PXA2xxI2CState), 1447 VMSTATE_UINT8(data, PXA2xxI2CState), 1448 VMSTATE_STRUCT_POINTER(slave, PXA2xxI2CState, 1449 vmstate_pxa2xx_i2c_slave, PXA2xxI2CSlaveState), 1450 VMSTATE_END_OF_LIST() 1451 } 1452 }; 1453 1454 static int pxa2xx_i2c_slave_init(I2CSlave *i2c) 1455 { 1456 /* Nothing to do. */ 1457 return 0; 1458 } 1459 1460 static void pxa2xx_i2c_slave_class_init(ObjectClass *klass, void *data) 1461 { 1462 I2CSlaveClass *k = I2C_SLAVE_CLASS(klass); 1463 1464 k->init = pxa2xx_i2c_slave_init; 1465 k->event = pxa2xx_i2c_event; 1466 k->recv = pxa2xx_i2c_rx; 1467 k->send = pxa2xx_i2c_tx; 1468 } 1469 1470 static const TypeInfo pxa2xx_i2c_slave_info = { 1471 .name = TYPE_PXA2XX_I2C_SLAVE, 1472 .parent = TYPE_I2C_SLAVE, 1473 .instance_size = sizeof(PXA2xxI2CSlaveState), 1474 .class_init = pxa2xx_i2c_slave_class_init, 1475 }; 1476 1477 PXA2xxI2CState *pxa2xx_i2c_init(hwaddr base, 1478 qemu_irq irq, uint32_t region_size) 1479 { 1480 DeviceState *dev; 1481 SysBusDevice *i2c_dev; 1482 PXA2xxI2CState *s; 1483 I2CBus *i2cbus; 1484 1485 dev = qdev_create(NULL, TYPE_PXA2XX_I2C); 1486 qdev_prop_set_uint32(dev, "size", region_size + 1); 1487 qdev_prop_set_uint32(dev, "offset", base & region_size); 1488 qdev_init_nofail(dev); 1489 1490 i2c_dev = SYS_BUS_DEVICE(dev); 1491 sysbus_mmio_map(i2c_dev, 0, base & ~region_size); 1492 sysbus_connect_irq(i2c_dev, 0, irq); 1493 1494 s = PXA2XX_I2C(i2c_dev); 1495 /* FIXME: Should the slave device really be on a separate bus? */ 1496 i2cbus = i2c_init_bus(dev, "dummy"); 1497 dev = i2c_create_slave(i2cbus, TYPE_PXA2XX_I2C_SLAVE, 0); 1498 s->slave = PXA2XX_I2C_SLAVE(dev); 1499 s->slave->host = s; 1500 1501 return s; 1502 } 1503 1504 static int pxa2xx_i2c_initfn(SysBusDevice *sbd) 1505 { 1506 DeviceState *dev = DEVICE(sbd); 1507 PXA2xxI2CState *s = PXA2XX_I2C(dev); 1508 1509 s->bus = i2c_init_bus(dev, "i2c"); 1510 1511 memory_region_init_io(&s->iomem, OBJECT(s), &pxa2xx_i2c_ops, s, 1512 "pxa2xx-i2c", s->region_size); 1513 sysbus_init_mmio(sbd, &s->iomem); 1514 sysbus_init_irq(sbd, &s->irq); 1515 1516 return 0; 1517 } 1518 1519 I2CBus *pxa2xx_i2c_bus(PXA2xxI2CState *s) 1520 { 1521 return s->bus; 1522 } 1523 1524 static Property pxa2xx_i2c_properties[] = { 1525 DEFINE_PROP_UINT32("size", PXA2xxI2CState, region_size, 0x10000), 1526 DEFINE_PROP_UINT32("offset", PXA2xxI2CState, offset, 0), 1527 DEFINE_PROP_END_OF_LIST(), 1528 }; 1529 1530 static void pxa2xx_i2c_class_init(ObjectClass *klass, void *data) 1531 { 1532 DeviceClass *dc = DEVICE_CLASS(klass); 1533 SysBusDeviceClass *k = SYS_BUS_DEVICE_CLASS(klass); 1534 1535 k->init = pxa2xx_i2c_initfn; 1536 dc->desc = "PXA2xx I2C Bus Controller"; 1537 dc->vmsd = &vmstate_pxa2xx_i2c; 1538 dc->props = pxa2xx_i2c_properties; 1539 } 1540 1541 static const TypeInfo pxa2xx_i2c_info = { 1542 .name = TYPE_PXA2XX_I2C, 1543 .parent = TYPE_SYS_BUS_DEVICE, 1544 .instance_size = sizeof(PXA2xxI2CState), 1545 .class_init = pxa2xx_i2c_class_init, 1546 }; 1547 1548 /* PXA Inter-IC Sound Controller */ 1549 static void pxa2xx_i2s_reset(PXA2xxI2SState *i2s) 1550 { 1551 i2s->rx_len = 0; 1552 i2s->tx_len = 0; 1553 i2s->fifo_len = 0; 1554 i2s->clk = 0x1a; 1555 i2s->control[0] = 0x00; 1556 i2s->control[1] = 0x00; 1557 i2s->status = 0x00; 1558 i2s->mask = 0x00; 1559 } 1560 1561 #define SACR_TFTH(val) ((val >> 8) & 0xf) 1562 #define SACR_RFTH(val) ((val >> 12) & 0xf) 1563 #define SACR_DREC(val) (val & (1 << 3)) 1564 #define SACR_DPRL(val) (val & (1 << 4)) 1565 1566 static inline void pxa2xx_i2s_update(PXA2xxI2SState *i2s) 1567 { 1568 int rfs, tfs; 1569 rfs = SACR_RFTH(i2s->control[0]) < i2s->rx_len && 1570 !SACR_DREC(i2s->control[1]); 1571 tfs = (i2s->tx_len || i2s->fifo_len < SACR_TFTH(i2s->control[0])) && 1572 i2s->enable && !SACR_DPRL(i2s->control[1]); 1573 1574 qemu_set_irq(i2s->rx_dma, rfs); 1575 qemu_set_irq(i2s->tx_dma, tfs); 1576 1577 i2s->status &= 0xe0; 1578 if (i2s->fifo_len < 16 || !i2s->enable) 1579 i2s->status |= 1 << 0; /* TNF */ 1580 if (i2s->rx_len) 1581 i2s->status |= 1 << 1; /* RNE */ 1582 if (i2s->enable) 1583 i2s->status |= 1 << 2; /* BSY */ 1584 if (tfs) 1585 i2s->status |= 1 << 3; /* TFS */ 1586 if (rfs) 1587 i2s->status |= 1 << 4; /* RFS */ 1588 if (!(i2s->tx_len && i2s->enable)) 1589 i2s->status |= i2s->fifo_len << 8; /* TFL */ 1590 i2s->status |= MAX(i2s->rx_len, 0xf) << 12; /* RFL */ 1591 1592 qemu_set_irq(i2s->irq, i2s->status & i2s->mask); 1593 } 1594 1595 #define SACR0 0x00 /* Serial Audio Global Control register */ 1596 #define SACR1 0x04 /* Serial Audio I2S/MSB-Justified Control register */ 1597 #define SASR0 0x0c /* Serial Audio Interface and FIFO Status register */ 1598 #define SAIMR 0x14 /* Serial Audio Interrupt Mask register */ 1599 #define SAICR 0x18 /* Serial Audio Interrupt Clear register */ 1600 #define SADIV 0x60 /* Serial Audio Clock Divider register */ 1601 #define SADR 0x80 /* Serial Audio Data register */ 1602 1603 static uint64_t pxa2xx_i2s_read(void *opaque, hwaddr addr, 1604 unsigned size) 1605 { 1606 PXA2xxI2SState *s = (PXA2xxI2SState *) opaque; 1607 1608 switch (addr) { 1609 case SACR0: 1610 return s->control[0]; 1611 case SACR1: 1612 return s->control[1]; 1613 case SASR0: 1614 return s->status; 1615 case SAIMR: 1616 return s->mask; 1617 case SAICR: 1618 return 0; 1619 case SADIV: 1620 return s->clk; 1621 case SADR: 1622 if (s->rx_len > 0) { 1623 s->rx_len --; 1624 pxa2xx_i2s_update(s); 1625 return s->codec_in(s->opaque); 1626 } 1627 return 0; 1628 default: 1629 printf("%s: Bad register " REG_FMT "\n", __FUNCTION__, addr); 1630 break; 1631 } 1632 return 0; 1633 } 1634 1635 static void pxa2xx_i2s_write(void *opaque, hwaddr addr, 1636 uint64_t value, unsigned size) 1637 { 1638 PXA2xxI2SState *s = (PXA2xxI2SState *) opaque; 1639 uint32_t *sample; 1640 1641 switch (addr) { 1642 case SACR0: 1643 if (value & (1 << 3)) /* RST */ 1644 pxa2xx_i2s_reset(s); 1645 s->control[0] = value & 0xff3d; 1646 if (!s->enable && (value & 1) && s->tx_len) { /* ENB */ 1647 for (sample = s->fifo; s->fifo_len > 0; s->fifo_len --, sample ++) 1648 s->codec_out(s->opaque, *sample); 1649 s->status &= ~(1 << 7); /* I2SOFF */ 1650 } 1651 if (value & (1 << 4)) /* EFWR */ 1652 printf("%s: Attempt to use special function\n", __FUNCTION__); 1653 s->enable = (value & 9) == 1; /* ENB && !RST*/ 1654 pxa2xx_i2s_update(s); 1655 break; 1656 case SACR1: 1657 s->control[1] = value & 0x0039; 1658 if (value & (1 << 5)) /* ENLBF */ 1659 printf("%s: Attempt to use loopback function\n", __FUNCTION__); 1660 if (value & (1 << 4)) /* DPRL */ 1661 s->fifo_len = 0; 1662 pxa2xx_i2s_update(s); 1663 break; 1664 case SAIMR: 1665 s->mask = value & 0x0078; 1666 pxa2xx_i2s_update(s); 1667 break; 1668 case SAICR: 1669 s->status &= ~(value & (3 << 5)); 1670 pxa2xx_i2s_update(s); 1671 break; 1672 case SADIV: 1673 s->clk = value & 0x007f; 1674 break; 1675 case SADR: 1676 if (s->tx_len && s->enable) { 1677 s->tx_len --; 1678 pxa2xx_i2s_update(s); 1679 s->codec_out(s->opaque, value); 1680 } else if (s->fifo_len < 16) { 1681 s->fifo[s->fifo_len ++] = value; 1682 pxa2xx_i2s_update(s); 1683 } 1684 break; 1685 default: 1686 printf("%s: Bad register " REG_FMT "\n", __FUNCTION__, addr); 1687 } 1688 } 1689 1690 static const MemoryRegionOps pxa2xx_i2s_ops = { 1691 .read = pxa2xx_i2s_read, 1692 .write = pxa2xx_i2s_write, 1693 .endianness = DEVICE_NATIVE_ENDIAN, 1694 }; 1695 1696 static const VMStateDescription vmstate_pxa2xx_i2s = { 1697 .name = "pxa2xx_i2s", 1698 .version_id = 0, 1699 .minimum_version_id = 0, 1700 .fields = (VMStateField[]) { 1701 VMSTATE_UINT32_ARRAY(control, PXA2xxI2SState, 2), 1702 VMSTATE_UINT32(status, PXA2xxI2SState), 1703 VMSTATE_UINT32(mask, PXA2xxI2SState), 1704 VMSTATE_UINT32(clk, PXA2xxI2SState), 1705 VMSTATE_INT32(enable, PXA2xxI2SState), 1706 VMSTATE_INT32(rx_len, PXA2xxI2SState), 1707 VMSTATE_INT32(tx_len, PXA2xxI2SState), 1708 VMSTATE_INT32(fifo_len, PXA2xxI2SState), 1709 VMSTATE_END_OF_LIST() 1710 } 1711 }; 1712 1713 static void pxa2xx_i2s_data_req(void *opaque, int tx, int rx) 1714 { 1715 PXA2xxI2SState *s = (PXA2xxI2SState *) opaque; 1716 uint32_t *sample; 1717 1718 /* Signal FIFO errors */ 1719 if (s->enable && s->tx_len) 1720 s->status |= 1 << 5; /* TUR */ 1721 if (s->enable && s->rx_len) 1722 s->status |= 1 << 6; /* ROR */ 1723 1724 /* Should be tx - MIN(tx, s->fifo_len) but we don't really need to 1725 * handle the cases where it makes a difference. */ 1726 s->tx_len = tx - s->fifo_len; 1727 s->rx_len = rx; 1728 /* Note that is s->codec_out wasn't set, we wouldn't get called. */ 1729 if (s->enable) 1730 for (sample = s->fifo; s->fifo_len; s->fifo_len --, sample ++) 1731 s->codec_out(s->opaque, *sample); 1732 pxa2xx_i2s_update(s); 1733 } 1734 1735 static PXA2xxI2SState *pxa2xx_i2s_init(MemoryRegion *sysmem, 1736 hwaddr base, 1737 qemu_irq irq, qemu_irq rx_dma, qemu_irq tx_dma) 1738 { 1739 PXA2xxI2SState *s = g_new0(PXA2xxI2SState, 1); 1740 1741 s->irq = irq; 1742 s->rx_dma = rx_dma; 1743 s->tx_dma = tx_dma; 1744 s->data_req = pxa2xx_i2s_data_req; 1745 1746 pxa2xx_i2s_reset(s); 1747 1748 memory_region_init_io(&s->iomem, NULL, &pxa2xx_i2s_ops, s, 1749 "pxa2xx-i2s", 0x100000); 1750 memory_region_add_subregion(sysmem, base, &s->iomem); 1751 1752 vmstate_register(NULL, base, &vmstate_pxa2xx_i2s, s); 1753 1754 return s; 1755 } 1756 1757 /* PXA Fast Infra-red Communications Port */ 1758 #define TYPE_PXA2XX_FIR "pxa2xx-fir" 1759 #define PXA2XX_FIR(obj) OBJECT_CHECK(PXA2xxFIrState, (obj), TYPE_PXA2XX_FIR) 1760 1761 struct PXA2xxFIrState { 1762 /*< private >*/ 1763 SysBusDevice parent_obj; 1764 /*< public >*/ 1765 1766 MemoryRegion iomem; 1767 qemu_irq irq; 1768 qemu_irq rx_dma; 1769 qemu_irq tx_dma; 1770 uint32_t enable; 1771 CharDriverState *chr; 1772 1773 uint8_t control[3]; 1774 uint8_t status[2]; 1775 1776 uint32_t rx_len; 1777 uint32_t rx_start; 1778 uint8_t rx_fifo[64]; 1779 }; 1780 1781 static void pxa2xx_fir_reset(DeviceState *d) 1782 { 1783 PXA2xxFIrState *s = PXA2XX_FIR(d); 1784 1785 s->control[0] = 0x00; 1786 s->control[1] = 0x00; 1787 s->control[2] = 0x00; 1788 s->status[0] = 0x00; 1789 s->status[1] = 0x00; 1790 s->enable = 0; 1791 } 1792 1793 static inline void pxa2xx_fir_update(PXA2xxFIrState *s) 1794 { 1795 static const int tresh[4] = { 8, 16, 32, 0 }; 1796 int intr = 0; 1797 if ((s->control[0] & (1 << 4)) && /* RXE */ 1798 s->rx_len >= tresh[s->control[2] & 3]) /* TRIG */ 1799 s->status[0] |= 1 << 4; /* RFS */ 1800 else 1801 s->status[0] &= ~(1 << 4); /* RFS */ 1802 if (s->control[0] & (1 << 3)) /* TXE */ 1803 s->status[0] |= 1 << 3; /* TFS */ 1804 else 1805 s->status[0] &= ~(1 << 3); /* TFS */ 1806 if (s->rx_len) 1807 s->status[1] |= 1 << 2; /* RNE */ 1808 else 1809 s->status[1] &= ~(1 << 2); /* RNE */ 1810 if (s->control[0] & (1 << 4)) /* RXE */ 1811 s->status[1] |= 1 << 0; /* RSY */ 1812 else 1813 s->status[1] &= ~(1 << 0); /* RSY */ 1814 1815 intr |= (s->control[0] & (1 << 5)) && /* RIE */ 1816 (s->status[0] & (1 << 4)); /* RFS */ 1817 intr |= (s->control[0] & (1 << 6)) && /* TIE */ 1818 (s->status[0] & (1 << 3)); /* TFS */ 1819 intr |= (s->control[2] & (1 << 4)) && /* TRAIL */ 1820 (s->status[0] & (1 << 6)); /* EOC */ 1821 intr |= (s->control[0] & (1 << 2)) && /* TUS */ 1822 (s->status[0] & (1 << 1)); /* TUR */ 1823 intr |= s->status[0] & 0x25; /* FRE, RAB, EIF */ 1824 1825 qemu_set_irq(s->rx_dma, (s->status[0] >> 4) & 1); 1826 qemu_set_irq(s->tx_dma, (s->status[0] >> 3) & 1); 1827 1828 qemu_set_irq(s->irq, intr && s->enable); 1829 } 1830 1831 #define ICCR0 0x00 /* FICP Control register 0 */ 1832 #define ICCR1 0x04 /* FICP Control register 1 */ 1833 #define ICCR2 0x08 /* FICP Control register 2 */ 1834 #define ICDR 0x0c /* FICP Data register */ 1835 #define ICSR0 0x14 /* FICP Status register 0 */ 1836 #define ICSR1 0x18 /* FICP Status register 1 */ 1837 #define ICFOR 0x1c /* FICP FIFO Occupancy Status register */ 1838 1839 static uint64_t pxa2xx_fir_read(void *opaque, hwaddr addr, 1840 unsigned size) 1841 { 1842 PXA2xxFIrState *s = (PXA2xxFIrState *) opaque; 1843 uint8_t ret; 1844 1845 switch (addr) { 1846 case ICCR0: 1847 return s->control[0]; 1848 case ICCR1: 1849 return s->control[1]; 1850 case ICCR2: 1851 return s->control[2]; 1852 case ICDR: 1853 s->status[0] &= ~0x01; 1854 s->status[1] &= ~0x72; 1855 if (s->rx_len) { 1856 s->rx_len --; 1857 ret = s->rx_fifo[s->rx_start ++]; 1858 s->rx_start &= 63; 1859 pxa2xx_fir_update(s); 1860 return ret; 1861 } 1862 printf("%s: Rx FIFO underrun.\n", __FUNCTION__); 1863 break; 1864 case ICSR0: 1865 return s->status[0]; 1866 case ICSR1: 1867 return s->status[1] | (1 << 3); /* TNF */ 1868 case ICFOR: 1869 return s->rx_len; 1870 default: 1871 printf("%s: Bad register " REG_FMT "\n", __FUNCTION__, addr); 1872 break; 1873 } 1874 return 0; 1875 } 1876 1877 static void pxa2xx_fir_write(void *opaque, hwaddr addr, 1878 uint64_t value64, unsigned size) 1879 { 1880 PXA2xxFIrState *s = (PXA2xxFIrState *) opaque; 1881 uint32_t value = value64; 1882 uint8_t ch; 1883 1884 switch (addr) { 1885 case ICCR0: 1886 s->control[0] = value; 1887 if (!(value & (1 << 4))) /* RXE */ 1888 s->rx_len = s->rx_start = 0; 1889 if (!(value & (1 << 3))) { /* TXE */ 1890 /* Nop */ 1891 } 1892 s->enable = value & 1; /* ITR */ 1893 if (!s->enable) 1894 s->status[0] = 0; 1895 pxa2xx_fir_update(s); 1896 break; 1897 case ICCR1: 1898 s->control[1] = value; 1899 break; 1900 case ICCR2: 1901 s->control[2] = value & 0x3f; 1902 pxa2xx_fir_update(s); 1903 break; 1904 case ICDR: 1905 if (s->control[2] & (1 << 2)) /* TXP */ 1906 ch = value; 1907 else 1908 ch = ~value; 1909 if (s->chr && s->enable && (s->control[0] & (1 << 3))) /* TXE */ 1910 qemu_chr_fe_write(s->chr, &ch, 1); 1911 break; 1912 case ICSR0: 1913 s->status[0] &= ~(value & 0x66); 1914 pxa2xx_fir_update(s); 1915 break; 1916 case ICFOR: 1917 break; 1918 default: 1919 printf("%s: Bad register " REG_FMT "\n", __FUNCTION__, addr); 1920 } 1921 } 1922 1923 static const MemoryRegionOps pxa2xx_fir_ops = { 1924 .read = pxa2xx_fir_read, 1925 .write = pxa2xx_fir_write, 1926 .endianness = DEVICE_NATIVE_ENDIAN, 1927 }; 1928 1929 static int pxa2xx_fir_is_empty(void *opaque) 1930 { 1931 PXA2xxFIrState *s = (PXA2xxFIrState *) opaque; 1932 return (s->rx_len < 64); 1933 } 1934 1935 static void pxa2xx_fir_rx(void *opaque, const uint8_t *buf, int size) 1936 { 1937 PXA2xxFIrState *s = (PXA2xxFIrState *) opaque; 1938 if (!(s->control[0] & (1 << 4))) /* RXE */ 1939 return; 1940 1941 while (size --) { 1942 s->status[1] |= 1 << 4; /* EOF */ 1943 if (s->rx_len >= 64) { 1944 s->status[1] |= 1 << 6; /* ROR */ 1945 break; 1946 } 1947 1948 if (s->control[2] & (1 << 3)) /* RXP */ 1949 s->rx_fifo[(s->rx_start + s->rx_len ++) & 63] = *(buf ++); 1950 else 1951 s->rx_fifo[(s->rx_start + s->rx_len ++) & 63] = ~*(buf ++); 1952 } 1953 1954 pxa2xx_fir_update(s); 1955 } 1956 1957 static void pxa2xx_fir_event(void *opaque, int event) 1958 { 1959 } 1960 1961 static void pxa2xx_fir_instance_init(Object *obj) 1962 { 1963 PXA2xxFIrState *s = PXA2XX_FIR(obj); 1964 SysBusDevice *sbd = SYS_BUS_DEVICE(obj); 1965 1966 memory_region_init_io(&s->iomem, obj, &pxa2xx_fir_ops, s, 1967 "pxa2xx-fir", 0x1000); 1968 sysbus_init_mmio(sbd, &s->iomem); 1969 sysbus_init_irq(sbd, &s->irq); 1970 sysbus_init_irq(sbd, &s->rx_dma); 1971 sysbus_init_irq(sbd, &s->tx_dma); 1972 } 1973 1974 static void pxa2xx_fir_realize(DeviceState *dev, Error **errp) 1975 { 1976 PXA2xxFIrState *s = PXA2XX_FIR(dev); 1977 1978 if (s->chr) { 1979 qemu_chr_fe_claim_no_fail(s->chr); 1980 qemu_chr_add_handlers(s->chr, pxa2xx_fir_is_empty, 1981 pxa2xx_fir_rx, pxa2xx_fir_event, s); 1982 } 1983 } 1984 1985 static bool pxa2xx_fir_vmstate_validate(void *opaque, int version_id) 1986 { 1987 PXA2xxFIrState *s = opaque; 1988 1989 return s->rx_start < ARRAY_SIZE(s->rx_fifo); 1990 } 1991 1992 static const VMStateDescription pxa2xx_fir_vmsd = { 1993 .name = "pxa2xx-fir", 1994 .version_id = 1, 1995 .minimum_version_id = 1, 1996 .fields = (VMStateField[]) { 1997 VMSTATE_UINT32(enable, PXA2xxFIrState), 1998 VMSTATE_UINT8_ARRAY(control, PXA2xxFIrState, 3), 1999 VMSTATE_UINT8_ARRAY(status, PXA2xxFIrState, 2), 2000 VMSTATE_UINT32(rx_len, PXA2xxFIrState), 2001 VMSTATE_UINT32(rx_start, PXA2xxFIrState), 2002 VMSTATE_VALIDATE("fifo is 64 bytes", pxa2xx_fir_vmstate_validate), 2003 VMSTATE_UINT8_ARRAY(rx_fifo, PXA2xxFIrState, 64), 2004 VMSTATE_END_OF_LIST() 2005 } 2006 }; 2007 2008 static Property pxa2xx_fir_properties[] = { 2009 DEFINE_PROP_CHR("chardev", PXA2xxFIrState, chr), 2010 DEFINE_PROP_END_OF_LIST(), 2011 }; 2012 2013 static void pxa2xx_fir_class_init(ObjectClass *klass, void *data) 2014 { 2015 DeviceClass *dc = DEVICE_CLASS(klass); 2016 2017 dc->realize = pxa2xx_fir_realize; 2018 dc->vmsd = &pxa2xx_fir_vmsd; 2019 dc->props = pxa2xx_fir_properties; 2020 dc->reset = pxa2xx_fir_reset; 2021 } 2022 2023 static const TypeInfo pxa2xx_fir_info = { 2024 .name = TYPE_PXA2XX_FIR, 2025 .parent = TYPE_SYS_BUS_DEVICE, 2026 .instance_size = sizeof(PXA2xxFIrState), 2027 .class_init = pxa2xx_fir_class_init, 2028 .instance_init = pxa2xx_fir_instance_init, 2029 }; 2030 2031 static PXA2xxFIrState *pxa2xx_fir_init(MemoryRegion *sysmem, 2032 hwaddr base, 2033 qemu_irq irq, qemu_irq rx_dma, 2034 qemu_irq tx_dma, 2035 CharDriverState *chr) 2036 { 2037 DeviceState *dev; 2038 SysBusDevice *sbd; 2039 2040 dev = qdev_create(NULL, TYPE_PXA2XX_FIR); 2041 qdev_prop_set_chr(dev, "chardev", chr); 2042 qdev_init_nofail(dev); 2043 sbd = SYS_BUS_DEVICE(dev); 2044 sysbus_mmio_map(sbd, 0, base); 2045 sysbus_connect_irq(sbd, 0, irq); 2046 sysbus_connect_irq(sbd, 1, rx_dma); 2047 sysbus_connect_irq(sbd, 2, tx_dma); 2048 return PXA2XX_FIR(dev); 2049 } 2050 2051 static void pxa2xx_reset(void *opaque, int line, int level) 2052 { 2053 PXA2xxState *s = (PXA2xxState *) opaque; 2054 2055 if (level && (s->pm_regs[PCFR >> 2] & 0x10)) { /* GPR_EN */ 2056 cpu_reset(CPU(s->cpu)); 2057 /* TODO: reset peripherals */ 2058 } 2059 } 2060 2061 /* Initialise a PXA270 integrated chip (ARM based core). */ 2062 PXA2xxState *pxa270_init(MemoryRegion *address_space, 2063 unsigned int sdram_size, const char *revision) 2064 { 2065 PXA2xxState *s; 2066 int i; 2067 DriveInfo *dinfo; 2068 s = g_new0(PXA2xxState, 1); 2069 2070 if (revision && strncmp(revision, "pxa27", 5)) { 2071 fprintf(stderr, "Machine requires a PXA27x processor.\n"); 2072 exit(1); 2073 } 2074 if (!revision) 2075 revision = "pxa270"; 2076 2077 s->cpu = cpu_arm_init(revision); 2078 if (s->cpu == NULL) { 2079 fprintf(stderr, "Unable to find CPU definition\n"); 2080 exit(1); 2081 } 2082 s->reset = qemu_allocate_irq(pxa2xx_reset, s, 0); 2083 2084 /* SDRAM & Internal Memory Storage */ 2085 memory_region_init_ram(&s->sdram, NULL, "pxa270.sdram", sdram_size, 2086 &error_fatal); 2087 vmstate_register_ram_global(&s->sdram); 2088 memory_region_add_subregion(address_space, PXA2XX_SDRAM_BASE, &s->sdram); 2089 memory_region_init_ram(&s->internal, NULL, "pxa270.internal", 0x40000, 2090 &error_fatal); 2091 vmstate_register_ram_global(&s->internal); 2092 memory_region_add_subregion(address_space, PXA2XX_INTERNAL_BASE, 2093 &s->internal); 2094 2095 s->pic = pxa2xx_pic_init(0x40d00000, s->cpu); 2096 2097 s->dma = pxa27x_dma_init(0x40000000, 2098 qdev_get_gpio_in(s->pic, PXA2XX_PIC_DMA)); 2099 2100 sysbus_create_varargs("pxa27x-timer", 0x40a00000, 2101 qdev_get_gpio_in(s->pic, PXA2XX_PIC_OST_0 + 0), 2102 qdev_get_gpio_in(s->pic, PXA2XX_PIC_OST_0 + 1), 2103 qdev_get_gpio_in(s->pic, PXA2XX_PIC_OST_0 + 2), 2104 qdev_get_gpio_in(s->pic, PXA2XX_PIC_OST_0 + 3), 2105 qdev_get_gpio_in(s->pic, PXA27X_PIC_OST_4_11), 2106 NULL); 2107 2108 s->gpio = pxa2xx_gpio_init(0x40e00000, s->cpu, s->pic, 121); 2109 2110 dinfo = drive_get(IF_SD, 0, 0); 2111 if (!dinfo) { 2112 fprintf(stderr, "qemu: missing SecureDigital device\n"); 2113 exit(1); 2114 } 2115 s->mmc = pxa2xx_mmci_init(address_space, 0x41100000, 2116 blk_by_legacy_dinfo(dinfo), 2117 qdev_get_gpio_in(s->pic, PXA2XX_PIC_MMC), 2118 qdev_get_gpio_in(s->dma, PXA2XX_RX_RQ_MMCI), 2119 qdev_get_gpio_in(s->dma, PXA2XX_TX_RQ_MMCI)); 2120 2121 for (i = 0; pxa270_serial[i].io_base; i++) { 2122 if (serial_hds[i]) { 2123 serial_mm_init(address_space, pxa270_serial[i].io_base, 2, 2124 qdev_get_gpio_in(s->pic, pxa270_serial[i].irqn), 2125 14857000 / 16, serial_hds[i], 2126 DEVICE_NATIVE_ENDIAN); 2127 } else { 2128 break; 2129 } 2130 } 2131 if (serial_hds[i]) 2132 s->fir = pxa2xx_fir_init(address_space, 0x40800000, 2133 qdev_get_gpio_in(s->pic, PXA2XX_PIC_ICP), 2134 qdev_get_gpio_in(s->dma, PXA2XX_RX_RQ_ICP), 2135 qdev_get_gpio_in(s->dma, PXA2XX_TX_RQ_ICP), 2136 serial_hds[i]); 2137 2138 s->lcd = pxa2xx_lcdc_init(address_space, 0x44000000, 2139 qdev_get_gpio_in(s->pic, PXA2XX_PIC_LCD)); 2140 2141 s->cm_base = 0x41300000; 2142 s->cm_regs[CCCR >> 2] = 0x02000210; /* 416.0 MHz */ 2143 s->clkcfg = 0x00000009; /* Turbo mode active */ 2144 memory_region_init_io(&s->cm_iomem, NULL, &pxa2xx_cm_ops, s, "pxa2xx-cm", 0x1000); 2145 memory_region_add_subregion(address_space, s->cm_base, &s->cm_iomem); 2146 vmstate_register(NULL, 0, &vmstate_pxa2xx_cm, s); 2147 2148 pxa2xx_setup_cp14(s); 2149 2150 s->mm_base = 0x48000000; 2151 s->mm_regs[MDMRS >> 2] = 0x00020002; 2152 s->mm_regs[MDREFR >> 2] = 0x03ca4000; 2153 s->mm_regs[MECR >> 2] = 0x00000001; /* Two PC Card sockets */ 2154 memory_region_init_io(&s->mm_iomem, NULL, &pxa2xx_mm_ops, s, "pxa2xx-mm", 0x1000); 2155 memory_region_add_subregion(address_space, s->mm_base, &s->mm_iomem); 2156 vmstate_register(NULL, 0, &vmstate_pxa2xx_mm, s); 2157 2158 s->pm_base = 0x40f00000; 2159 memory_region_init_io(&s->pm_iomem, NULL, &pxa2xx_pm_ops, s, "pxa2xx-pm", 0x100); 2160 memory_region_add_subregion(address_space, s->pm_base, &s->pm_iomem); 2161 vmstate_register(NULL, 0, &vmstate_pxa2xx_pm, s); 2162 2163 for (i = 0; pxa27x_ssp[i].io_base; i ++); 2164 s->ssp = g_new0(SSIBus *, i); 2165 for (i = 0; pxa27x_ssp[i].io_base; i ++) { 2166 DeviceState *dev; 2167 dev = sysbus_create_simple(TYPE_PXA2XX_SSP, pxa27x_ssp[i].io_base, 2168 qdev_get_gpio_in(s->pic, pxa27x_ssp[i].irqn)); 2169 s->ssp[i] = (SSIBus *)qdev_get_child_bus(dev, "ssi"); 2170 } 2171 2172 if (usb_enabled()) { 2173 sysbus_create_simple("sysbus-ohci", 0x4c000000, 2174 qdev_get_gpio_in(s->pic, PXA2XX_PIC_USBH1)); 2175 } 2176 2177 s->pcmcia[0] = pxa2xx_pcmcia_init(address_space, 0x20000000); 2178 s->pcmcia[1] = pxa2xx_pcmcia_init(address_space, 0x30000000); 2179 2180 sysbus_create_simple(TYPE_PXA2XX_RTC, 0x40900000, 2181 qdev_get_gpio_in(s->pic, PXA2XX_PIC_RTCALARM)); 2182 2183 s->i2c[0] = pxa2xx_i2c_init(0x40301600, 2184 qdev_get_gpio_in(s->pic, PXA2XX_PIC_I2C), 0xffff); 2185 s->i2c[1] = pxa2xx_i2c_init(0x40f00100, 2186 qdev_get_gpio_in(s->pic, PXA2XX_PIC_PWRI2C), 0xff); 2187 2188 s->i2s = pxa2xx_i2s_init(address_space, 0x40400000, 2189 qdev_get_gpio_in(s->pic, PXA2XX_PIC_I2S), 2190 qdev_get_gpio_in(s->dma, PXA2XX_RX_RQ_I2S), 2191 qdev_get_gpio_in(s->dma, PXA2XX_TX_RQ_I2S)); 2192 2193 s->kp = pxa27x_keypad_init(address_space, 0x41500000, 2194 qdev_get_gpio_in(s->pic, PXA2XX_PIC_KEYPAD)); 2195 2196 /* GPIO1 resets the processor */ 2197 /* The handler can be overridden by board-specific code */ 2198 qdev_connect_gpio_out(s->gpio, 1, s->reset); 2199 return s; 2200 } 2201 2202 /* Initialise a PXA255 integrated chip (ARM based core). */ 2203 PXA2xxState *pxa255_init(MemoryRegion *address_space, unsigned int sdram_size) 2204 { 2205 PXA2xxState *s; 2206 int i; 2207 DriveInfo *dinfo; 2208 2209 s = g_new0(PXA2xxState, 1); 2210 2211 s->cpu = cpu_arm_init("pxa255"); 2212 if (s->cpu == NULL) { 2213 fprintf(stderr, "Unable to find CPU definition\n"); 2214 exit(1); 2215 } 2216 s->reset = qemu_allocate_irq(pxa2xx_reset, s, 0); 2217 2218 /* SDRAM & Internal Memory Storage */ 2219 memory_region_init_ram(&s->sdram, NULL, "pxa255.sdram", sdram_size, 2220 &error_fatal); 2221 vmstate_register_ram_global(&s->sdram); 2222 memory_region_add_subregion(address_space, PXA2XX_SDRAM_BASE, &s->sdram); 2223 memory_region_init_ram(&s->internal, NULL, "pxa255.internal", 2224 PXA2XX_INTERNAL_SIZE, &error_fatal); 2225 vmstate_register_ram_global(&s->internal); 2226 memory_region_add_subregion(address_space, PXA2XX_INTERNAL_BASE, 2227 &s->internal); 2228 2229 s->pic = pxa2xx_pic_init(0x40d00000, s->cpu); 2230 2231 s->dma = pxa255_dma_init(0x40000000, 2232 qdev_get_gpio_in(s->pic, PXA2XX_PIC_DMA)); 2233 2234 sysbus_create_varargs("pxa25x-timer", 0x40a00000, 2235 qdev_get_gpio_in(s->pic, PXA2XX_PIC_OST_0 + 0), 2236 qdev_get_gpio_in(s->pic, PXA2XX_PIC_OST_0 + 1), 2237 qdev_get_gpio_in(s->pic, PXA2XX_PIC_OST_0 + 2), 2238 qdev_get_gpio_in(s->pic, PXA2XX_PIC_OST_0 + 3), 2239 NULL); 2240 2241 s->gpio = pxa2xx_gpio_init(0x40e00000, s->cpu, s->pic, 85); 2242 2243 dinfo = drive_get(IF_SD, 0, 0); 2244 if (!dinfo) { 2245 fprintf(stderr, "qemu: missing SecureDigital device\n"); 2246 exit(1); 2247 } 2248 s->mmc = pxa2xx_mmci_init(address_space, 0x41100000, 2249 blk_by_legacy_dinfo(dinfo), 2250 qdev_get_gpio_in(s->pic, PXA2XX_PIC_MMC), 2251 qdev_get_gpio_in(s->dma, PXA2XX_RX_RQ_MMCI), 2252 qdev_get_gpio_in(s->dma, PXA2XX_TX_RQ_MMCI)); 2253 2254 for (i = 0; pxa255_serial[i].io_base; i++) { 2255 if (serial_hds[i]) { 2256 serial_mm_init(address_space, pxa255_serial[i].io_base, 2, 2257 qdev_get_gpio_in(s->pic, pxa255_serial[i].irqn), 2258 14745600 / 16, serial_hds[i], 2259 DEVICE_NATIVE_ENDIAN); 2260 } else { 2261 break; 2262 } 2263 } 2264 if (serial_hds[i]) 2265 s->fir = pxa2xx_fir_init(address_space, 0x40800000, 2266 qdev_get_gpio_in(s->pic, PXA2XX_PIC_ICP), 2267 qdev_get_gpio_in(s->dma, PXA2XX_RX_RQ_ICP), 2268 qdev_get_gpio_in(s->dma, PXA2XX_TX_RQ_ICP), 2269 serial_hds[i]); 2270 2271 s->lcd = pxa2xx_lcdc_init(address_space, 0x44000000, 2272 qdev_get_gpio_in(s->pic, PXA2XX_PIC_LCD)); 2273 2274 s->cm_base = 0x41300000; 2275 s->cm_regs[CCCR >> 2] = 0x02000210; /* 416.0 MHz */ 2276 s->clkcfg = 0x00000009; /* Turbo mode active */ 2277 memory_region_init_io(&s->cm_iomem, NULL, &pxa2xx_cm_ops, s, "pxa2xx-cm", 0x1000); 2278 memory_region_add_subregion(address_space, s->cm_base, &s->cm_iomem); 2279 vmstate_register(NULL, 0, &vmstate_pxa2xx_cm, s); 2280 2281 pxa2xx_setup_cp14(s); 2282 2283 s->mm_base = 0x48000000; 2284 s->mm_regs[MDMRS >> 2] = 0x00020002; 2285 s->mm_regs[MDREFR >> 2] = 0x03ca4000; 2286 s->mm_regs[MECR >> 2] = 0x00000001; /* Two PC Card sockets */ 2287 memory_region_init_io(&s->mm_iomem, NULL, &pxa2xx_mm_ops, s, "pxa2xx-mm", 0x1000); 2288 memory_region_add_subregion(address_space, s->mm_base, &s->mm_iomem); 2289 vmstate_register(NULL, 0, &vmstate_pxa2xx_mm, s); 2290 2291 s->pm_base = 0x40f00000; 2292 memory_region_init_io(&s->pm_iomem, NULL, &pxa2xx_pm_ops, s, "pxa2xx-pm", 0x100); 2293 memory_region_add_subregion(address_space, s->pm_base, &s->pm_iomem); 2294 vmstate_register(NULL, 0, &vmstate_pxa2xx_pm, s); 2295 2296 for (i = 0; pxa255_ssp[i].io_base; i ++); 2297 s->ssp = g_new0(SSIBus *, i); 2298 for (i = 0; pxa255_ssp[i].io_base; i ++) { 2299 DeviceState *dev; 2300 dev = sysbus_create_simple(TYPE_PXA2XX_SSP, pxa255_ssp[i].io_base, 2301 qdev_get_gpio_in(s->pic, pxa255_ssp[i].irqn)); 2302 s->ssp[i] = (SSIBus *)qdev_get_child_bus(dev, "ssi"); 2303 } 2304 2305 if (usb_enabled()) { 2306 sysbus_create_simple("sysbus-ohci", 0x4c000000, 2307 qdev_get_gpio_in(s->pic, PXA2XX_PIC_USBH1)); 2308 } 2309 2310 s->pcmcia[0] = pxa2xx_pcmcia_init(address_space, 0x20000000); 2311 s->pcmcia[1] = pxa2xx_pcmcia_init(address_space, 0x30000000); 2312 2313 sysbus_create_simple(TYPE_PXA2XX_RTC, 0x40900000, 2314 qdev_get_gpio_in(s->pic, PXA2XX_PIC_RTCALARM)); 2315 2316 s->i2c[0] = pxa2xx_i2c_init(0x40301600, 2317 qdev_get_gpio_in(s->pic, PXA2XX_PIC_I2C), 0xffff); 2318 s->i2c[1] = pxa2xx_i2c_init(0x40f00100, 2319 qdev_get_gpio_in(s->pic, PXA2XX_PIC_PWRI2C), 0xff); 2320 2321 s->i2s = pxa2xx_i2s_init(address_space, 0x40400000, 2322 qdev_get_gpio_in(s->pic, PXA2XX_PIC_I2S), 2323 qdev_get_gpio_in(s->dma, PXA2XX_RX_RQ_I2S), 2324 qdev_get_gpio_in(s->dma, PXA2XX_TX_RQ_I2S)); 2325 2326 /* GPIO1 resets the processor */ 2327 /* The handler can be overridden by board-specific code */ 2328 qdev_connect_gpio_out(s->gpio, 1, s->reset); 2329 return s; 2330 } 2331 2332 static void pxa2xx_ssp_class_init(ObjectClass *klass, void *data) 2333 { 2334 SysBusDeviceClass *sdc = SYS_BUS_DEVICE_CLASS(klass); 2335 DeviceClass *dc = DEVICE_CLASS(klass); 2336 2337 sdc->init = pxa2xx_ssp_init; 2338 dc->reset = pxa2xx_ssp_reset; 2339 dc->vmsd = &vmstate_pxa2xx_ssp; 2340 } 2341 2342 static const TypeInfo pxa2xx_ssp_info = { 2343 .name = TYPE_PXA2XX_SSP, 2344 .parent = TYPE_SYS_BUS_DEVICE, 2345 .instance_size = sizeof(PXA2xxSSPState), 2346 .class_init = pxa2xx_ssp_class_init, 2347 }; 2348 2349 static void pxa2xx_register_types(void) 2350 { 2351 type_register_static(&pxa2xx_i2c_slave_info); 2352 type_register_static(&pxa2xx_ssp_info); 2353 type_register_static(&pxa2xx_i2c_info); 2354 type_register_static(&pxa2xx_rtc_sysbus_info); 2355 type_register_static(&pxa2xx_fir_info); 2356 } 2357 2358 type_init(pxa2xx_register_types) 2359