1 /* 2 * Intel XScale PXA255/270 processor support. 3 * 4 * Copyright (c) 2006 Openedhand Ltd. 5 * Written by Andrzej Zaborowski <balrog@zabor.org> 6 * 7 * This code is licensed under the GPL. 8 */ 9 10 #include "qemu/osdep.h" 11 #include "qemu-common.h" 12 #include "qemu/error-report.h" 13 #include "qemu/module.h" 14 #include "qapi/error.h" 15 #include "cpu.h" 16 #include "hw/sysbus.h" 17 #include "migration/vmstate.h" 18 #include "hw/arm/pxa.h" 19 #include "sysemu/sysemu.h" 20 #include "hw/char/serial.h" 21 #include "hw/i2c/i2c.h" 22 #include "hw/irq.h" 23 #include "hw/qdev-properties.h" 24 #include "hw/ssi/ssi.h" 25 #include "hw/sd/sd.h" 26 #include "chardev/char-fe.h" 27 #include "sysemu/blockdev.h" 28 #include "sysemu/qtest.h" 29 #include "qemu/cutils.h" 30 #include "qemu/log.h" 31 #include "qom/object.h" 32 33 static struct { 34 hwaddr io_base; 35 int irqn; 36 } pxa255_serial[] = { 37 { 0x40100000, PXA2XX_PIC_FFUART }, 38 { 0x40200000, PXA2XX_PIC_BTUART }, 39 { 0x40700000, PXA2XX_PIC_STUART }, 40 { 0x41600000, PXA25X_PIC_HWUART }, 41 { 0, 0 } 42 }, pxa270_serial[] = { 43 { 0x40100000, PXA2XX_PIC_FFUART }, 44 { 0x40200000, PXA2XX_PIC_BTUART }, 45 { 0x40700000, PXA2XX_PIC_STUART }, 46 { 0, 0 } 47 }; 48 49 typedef struct PXASSPDef { 50 hwaddr io_base; 51 int irqn; 52 } PXASSPDef; 53 54 #if 0 55 static PXASSPDef pxa250_ssp[] = { 56 { 0x41000000, PXA2XX_PIC_SSP }, 57 { 0, 0 } 58 }; 59 #endif 60 61 static PXASSPDef pxa255_ssp[] = { 62 { 0x41000000, PXA2XX_PIC_SSP }, 63 { 0x41400000, PXA25X_PIC_NSSP }, 64 { 0, 0 } 65 }; 66 67 #if 0 68 static PXASSPDef pxa26x_ssp[] = { 69 { 0x41000000, PXA2XX_PIC_SSP }, 70 { 0x41400000, PXA25X_PIC_NSSP }, 71 { 0x41500000, PXA26X_PIC_ASSP }, 72 { 0, 0 } 73 }; 74 #endif 75 76 static PXASSPDef pxa27x_ssp[] = { 77 { 0x41000000, PXA2XX_PIC_SSP }, 78 { 0x41700000, PXA27X_PIC_SSP2 }, 79 { 0x41900000, PXA2XX_PIC_SSP3 }, 80 { 0, 0 } 81 }; 82 83 #define PMCR 0x00 /* Power Manager Control register */ 84 #define PSSR 0x04 /* Power Manager Sleep Status register */ 85 #define PSPR 0x08 /* Power Manager Scratch-Pad register */ 86 #define PWER 0x0c /* Power Manager Wake-Up Enable register */ 87 #define PRER 0x10 /* Power Manager Rising-Edge Detect Enable register */ 88 #define PFER 0x14 /* Power Manager Falling-Edge Detect Enable register */ 89 #define PEDR 0x18 /* Power Manager Edge-Detect Status register */ 90 #define PCFR 0x1c /* Power Manager General Configuration register */ 91 #define PGSR0 0x20 /* Power Manager GPIO Sleep-State register 0 */ 92 #define PGSR1 0x24 /* Power Manager GPIO Sleep-State register 1 */ 93 #define PGSR2 0x28 /* Power Manager GPIO Sleep-State register 2 */ 94 #define PGSR3 0x2c /* Power Manager GPIO Sleep-State register 3 */ 95 #define RCSR 0x30 /* Reset Controller Status register */ 96 #define PSLR 0x34 /* Power Manager Sleep Configuration register */ 97 #define PTSR 0x38 /* Power Manager Standby Configuration register */ 98 #define PVCR 0x40 /* Power Manager Voltage Change Control register */ 99 #define PUCR 0x4c /* Power Manager USIM Card Control/Status register */ 100 #define PKWR 0x50 /* Power Manager Keyboard Wake-Up Enable register */ 101 #define PKSR 0x54 /* Power Manager Keyboard Level-Detect Status */ 102 #define PCMD0 0x80 /* Power Manager I2C Command register File 0 */ 103 #define PCMD31 0xfc /* Power Manager I2C Command register File 31 */ 104 105 static uint64_t pxa2xx_pm_read(void *opaque, hwaddr addr, 106 unsigned size) 107 { 108 PXA2xxState *s = (PXA2xxState *) opaque; 109 110 switch (addr) { 111 case PMCR ... PCMD31: 112 if (addr & 3) 113 goto fail; 114 115 return s->pm_regs[addr >> 2]; 116 default: 117 fail: 118 qemu_log_mask(LOG_GUEST_ERROR, 119 "%s: Bad read offset 0x%"HWADDR_PRIx"\n", 120 __func__, addr); 121 break; 122 } 123 return 0; 124 } 125 126 static void pxa2xx_pm_write(void *opaque, hwaddr addr, 127 uint64_t value, unsigned size) 128 { 129 PXA2xxState *s = (PXA2xxState *) opaque; 130 131 switch (addr) { 132 case PMCR: 133 /* Clear the write-one-to-clear bits... */ 134 s->pm_regs[addr >> 2] &= ~(value & 0x2a); 135 /* ...and set the plain r/w bits */ 136 s->pm_regs[addr >> 2] &= ~0x15; 137 s->pm_regs[addr >> 2] |= value & 0x15; 138 break; 139 140 case PSSR: /* Read-clean registers */ 141 case RCSR: 142 case PKSR: 143 s->pm_regs[addr >> 2] &= ~value; 144 break; 145 146 default: /* Read-write registers */ 147 if (!(addr & 3)) { 148 s->pm_regs[addr >> 2] = value; 149 break; 150 } 151 qemu_log_mask(LOG_GUEST_ERROR, 152 "%s: Bad write offset 0x%"HWADDR_PRIx"\n", 153 __func__, addr); 154 break; 155 } 156 } 157 158 static const MemoryRegionOps pxa2xx_pm_ops = { 159 .read = pxa2xx_pm_read, 160 .write = pxa2xx_pm_write, 161 .endianness = DEVICE_NATIVE_ENDIAN, 162 }; 163 164 static const VMStateDescription vmstate_pxa2xx_pm = { 165 .name = "pxa2xx_pm", 166 .version_id = 0, 167 .minimum_version_id = 0, 168 .fields = (VMStateField[]) { 169 VMSTATE_UINT32_ARRAY(pm_regs, PXA2xxState, 0x40), 170 VMSTATE_END_OF_LIST() 171 } 172 }; 173 174 #define CCCR 0x00 /* Core Clock Configuration register */ 175 #define CKEN 0x04 /* Clock Enable register */ 176 #define OSCC 0x08 /* Oscillator Configuration register */ 177 #define CCSR 0x0c /* Core Clock Status register */ 178 179 static uint64_t pxa2xx_cm_read(void *opaque, hwaddr addr, 180 unsigned size) 181 { 182 PXA2xxState *s = (PXA2xxState *) opaque; 183 184 switch (addr) { 185 case CCCR: 186 case CKEN: 187 case OSCC: 188 return s->cm_regs[addr >> 2]; 189 190 case CCSR: 191 return s->cm_regs[CCCR >> 2] | (3 << 28); 192 193 default: 194 qemu_log_mask(LOG_GUEST_ERROR, 195 "%s: Bad read offset 0x%"HWADDR_PRIx"\n", 196 __func__, addr); 197 break; 198 } 199 return 0; 200 } 201 202 static void pxa2xx_cm_write(void *opaque, hwaddr addr, 203 uint64_t value, unsigned size) 204 { 205 PXA2xxState *s = (PXA2xxState *) opaque; 206 207 switch (addr) { 208 case CCCR: 209 case CKEN: 210 s->cm_regs[addr >> 2] = value; 211 break; 212 213 case OSCC: 214 s->cm_regs[addr >> 2] &= ~0x6c; 215 s->cm_regs[addr >> 2] |= value & 0x6e; 216 if ((value >> 1) & 1) /* OON */ 217 s->cm_regs[addr >> 2] |= 1 << 0; /* Oscillator is now stable */ 218 break; 219 220 default: 221 qemu_log_mask(LOG_GUEST_ERROR, 222 "%s: Bad write offset 0x%"HWADDR_PRIx"\n", 223 __func__, addr); 224 break; 225 } 226 } 227 228 static const MemoryRegionOps pxa2xx_cm_ops = { 229 .read = pxa2xx_cm_read, 230 .write = pxa2xx_cm_write, 231 .endianness = DEVICE_NATIVE_ENDIAN, 232 }; 233 234 static const VMStateDescription vmstate_pxa2xx_cm = { 235 .name = "pxa2xx_cm", 236 .version_id = 0, 237 .minimum_version_id = 0, 238 .fields = (VMStateField[]) { 239 VMSTATE_UINT32_ARRAY(cm_regs, PXA2xxState, 4), 240 VMSTATE_UINT32(clkcfg, PXA2xxState), 241 VMSTATE_UINT32(pmnc, PXA2xxState), 242 VMSTATE_END_OF_LIST() 243 } 244 }; 245 246 static uint64_t pxa2xx_clkcfg_read(CPUARMState *env, const ARMCPRegInfo *ri) 247 { 248 PXA2xxState *s = (PXA2xxState *)ri->opaque; 249 return s->clkcfg; 250 } 251 252 static void pxa2xx_clkcfg_write(CPUARMState *env, const ARMCPRegInfo *ri, 253 uint64_t value) 254 { 255 PXA2xxState *s = (PXA2xxState *)ri->opaque; 256 s->clkcfg = value & 0xf; 257 if (value & 2) { 258 printf("%s: CPU frequency change attempt\n", __func__); 259 } 260 } 261 262 static void pxa2xx_pwrmode_write(CPUARMState *env, const ARMCPRegInfo *ri, 263 uint64_t value) 264 { 265 PXA2xxState *s = (PXA2xxState *)ri->opaque; 266 static const char *pwrmode[8] = { 267 "Normal", "Idle", "Deep-idle", "Standby", 268 "Sleep", "reserved (!)", "reserved (!)", "Deep-sleep", 269 }; 270 271 if (value & 8) { 272 printf("%s: CPU voltage change attempt\n", __func__); 273 } 274 switch (value & 7) { 275 case 0: 276 /* Do nothing */ 277 break; 278 279 case 1: 280 /* Idle */ 281 if (!(s->cm_regs[CCCR >> 2] & (1U << 31))) { /* CPDIS */ 282 cpu_interrupt(CPU(s->cpu), CPU_INTERRUPT_HALT); 283 break; 284 } 285 /* Fall through. */ 286 287 case 2: 288 /* Deep-Idle */ 289 cpu_interrupt(CPU(s->cpu), CPU_INTERRUPT_HALT); 290 s->pm_regs[RCSR >> 2] |= 0x8; /* Set GPR */ 291 goto message; 292 293 case 3: 294 s->cpu->env.uncached_cpsr = ARM_CPU_MODE_SVC; 295 s->cpu->env.daif = PSTATE_A | PSTATE_F | PSTATE_I; 296 s->cpu->env.cp15.sctlr_ns = 0; 297 s->cpu->env.cp15.cpacr_el1 = 0; 298 s->cpu->env.cp15.ttbr0_el[1] = 0; 299 s->cpu->env.cp15.dacr_ns = 0; 300 s->pm_regs[PSSR >> 2] |= 0x8; /* Set STS */ 301 s->pm_regs[RCSR >> 2] |= 0x8; /* Set GPR */ 302 303 /* 304 * The scratch-pad register is almost universally used 305 * for storing the return address on suspend. For the 306 * lack of a resuming bootloader, perform a jump 307 * directly to that address. 308 */ 309 memset(s->cpu->env.regs, 0, 4 * 15); 310 s->cpu->env.regs[15] = s->pm_regs[PSPR >> 2]; 311 312 #if 0 313 buffer = 0xe59ff000; /* ldr pc, [pc, #0] */ 314 cpu_physical_memory_write(0, &buffer, 4); 315 buffer = s->pm_regs[PSPR >> 2]; 316 cpu_physical_memory_write(8, &buffer, 4); 317 #endif 318 319 /* Suspend */ 320 cpu_interrupt(current_cpu, CPU_INTERRUPT_HALT); 321 322 goto message; 323 324 default: 325 message: 326 printf("%s: machine entered %s mode\n", __func__, 327 pwrmode[value & 7]); 328 } 329 } 330 331 static uint64_t pxa2xx_cppmnc_read(CPUARMState *env, const ARMCPRegInfo *ri) 332 { 333 PXA2xxState *s = (PXA2xxState *)ri->opaque; 334 return s->pmnc; 335 } 336 337 static void pxa2xx_cppmnc_write(CPUARMState *env, const ARMCPRegInfo *ri, 338 uint64_t value) 339 { 340 PXA2xxState *s = (PXA2xxState *)ri->opaque; 341 s->pmnc = value; 342 } 343 344 static uint64_t pxa2xx_cpccnt_read(CPUARMState *env, const ARMCPRegInfo *ri) 345 { 346 PXA2xxState *s = (PXA2xxState *)ri->opaque; 347 if (s->pmnc & 1) { 348 return qemu_clock_get_ns(QEMU_CLOCK_VIRTUAL); 349 } else { 350 return 0; 351 } 352 } 353 354 static const ARMCPRegInfo pxa_cp_reginfo[] = { 355 /* cp14 crm==1: perf registers */ 356 { .name = "CPPMNC", .cp = 14, .crn = 0, .crm = 1, .opc1 = 0, .opc2 = 0, 357 .access = PL1_RW, .type = ARM_CP_IO, 358 .readfn = pxa2xx_cppmnc_read, .writefn = pxa2xx_cppmnc_write }, 359 { .name = "CPCCNT", .cp = 14, .crn = 1, .crm = 1, .opc1 = 0, .opc2 = 0, 360 .access = PL1_RW, .type = ARM_CP_IO, 361 .readfn = pxa2xx_cpccnt_read, .writefn = arm_cp_write_ignore }, 362 { .name = "CPINTEN", .cp = 14, .crn = 4, .crm = 1, .opc1 = 0, .opc2 = 0, 363 .access = PL1_RW, .type = ARM_CP_CONST, .resetvalue = 0 }, 364 { .name = "CPFLAG", .cp = 14, .crn = 5, .crm = 1, .opc1 = 0, .opc2 = 0, 365 .access = PL1_RW, .type = ARM_CP_CONST, .resetvalue = 0 }, 366 { .name = "CPEVTSEL", .cp = 14, .crn = 8, .crm = 1, .opc1 = 0, .opc2 = 0, 367 .access = PL1_RW, .type = ARM_CP_CONST, .resetvalue = 0 }, 368 /* cp14 crm==2: performance count registers */ 369 { .name = "CPPMN0", .cp = 14, .crn = 0, .crm = 2, .opc1 = 0, .opc2 = 0, 370 .access = PL1_RW, .type = ARM_CP_CONST, .resetvalue = 0 }, 371 { .name = "CPPMN1", .cp = 14, .crn = 1, .crm = 2, .opc1 = 0, .opc2 = 0, 372 .access = PL1_RW, .type = ARM_CP_CONST, .resetvalue = 0 }, 373 { .name = "CPPMN2", .cp = 14, .crn = 2, .crm = 2, .opc1 = 0, .opc2 = 0, 374 .access = PL1_RW, .type = ARM_CP_CONST, .resetvalue = 0 }, 375 { .name = "CPPMN3", .cp = 14, .crn = 2, .crm = 3, .opc1 = 0, .opc2 = 0, 376 .access = PL1_RW, .type = ARM_CP_CONST, .resetvalue = 0 }, 377 /* cp14 crn==6: CLKCFG */ 378 { .name = "CLKCFG", .cp = 14, .crn = 6, .crm = 0, .opc1 = 0, .opc2 = 0, 379 .access = PL1_RW, .type = ARM_CP_IO, 380 .readfn = pxa2xx_clkcfg_read, .writefn = pxa2xx_clkcfg_write }, 381 /* cp14 crn==7: PWRMODE */ 382 { .name = "PWRMODE", .cp = 14, .crn = 7, .crm = 0, .opc1 = 0, .opc2 = 0, 383 .access = PL1_RW, .type = ARM_CP_IO, 384 .readfn = arm_cp_read_zero, .writefn = pxa2xx_pwrmode_write }, 385 REGINFO_SENTINEL 386 }; 387 388 static void pxa2xx_setup_cp14(PXA2xxState *s) 389 { 390 define_arm_cp_regs_with_opaque(s->cpu, pxa_cp_reginfo, s); 391 } 392 393 #define MDCNFG 0x00 /* SDRAM Configuration register */ 394 #define MDREFR 0x04 /* SDRAM Refresh Control register */ 395 #define MSC0 0x08 /* Static Memory Control register 0 */ 396 #define MSC1 0x0c /* Static Memory Control register 1 */ 397 #define MSC2 0x10 /* Static Memory Control register 2 */ 398 #define MECR 0x14 /* Expansion Memory Bus Config register */ 399 #define SXCNFG 0x1c /* Synchronous Static Memory Config register */ 400 #define MCMEM0 0x28 /* PC Card Memory Socket 0 Timing register */ 401 #define MCMEM1 0x2c /* PC Card Memory Socket 1 Timing register */ 402 #define MCATT0 0x30 /* PC Card Attribute Socket 0 register */ 403 #define MCATT1 0x34 /* PC Card Attribute Socket 1 register */ 404 #define MCIO0 0x38 /* PC Card I/O Socket 0 Timing register */ 405 #define MCIO1 0x3c /* PC Card I/O Socket 1 Timing register */ 406 #define MDMRS 0x40 /* SDRAM Mode Register Set Config register */ 407 #define BOOT_DEF 0x44 /* Boot-time Default Configuration register */ 408 #define ARB_CNTL 0x48 /* Arbiter Control register */ 409 #define BSCNTR0 0x4c /* Memory Buffer Strength Control register 0 */ 410 #define BSCNTR1 0x50 /* Memory Buffer Strength Control register 1 */ 411 #define LCDBSCNTR 0x54 /* LCD Buffer Strength Control register */ 412 #define MDMRSLP 0x58 /* Low Power SDRAM Mode Set Config register */ 413 #define BSCNTR2 0x5c /* Memory Buffer Strength Control register 2 */ 414 #define BSCNTR3 0x60 /* Memory Buffer Strength Control register 3 */ 415 #define SA1110 0x64 /* SA-1110 Memory Compatibility register */ 416 417 static uint64_t pxa2xx_mm_read(void *opaque, hwaddr addr, 418 unsigned size) 419 { 420 PXA2xxState *s = (PXA2xxState *) opaque; 421 422 switch (addr) { 423 case MDCNFG ... SA1110: 424 if ((addr & 3) == 0) 425 return s->mm_regs[addr >> 2]; 426 /* fall through */ 427 default: 428 qemu_log_mask(LOG_GUEST_ERROR, 429 "%s: Bad read offset 0x%"HWADDR_PRIx"\n", 430 __func__, addr); 431 break; 432 } 433 return 0; 434 } 435 436 static void pxa2xx_mm_write(void *opaque, hwaddr addr, 437 uint64_t value, unsigned size) 438 { 439 PXA2xxState *s = (PXA2xxState *) opaque; 440 441 switch (addr) { 442 case MDCNFG ... SA1110: 443 if ((addr & 3) == 0) { 444 s->mm_regs[addr >> 2] = value; 445 break; 446 } 447 448 default: 449 qemu_log_mask(LOG_GUEST_ERROR, 450 "%s: Bad write offset 0x%"HWADDR_PRIx"\n", 451 __func__, addr); 452 break; 453 } 454 } 455 456 static const MemoryRegionOps pxa2xx_mm_ops = { 457 .read = pxa2xx_mm_read, 458 .write = pxa2xx_mm_write, 459 .endianness = DEVICE_NATIVE_ENDIAN, 460 }; 461 462 static const VMStateDescription vmstate_pxa2xx_mm = { 463 .name = "pxa2xx_mm", 464 .version_id = 0, 465 .minimum_version_id = 0, 466 .fields = (VMStateField[]) { 467 VMSTATE_UINT32_ARRAY(mm_regs, PXA2xxState, 0x1a), 468 VMSTATE_END_OF_LIST() 469 } 470 }; 471 472 #define TYPE_PXA2XX_SSP "pxa2xx-ssp" 473 typedef struct PXA2xxSSPState PXA2xxSSPState; 474 DECLARE_INSTANCE_CHECKER(PXA2xxSSPState, PXA2XX_SSP, 475 TYPE_PXA2XX_SSP) 476 477 /* Synchronous Serial Ports */ 478 struct PXA2xxSSPState { 479 /*< private >*/ 480 SysBusDevice parent_obj; 481 /*< public >*/ 482 483 MemoryRegion iomem; 484 qemu_irq irq; 485 uint32_t enable; 486 SSIBus *bus; 487 488 uint32_t sscr[2]; 489 uint32_t sspsp; 490 uint32_t ssto; 491 uint32_t ssitr; 492 uint32_t sssr; 493 uint8_t sstsa; 494 uint8_t ssrsa; 495 uint8_t ssacd; 496 497 uint32_t rx_fifo[16]; 498 uint32_t rx_level; 499 uint32_t rx_start; 500 }; 501 502 static bool pxa2xx_ssp_vmstate_validate(void *opaque, int version_id) 503 { 504 PXA2xxSSPState *s = opaque; 505 506 return s->rx_start < sizeof(s->rx_fifo); 507 } 508 509 static const VMStateDescription vmstate_pxa2xx_ssp = { 510 .name = "pxa2xx-ssp", 511 .version_id = 1, 512 .minimum_version_id = 1, 513 .fields = (VMStateField[]) { 514 VMSTATE_UINT32(enable, PXA2xxSSPState), 515 VMSTATE_UINT32_ARRAY(sscr, PXA2xxSSPState, 2), 516 VMSTATE_UINT32(sspsp, PXA2xxSSPState), 517 VMSTATE_UINT32(ssto, PXA2xxSSPState), 518 VMSTATE_UINT32(ssitr, PXA2xxSSPState), 519 VMSTATE_UINT32(sssr, PXA2xxSSPState), 520 VMSTATE_UINT8(sstsa, PXA2xxSSPState), 521 VMSTATE_UINT8(ssrsa, PXA2xxSSPState), 522 VMSTATE_UINT8(ssacd, PXA2xxSSPState), 523 VMSTATE_UINT32(rx_level, PXA2xxSSPState), 524 VMSTATE_UINT32(rx_start, PXA2xxSSPState), 525 VMSTATE_VALIDATE("fifo is 16 bytes", pxa2xx_ssp_vmstate_validate), 526 VMSTATE_UINT32_ARRAY(rx_fifo, PXA2xxSSPState, 16), 527 VMSTATE_END_OF_LIST() 528 } 529 }; 530 531 #define SSCR0 0x00 /* SSP Control register 0 */ 532 #define SSCR1 0x04 /* SSP Control register 1 */ 533 #define SSSR 0x08 /* SSP Status register */ 534 #define SSITR 0x0c /* SSP Interrupt Test register */ 535 #define SSDR 0x10 /* SSP Data register */ 536 #define SSTO 0x28 /* SSP Time-Out register */ 537 #define SSPSP 0x2c /* SSP Programmable Serial Protocol register */ 538 #define SSTSA 0x30 /* SSP TX Time Slot Active register */ 539 #define SSRSA 0x34 /* SSP RX Time Slot Active register */ 540 #define SSTSS 0x38 /* SSP Time Slot Status register */ 541 #define SSACD 0x3c /* SSP Audio Clock Divider register */ 542 543 /* Bitfields for above registers */ 544 #define SSCR0_SPI(x) (((x) & 0x30) == 0x00) 545 #define SSCR0_SSP(x) (((x) & 0x30) == 0x10) 546 #define SSCR0_UWIRE(x) (((x) & 0x30) == 0x20) 547 #define SSCR0_PSP(x) (((x) & 0x30) == 0x30) 548 #define SSCR0_SSE (1 << 7) 549 #define SSCR0_RIM (1 << 22) 550 #define SSCR0_TIM (1 << 23) 551 #define SSCR0_MOD (1U << 31) 552 #define SSCR0_DSS(x) (((((x) >> 16) & 0x10) | ((x) & 0xf)) + 1) 553 #define SSCR1_RIE (1 << 0) 554 #define SSCR1_TIE (1 << 1) 555 #define SSCR1_LBM (1 << 2) 556 #define SSCR1_MWDS (1 << 5) 557 #define SSCR1_TFT(x) ((((x) >> 6) & 0xf) + 1) 558 #define SSCR1_RFT(x) ((((x) >> 10) & 0xf) + 1) 559 #define SSCR1_EFWR (1 << 14) 560 #define SSCR1_PINTE (1 << 18) 561 #define SSCR1_TINTE (1 << 19) 562 #define SSCR1_RSRE (1 << 20) 563 #define SSCR1_TSRE (1 << 21) 564 #define SSCR1_EBCEI (1 << 29) 565 #define SSITR_INT (7 << 5) 566 #define SSSR_TNF (1 << 2) 567 #define SSSR_RNE (1 << 3) 568 #define SSSR_TFS (1 << 5) 569 #define SSSR_RFS (1 << 6) 570 #define SSSR_ROR (1 << 7) 571 #define SSSR_PINT (1 << 18) 572 #define SSSR_TINT (1 << 19) 573 #define SSSR_EOC (1 << 20) 574 #define SSSR_TUR (1 << 21) 575 #define SSSR_BCE (1 << 23) 576 #define SSSR_RW 0x00bc0080 577 578 static void pxa2xx_ssp_int_update(PXA2xxSSPState *s) 579 { 580 int level = 0; 581 582 level |= s->ssitr & SSITR_INT; 583 level |= (s->sssr & SSSR_BCE) && (s->sscr[1] & SSCR1_EBCEI); 584 level |= (s->sssr & SSSR_TUR) && !(s->sscr[0] & SSCR0_TIM); 585 level |= (s->sssr & SSSR_EOC) && (s->sssr & (SSSR_TINT | SSSR_PINT)); 586 level |= (s->sssr & SSSR_TINT) && (s->sscr[1] & SSCR1_TINTE); 587 level |= (s->sssr & SSSR_PINT) && (s->sscr[1] & SSCR1_PINTE); 588 level |= (s->sssr & SSSR_ROR) && !(s->sscr[0] & SSCR0_RIM); 589 level |= (s->sssr & SSSR_RFS) && (s->sscr[1] & SSCR1_RIE); 590 level |= (s->sssr & SSSR_TFS) && (s->sscr[1] & SSCR1_TIE); 591 qemu_set_irq(s->irq, !!level); 592 } 593 594 static void pxa2xx_ssp_fifo_update(PXA2xxSSPState *s) 595 { 596 s->sssr &= ~(0xf << 12); /* Clear RFL */ 597 s->sssr &= ~(0xf << 8); /* Clear TFL */ 598 s->sssr &= ~SSSR_TFS; 599 s->sssr &= ~SSSR_TNF; 600 if (s->enable) { 601 s->sssr |= ((s->rx_level - 1) & 0xf) << 12; 602 if (s->rx_level >= SSCR1_RFT(s->sscr[1])) 603 s->sssr |= SSSR_RFS; 604 else 605 s->sssr &= ~SSSR_RFS; 606 if (s->rx_level) 607 s->sssr |= SSSR_RNE; 608 else 609 s->sssr &= ~SSSR_RNE; 610 /* TX FIFO is never filled, so it is always in underrun 611 condition if SSP is enabled */ 612 s->sssr |= SSSR_TFS; 613 s->sssr |= SSSR_TNF; 614 } 615 616 pxa2xx_ssp_int_update(s); 617 } 618 619 static uint64_t pxa2xx_ssp_read(void *opaque, hwaddr addr, 620 unsigned size) 621 { 622 PXA2xxSSPState *s = (PXA2xxSSPState *) opaque; 623 uint32_t retval; 624 625 switch (addr) { 626 case SSCR0: 627 return s->sscr[0]; 628 case SSCR1: 629 return s->sscr[1]; 630 case SSPSP: 631 return s->sspsp; 632 case SSTO: 633 return s->ssto; 634 case SSITR: 635 return s->ssitr; 636 case SSSR: 637 return s->sssr | s->ssitr; 638 case SSDR: 639 if (!s->enable) 640 return 0xffffffff; 641 if (s->rx_level < 1) { 642 printf("%s: SSP Rx Underrun\n", __func__); 643 return 0xffffffff; 644 } 645 s->rx_level --; 646 retval = s->rx_fifo[s->rx_start ++]; 647 s->rx_start &= 0xf; 648 pxa2xx_ssp_fifo_update(s); 649 return retval; 650 case SSTSA: 651 return s->sstsa; 652 case SSRSA: 653 return s->ssrsa; 654 case SSTSS: 655 return 0; 656 case SSACD: 657 return s->ssacd; 658 default: 659 qemu_log_mask(LOG_GUEST_ERROR, 660 "%s: Bad read offset 0x%"HWADDR_PRIx"\n", 661 __func__, addr); 662 break; 663 } 664 return 0; 665 } 666 667 static void pxa2xx_ssp_write(void *opaque, hwaddr addr, 668 uint64_t value64, unsigned size) 669 { 670 PXA2xxSSPState *s = (PXA2xxSSPState *) opaque; 671 uint32_t value = value64; 672 673 switch (addr) { 674 case SSCR0: 675 s->sscr[0] = value & 0xc7ffffff; 676 s->enable = value & SSCR0_SSE; 677 if (value & SSCR0_MOD) 678 printf("%s: Attempt to use network mode\n", __func__); 679 if (s->enable && SSCR0_DSS(value) < 4) 680 printf("%s: Wrong data size: %i bits\n", __func__, 681 SSCR0_DSS(value)); 682 if (!(value & SSCR0_SSE)) { 683 s->sssr = 0; 684 s->ssitr = 0; 685 s->rx_level = 0; 686 } 687 pxa2xx_ssp_fifo_update(s); 688 break; 689 690 case SSCR1: 691 s->sscr[1] = value; 692 if (value & (SSCR1_LBM | SSCR1_EFWR)) 693 printf("%s: Attempt to use SSP test mode\n", __func__); 694 pxa2xx_ssp_fifo_update(s); 695 break; 696 697 case SSPSP: 698 s->sspsp = value; 699 break; 700 701 case SSTO: 702 s->ssto = value; 703 break; 704 705 case SSITR: 706 s->ssitr = value & SSITR_INT; 707 pxa2xx_ssp_int_update(s); 708 break; 709 710 case SSSR: 711 s->sssr &= ~(value & SSSR_RW); 712 pxa2xx_ssp_int_update(s); 713 break; 714 715 case SSDR: 716 if (SSCR0_UWIRE(s->sscr[0])) { 717 if (s->sscr[1] & SSCR1_MWDS) 718 value &= 0xffff; 719 else 720 value &= 0xff; 721 } else 722 /* Note how 32bits overflow does no harm here */ 723 value &= (1 << SSCR0_DSS(s->sscr[0])) - 1; 724 725 /* Data goes from here to the Tx FIFO and is shifted out from 726 * there directly to the slave, no need to buffer it. 727 */ 728 if (s->enable) { 729 uint32_t readval; 730 readval = ssi_transfer(s->bus, value); 731 if (s->rx_level < 0x10) { 732 s->rx_fifo[(s->rx_start + s->rx_level ++) & 0xf] = readval; 733 } else { 734 s->sssr |= SSSR_ROR; 735 } 736 } 737 pxa2xx_ssp_fifo_update(s); 738 break; 739 740 case SSTSA: 741 s->sstsa = value; 742 break; 743 744 case SSRSA: 745 s->ssrsa = value; 746 break; 747 748 case SSACD: 749 s->ssacd = value; 750 break; 751 752 default: 753 qemu_log_mask(LOG_GUEST_ERROR, 754 "%s: Bad write offset 0x%"HWADDR_PRIx"\n", 755 __func__, addr); 756 break; 757 } 758 } 759 760 static const MemoryRegionOps pxa2xx_ssp_ops = { 761 .read = pxa2xx_ssp_read, 762 .write = pxa2xx_ssp_write, 763 .endianness = DEVICE_NATIVE_ENDIAN, 764 }; 765 766 static void pxa2xx_ssp_reset(DeviceState *d) 767 { 768 PXA2xxSSPState *s = PXA2XX_SSP(d); 769 770 s->enable = 0; 771 s->sscr[0] = s->sscr[1] = 0; 772 s->sspsp = 0; 773 s->ssto = 0; 774 s->ssitr = 0; 775 s->sssr = 0; 776 s->sstsa = 0; 777 s->ssrsa = 0; 778 s->ssacd = 0; 779 s->rx_start = s->rx_level = 0; 780 } 781 782 static void pxa2xx_ssp_init(Object *obj) 783 { 784 DeviceState *dev = DEVICE(obj); 785 PXA2xxSSPState *s = PXA2XX_SSP(obj); 786 SysBusDevice *sbd = SYS_BUS_DEVICE(obj); 787 sysbus_init_irq(sbd, &s->irq); 788 789 memory_region_init_io(&s->iomem, obj, &pxa2xx_ssp_ops, s, 790 "pxa2xx-ssp", 0x1000); 791 sysbus_init_mmio(sbd, &s->iomem); 792 793 s->bus = ssi_create_bus(dev, "ssi"); 794 } 795 796 /* Real-Time Clock */ 797 #define RCNR 0x00 /* RTC Counter register */ 798 #define RTAR 0x04 /* RTC Alarm register */ 799 #define RTSR 0x08 /* RTC Status register */ 800 #define RTTR 0x0c /* RTC Timer Trim register */ 801 #define RDCR 0x10 /* RTC Day Counter register */ 802 #define RYCR 0x14 /* RTC Year Counter register */ 803 #define RDAR1 0x18 /* RTC Wristwatch Day Alarm register 1 */ 804 #define RYAR1 0x1c /* RTC Wristwatch Year Alarm register 1 */ 805 #define RDAR2 0x20 /* RTC Wristwatch Day Alarm register 2 */ 806 #define RYAR2 0x24 /* RTC Wristwatch Year Alarm register 2 */ 807 #define SWCR 0x28 /* RTC Stopwatch Counter register */ 808 #define SWAR1 0x2c /* RTC Stopwatch Alarm register 1 */ 809 #define SWAR2 0x30 /* RTC Stopwatch Alarm register 2 */ 810 #define RTCPICR 0x34 /* RTC Periodic Interrupt Counter register */ 811 #define PIAR 0x38 /* RTC Periodic Interrupt Alarm register */ 812 813 #define TYPE_PXA2XX_RTC "pxa2xx_rtc" 814 typedef struct PXA2xxRTCState PXA2xxRTCState; 815 DECLARE_INSTANCE_CHECKER(PXA2xxRTCState, PXA2XX_RTC, 816 TYPE_PXA2XX_RTC) 817 818 struct PXA2xxRTCState { 819 /*< private >*/ 820 SysBusDevice parent_obj; 821 /*< public >*/ 822 823 MemoryRegion iomem; 824 uint32_t rttr; 825 uint32_t rtsr; 826 uint32_t rtar; 827 uint32_t rdar1; 828 uint32_t rdar2; 829 uint32_t ryar1; 830 uint32_t ryar2; 831 uint32_t swar1; 832 uint32_t swar2; 833 uint32_t piar; 834 uint32_t last_rcnr; 835 uint32_t last_rdcr; 836 uint32_t last_rycr; 837 uint32_t last_swcr; 838 uint32_t last_rtcpicr; 839 int64_t last_hz; 840 int64_t last_sw; 841 int64_t last_pi; 842 QEMUTimer *rtc_hz; 843 QEMUTimer *rtc_rdal1; 844 QEMUTimer *rtc_rdal2; 845 QEMUTimer *rtc_swal1; 846 QEMUTimer *rtc_swal2; 847 QEMUTimer *rtc_pi; 848 qemu_irq rtc_irq; 849 }; 850 851 static inline void pxa2xx_rtc_int_update(PXA2xxRTCState *s) 852 { 853 qemu_set_irq(s->rtc_irq, !!(s->rtsr & 0x2553)); 854 } 855 856 static void pxa2xx_rtc_hzupdate(PXA2xxRTCState *s) 857 { 858 int64_t rt = qemu_clock_get_ms(rtc_clock); 859 s->last_rcnr += ((rt - s->last_hz) << 15) / 860 (1000 * ((s->rttr & 0xffff) + 1)); 861 s->last_rdcr += ((rt - s->last_hz) << 15) / 862 (1000 * ((s->rttr & 0xffff) + 1)); 863 s->last_hz = rt; 864 } 865 866 static void pxa2xx_rtc_swupdate(PXA2xxRTCState *s) 867 { 868 int64_t rt = qemu_clock_get_ms(rtc_clock); 869 if (s->rtsr & (1 << 12)) 870 s->last_swcr += (rt - s->last_sw) / 10; 871 s->last_sw = rt; 872 } 873 874 static void pxa2xx_rtc_piupdate(PXA2xxRTCState *s) 875 { 876 int64_t rt = qemu_clock_get_ms(rtc_clock); 877 if (s->rtsr & (1 << 15)) 878 s->last_swcr += rt - s->last_pi; 879 s->last_pi = rt; 880 } 881 882 static inline void pxa2xx_rtc_alarm_update(PXA2xxRTCState *s, 883 uint32_t rtsr) 884 { 885 if ((rtsr & (1 << 2)) && !(rtsr & (1 << 0))) 886 timer_mod(s->rtc_hz, s->last_hz + 887 (((s->rtar - s->last_rcnr) * 1000 * 888 ((s->rttr & 0xffff) + 1)) >> 15)); 889 else 890 timer_del(s->rtc_hz); 891 892 if ((rtsr & (1 << 5)) && !(rtsr & (1 << 4))) 893 timer_mod(s->rtc_rdal1, s->last_hz + 894 (((s->rdar1 - s->last_rdcr) * 1000 * 895 ((s->rttr & 0xffff) + 1)) >> 15)); /* TODO: fixup */ 896 else 897 timer_del(s->rtc_rdal1); 898 899 if ((rtsr & (1 << 7)) && !(rtsr & (1 << 6))) 900 timer_mod(s->rtc_rdal2, s->last_hz + 901 (((s->rdar2 - s->last_rdcr) * 1000 * 902 ((s->rttr & 0xffff) + 1)) >> 15)); /* TODO: fixup */ 903 else 904 timer_del(s->rtc_rdal2); 905 906 if ((rtsr & 0x1200) == 0x1200 && !(rtsr & (1 << 8))) 907 timer_mod(s->rtc_swal1, s->last_sw + 908 (s->swar1 - s->last_swcr) * 10); /* TODO: fixup */ 909 else 910 timer_del(s->rtc_swal1); 911 912 if ((rtsr & 0x1800) == 0x1800 && !(rtsr & (1 << 10))) 913 timer_mod(s->rtc_swal2, s->last_sw + 914 (s->swar2 - s->last_swcr) * 10); /* TODO: fixup */ 915 else 916 timer_del(s->rtc_swal2); 917 918 if ((rtsr & 0xc000) == 0xc000 && !(rtsr & (1 << 13))) 919 timer_mod(s->rtc_pi, s->last_pi + 920 (s->piar & 0xffff) - s->last_rtcpicr); 921 else 922 timer_del(s->rtc_pi); 923 } 924 925 static inline void pxa2xx_rtc_hz_tick(void *opaque) 926 { 927 PXA2xxRTCState *s = (PXA2xxRTCState *) opaque; 928 s->rtsr |= (1 << 0); 929 pxa2xx_rtc_alarm_update(s, s->rtsr); 930 pxa2xx_rtc_int_update(s); 931 } 932 933 static inline void pxa2xx_rtc_rdal1_tick(void *opaque) 934 { 935 PXA2xxRTCState *s = (PXA2xxRTCState *) opaque; 936 s->rtsr |= (1 << 4); 937 pxa2xx_rtc_alarm_update(s, s->rtsr); 938 pxa2xx_rtc_int_update(s); 939 } 940 941 static inline void pxa2xx_rtc_rdal2_tick(void *opaque) 942 { 943 PXA2xxRTCState *s = (PXA2xxRTCState *) opaque; 944 s->rtsr |= (1 << 6); 945 pxa2xx_rtc_alarm_update(s, s->rtsr); 946 pxa2xx_rtc_int_update(s); 947 } 948 949 static inline void pxa2xx_rtc_swal1_tick(void *opaque) 950 { 951 PXA2xxRTCState *s = (PXA2xxRTCState *) opaque; 952 s->rtsr |= (1 << 8); 953 pxa2xx_rtc_alarm_update(s, s->rtsr); 954 pxa2xx_rtc_int_update(s); 955 } 956 957 static inline void pxa2xx_rtc_swal2_tick(void *opaque) 958 { 959 PXA2xxRTCState *s = (PXA2xxRTCState *) opaque; 960 s->rtsr |= (1 << 10); 961 pxa2xx_rtc_alarm_update(s, s->rtsr); 962 pxa2xx_rtc_int_update(s); 963 } 964 965 static inline void pxa2xx_rtc_pi_tick(void *opaque) 966 { 967 PXA2xxRTCState *s = (PXA2xxRTCState *) opaque; 968 s->rtsr |= (1 << 13); 969 pxa2xx_rtc_piupdate(s); 970 s->last_rtcpicr = 0; 971 pxa2xx_rtc_alarm_update(s, s->rtsr); 972 pxa2xx_rtc_int_update(s); 973 } 974 975 static uint64_t pxa2xx_rtc_read(void *opaque, hwaddr addr, 976 unsigned size) 977 { 978 PXA2xxRTCState *s = (PXA2xxRTCState *) opaque; 979 980 switch (addr) { 981 case RTTR: 982 return s->rttr; 983 case RTSR: 984 return s->rtsr; 985 case RTAR: 986 return s->rtar; 987 case RDAR1: 988 return s->rdar1; 989 case RDAR2: 990 return s->rdar2; 991 case RYAR1: 992 return s->ryar1; 993 case RYAR2: 994 return s->ryar2; 995 case SWAR1: 996 return s->swar1; 997 case SWAR2: 998 return s->swar2; 999 case PIAR: 1000 return s->piar; 1001 case RCNR: 1002 return s->last_rcnr + 1003 ((qemu_clock_get_ms(rtc_clock) - s->last_hz) << 15) / 1004 (1000 * ((s->rttr & 0xffff) + 1)); 1005 case RDCR: 1006 return s->last_rdcr + 1007 ((qemu_clock_get_ms(rtc_clock) - s->last_hz) << 15) / 1008 (1000 * ((s->rttr & 0xffff) + 1)); 1009 case RYCR: 1010 return s->last_rycr; 1011 case SWCR: 1012 if (s->rtsr & (1 << 12)) 1013 return s->last_swcr + 1014 (qemu_clock_get_ms(rtc_clock) - s->last_sw) / 10; 1015 else 1016 return s->last_swcr; 1017 default: 1018 qemu_log_mask(LOG_GUEST_ERROR, 1019 "%s: Bad read offset 0x%"HWADDR_PRIx"\n", 1020 __func__, addr); 1021 break; 1022 } 1023 return 0; 1024 } 1025 1026 static void pxa2xx_rtc_write(void *opaque, hwaddr addr, 1027 uint64_t value64, unsigned size) 1028 { 1029 PXA2xxRTCState *s = (PXA2xxRTCState *) opaque; 1030 uint32_t value = value64; 1031 1032 switch (addr) { 1033 case RTTR: 1034 if (!(s->rttr & (1U << 31))) { 1035 pxa2xx_rtc_hzupdate(s); 1036 s->rttr = value; 1037 pxa2xx_rtc_alarm_update(s, s->rtsr); 1038 } 1039 break; 1040 1041 case RTSR: 1042 if ((s->rtsr ^ value) & (1 << 15)) 1043 pxa2xx_rtc_piupdate(s); 1044 1045 if ((s->rtsr ^ value) & (1 << 12)) 1046 pxa2xx_rtc_swupdate(s); 1047 1048 if (((s->rtsr ^ value) & 0x4aac) | (value & ~0xdaac)) 1049 pxa2xx_rtc_alarm_update(s, value); 1050 1051 s->rtsr = (value & 0xdaac) | (s->rtsr & ~(value & ~0xdaac)); 1052 pxa2xx_rtc_int_update(s); 1053 break; 1054 1055 case RTAR: 1056 s->rtar = value; 1057 pxa2xx_rtc_alarm_update(s, s->rtsr); 1058 break; 1059 1060 case RDAR1: 1061 s->rdar1 = value; 1062 pxa2xx_rtc_alarm_update(s, s->rtsr); 1063 break; 1064 1065 case RDAR2: 1066 s->rdar2 = value; 1067 pxa2xx_rtc_alarm_update(s, s->rtsr); 1068 break; 1069 1070 case RYAR1: 1071 s->ryar1 = value; 1072 pxa2xx_rtc_alarm_update(s, s->rtsr); 1073 break; 1074 1075 case RYAR2: 1076 s->ryar2 = value; 1077 pxa2xx_rtc_alarm_update(s, s->rtsr); 1078 break; 1079 1080 case SWAR1: 1081 pxa2xx_rtc_swupdate(s); 1082 s->swar1 = value; 1083 s->last_swcr = 0; 1084 pxa2xx_rtc_alarm_update(s, s->rtsr); 1085 break; 1086 1087 case SWAR2: 1088 s->swar2 = value; 1089 pxa2xx_rtc_alarm_update(s, s->rtsr); 1090 break; 1091 1092 case PIAR: 1093 s->piar = value; 1094 pxa2xx_rtc_alarm_update(s, s->rtsr); 1095 break; 1096 1097 case RCNR: 1098 pxa2xx_rtc_hzupdate(s); 1099 s->last_rcnr = value; 1100 pxa2xx_rtc_alarm_update(s, s->rtsr); 1101 break; 1102 1103 case RDCR: 1104 pxa2xx_rtc_hzupdate(s); 1105 s->last_rdcr = value; 1106 pxa2xx_rtc_alarm_update(s, s->rtsr); 1107 break; 1108 1109 case RYCR: 1110 s->last_rycr = value; 1111 break; 1112 1113 case SWCR: 1114 pxa2xx_rtc_swupdate(s); 1115 s->last_swcr = value; 1116 pxa2xx_rtc_alarm_update(s, s->rtsr); 1117 break; 1118 1119 case RTCPICR: 1120 pxa2xx_rtc_piupdate(s); 1121 s->last_rtcpicr = value & 0xffff; 1122 pxa2xx_rtc_alarm_update(s, s->rtsr); 1123 break; 1124 1125 default: 1126 qemu_log_mask(LOG_GUEST_ERROR, 1127 "%s: Bad write offset 0x%"HWADDR_PRIx"\n", 1128 __func__, addr); 1129 } 1130 } 1131 1132 static const MemoryRegionOps pxa2xx_rtc_ops = { 1133 .read = pxa2xx_rtc_read, 1134 .write = pxa2xx_rtc_write, 1135 .endianness = DEVICE_NATIVE_ENDIAN, 1136 }; 1137 1138 static void pxa2xx_rtc_init(Object *obj) 1139 { 1140 PXA2xxRTCState *s = PXA2XX_RTC(obj); 1141 SysBusDevice *dev = SYS_BUS_DEVICE(obj); 1142 struct tm tm; 1143 int wom; 1144 1145 s->rttr = 0x7fff; 1146 s->rtsr = 0; 1147 1148 qemu_get_timedate(&tm, 0); 1149 wom = ((tm.tm_mday - 1) / 7) + 1; 1150 1151 s->last_rcnr = (uint32_t) mktimegm(&tm); 1152 s->last_rdcr = (wom << 20) | ((tm.tm_wday + 1) << 17) | 1153 (tm.tm_hour << 12) | (tm.tm_min << 6) | tm.tm_sec; 1154 s->last_rycr = ((tm.tm_year + 1900) << 9) | 1155 ((tm.tm_mon + 1) << 5) | tm.tm_mday; 1156 s->last_swcr = (tm.tm_hour << 19) | 1157 (tm.tm_min << 13) | (tm.tm_sec << 7); 1158 s->last_rtcpicr = 0; 1159 s->last_hz = s->last_sw = s->last_pi = qemu_clock_get_ms(rtc_clock); 1160 1161 sysbus_init_irq(dev, &s->rtc_irq); 1162 1163 memory_region_init_io(&s->iomem, obj, &pxa2xx_rtc_ops, s, 1164 "pxa2xx-rtc", 0x10000); 1165 sysbus_init_mmio(dev, &s->iomem); 1166 } 1167 1168 static void pxa2xx_rtc_realize(DeviceState *dev, Error **errp) 1169 { 1170 PXA2xxRTCState *s = PXA2XX_RTC(dev); 1171 s->rtc_hz = timer_new_ms(rtc_clock, pxa2xx_rtc_hz_tick, s); 1172 s->rtc_rdal1 = timer_new_ms(rtc_clock, pxa2xx_rtc_rdal1_tick, s); 1173 s->rtc_rdal2 = timer_new_ms(rtc_clock, pxa2xx_rtc_rdal2_tick, s); 1174 s->rtc_swal1 = timer_new_ms(rtc_clock, pxa2xx_rtc_swal1_tick, s); 1175 s->rtc_swal2 = timer_new_ms(rtc_clock, pxa2xx_rtc_swal2_tick, s); 1176 s->rtc_pi = timer_new_ms(rtc_clock, pxa2xx_rtc_pi_tick, s); 1177 } 1178 1179 static int pxa2xx_rtc_pre_save(void *opaque) 1180 { 1181 PXA2xxRTCState *s = (PXA2xxRTCState *) opaque; 1182 1183 pxa2xx_rtc_hzupdate(s); 1184 pxa2xx_rtc_piupdate(s); 1185 pxa2xx_rtc_swupdate(s); 1186 1187 return 0; 1188 } 1189 1190 static int pxa2xx_rtc_post_load(void *opaque, int version_id) 1191 { 1192 PXA2xxRTCState *s = (PXA2xxRTCState *) opaque; 1193 1194 pxa2xx_rtc_alarm_update(s, s->rtsr); 1195 1196 return 0; 1197 } 1198 1199 static const VMStateDescription vmstate_pxa2xx_rtc_regs = { 1200 .name = "pxa2xx_rtc", 1201 .version_id = 0, 1202 .minimum_version_id = 0, 1203 .pre_save = pxa2xx_rtc_pre_save, 1204 .post_load = pxa2xx_rtc_post_load, 1205 .fields = (VMStateField[]) { 1206 VMSTATE_UINT32(rttr, PXA2xxRTCState), 1207 VMSTATE_UINT32(rtsr, PXA2xxRTCState), 1208 VMSTATE_UINT32(rtar, PXA2xxRTCState), 1209 VMSTATE_UINT32(rdar1, PXA2xxRTCState), 1210 VMSTATE_UINT32(rdar2, PXA2xxRTCState), 1211 VMSTATE_UINT32(ryar1, PXA2xxRTCState), 1212 VMSTATE_UINT32(ryar2, PXA2xxRTCState), 1213 VMSTATE_UINT32(swar1, PXA2xxRTCState), 1214 VMSTATE_UINT32(swar2, PXA2xxRTCState), 1215 VMSTATE_UINT32(piar, PXA2xxRTCState), 1216 VMSTATE_UINT32(last_rcnr, PXA2xxRTCState), 1217 VMSTATE_UINT32(last_rdcr, PXA2xxRTCState), 1218 VMSTATE_UINT32(last_rycr, PXA2xxRTCState), 1219 VMSTATE_UINT32(last_swcr, PXA2xxRTCState), 1220 VMSTATE_UINT32(last_rtcpicr, PXA2xxRTCState), 1221 VMSTATE_INT64(last_hz, PXA2xxRTCState), 1222 VMSTATE_INT64(last_sw, PXA2xxRTCState), 1223 VMSTATE_INT64(last_pi, PXA2xxRTCState), 1224 VMSTATE_END_OF_LIST(), 1225 }, 1226 }; 1227 1228 static void pxa2xx_rtc_sysbus_class_init(ObjectClass *klass, void *data) 1229 { 1230 DeviceClass *dc = DEVICE_CLASS(klass); 1231 1232 dc->desc = "PXA2xx RTC Controller"; 1233 dc->vmsd = &vmstate_pxa2xx_rtc_regs; 1234 dc->realize = pxa2xx_rtc_realize; 1235 } 1236 1237 static const TypeInfo pxa2xx_rtc_sysbus_info = { 1238 .name = TYPE_PXA2XX_RTC, 1239 .parent = TYPE_SYS_BUS_DEVICE, 1240 .instance_size = sizeof(PXA2xxRTCState), 1241 .instance_init = pxa2xx_rtc_init, 1242 .class_init = pxa2xx_rtc_sysbus_class_init, 1243 }; 1244 1245 /* I2C Interface */ 1246 1247 #define TYPE_PXA2XX_I2C_SLAVE "pxa2xx-i2c-slave" 1248 typedef struct PXA2xxI2CSlaveState PXA2xxI2CSlaveState; 1249 DECLARE_INSTANCE_CHECKER(PXA2xxI2CSlaveState, PXA2XX_I2C_SLAVE, 1250 TYPE_PXA2XX_I2C_SLAVE) 1251 1252 struct PXA2xxI2CSlaveState { 1253 I2CSlave parent_obj; 1254 1255 PXA2xxI2CState *host; 1256 }; 1257 1258 struct PXA2xxI2CState { 1259 /*< private >*/ 1260 SysBusDevice parent_obj; 1261 /*< public >*/ 1262 1263 MemoryRegion iomem; 1264 PXA2xxI2CSlaveState *slave; 1265 I2CBus *bus; 1266 qemu_irq irq; 1267 uint32_t offset; 1268 uint32_t region_size; 1269 1270 uint16_t control; 1271 uint16_t status; 1272 uint8_t ibmr; 1273 uint8_t data; 1274 }; 1275 1276 #define IBMR 0x80 /* I2C Bus Monitor register */ 1277 #define IDBR 0x88 /* I2C Data Buffer register */ 1278 #define ICR 0x90 /* I2C Control register */ 1279 #define ISR 0x98 /* I2C Status register */ 1280 #define ISAR 0xa0 /* I2C Slave Address register */ 1281 1282 static void pxa2xx_i2c_update(PXA2xxI2CState *s) 1283 { 1284 uint16_t level = 0; 1285 level |= s->status & s->control & (1 << 10); /* BED */ 1286 level |= (s->status & (1 << 7)) && (s->control & (1 << 9)); /* IRF */ 1287 level |= (s->status & (1 << 6)) && (s->control & (1 << 8)); /* ITE */ 1288 level |= s->status & (1 << 9); /* SAD */ 1289 qemu_set_irq(s->irq, !!level); 1290 } 1291 1292 /* These are only stubs now. */ 1293 static int pxa2xx_i2c_event(I2CSlave *i2c, enum i2c_event event) 1294 { 1295 PXA2xxI2CSlaveState *slave = PXA2XX_I2C_SLAVE(i2c); 1296 PXA2xxI2CState *s = slave->host; 1297 1298 switch (event) { 1299 case I2C_START_SEND: 1300 s->status |= (1 << 9); /* set SAD */ 1301 s->status &= ~(1 << 0); /* clear RWM */ 1302 break; 1303 case I2C_START_RECV: 1304 s->status |= (1 << 9); /* set SAD */ 1305 s->status |= 1 << 0; /* set RWM */ 1306 break; 1307 case I2C_FINISH: 1308 s->status |= (1 << 4); /* set SSD */ 1309 break; 1310 case I2C_NACK: 1311 s->status |= 1 << 1; /* set ACKNAK */ 1312 break; 1313 } 1314 pxa2xx_i2c_update(s); 1315 1316 return 0; 1317 } 1318 1319 static uint8_t pxa2xx_i2c_rx(I2CSlave *i2c) 1320 { 1321 PXA2xxI2CSlaveState *slave = PXA2XX_I2C_SLAVE(i2c); 1322 PXA2xxI2CState *s = slave->host; 1323 1324 if ((s->control & (1 << 14)) || !(s->control & (1 << 6))) { 1325 return 0; 1326 } 1327 1328 if (s->status & (1 << 0)) { /* RWM */ 1329 s->status |= 1 << 6; /* set ITE */ 1330 } 1331 pxa2xx_i2c_update(s); 1332 1333 return s->data; 1334 } 1335 1336 static int pxa2xx_i2c_tx(I2CSlave *i2c, uint8_t data) 1337 { 1338 PXA2xxI2CSlaveState *slave = PXA2XX_I2C_SLAVE(i2c); 1339 PXA2xxI2CState *s = slave->host; 1340 1341 if ((s->control & (1 << 14)) || !(s->control & (1 << 6))) { 1342 return 1; 1343 } 1344 1345 if (!(s->status & (1 << 0))) { /* RWM */ 1346 s->status |= 1 << 7; /* set IRF */ 1347 s->data = data; 1348 } 1349 pxa2xx_i2c_update(s); 1350 1351 return 1; 1352 } 1353 1354 static uint64_t pxa2xx_i2c_read(void *opaque, hwaddr addr, 1355 unsigned size) 1356 { 1357 PXA2xxI2CState *s = (PXA2xxI2CState *) opaque; 1358 I2CSlave *slave; 1359 1360 addr -= s->offset; 1361 switch (addr) { 1362 case ICR: 1363 return s->control; 1364 case ISR: 1365 return s->status | (i2c_bus_busy(s->bus) << 2); 1366 case ISAR: 1367 slave = I2C_SLAVE(s->slave); 1368 return slave->address; 1369 case IDBR: 1370 return s->data; 1371 case IBMR: 1372 if (s->status & (1 << 2)) 1373 s->ibmr ^= 3; /* Fake SCL and SDA pin changes */ 1374 else 1375 s->ibmr = 0; 1376 return s->ibmr; 1377 default: 1378 qemu_log_mask(LOG_GUEST_ERROR, 1379 "%s: Bad read offset 0x%"HWADDR_PRIx"\n", 1380 __func__, addr); 1381 break; 1382 } 1383 return 0; 1384 } 1385 1386 static void pxa2xx_i2c_write(void *opaque, hwaddr addr, 1387 uint64_t value64, unsigned size) 1388 { 1389 PXA2xxI2CState *s = (PXA2xxI2CState *) opaque; 1390 uint32_t value = value64; 1391 int ack; 1392 1393 addr -= s->offset; 1394 switch (addr) { 1395 case ICR: 1396 s->control = value & 0xfff7; 1397 if ((value & (1 << 3)) && (value & (1 << 6))) { /* TB and IUE */ 1398 /* TODO: slave mode */ 1399 if (value & (1 << 0)) { /* START condition */ 1400 if (s->data & 1) 1401 s->status |= 1 << 0; /* set RWM */ 1402 else 1403 s->status &= ~(1 << 0); /* clear RWM */ 1404 ack = !i2c_start_transfer(s->bus, s->data >> 1, s->data & 1); 1405 } else { 1406 if (s->status & (1 << 0)) { /* RWM */ 1407 s->data = i2c_recv(s->bus); 1408 if (value & (1 << 2)) /* ACKNAK */ 1409 i2c_nack(s->bus); 1410 ack = 1; 1411 } else 1412 ack = !i2c_send(s->bus, s->data); 1413 } 1414 1415 if (value & (1 << 1)) /* STOP condition */ 1416 i2c_end_transfer(s->bus); 1417 1418 if (ack) { 1419 if (value & (1 << 0)) /* START condition */ 1420 s->status |= 1 << 6; /* set ITE */ 1421 else 1422 if (s->status & (1 << 0)) /* RWM */ 1423 s->status |= 1 << 7; /* set IRF */ 1424 else 1425 s->status |= 1 << 6; /* set ITE */ 1426 s->status &= ~(1 << 1); /* clear ACKNAK */ 1427 } else { 1428 s->status |= 1 << 6; /* set ITE */ 1429 s->status |= 1 << 10; /* set BED */ 1430 s->status |= 1 << 1; /* set ACKNAK */ 1431 } 1432 } 1433 if (!(value & (1 << 3)) && (value & (1 << 6))) /* !TB and IUE */ 1434 if (value & (1 << 4)) /* MA */ 1435 i2c_end_transfer(s->bus); 1436 pxa2xx_i2c_update(s); 1437 break; 1438 1439 case ISR: 1440 s->status &= ~(value & 0x07f0); 1441 pxa2xx_i2c_update(s); 1442 break; 1443 1444 case ISAR: 1445 i2c_set_slave_address(I2C_SLAVE(s->slave), value & 0x7f); 1446 break; 1447 1448 case IDBR: 1449 s->data = value & 0xff; 1450 break; 1451 1452 default: 1453 qemu_log_mask(LOG_GUEST_ERROR, 1454 "%s: Bad write offset 0x%"HWADDR_PRIx"\n", 1455 __func__, addr); 1456 } 1457 } 1458 1459 static const MemoryRegionOps pxa2xx_i2c_ops = { 1460 .read = pxa2xx_i2c_read, 1461 .write = pxa2xx_i2c_write, 1462 .endianness = DEVICE_NATIVE_ENDIAN, 1463 }; 1464 1465 static const VMStateDescription vmstate_pxa2xx_i2c_slave = { 1466 .name = "pxa2xx_i2c_slave", 1467 .version_id = 1, 1468 .minimum_version_id = 1, 1469 .fields = (VMStateField[]) { 1470 VMSTATE_I2C_SLAVE(parent_obj, PXA2xxI2CSlaveState), 1471 VMSTATE_END_OF_LIST() 1472 } 1473 }; 1474 1475 static const VMStateDescription vmstate_pxa2xx_i2c = { 1476 .name = "pxa2xx_i2c", 1477 .version_id = 1, 1478 .minimum_version_id = 1, 1479 .fields = (VMStateField[]) { 1480 VMSTATE_UINT16(control, PXA2xxI2CState), 1481 VMSTATE_UINT16(status, PXA2xxI2CState), 1482 VMSTATE_UINT8(ibmr, PXA2xxI2CState), 1483 VMSTATE_UINT8(data, PXA2xxI2CState), 1484 VMSTATE_STRUCT_POINTER(slave, PXA2xxI2CState, 1485 vmstate_pxa2xx_i2c_slave, PXA2xxI2CSlaveState), 1486 VMSTATE_END_OF_LIST() 1487 } 1488 }; 1489 1490 static void pxa2xx_i2c_slave_class_init(ObjectClass *klass, void *data) 1491 { 1492 I2CSlaveClass *k = I2C_SLAVE_CLASS(klass); 1493 1494 k->event = pxa2xx_i2c_event; 1495 k->recv = pxa2xx_i2c_rx; 1496 k->send = pxa2xx_i2c_tx; 1497 } 1498 1499 static const TypeInfo pxa2xx_i2c_slave_info = { 1500 .name = TYPE_PXA2XX_I2C_SLAVE, 1501 .parent = TYPE_I2C_SLAVE, 1502 .instance_size = sizeof(PXA2xxI2CSlaveState), 1503 .class_init = pxa2xx_i2c_slave_class_init, 1504 }; 1505 1506 PXA2xxI2CState *pxa2xx_i2c_init(hwaddr base, 1507 qemu_irq irq, uint32_t region_size) 1508 { 1509 DeviceState *dev; 1510 SysBusDevice *i2c_dev; 1511 PXA2xxI2CState *s; 1512 I2CBus *i2cbus; 1513 1514 dev = qdev_new(TYPE_PXA2XX_I2C); 1515 qdev_prop_set_uint32(dev, "size", region_size + 1); 1516 qdev_prop_set_uint32(dev, "offset", base & region_size); 1517 1518 i2c_dev = SYS_BUS_DEVICE(dev); 1519 sysbus_realize_and_unref(i2c_dev, &error_fatal); 1520 sysbus_mmio_map(i2c_dev, 0, base & ~region_size); 1521 sysbus_connect_irq(i2c_dev, 0, irq); 1522 1523 s = PXA2XX_I2C(i2c_dev); 1524 /* FIXME: Should the slave device really be on a separate bus? */ 1525 i2cbus = i2c_init_bus(dev, "dummy"); 1526 s->slave = PXA2XX_I2C_SLAVE(i2c_slave_create_simple(i2cbus, 1527 TYPE_PXA2XX_I2C_SLAVE, 1528 0)); 1529 s->slave->host = s; 1530 1531 return s; 1532 } 1533 1534 static void pxa2xx_i2c_initfn(Object *obj) 1535 { 1536 DeviceState *dev = DEVICE(obj); 1537 PXA2xxI2CState *s = PXA2XX_I2C(obj); 1538 SysBusDevice *sbd = SYS_BUS_DEVICE(obj); 1539 1540 s->bus = i2c_init_bus(dev, NULL); 1541 1542 memory_region_init_io(&s->iomem, obj, &pxa2xx_i2c_ops, s, 1543 "pxa2xx-i2c", s->region_size); 1544 sysbus_init_mmio(sbd, &s->iomem); 1545 sysbus_init_irq(sbd, &s->irq); 1546 } 1547 1548 I2CBus *pxa2xx_i2c_bus(PXA2xxI2CState *s) 1549 { 1550 return s->bus; 1551 } 1552 1553 static Property pxa2xx_i2c_properties[] = { 1554 DEFINE_PROP_UINT32("size", PXA2xxI2CState, region_size, 0x10000), 1555 DEFINE_PROP_UINT32("offset", PXA2xxI2CState, offset, 0), 1556 DEFINE_PROP_END_OF_LIST(), 1557 }; 1558 1559 static void pxa2xx_i2c_class_init(ObjectClass *klass, void *data) 1560 { 1561 DeviceClass *dc = DEVICE_CLASS(klass); 1562 1563 dc->desc = "PXA2xx I2C Bus Controller"; 1564 dc->vmsd = &vmstate_pxa2xx_i2c; 1565 device_class_set_props(dc, pxa2xx_i2c_properties); 1566 } 1567 1568 static const TypeInfo pxa2xx_i2c_info = { 1569 .name = TYPE_PXA2XX_I2C, 1570 .parent = TYPE_SYS_BUS_DEVICE, 1571 .instance_size = sizeof(PXA2xxI2CState), 1572 .instance_init = pxa2xx_i2c_initfn, 1573 .class_init = pxa2xx_i2c_class_init, 1574 }; 1575 1576 /* PXA Inter-IC Sound Controller */ 1577 static void pxa2xx_i2s_reset(PXA2xxI2SState *i2s) 1578 { 1579 i2s->rx_len = 0; 1580 i2s->tx_len = 0; 1581 i2s->fifo_len = 0; 1582 i2s->clk = 0x1a; 1583 i2s->control[0] = 0x00; 1584 i2s->control[1] = 0x00; 1585 i2s->status = 0x00; 1586 i2s->mask = 0x00; 1587 } 1588 1589 #define SACR_TFTH(val) ((val >> 8) & 0xf) 1590 #define SACR_RFTH(val) ((val >> 12) & 0xf) 1591 #define SACR_DREC(val) (val & (1 << 3)) 1592 #define SACR_DPRL(val) (val & (1 << 4)) 1593 1594 static inline void pxa2xx_i2s_update(PXA2xxI2SState *i2s) 1595 { 1596 int rfs, tfs; 1597 rfs = SACR_RFTH(i2s->control[0]) < i2s->rx_len && 1598 !SACR_DREC(i2s->control[1]); 1599 tfs = (i2s->tx_len || i2s->fifo_len < SACR_TFTH(i2s->control[0])) && 1600 i2s->enable && !SACR_DPRL(i2s->control[1]); 1601 1602 qemu_set_irq(i2s->rx_dma, rfs); 1603 qemu_set_irq(i2s->tx_dma, tfs); 1604 1605 i2s->status &= 0xe0; 1606 if (i2s->fifo_len < 16 || !i2s->enable) 1607 i2s->status |= 1 << 0; /* TNF */ 1608 if (i2s->rx_len) 1609 i2s->status |= 1 << 1; /* RNE */ 1610 if (i2s->enable) 1611 i2s->status |= 1 << 2; /* BSY */ 1612 if (tfs) 1613 i2s->status |= 1 << 3; /* TFS */ 1614 if (rfs) 1615 i2s->status |= 1 << 4; /* RFS */ 1616 if (!(i2s->tx_len && i2s->enable)) 1617 i2s->status |= i2s->fifo_len << 8; /* TFL */ 1618 i2s->status |= MAX(i2s->rx_len, 0xf) << 12; /* RFL */ 1619 1620 qemu_set_irq(i2s->irq, i2s->status & i2s->mask); 1621 } 1622 1623 #define SACR0 0x00 /* Serial Audio Global Control register */ 1624 #define SACR1 0x04 /* Serial Audio I2S/MSB-Justified Control register */ 1625 #define SASR0 0x0c /* Serial Audio Interface and FIFO Status register */ 1626 #define SAIMR 0x14 /* Serial Audio Interrupt Mask register */ 1627 #define SAICR 0x18 /* Serial Audio Interrupt Clear register */ 1628 #define SADIV 0x60 /* Serial Audio Clock Divider register */ 1629 #define SADR 0x80 /* Serial Audio Data register */ 1630 1631 static uint64_t pxa2xx_i2s_read(void *opaque, hwaddr addr, 1632 unsigned size) 1633 { 1634 PXA2xxI2SState *s = (PXA2xxI2SState *) opaque; 1635 1636 switch (addr) { 1637 case SACR0: 1638 return s->control[0]; 1639 case SACR1: 1640 return s->control[1]; 1641 case SASR0: 1642 return s->status; 1643 case SAIMR: 1644 return s->mask; 1645 case SAICR: 1646 return 0; 1647 case SADIV: 1648 return s->clk; 1649 case SADR: 1650 if (s->rx_len > 0) { 1651 s->rx_len --; 1652 pxa2xx_i2s_update(s); 1653 return s->codec_in(s->opaque); 1654 } 1655 return 0; 1656 default: 1657 qemu_log_mask(LOG_GUEST_ERROR, 1658 "%s: Bad read offset 0x%"HWADDR_PRIx"\n", 1659 __func__, addr); 1660 break; 1661 } 1662 return 0; 1663 } 1664 1665 static void pxa2xx_i2s_write(void *opaque, hwaddr addr, 1666 uint64_t value, unsigned size) 1667 { 1668 PXA2xxI2SState *s = (PXA2xxI2SState *) opaque; 1669 uint32_t *sample; 1670 1671 switch (addr) { 1672 case SACR0: 1673 if (value & (1 << 3)) /* RST */ 1674 pxa2xx_i2s_reset(s); 1675 s->control[0] = value & 0xff3d; 1676 if (!s->enable && (value & 1) && s->tx_len) { /* ENB */ 1677 for (sample = s->fifo; s->fifo_len > 0; s->fifo_len --, sample ++) 1678 s->codec_out(s->opaque, *sample); 1679 s->status &= ~(1 << 7); /* I2SOFF */ 1680 } 1681 if (value & (1 << 4)) /* EFWR */ 1682 printf("%s: Attempt to use special function\n", __func__); 1683 s->enable = (value & 9) == 1; /* ENB && !RST*/ 1684 pxa2xx_i2s_update(s); 1685 break; 1686 case SACR1: 1687 s->control[1] = value & 0x0039; 1688 if (value & (1 << 5)) /* ENLBF */ 1689 printf("%s: Attempt to use loopback function\n", __func__); 1690 if (value & (1 << 4)) /* DPRL */ 1691 s->fifo_len = 0; 1692 pxa2xx_i2s_update(s); 1693 break; 1694 case SAIMR: 1695 s->mask = value & 0x0078; 1696 pxa2xx_i2s_update(s); 1697 break; 1698 case SAICR: 1699 s->status &= ~(value & (3 << 5)); 1700 pxa2xx_i2s_update(s); 1701 break; 1702 case SADIV: 1703 s->clk = value & 0x007f; 1704 break; 1705 case SADR: 1706 if (s->tx_len && s->enable) { 1707 s->tx_len --; 1708 pxa2xx_i2s_update(s); 1709 s->codec_out(s->opaque, value); 1710 } else if (s->fifo_len < 16) { 1711 s->fifo[s->fifo_len ++] = value; 1712 pxa2xx_i2s_update(s); 1713 } 1714 break; 1715 default: 1716 qemu_log_mask(LOG_GUEST_ERROR, 1717 "%s: Bad write offset 0x%"HWADDR_PRIx"\n", 1718 __func__, addr); 1719 } 1720 } 1721 1722 static const MemoryRegionOps pxa2xx_i2s_ops = { 1723 .read = pxa2xx_i2s_read, 1724 .write = pxa2xx_i2s_write, 1725 .endianness = DEVICE_NATIVE_ENDIAN, 1726 }; 1727 1728 static const VMStateDescription vmstate_pxa2xx_i2s = { 1729 .name = "pxa2xx_i2s", 1730 .version_id = 0, 1731 .minimum_version_id = 0, 1732 .fields = (VMStateField[]) { 1733 VMSTATE_UINT32_ARRAY(control, PXA2xxI2SState, 2), 1734 VMSTATE_UINT32(status, PXA2xxI2SState), 1735 VMSTATE_UINT32(mask, PXA2xxI2SState), 1736 VMSTATE_UINT32(clk, PXA2xxI2SState), 1737 VMSTATE_INT32(enable, PXA2xxI2SState), 1738 VMSTATE_INT32(rx_len, PXA2xxI2SState), 1739 VMSTATE_INT32(tx_len, PXA2xxI2SState), 1740 VMSTATE_INT32(fifo_len, PXA2xxI2SState), 1741 VMSTATE_END_OF_LIST() 1742 } 1743 }; 1744 1745 static void pxa2xx_i2s_data_req(void *opaque, int tx, int rx) 1746 { 1747 PXA2xxI2SState *s = (PXA2xxI2SState *) opaque; 1748 uint32_t *sample; 1749 1750 /* Signal FIFO errors */ 1751 if (s->enable && s->tx_len) 1752 s->status |= 1 << 5; /* TUR */ 1753 if (s->enable && s->rx_len) 1754 s->status |= 1 << 6; /* ROR */ 1755 1756 /* Should be tx - MIN(tx, s->fifo_len) but we don't really need to 1757 * handle the cases where it makes a difference. */ 1758 s->tx_len = tx - s->fifo_len; 1759 s->rx_len = rx; 1760 /* Note that is s->codec_out wasn't set, we wouldn't get called. */ 1761 if (s->enable) 1762 for (sample = s->fifo; s->fifo_len; s->fifo_len --, sample ++) 1763 s->codec_out(s->opaque, *sample); 1764 pxa2xx_i2s_update(s); 1765 } 1766 1767 static PXA2xxI2SState *pxa2xx_i2s_init(MemoryRegion *sysmem, 1768 hwaddr base, 1769 qemu_irq irq, qemu_irq rx_dma, qemu_irq tx_dma) 1770 { 1771 PXA2xxI2SState *s = g_new0(PXA2xxI2SState, 1); 1772 1773 s->irq = irq; 1774 s->rx_dma = rx_dma; 1775 s->tx_dma = tx_dma; 1776 s->data_req = pxa2xx_i2s_data_req; 1777 1778 pxa2xx_i2s_reset(s); 1779 1780 memory_region_init_io(&s->iomem, NULL, &pxa2xx_i2s_ops, s, 1781 "pxa2xx-i2s", 0x100000); 1782 memory_region_add_subregion(sysmem, base, &s->iomem); 1783 1784 vmstate_register(NULL, base, &vmstate_pxa2xx_i2s, s); 1785 1786 return s; 1787 } 1788 1789 /* PXA Fast Infra-red Communications Port */ 1790 struct PXA2xxFIrState { 1791 /*< private >*/ 1792 SysBusDevice parent_obj; 1793 /*< public >*/ 1794 1795 MemoryRegion iomem; 1796 qemu_irq irq; 1797 qemu_irq rx_dma; 1798 qemu_irq tx_dma; 1799 uint32_t enable; 1800 CharBackend chr; 1801 1802 uint8_t control[3]; 1803 uint8_t status[2]; 1804 1805 uint32_t rx_len; 1806 uint32_t rx_start; 1807 uint8_t rx_fifo[64]; 1808 }; 1809 1810 static void pxa2xx_fir_reset(DeviceState *d) 1811 { 1812 PXA2xxFIrState *s = PXA2XX_FIR(d); 1813 1814 s->control[0] = 0x00; 1815 s->control[1] = 0x00; 1816 s->control[2] = 0x00; 1817 s->status[0] = 0x00; 1818 s->status[1] = 0x00; 1819 s->enable = 0; 1820 } 1821 1822 static inline void pxa2xx_fir_update(PXA2xxFIrState *s) 1823 { 1824 static const int tresh[4] = { 8, 16, 32, 0 }; 1825 int intr = 0; 1826 if ((s->control[0] & (1 << 4)) && /* RXE */ 1827 s->rx_len >= tresh[s->control[2] & 3]) /* TRIG */ 1828 s->status[0] |= 1 << 4; /* RFS */ 1829 else 1830 s->status[0] &= ~(1 << 4); /* RFS */ 1831 if (s->control[0] & (1 << 3)) /* TXE */ 1832 s->status[0] |= 1 << 3; /* TFS */ 1833 else 1834 s->status[0] &= ~(1 << 3); /* TFS */ 1835 if (s->rx_len) 1836 s->status[1] |= 1 << 2; /* RNE */ 1837 else 1838 s->status[1] &= ~(1 << 2); /* RNE */ 1839 if (s->control[0] & (1 << 4)) /* RXE */ 1840 s->status[1] |= 1 << 0; /* RSY */ 1841 else 1842 s->status[1] &= ~(1 << 0); /* RSY */ 1843 1844 intr |= (s->control[0] & (1 << 5)) && /* RIE */ 1845 (s->status[0] & (1 << 4)); /* RFS */ 1846 intr |= (s->control[0] & (1 << 6)) && /* TIE */ 1847 (s->status[0] & (1 << 3)); /* TFS */ 1848 intr |= (s->control[2] & (1 << 4)) && /* TRAIL */ 1849 (s->status[0] & (1 << 6)); /* EOC */ 1850 intr |= (s->control[0] & (1 << 2)) && /* TUS */ 1851 (s->status[0] & (1 << 1)); /* TUR */ 1852 intr |= s->status[0] & 0x25; /* FRE, RAB, EIF */ 1853 1854 qemu_set_irq(s->rx_dma, (s->status[0] >> 4) & 1); 1855 qemu_set_irq(s->tx_dma, (s->status[0] >> 3) & 1); 1856 1857 qemu_set_irq(s->irq, intr && s->enable); 1858 } 1859 1860 #define ICCR0 0x00 /* FICP Control register 0 */ 1861 #define ICCR1 0x04 /* FICP Control register 1 */ 1862 #define ICCR2 0x08 /* FICP Control register 2 */ 1863 #define ICDR 0x0c /* FICP Data register */ 1864 #define ICSR0 0x14 /* FICP Status register 0 */ 1865 #define ICSR1 0x18 /* FICP Status register 1 */ 1866 #define ICFOR 0x1c /* FICP FIFO Occupancy Status register */ 1867 1868 static uint64_t pxa2xx_fir_read(void *opaque, hwaddr addr, 1869 unsigned size) 1870 { 1871 PXA2xxFIrState *s = (PXA2xxFIrState *) opaque; 1872 uint8_t ret; 1873 1874 switch (addr) { 1875 case ICCR0: 1876 return s->control[0]; 1877 case ICCR1: 1878 return s->control[1]; 1879 case ICCR2: 1880 return s->control[2]; 1881 case ICDR: 1882 s->status[0] &= ~0x01; 1883 s->status[1] &= ~0x72; 1884 if (s->rx_len) { 1885 s->rx_len --; 1886 ret = s->rx_fifo[s->rx_start ++]; 1887 s->rx_start &= 63; 1888 pxa2xx_fir_update(s); 1889 return ret; 1890 } 1891 printf("%s: Rx FIFO underrun.\n", __func__); 1892 break; 1893 case ICSR0: 1894 return s->status[0]; 1895 case ICSR1: 1896 return s->status[1] | (1 << 3); /* TNF */ 1897 case ICFOR: 1898 return s->rx_len; 1899 default: 1900 qemu_log_mask(LOG_GUEST_ERROR, 1901 "%s: Bad read offset 0x%"HWADDR_PRIx"\n", 1902 __func__, addr); 1903 break; 1904 } 1905 return 0; 1906 } 1907 1908 static void pxa2xx_fir_write(void *opaque, hwaddr addr, 1909 uint64_t value64, unsigned size) 1910 { 1911 PXA2xxFIrState *s = (PXA2xxFIrState *) opaque; 1912 uint32_t value = value64; 1913 uint8_t ch; 1914 1915 switch (addr) { 1916 case ICCR0: 1917 s->control[0] = value; 1918 if (!(value & (1 << 4))) /* RXE */ 1919 s->rx_len = s->rx_start = 0; 1920 if (!(value & (1 << 3))) { /* TXE */ 1921 /* Nop */ 1922 } 1923 s->enable = value & 1; /* ITR */ 1924 if (!s->enable) 1925 s->status[0] = 0; 1926 pxa2xx_fir_update(s); 1927 break; 1928 case ICCR1: 1929 s->control[1] = value; 1930 break; 1931 case ICCR2: 1932 s->control[2] = value & 0x3f; 1933 pxa2xx_fir_update(s); 1934 break; 1935 case ICDR: 1936 if (s->control[2] & (1 << 2)) { /* TXP */ 1937 ch = value; 1938 } else { 1939 ch = ~value; 1940 } 1941 if (s->enable && (s->control[0] & (1 << 3))) { /* TXE */ 1942 /* XXX this blocks entire thread. Rewrite to use 1943 * qemu_chr_fe_write and background I/O callbacks */ 1944 qemu_chr_fe_write_all(&s->chr, &ch, 1); 1945 } 1946 break; 1947 case ICSR0: 1948 s->status[0] &= ~(value & 0x66); 1949 pxa2xx_fir_update(s); 1950 break; 1951 case ICFOR: 1952 break; 1953 default: 1954 qemu_log_mask(LOG_GUEST_ERROR, 1955 "%s: Bad write offset 0x%"HWADDR_PRIx"\n", 1956 __func__, addr); 1957 } 1958 } 1959 1960 static const MemoryRegionOps pxa2xx_fir_ops = { 1961 .read = pxa2xx_fir_read, 1962 .write = pxa2xx_fir_write, 1963 .endianness = DEVICE_NATIVE_ENDIAN, 1964 }; 1965 1966 static int pxa2xx_fir_is_empty(void *opaque) 1967 { 1968 PXA2xxFIrState *s = (PXA2xxFIrState *) opaque; 1969 return (s->rx_len < 64); 1970 } 1971 1972 static void pxa2xx_fir_rx(void *opaque, const uint8_t *buf, int size) 1973 { 1974 PXA2xxFIrState *s = (PXA2xxFIrState *) opaque; 1975 if (!(s->control[0] & (1 << 4))) /* RXE */ 1976 return; 1977 1978 while (size --) { 1979 s->status[1] |= 1 << 4; /* EOF */ 1980 if (s->rx_len >= 64) { 1981 s->status[1] |= 1 << 6; /* ROR */ 1982 break; 1983 } 1984 1985 if (s->control[2] & (1 << 3)) /* RXP */ 1986 s->rx_fifo[(s->rx_start + s->rx_len ++) & 63] = *(buf ++); 1987 else 1988 s->rx_fifo[(s->rx_start + s->rx_len ++) & 63] = ~*(buf ++); 1989 } 1990 1991 pxa2xx_fir_update(s); 1992 } 1993 1994 static void pxa2xx_fir_event(void *opaque, QEMUChrEvent event) 1995 { 1996 } 1997 1998 static void pxa2xx_fir_instance_init(Object *obj) 1999 { 2000 PXA2xxFIrState *s = PXA2XX_FIR(obj); 2001 SysBusDevice *sbd = SYS_BUS_DEVICE(obj); 2002 2003 memory_region_init_io(&s->iomem, obj, &pxa2xx_fir_ops, s, 2004 "pxa2xx-fir", 0x1000); 2005 sysbus_init_mmio(sbd, &s->iomem); 2006 sysbus_init_irq(sbd, &s->irq); 2007 sysbus_init_irq(sbd, &s->rx_dma); 2008 sysbus_init_irq(sbd, &s->tx_dma); 2009 } 2010 2011 static void pxa2xx_fir_realize(DeviceState *dev, Error **errp) 2012 { 2013 PXA2xxFIrState *s = PXA2XX_FIR(dev); 2014 2015 qemu_chr_fe_set_handlers(&s->chr, pxa2xx_fir_is_empty, 2016 pxa2xx_fir_rx, pxa2xx_fir_event, NULL, s, NULL, 2017 true); 2018 } 2019 2020 static bool pxa2xx_fir_vmstate_validate(void *opaque, int version_id) 2021 { 2022 PXA2xxFIrState *s = opaque; 2023 2024 return s->rx_start < ARRAY_SIZE(s->rx_fifo); 2025 } 2026 2027 static const VMStateDescription pxa2xx_fir_vmsd = { 2028 .name = "pxa2xx-fir", 2029 .version_id = 1, 2030 .minimum_version_id = 1, 2031 .fields = (VMStateField[]) { 2032 VMSTATE_UINT32(enable, PXA2xxFIrState), 2033 VMSTATE_UINT8_ARRAY(control, PXA2xxFIrState, 3), 2034 VMSTATE_UINT8_ARRAY(status, PXA2xxFIrState, 2), 2035 VMSTATE_UINT32(rx_len, PXA2xxFIrState), 2036 VMSTATE_UINT32(rx_start, PXA2xxFIrState), 2037 VMSTATE_VALIDATE("fifo is 64 bytes", pxa2xx_fir_vmstate_validate), 2038 VMSTATE_UINT8_ARRAY(rx_fifo, PXA2xxFIrState, 64), 2039 VMSTATE_END_OF_LIST() 2040 } 2041 }; 2042 2043 static Property pxa2xx_fir_properties[] = { 2044 DEFINE_PROP_CHR("chardev", PXA2xxFIrState, chr), 2045 DEFINE_PROP_END_OF_LIST(), 2046 }; 2047 2048 static void pxa2xx_fir_class_init(ObjectClass *klass, void *data) 2049 { 2050 DeviceClass *dc = DEVICE_CLASS(klass); 2051 2052 dc->realize = pxa2xx_fir_realize; 2053 dc->vmsd = &pxa2xx_fir_vmsd; 2054 device_class_set_props(dc, pxa2xx_fir_properties); 2055 dc->reset = pxa2xx_fir_reset; 2056 } 2057 2058 static const TypeInfo pxa2xx_fir_info = { 2059 .name = TYPE_PXA2XX_FIR, 2060 .parent = TYPE_SYS_BUS_DEVICE, 2061 .instance_size = sizeof(PXA2xxFIrState), 2062 .class_init = pxa2xx_fir_class_init, 2063 .instance_init = pxa2xx_fir_instance_init, 2064 }; 2065 2066 static PXA2xxFIrState *pxa2xx_fir_init(MemoryRegion *sysmem, 2067 hwaddr base, 2068 qemu_irq irq, qemu_irq rx_dma, 2069 qemu_irq tx_dma, 2070 Chardev *chr) 2071 { 2072 DeviceState *dev; 2073 SysBusDevice *sbd; 2074 2075 dev = qdev_new(TYPE_PXA2XX_FIR); 2076 qdev_prop_set_chr(dev, "chardev", chr); 2077 sbd = SYS_BUS_DEVICE(dev); 2078 sysbus_realize_and_unref(sbd, &error_fatal); 2079 sysbus_mmio_map(sbd, 0, base); 2080 sysbus_connect_irq(sbd, 0, irq); 2081 sysbus_connect_irq(sbd, 1, rx_dma); 2082 sysbus_connect_irq(sbd, 2, tx_dma); 2083 return PXA2XX_FIR(dev); 2084 } 2085 2086 static void pxa2xx_reset(void *opaque, int line, int level) 2087 { 2088 PXA2xxState *s = (PXA2xxState *) opaque; 2089 2090 if (level && (s->pm_regs[PCFR >> 2] & 0x10)) { /* GPR_EN */ 2091 cpu_reset(CPU(s->cpu)); 2092 /* TODO: reset peripherals */ 2093 } 2094 } 2095 2096 /* Initialise a PXA270 integrated chip (ARM based core). */ 2097 PXA2xxState *pxa270_init(MemoryRegion *address_space, 2098 unsigned int sdram_size, const char *cpu_type) 2099 { 2100 PXA2xxState *s; 2101 int i; 2102 DriveInfo *dinfo; 2103 s = g_new0(PXA2xxState, 1); 2104 2105 if (strncmp(cpu_type, "pxa27", 5)) { 2106 error_report("Machine requires a PXA27x processor"); 2107 exit(1); 2108 } 2109 2110 s->cpu = ARM_CPU(cpu_create(cpu_type)); 2111 s->reset = qemu_allocate_irq(pxa2xx_reset, s, 0); 2112 2113 /* SDRAM & Internal Memory Storage */ 2114 memory_region_init_ram(&s->sdram, NULL, "pxa270.sdram", sdram_size, 2115 &error_fatal); 2116 memory_region_add_subregion(address_space, PXA2XX_SDRAM_BASE, &s->sdram); 2117 memory_region_init_ram(&s->internal, NULL, "pxa270.internal", 0x40000, 2118 &error_fatal); 2119 memory_region_add_subregion(address_space, PXA2XX_INTERNAL_BASE, 2120 &s->internal); 2121 2122 s->pic = pxa2xx_pic_init(0x40d00000, s->cpu); 2123 2124 s->dma = pxa27x_dma_init(0x40000000, 2125 qdev_get_gpio_in(s->pic, PXA2XX_PIC_DMA)); 2126 2127 sysbus_create_varargs("pxa27x-timer", 0x40a00000, 2128 qdev_get_gpio_in(s->pic, PXA2XX_PIC_OST_0 + 0), 2129 qdev_get_gpio_in(s->pic, PXA2XX_PIC_OST_0 + 1), 2130 qdev_get_gpio_in(s->pic, PXA2XX_PIC_OST_0 + 2), 2131 qdev_get_gpio_in(s->pic, PXA2XX_PIC_OST_0 + 3), 2132 qdev_get_gpio_in(s->pic, PXA27X_PIC_OST_4_11), 2133 NULL); 2134 2135 s->gpio = pxa2xx_gpio_init(0x40e00000, s->cpu, s->pic, 121); 2136 2137 s->mmc = pxa2xx_mmci_init(address_space, 0x41100000, 2138 qdev_get_gpio_in(s->pic, PXA2XX_PIC_MMC), 2139 qdev_get_gpio_in(s->dma, PXA2XX_RX_RQ_MMCI), 2140 qdev_get_gpio_in(s->dma, PXA2XX_TX_RQ_MMCI)); 2141 dinfo = drive_get(IF_SD, 0, 0); 2142 if (dinfo) { 2143 DeviceState *carddev; 2144 2145 /* Create and plug in the sd card */ 2146 carddev = qdev_new(TYPE_SD_CARD); 2147 qdev_prop_set_drive_err(carddev, "drive", 2148 blk_by_legacy_dinfo(dinfo), &error_fatal); 2149 qdev_realize_and_unref(carddev, qdev_get_child_bus(DEVICE(s->mmc), 2150 "sd-bus"), 2151 &error_fatal); 2152 } else if (!qtest_enabled()) { 2153 warn_report("missing SecureDigital device"); 2154 } 2155 2156 for (i = 0; pxa270_serial[i].io_base; i++) { 2157 if (serial_hd(i)) { 2158 serial_mm_init(address_space, pxa270_serial[i].io_base, 2, 2159 qdev_get_gpio_in(s->pic, pxa270_serial[i].irqn), 2160 14857000 / 16, serial_hd(i), 2161 DEVICE_NATIVE_ENDIAN); 2162 } else { 2163 break; 2164 } 2165 } 2166 if (serial_hd(i)) 2167 s->fir = pxa2xx_fir_init(address_space, 0x40800000, 2168 qdev_get_gpio_in(s->pic, PXA2XX_PIC_ICP), 2169 qdev_get_gpio_in(s->dma, PXA2XX_RX_RQ_ICP), 2170 qdev_get_gpio_in(s->dma, PXA2XX_TX_RQ_ICP), 2171 serial_hd(i)); 2172 2173 s->lcd = pxa2xx_lcdc_init(address_space, 0x44000000, 2174 qdev_get_gpio_in(s->pic, PXA2XX_PIC_LCD)); 2175 2176 s->cm_base = 0x41300000; 2177 s->cm_regs[CCCR >> 2] = 0x02000210; /* 416.0 MHz */ 2178 s->clkcfg = 0x00000009; /* Turbo mode active */ 2179 memory_region_init_io(&s->cm_iomem, NULL, &pxa2xx_cm_ops, s, "pxa2xx-cm", 0x1000); 2180 memory_region_add_subregion(address_space, s->cm_base, &s->cm_iomem); 2181 vmstate_register(NULL, 0, &vmstate_pxa2xx_cm, s); 2182 2183 pxa2xx_setup_cp14(s); 2184 2185 s->mm_base = 0x48000000; 2186 s->mm_regs[MDMRS >> 2] = 0x00020002; 2187 s->mm_regs[MDREFR >> 2] = 0x03ca4000; 2188 s->mm_regs[MECR >> 2] = 0x00000001; /* Two PC Card sockets */ 2189 memory_region_init_io(&s->mm_iomem, NULL, &pxa2xx_mm_ops, s, "pxa2xx-mm", 0x1000); 2190 memory_region_add_subregion(address_space, s->mm_base, &s->mm_iomem); 2191 vmstate_register(NULL, 0, &vmstate_pxa2xx_mm, s); 2192 2193 s->pm_base = 0x40f00000; 2194 memory_region_init_io(&s->pm_iomem, NULL, &pxa2xx_pm_ops, s, "pxa2xx-pm", 0x100); 2195 memory_region_add_subregion(address_space, s->pm_base, &s->pm_iomem); 2196 vmstate_register(NULL, 0, &vmstate_pxa2xx_pm, s); 2197 2198 for (i = 0; pxa27x_ssp[i].io_base; i ++); 2199 s->ssp = g_new0(SSIBus *, i); 2200 for (i = 0; pxa27x_ssp[i].io_base; i ++) { 2201 DeviceState *dev; 2202 dev = sysbus_create_simple(TYPE_PXA2XX_SSP, pxa27x_ssp[i].io_base, 2203 qdev_get_gpio_in(s->pic, pxa27x_ssp[i].irqn)); 2204 s->ssp[i] = (SSIBus *)qdev_get_child_bus(dev, "ssi"); 2205 } 2206 2207 sysbus_create_simple("sysbus-ohci", 0x4c000000, 2208 qdev_get_gpio_in(s->pic, PXA2XX_PIC_USBH1)); 2209 2210 s->pcmcia[0] = pxa2xx_pcmcia_init(address_space, 0x20000000); 2211 s->pcmcia[1] = pxa2xx_pcmcia_init(address_space, 0x30000000); 2212 2213 sysbus_create_simple(TYPE_PXA2XX_RTC, 0x40900000, 2214 qdev_get_gpio_in(s->pic, PXA2XX_PIC_RTCALARM)); 2215 2216 s->i2c[0] = pxa2xx_i2c_init(0x40301600, 2217 qdev_get_gpio_in(s->pic, PXA2XX_PIC_I2C), 0xffff); 2218 s->i2c[1] = pxa2xx_i2c_init(0x40f00100, 2219 qdev_get_gpio_in(s->pic, PXA2XX_PIC_PWRI2C), 0xff); 2220 2221 s->i2s = pxa2xx_i2s_init(address_space, 0x40400000, 2222 qdev_get_gpio_in(s->pic, PXA2XX_PIC_I2S), 2223 qdev_get_gpio_in(s->dma, PXA2XX_RX_RQ_I2S), 2224 qdev_get_gpio_in(s->dma, PXA2XX_TX_RQ_I2S)); 2225 2226 s->kp = pxa27x_keypad_init(address_space, 0x41500000, 2227 qdev_get_gpio_in(s->pic, PXA2XX_PIC_KEYPAD)); 2228 2229 /* GPIO1 resets the processor */ 2230 /* The handler can be overridden by board-specific code */ 2231 qdev_connect_gpio_out(s->gpio, 1, s->reset); 2232 return s; 2233 } 2234 2235 /* Initialise a PXA255 integrated chip (ARM based core). */ 2236 PXA2xxState *pxa255_init(MemoryRegion *address_space, unsigned int sdram_size) 2237 { 2238 PXA2xxState *s; 2239 int i; 2240 DriveInfo *dinfo; 2241 2242 s = g_new0(PXA2xxState, 1); 2243 2244 s->cpu = ARM_CPU(cpu_create(ARM_CPU_TYPE_NAME("pxa255"))); 2245 s->reset = qemu_allocate_irq(pxa2xx_reset, s, 0); 2246 2247 /* SDRAM & Internal Memory Storage */ 2248 memory_region_init_ram(&s->sdram, NULL, "pxa255.sdram", sdram_size, 2249 &error_fatal); 2250 memory_region_add_subregion(address_space, PXA2XX_SDRAM_BASE, &s->sdram); 2251 memory_region_init_ram(&s->internal, NULL, "pxa255.internal", 2252 PXA2XX_INTERNAL_SIZE, &error_fatal); 2253 memory_region_add_subregion(address_space, PXA2XX_INTERNAL_BASE, 2254 &s->internal); 2255 2256 s->pic = pxa2xx_pic_init(0x40d00000, s->cpu); 2257 2258 s->dma = pxa255_dma_init(0x40000000, 2259 qdev_get_gpio_in(s->pic, PXA2XX_PIC_DMA)); 2260 2261 sysbus_create_varargs("pxa25x-timer", 0x40a00000, 2262 qdev_get_gpio_in(s->pic, PXA2XX_PIC_OST_0 + 0), 2263 qdev_get_gpio_in(s->pic, PXA2XX_PIC_OST_0 + 1), 2264 qdev_get_gpio_in(s->pic, PXA2XX_PIC_OST_0 + 2), 2265 qdev_get_gpio_in(s->pic, PXA2XX_PIC_OST_0 + 3), 2266 NULL); 2267 2268 s->gpio = pxa2xx_gpio_init(0x40e00000, s->cpu, s->pic, 85); 2269 2270 s->mmc = pxa2xx_mmci_init(address_space, 0x41100000, 2271 qdev_get_gpio_in(s->pic, PXA2XX_PIC_MMC), 2272 qdev_get_gpio_in(s->dma, PXA2XX_RX_RQ_MMCI), 2273 qdev_get_gpio_in(s->dma, PXA2XX_TX_RQ_MMCI)); 2274 dinfo = drive_get(IF_SD, 0, 0); 2275 if (dinfo) { 2276 DeviceState *carddev; 2277 2278 /* Create and plug in the sd card */ 2279 carddev = qdev_new(TYPE_SD_CARD); 2280 qdev_prop_set_drive_err(carddev, "drive", 2281 blk_by_legacy_dinfo(dinfo), &error_fatal); 2282 qdev_realize_and_unref(carddev, qdev_get_child_bus(DEVICE(s->mmc), 2283 "sd-bus"), 2284 &error_fatal); 2285 } else if (!qtest_enabled()) { 2286 warn_report("missing SecureDigital device"); 2287 } 2288 2289 for (i = 0; pxa255_serial[i].io_base; i++) { 2290 if (serial_hd(i)) { 2291 serial_mm_init(address_space, pxa255_serial[i].io_base, 2, 2292 qdev_get_gpio_in(s->pic, pxa255_serial[i].irqn), 2293 14745600 / 16, serial_hd(i), 2294 DEVICE_NATIVE_ENDIAN); 2295 } else { 2296 break; 2297 } 2298 } 2299 if (serial_hd(i)) 2300 s->fir = pxa2xx_fir_init(address_space, 0x40800000, 2301 qdev_get_gpio_in(s->pic, PXA2XX_PIC_ICP), 2302 qdev_get_gpio_in(s->dma, PXA2XX_RX_RQ_ICP), 2303 qdev_get_gpio_in(s->dma, PXA2XX_TX_RQ_ICP), 2304 serial_hd(i)); 2305 2306 s->lcd = pxa2xx_lcdc_init(address_space, 0x44000000, 2307 qdev_get_gpio_in(s->pic, PXA2XX_PIC_LCD)); 2308 2309 s->cm_base = 0x41300000; 2310 s->cm_regs[CCCR >> 2] = 0x00000121; /* from datasheet */ 2311 s->cm_regs[CKEN >> 2] = 0x00017def; /* from datasheet */ 2312 2313 s->clkcfg = 0x00000009; /* Turbo mode active */ 2314 memory_region_init_io(&s->cm_iomem, NULL, &pxa2xx_cm_ops, s, "pxa2xx-cm", 0x1000); 2315 memory_region_add_subregion(address_space, s->cm_base, &s->cm_iomem); 2316 vmstate_register(NULL, 0, &vmstate_pxa2xx_cm, s); 2317 2318 pxa2xx_setup_cp14(s); 2319 2320 s->mm_base = 0x48000000; 2321 s->mm_regs[MDMRS >> 2] = 0x00020002; 2322 s->mm_regs[MDREFR >> 2] = 0x03ca4000; 2323 s->mm_regs[MECR >> 2] = 0x00000001; /* Two PC Card sockets */ 2324 memory_region_init_io(&s->mm_iomem, NULL, &pxa2xx_mm_ops, s, "pxa2xx-mm", 0x1000); 2325 memory_region_add_subregion(address_space, s->mm_base, &s->mm_iomem); 2326 vmstate_register(NULL, 0, &vmstate_pxa2xx_mm, s); 2327 2328 s->pm_base = 0x40f00000; 2329 memory_region_init_io(&s->pm_iomem, NULL, &pxa2xx_pm_ops, s, "pxa2xx-pm", 0x100); 2330 memory_region_add_subregion(address_space, s->pm_base, &s->pm_iomem); 2331 vmstate_register(NULL, 0, &vmstate_pxa2xx_pm, s); 2332 2333 for (i = 0; pxa255_ssp[i].io_base; i ++); 2334 s->ssp = g_new0(SSIBus *, i); 2335 for (i = 0; pxa255_ssp[i].io_base; i ++) { 2336 DeviceState *dev; 2337 dev = sysbus_create_simple(TYPE_PXA2XX_SSP, pxa255_ssp[i].io_base, 2338 qdev_get_gpio_in(s->pic, pxa255_ssp[i].irqn)); 2339 s->ssp[i] = (SSIBus *)qdev_get_child_bus(dev, "ssi"); 2340 } 2341 2342 s->pcmcia[0] = pxa2xx_pcmcia_init(address_space, 0x20000000); 2343 s->pcmcia[1] = pxa2xx_pcmcia_init(address_space, 0x30000000); 2344 2345 sysbus_create_simple(TYPE_PXA2XX_RTC, 0x40900000, 2346 qdev_get_gpio_in(s->pic, PXA2XX_PIC_RTCALARM)); 2347 2348 s->i2c[0] = pxa2xx_i2c_init(0x40301600, 2349 qdev_get_gpio_in(s->pic, PXA2XX_PIC_I2C), 0xffff); 2350 s->i2c[1] = pxa2xx_i2c_init(0x40f00100, 2351 qdev_get_gpio_in(s->pic, PXA2XX_PIC_PWRI2C), 0xff); 2352 2353 s->i2s = pxa2xx_i2s_init(address_space, 0x40400000, 2354 qdev_get_gpio_in(s->pic, PXA2XX_PIC_I2S), 2355 qdev_get_gpio_in(s->dma, PXA2XX_RX_RQ_I2S), 2356 qdev_get_gpio_in(s->dma, PXA2XX_TX_RQ_I2S)); 2357 2358 /* GPIO1 resets the processor */ 2359 /* The handler can be overridden by board-specific code */ 2360 qdev_connect_gpio_out(s->gpio, 1, s->reset); 2361 return s; 2362 } 2363 2364 static void pxa2xx_ssp_class_init(ObjectClass *klass, void *data) 2365 { 2366 DeviceClass *dc = DEVICE_CLASS(klass); 2367 2368 dc->reset = pxa2xx_ssp_reset; 2369 dc->vmsd = &vmstate_pxa2xx_ssp; 2370 } 2371 2372 static const TypeInfo pxa2xx_ssp_info = { 2373 .name = TYPE_PXA2XX_SSP, 2374 .parent = TYPE_SYS_BUS_DEVICE, 2375 .instance_size = sizeof(PXA2xxSSPState), 2376 .instance_init = pxa2xx_ssp_init, 2377 .class_init = pxa2xx_ssp_class_init, 2378 }; 2379 2380 static void pxa2xx_register_types(void) 2381 { 2382 type_register_static(&pxa2xx_i2c_slave_info); 2383 type_register_static(&pxa2xx_ssp_info); 2384 type_register_static(&pxa2xx_i2c_info); 2385 type_register_static(&pxa2xx_rtc_sysbus_info); 2386 type_register_static(&pxa2xx_fir_info); 2387 } 2388 2389 type_init(pxa2xx_register_types) 2390