1 /* 2 * Intel XScale PXA255/270 processor support. 3 * 4 * Copyright (c) 2006 Openedhand Ltd. 5 * Written by Andrzej Zaborowski <balrog@zabor.org> 6 * 7 * This code is licensed under the GPL. 8 */ 9 10 #include "hw/sysbus.h" 11 #include "hw/arm/pxa.h" 12 #include "sysemu/sysemu.h" 13 #include "hw/char/serial.h" 14 #include "hw/i2c/i2c.h" 15 #include "hw/ssi.h" 16 #include "sysemu/char.h" 17 #include "sysemu/blockdev.h" 18 19 static struct { 20 hwaddr io_base; 21 int irqn; 22 } pxa255_serial[] = { 23 { 0x40100000, PXA2XX_PIC_FFUART }, 24 { 0x40200000, PXA2XX_PIC_BTUART }, 25 { 0x40700000, PXA2XX_PIC_STUART }, 26 { 0x41600000, PXA25X_PIC_HWUART }, 27 { 0, 0 } 28 }, pxa270_serial[] = { 29 { 0x40100000, PXA2XX_PIC_FFUART }, 30 { 0x40200000, PXA2XX_PIC_BTUART }, 31 { 0x40700000, PXA2XX_PIC_STUART }, 32 { 0, 0 } 33 }; 34 35 typedef struct PXASSPDef { 36 hwaddr io_base; 37 int irqn; 38 } PXASSPDef; 39 40 #if 0 41 static PXASSPDef pxa250_ssp[] = { 42 { 0x41000000, PXA2XX_PIC_SSP }, 43 { 0, 0 } 44 }; 45 #endif 46 47 static PXASSPDef pxa255_ssp[] = { 48 { 0x41000000, PXA2XX_PIC_SSP }, 49 { 0x41400000, PXA25X_PIC_NSSP }, 50 { 0, 0 } 51 }; 52 53 #if 0 54 static PXASSPDef pxa26x_ssp[] = { 55 { 0x41000000, PXA2XX_PIC_SSP }, 56 { 0x41400000, PXA25X_PIC_NSSP }, 57 { 0x41500000, PXA26X_PIC_ASSP }, 58 { 0, 0 } 59 }; 60 #endif 61 62 static PXASSPDef pxa27x_ssp[] = { 63 { 0x41000000, PXA2XX_PIC_SSP }, 64 { 0x41700000, PXA27X_PIC_SSP2 }, 65 { 0x41900000, PXA2XX_PIC_SSP3 }, 66 { 0, 0 } 67 }; 68 69 #define PMCR 0x00 /* Power Manager Control register */ 70 #define PSSR 0x04 /* Power Manager Sleep Status register */ 71 #define PSPR 0x08 /* Power Manager Scratch-Pad register */ 72 #define PWER 0x0c /* Power Manager Wake-Up Enable register */ 73 #define PRER 0x10 /* Power Manager Rising-Edge Detect Enable register */ 74 #define PFER 0x14 /* Power Manager Falling-Edge Detect Enable register */ 75 #define PEDR 0x18 /* Power Manager Edge-Detect Status register */ 76 #define PCFR 0x1c /* Power Manager General Configuration register */ 77 #define PGSR0 0x20 /* Power Manager GPIO Sleep-State register 0 */ 78 #define PGSR1 0x24 /* Power Manager GPIO Sleep-State register 1 */ 79 #define PGSR2 0x28 /* Power Manager GPIO Sleep-State register 2 */ 80 #define PGSR3 0x2c /* Power Manager GPIO Sleep-State register 3 */ 81 #define RCSR 0x30 /* Reset Controller Status register */ 82 #define PSLR 0x34 /* Power Manager Sleep Configuration register */ 83 #define PTSR 0x38 /* Power Manager Standby Configuration register */ 84 #define PVCR 0x40 /* Power Manager Voltage Change Control register */ 85 #define PUCR 0x4c /* Power Manager USIM Card Control/Status register */ 86 #define PKWR 0x50 /* Power Manager Keyboard Wake-Up Enable register */ 87 #define PKSR 0x54 /* Power Manager Keyboard Level-Detect Status */ 88 #define PCMD0 0x80 /* Power Manager I2C Command register File 0 */ 89 #define PCMD31 0xfc /* Power Manager I2C Command register File 31 */ 90 91 static uint64_t pxa2xx_pm_read(void *opaque, hwaddr addr, 92 unsigned size) 93 { 94 PXA2xxState *s = (PXA2xxState *) opaque; 95 96 switch (addr) { 97 case PMCR ... PCMD31: 98 if (addr & 3) 99 goto fail; 100 101 return s->pm_regs[addr >> 2]; 102 default: 103 fail: 104 printf("%s: Bad register " REG_FMT "\n", __FUNCTION__, addr); 105 break; 106 } 107 return 0; 108 } 109 110 static void pxa2xx_pm_write(void *opaque, hwaddr addr, 111 uint64_t value, unsigned size) 112 { 113 PXA2xxState *s = (PXA2xxState *) opaque; 114 115 switch (addr) { 116 case PMCR: 117 /* Clear the write-one-to-clear bits... */ 118 s->pm_regs[addr >> 2] &= ~(value & 0x2a); 119 /* ...and set the plain r/w bits */ 120 s->pm_regs[addr >> 2] &= ~0x15; 121 s->pm_regs[addr >> 2] |= value & 0x15; 122 break; 123 124 case PSSR: /* Read-clean registers */ 125 case RCSR: 126 case PKSR: 127 s->pm_regs[addr >> 2] &= ~value; 128 break; 129 130 default: /* Read-write registers */ 131 if (!(addr & 3)) { 132 s->pm_regs[addr >> 2] = value; 133 break; 134 } 135 136 printf("%s: Bad register " REG_FMT "\n", __FUNCTION__, addr); 137 break; 138 } 139 } 140 141 static const MemoryRegionOps pxa2xx_pm_ops = { 142 .read = pxa2xx_pm_read, 143 .write = pxa2xx_pm_write, 144 .endianness = DEVICE_NATIVE_ENDIAN, 145 }; 146 147 static const VMStateDescription vmstate_pxa2xx_pm = { 148 .name = "pxa2xx_pm", 149 .version_id = 0, 150 .minimum_version_id = 0, 151 .fields = (VMStateField[]) { 152 VMSTATE_UINT32_ARRAY(pm_regs, PXA2xxState, 0x40), 153 VMSTATE_END_OF_LIST() 154 } 155 }; 156 157 #define CCCR 0x00 /* Core Clock Configuration register */ 158 #define CKEN 0x04 /* Clock Enable register */ 159 #define OSCC 0x08 /* Oscillator Configuration register */ 160 #define CCSR 0x0c /* Core Clock Status register */ 161 162 static uint64_t pxa2xx_cm_read(void *opaque, hwaddr addr, 163 unsigned size) 164 { 165 PXA2xxState *s = (PXA2xxState *) opaque; 166 167 switch (addr) { 168 case CCCR: 169 case CKEN: 170 case OSCC: 171 return s->cm_regs[addr >> 2]; 172 173 case CCSR: 174 return s->cm_regs[CCCR >> 2] | (3 << 28); 175 176 default: 177 printf("%s: Bad register " REG_FMT "\n", __FUNCTION__, addr); 178 break; 179 } 180 return 0; 181 } 182 183 static void pxa2xx_cm_write(void *opaque, hwaddr addr, 184 uint64_t value, unsigned size) 185 { 186 PXA2xxState *s = (PXA2xxState *) opaque; 187 188 switch (addr) { 189 case CCCR: 190 case CKEN: 191 s->cm_regs[addr >> 2] = value; 192 break; 193 194 case OSCC: 195 s->cm_regs[addr >> 2] &= ~0x6c; 196 s->cm_regs[addr >> 2] |= value & 0x6e; 197 if ((value >> 1) & 1) /* OON */ 198 s->cm_regs[addr >> 2] |= 1 << 0; /* Oscillator is now stable */ 199 break; 200 201 default: 202 printf("%s: Bad register " REG_FMT "\n", __FUNCTION__, addr); 203 break; 204 } 205 } 206 207 static const MemoryRegionOps pxa2xx_cm_ops = { 208 .read = pxa2xx_cm_read, 209 .write = pxa2xx_cm_write, 210 .endianness = DEVICE_NATIVE_ENDIAN, 211 }; 212 213 static const VMStateDescription vmstate_pxa2xx_cm = { 214 .name = "pxa2xx_cm", 215 .version_id = 0, 216 .minimum_version_id = 0, 217 .fields = (VMStateField[]) { 218 VMSTATE_UINT32_ARRAY(cm_regs, PXA2xxState, 4), 219 VMSTATE_UINT32(clkcfg, PXA2xxState), 220 VMSTATE_UINT32(pmnc, PXA2xxState), 221 VMSTATE_END_OF_LIST() 222 } 223 }; 224 225 static uint64_t pxa2xx_clkcfg_read(CPUARMState *env, const ARMCPRegInfo *ri) 226 { 227 PXA2xxState *s = (PXA2xxState *)ri->opaque; 228 return s->clkcfg; 229 } 230 231 static void pxa2xx_clkcfg_write(CPUARMState *env, const ARMCPRegInfo *ri, 232 uint64_t value) 233 { 234 PXA2xxState *s = (PXA2xxState *)ri->opaque; 235 s->clkcfg = value & 0xf; 236 if (value & 2) { 237 printf("%s: CPU frequency change attempt\n", __func__); 238 } 239 } 240 241 static void pxa2xx_pwrmode_write(CPUARMState *env, const ARMCPRegInfo *ri, 242 uint64_t value) 243 { 244 PXA2xxState *s = (PXA2xxState *)ri->opaque; 245 static const char *pwrmode[8] = { 246 "Normal", "Idle", "Deep-idle", "Standby", 247 "Sleep", "reserved (!)", "reserved (!)", "Deep-sleep", 248 }; 249 250 if (value & 8) { 251 printf("%s: CPU voltage change attempt\n", __func__); 252 } 253 switch (value & 7) { 254 case 0: 255 /* Do nothing */ 256 break; 257 258 case 1: 259 /* Idle */ 260 if (!(s->cm_regs[CCCR >> 2] & (1U << 31))) { /* CPDIS */ 261 cpu_interrupt(CPU(s->cpu), CPU_INTERRUPT_HALT); 262 break; 263 } 264 /* Fall through. */ 265 266 case 2: 267 /* Deep-Idle */ 268 cpu_interrupt(CPU(s->cpu), CPU_INTERRUPT_HALT); 269 s->pm_regs[RCSR >> 2] |= 0x8; /* Set GPR */ 270 goto message; 271 272 case 3: 273 s->cpu->env.uncached_cpsr = ARM_CPU_MODE_SVC; 274 s->cpu->env.daif = PSTATE_A | PSTATE_F | PSTATE_I; 275 s->cpu->env.cp15.c1_sys = 0; 276 s->cpu->env.cp15.c1_coproc = 0; 277 s->cpu->env.cp15.ttbr0_el1 = 0; 278 s->cpu->env.cp15.c3 = 0; 279 s->pm_regs[PSSR >> 2] |= 0x8; /* Set STS */ 280 s->pm_regs[RCSR >> 2] |= 0x8; /* Set GPR */ 281 282 /* 283 * The scratch-pad register is almost universally used 284 * for storing the return address on suspend. For the 285 * lack of a resuming bootloader, perform a jump 286 * directly to that address. 287 */ 288 memset(s->cpu->env.regs, 0, 4 * 15); 289 s->cpu->env.regs[15] = s->pm_regs[PSPR >> 2]; 290 291 #if 0 292 buffer = 0xe59ff000; /* ldr pc, [pc, #0] */ 293 cpu_physical_memory_write(0, &buffer, 4); 294 buffer = s->pm_regs[PSPR >> 2]; 295 cpu_physical_memory_write(8, &buffer, 4); 296 #endif 297 298 /* Suspend */ 299 cpu_interrupt(current_cpu, CPU_INTERRUPT_HALT); 300 301 goto message; 302 303 default: 304 message: 305 printf("%s: machine entered %s mode\n", __func__, 306 pwrmode[value & 7]); 307 } 308 } 309 310 static uint64_t pxa2xx_cppmnc_read(CPUARMState *env, const ARMCPRegInfo *ri) 311 { 312 PXA2xxState *s = (PXA2xxState *)ri->opaque; 313 return s->pmnc; 314 } 315 316 static void pxa2xx_cppmnc_write(CPUARMState *env, const ARMCPRegInfo *ri, 317 uint64_t value) 318 { 319 PXA2xxState *s = (PXA2xxState *)ri->opaque; 320 s->pmnc = value; 321 } 322 323 static uint64_t pxa2xx_cpccnt_read(CPUARMState *env, const ARMCPRegInfo *ri) 324 { 325 PXA2xxState *s = (PXA2xxState *)ri->opaque; 326 if (s->pmnc & 1) { 327 return qemu_clock_get_ns(QEMU_CLOCK_VIRTUAL); 328 } else { 329 return 0; 330 } 331 } 332 333 static const ARMCPRegInfo pxa_cp_reginfo[] = { 334 /* cp14 crm==1: perf registers */ 335 { .name = "CPPMNC", .cp = 14, .crn = 0, .crm = 1, .opc1 = 0, .opc2 = 0, 336 .access = PL1_RW, 337 .readfn = pxa2xx_cppmnc_read, .writefn = pxa2xx_cppmnc_write }, 338 { .name = "CPCCNT", .cp = 14, .crn = 1, .crm = 1, .opc1 = 0, .opc2 = 0, 339 .access = PL1_RW, 340 .readfn = pxa2xx_cpccnt_read, .writefn = arm_cp_write_ignore }, 341 { .name = "CPINTEN", .cp = 14, .crn = 4, .crm = 1, .opc1 = 0, .opc2 = 0, 342 .access = PL1_RW, .type = ARM_CP_CONST, .resetvalue = 0 }, 343 { .name = "CPFLAG", .cp = 14, .crn = 5, .crm = 1, .opc1 = 0, .opc2 = 0, 344 .access = PL1_RW, .type = ARM_CP_CONST, .resetvalue = 0 }, 345 { .name = "CPEVTSEL", .cp = 14, .crn = 8, .crm = 1, .opc1 = 0, .opc2 = 0, 346 .access = PL1_RW, .type = ARM_CP_CONST, .resetvalue = 0 }, 347 /* cp14 crm==2: performance count registers */ 348 { .name = "CPPMN0", .cp = 14, .crn = 0, .crm = 2, .opc1 = 0, .opc2 = 0, 349 .access = PL1_RW, .type = ARM_CP_CONST, .resetvalue = 0 }, 350 { .name = "CPPMN1", .cp = 14, .crn = 1, .crm = 2, .opc1 = 0, .opc2 = 0, 351 .access = PL1_RW, .type = ARM_CP_CONST, .resetvalue = 0 }, 352 { .name = "CPPMN2", .cp = 14, .crn = 2, .crm = 2, .opc1 = 0, .opc2 = 0, 353 .access = PL1_RW, .type = ARM_CP_CONST, .resetvalue = 0 }, 354 { .name = "CPPMN3", .cp = 14, .crn = 2, .crm = 3, .opc1 = 0, .opc2 = 0, 355 .access = PL1_RW, .type = ARM_CP_CONST, .resetvalue = 0 }, 356 /* cp14 crn==6: CLKCFG */ 357 { .name = "CLKCFG", .cp = 14, .crn = 6, .crm = 0, .opc1 = 0, .opc2 = 0, 358 .access = PL1_RW, 359 .readfn = pxa2xx_clkcfg_read, .writefn = pxa2xx_clkcfg_write }, 360 /* cp14 crn==7: PWRMODE */ 361 { .name = "PWRMODE", .cp = 14, .crn = 7, .crm = 0, .opc1 = 0, .opc2 = 0, 362 .access = PL1_RW, 363 .readfn = arm_cp_read_zero, .writefn = pxa2xx_pwrmode_write }, 364 REGINFO_SENTINEL 365 }; 366 367 static void pxa2xx_setup_cp14(PXA2xxState *s) 368 { 369 define_arm_cp_regs_with_opaque(s->cpu, pxa_cp_reginfo, s); 370 } 371 372 #define MDCNFG 0x00 /* SDRAM Configuration register */ 373 #define MDREFR 0x04 /* SDRAM Refresh Control register */ 374 #define MSC0 0x08 /* Static Memory Control register 0 */ 375 #define MSC1 0x0c /* Static Memory Control register 1 */ 376 #define MSC2 0x10 /* Static Memory Control register 2 */ 377 #define MECR 0x14 /* Expansion Memory Bus Config register */ 378 #define SXCNFG 0x1c /* Synchronous Static Memory Config register */ 379 #define MCMEM0 0x28 /* PC Card Memory Socket 0 Timing register */ 380 #define MCMEM1 0x2c /* PC Card Memory Socket 1 Timing register */ 381 #define MCATT0 0x30 /* PC Card Attribute Socket 0 register */ 382 #define MCATT1 0x34 /* PC Card Attribute Socket 1 register */ 383 #define MCIO0 0x38 /* PC Card I/O Socket 0 Timing register */ 384 #define MCIO1 0x3c /* PC Card I/O Socket 1 Timing register */ 385 #define MDMRS 0x40 /* SDRAM Mode Register Set Config register */ 386 #define BOOT_DEF 0x44 /* Boot-time Default Configuration register */ 387 #define ARB_CNTL 0x48 /* Arbiter Control register */ 388 #define BSCNTR0 0x4c /* Memory Buffer Strength Control register 0 */ 389 #define BSCNTR1 0x50 /* Memory Buffer Strength Control register 1 */ 390 #define LCDBSCNTR 0x54 /* LCD Buffer Strength Control register */ 391 #define MDMRSLP 0x58 /* Low Power SDRAM Mode Set Config register */ 392 #define BSCNTR2 0x5c /* Memory Buffer Strength Control register 2 */ 393 #define BSCNTR3 0x60 /* Memory Buffer Strength Control register 3 */ 394 #define SA1110 0x64 /* SA-1110 Memory Compatibility register */ 395 396 static uint64_t pxa2xx_mm_read(void *opaque, hwaddr addr, 397 unsigned size) 398 { 399 PXA2xxState *s = (PXA2xxState *) opaque; 400 401 switch (addr) { 402 case MDCNFG ... SA1110: 403 if ((addr & 3) == 0) 404 return s->mm_regs[addr >> 2]; 405 406 default: 407 printf("%s: Bad register " REG_FMT "\n", __FUNCTION__, addr); 408 break; 409 } 410 return 0; 411 } 412 413 static void pxa2xx_mm_write(void *opaque, hwaddr addr, 414 uint64_t value, unsigned size) 415 { 416 PXA2xxState *s = (PXA2xxState *) opaque; 417 418 switch (addr) { 419 case MDCNFG ... SA1110: 420 if ((addr & 3) == 0) { 421 s->mm_regs[addr >> 2] = value; 422 break; 423 } 424 425 default: 426 printf("%s: Bad register " REG_FMT "\n", __FUNCTION__, addr); 427 break; 428 } 429 } 430 431 static const MemoryRegionOps pxa2xx_mm_ops = { 432 .read = pxa2xx_mm_read, 433 .write = pxa2xx_mm_write, 434 .endianness = DEVICE_NATIVE_ENDIAN, 435 }; 436 437 static const VMStateDescription vmstate_pxa2xx_mm = { 438 .name = "pxa2xx_mm", 439 .version_id = 0, 440 .minimum_version_id = 0, 441 .fields = (VMStateField[]) { 442 VMSTATE_UINT32_ARRAY(mm_regs, PXA2xxState, 0x1a), 443 VMSTATE_END_OF_LIST() 444 } 445 }; 446 447 #define TYPE_PXA2XX_SSP "pxa2xx-ssp" 448 #define PXA2XX_SSP(obj) \ 449 OBJECT_CHECK(PXA2xxSSPState, (obj), TYPE_PXA2XX_SSP) 450 451 /* Synchronous Serial Ports */ 452 typedef struct { 453 /*< private >*/ 454 SysBusDevice parent_obj; 455 /*< public >*/ 456 457 MemoryRegion iomem; 458 qemu_irq irq; 459 int enable; 460 SSIBus *bus; 461 462 uint32_t sscr[2]; 463 uint32_t sspsp; 464 uint32_t ssto; 465 uint32_t ssitr; 466 uint32_t sssr; 467 uint8_t sstsa; 468 uint8_t ssrsa; 469 uint8_t ssacd; 470 471 uint32_t rx_fifo[16]; 472 int rx_level; 473 int rx_start; 474 } PXA2xxSSPState; 475 476 #define SSCR0 0x00 /* SSP Control register 0 */ 477 #define SSCR1 0x04 /* SSP Control register 1 */ 478 #define SSSR 0x08 /* SSP Status register */ 479 #define SSITR 0x0c /* SSP Interrupt Test register */ 480 #define SSDR 0x10 /* SSP Data register */ 481 #define SSTO 0x28 /* SSP Time-Out register */ 482 #define SSPSP 0x2c /* SSP Programmable Serial Protocol register */ 483 #define SSTSA 0x30 /* SSP TX Time Slot Active register */ 484 #define SSRSA 0x34 /* SSP RX Time Slot Active register */ 485 #define SSTSS 0x38 /* SSP Time Slot Status register */ 486 #define SSACD 0x3c /* SSP Audio Clock Divider register */ 487 488 /* Bitfields for above registers */ 489 #define SSCR0_SPI(x) (((x) & 0x30) == 0x00) 490 #define SSCR0_SSP(x) (((x) & 0x30) == 0x10) 491 #define SSCR0_UWIRE(x) (((x) & 0x30) == 0x20) 492 #define SSCR0_PSP(x) (((x) & 0x30) == 0x30) 493 #define SSCR0_SSE (1 << 7) 494 #define SSCR0_RIM (1 << 22) 495 #define SSCR0_TIM (1 << 23) 496 #define SSCR0_MOD (1U << 31) 497 #define SSCR0_DSS(x) (((((x) >> 16) & 0x10) | ((x) & 0xf)) + 1) 498 #define SSCR1_RIE (1 << 0) 499 #define SSCR1_TIE (1 << 1) 500 #define SSCR1_LBM (1 << 2) 501 #define SSCR1_MWDS (1 << 5) 502 #define SSCR1_TFT(x) ((((x) >> 6) & 0xf) + 1) 503 #define SSCR1_RFT(x) ((((x) >> 10) & 0xf) + 1) 504 #define SSCR1_EFWR (1 << 14) 505 #define SSCR1_PINTE (1 << 18) 506 #define SSCR1_TINTE (1 << 19) 507 #define SSCR1_RSRE (1 << 20) 508 #define SSCR1_TSRE (1 << 21) 509 #define SSCR1_EBCEI (1 << 29) 510 #define SSITR_INT (7 << 5) 511 #define SSSR_TNF (1 << 2) 512 #define SSSR_RNE (1 << 3) 513 #define SSSR_TFS (1 << 5) 514 #define SSSR_RFS (1 << 6) 515 #define SSSR_ROR (1 << 7) 516 #define SSSR_PINT (1 << 18) 517 #define SSSR_TINT (1 << 19) 518 #define SSSR_EOC (1 << 20) 519 #define SSSR_TUR (1 << 21) 520 #define SSSR_BCE (1 << 23) 521 #define SSSR_RW 0x00bc0080 522 523 static void pxa2xx_ssp_int_update(PXA2xxSSPState *s) 524 { 525 int level = 0; 526 527 level |= s->ssitr & SSITR_INT; 528 level |= (s->sssr & SSSR_BCE) && (s->sscr[1] & SSCR1_EBCEI); 529 level |= (s->sssr & SSSR_TUR) && !(s->sscr[0] & SSCR0_TIM); 530 level |= (s->sssr & SSSR_EOC) && (s->sssr & (SSSR_TINT | SSSR_PINT)); 531 level |= (s->sssr & SSSR_TINT) && (s->sscr[1] & SSCR1_TINTE); 532 level |= (s->sssr & SSSR_PINT) && (s->sscr[1] & SSCR1_PINTE); 533 level |= (s->sssr & SSSR_ROR) && !(s->sscr[0] & SSCR0_RIM); 534 level |= (s->sssr & SSSR_RFS) && (s->sscr[1] & SSCR1_RIE); 535 level |= (s->sssr & SSSR_TFS) && (s->sscr[1] & SSCR1_TIE); 536 qemu_set_irq(s->irq, !!level); 537 } 538 539 static void pxa2xx_ssp_fifo_update(PXA2xxSSPState *s) 540 { 541 s->sssr &= ~(0xf << 12); /* Clear RFL */ 542 s->sssr &= ~(0xf << 8); /* Clear TFL */ 543 s->sssr &= ~SSSR_TFS; 544 s->sssr &= ~SSSR_TNF; 545 if (s->enable) { 546 s->sssr |= ((s->rx_level - 1) & 0xf) << 12; 547 if (s->rx_level >= SSCR1_RFT(s->sscr[1])) 548 s->sssr |= SSSR_RFS; 549 else 550 s->sssr &= ~SSSR_RFS; 551 if (s->rx_level) 552 s->sssr |= SSSR_RNE; 553 else 554 s->sssr &= ~SSSR_RNE; 555 /* TX FIFO is never filled, so it is always in underrun 556 condition if SSP is enabled */ 557 s->sssr |= SSSR_TFS; 558 s->sssr |= SSSR_TNF; 559 } 560 561 pxa2xx_ssp_int_update(s); 562 } 563 564 static uint64_t pxa2xx_ssp_read(void *opaque, hwaddr addr, 565 unsigned size) 566 { 567 PXA2xxSSPState *s = (PXA2xxSSPState *) opaque; 568 uint32_t retval; 569 570 switch (addr) { 571 case SSCR0: 572 return s->sscr[0]; 573 case SSCR1: 574 return s->sscr[1]; 575 case SSPSP: 576 return s->sspsp; 577 case SSTO: 578 return s->ssto; 579 case SSITR: 580 return s->ssitr; 581 case SSSR: 582 return s->sssr | s->ssitr; 583 case SSDR: 584 if (!s->enable) 585 return 0xffffffff; 586 if (s->rx_level < 1) { 587 printf("%s: SSP Rx Underrun\n", __FUNCTION__); 588 return 0xffffffff; 589 } 590 s->rx_level --; 591 retval = s->rx_fifo[s->rx_start ++]; 592 s->rx_start &= 0xf; 593 pxa2xx_ssp_fifo_update(s); 594 return retval; 595 case SSTSA: 596 return s->sstsa; 597 case SSRSA: 598 return s->ssrsa; 599 case SSTSS: 600 return 0; 601 case SSACD: 602 return s->ssacd; 603 default: 604 printf("%s: Bad register " REG_FMT "\n", __FUNCTION__, addr); 605 break; 606 } 607 return 0; 608 } 609 610 static void pxa2xx_ssp_write(void *opaque, hwaddr addr, 611 uint64_t value64, unsigned size) 612 { 613 PXA2xxSSPState *s = (PXA2xxSSPState *) opaque; 614 uint32_t value = value64; 615 616 switch (addr) { 617 case SSCR0: 618 s->sscr[0] = value & 0xc7ffffff; 619 s->enable = value & SSCR0_SSE; 620 if (value & SSCR0_MOD) 621 printf("%s: Attempt to use network mode\n", __FUNCTION__); 622 if (s->enable && SSCR0_DSS(value) < 4) 623 printf("%s: Wrong data size: %i bits\n", __FUNCTION__, 624 SSCR0_DSS(value)); 625 if (!(value & SSCR0_SSE)) { 626 s->sssr = 0; 627 s->ssitr = 0; 628 s->rx_level = 0; 629 } 630 pxa2xx_ssp_fifo_update(s); 631 break; 632 633 case SSCR1: 634 s->sscr[1] = value; 635 if (value & (SSCR1_LBM | SSCR1_EFWR)) 636 printf("%s: Attempt to use SSP test mode\n", __FUNCTION__); 637 pxa2xx_ssp_fifo_update(s); 638 break; 639 640 case SSPSP: 641 s->sspsp = value; 642 break; 643 644 case SSTO: 645 s->ssto = value; 646 break; 647 648 case SSITR: 649 s->ssitr = value & SSITR_INT; 650 pxa2xx_ssp_int_update(s); 651 break; 652 653 case SSSR: 654 s->sssr &= ~(value & SSSR_RW); 655 pxa2xx_ssp_int_update(s); 656 break; 657 658 case SSDR: 659 if (SSCR0_UWIRE(s->sscr[0])) { 660 if (s->sscr[1] & SSCR1_MWDS) 661 value &= 0xffff; 662 else 663 value &= 0xff; 664 } else 665 /* Note how 32bits overflow does no harm here */ 666 value &= (1 << SSCR0_DSS(s->sscr[0])) - 1; 667 668 /* Data goes from here to the Tx FIFO and is shifted out from 669 * there directly to the slave, no need to buffer it. 670 */ 671 if (s->enable) { 672 uint32_t readval; 673 readval = ssi_transfer(s->bus, value); 674 if (s->rx_level < 0x10) { 675 s->rx_fifo[(s->rx_start + s->rx_level ++) & 0xf] = readval; 676 } else { 677 s->sssr |= SSSR_ROR; 678 } 679 } 680 pxa2xx_ssp_fifo_update(s); 681 break; 682 683 case SSTSA: 684 s->sstsa = value; 685 break; 686 687 case SSRSA: 688 s->ssrsa = value; 689 break; 690 691 case SSACD: 692 s->ssacd = value; 693 break; 694 695 default: 696 printf("%s: Bad register " REG_FMT "\n", __FUNCTION__, addr); 697 break; 698 } 699 } 700 701 static const MemoryRegionOps pxa2xx_ssp_ops = { 702 .read = pxa2xx_ssp_read, 703 .write = pxa2xx_ssp_write, 704 .endianness = DEVICE_NATIVE_ENDIAN, 705 }; 706 707 static void pxa2xx_ssp_save(QEMUFile *f, void *opaque) 708 { 709 PXA2xxSSPState *s = (PXA2xxSSPState *) opaque; 710 int i; 711 712 qemu_put_be32(f, s->enable); 713 714 qemu_put_be32s(f, &s->sscr[0]); 715 qemu_put_be32s(f, &s->sscr[1]); 716 qemu_put_be32s(f, &s->sspsp); 717 qemu_put_be32s(f, &s->ssto); 718 qemu_put_be32s(f, &s->ssitr); 719 qemu_put_be32s(f, &s->sssr); 720 qemu_put_8s(f, &s->sstsa); 721 qemu_put_8s(f, &s->ssrsa); 722 qemu_put_8s(f, &s->ssacd); 723 724 qemu_put_byte(f, s->rx_level); 725 for (i = 0; i < s->rx_level; i ++) 726 qemu_put_byte(f, s->rx_fifo[(s->rx_start + i) & 0xf]); 727 } 728 729 static int pxa2xx_ssp_load(QEMUFile *f, void *opaque, int version_id) 730 { 731 PXA2xxSSPState *s = (PXA2xxSSPState *) opaque; 732 int i, v; 733 734 s->enable = qemu_get_be32(f); 735 736 qemu_get_be32s(f, &s->sscr[0]); 737 qemu_get_be32s(f, &s->sscr[1]); 738 qemu_get_be32s(f, &s->sspsp); 739 qemu_get_be32s(f, &s->ssto); 740 qemu_get_be32s(f, &s->ssitr); 741 qemu_get_be32s(f, &s->sssr); 742 qemu_get_8s(f, &s->sstsa); 743 qemu_get_8s(f, &s->ssrsa); 744 qemu_get_8s(f, &s->ssacd); 745 746 v = qemu_get_byte(f); 747 if (v < 0 || v > ARRAY_SIZE(s->rx_fifo)) { 748 return -EINVAL; 749 } 750 s->rx_level = v; 751 s->rx_start = 0; 752 for (i = 0; i < s->rx_level; i ++) 753 s->rx_fifo[i] = qemu_get_byte(f); 754 755 return 0; 756 } 757 758 static int pxa2xx_ssp_init(SysBusDevice *sbd) 759 { 760 DeviceState *dev = DEVICE(sbd); 761 PXA2xxSSPState *s = PXA2XX_SSP(dev); 762 763 sysbus_init_irq(sbd, &s->irq); 764 765 memory_region_init_io(&s->iomem, OBJECT(s), &pxa2xx_ssp_ops, s, 766 "pxa2xx-ssp", 0x1000); 767 sysbus_init_mmio(sbd, &s->iomem); 768 register_savevm(dev, "pxa2xx_ssp", -1, 0, 769 pxa2xx_ssp_save, pxa2xx_ssp_load, s); 770 771 s->bus = ssi_create_bus(dev, "ssi"); 772 return 0; 773 } 774 775 /* Real-Time Clock */ 776 #define RCNR 0x00 /* RTC Counter register */ 777 #define RTAR 0x04 /* RTC Alarm register */ 778 #define RTSR 0x08 /* RTC Status register */ 779 #define RTTR 0x0c /* RTC Timer Trim register */ 780 #define RDCR 0x10 /* RTC Day Counter register */ 781 #define RYCR 0x14 /* RTC Year Counter register */ 782 #define RDAR1 0x18 /* RTC Wristwatch Day Alarm register 1 */ 783 #define RYAR1 0x1c /* RTC Wristwatch Year Alarm register 1 */ 784 #define RDAR2 0x20 /* RTC Wristwatch Day Alarm register 2 */ 785 #define RYAR2 0x24 /* RTC Wristwatch Year Alarm register 2 */ 786 #define SWCR 0x28 /* RTC Stopwatch Counter register */ 787 #define SWAR1 0x2c /* RTC Stopwatch Alarm register 1 */ 788 #define SWAR2 0x30 /* RTC Stopwatch Alarm register 2 */ 789 #define RTCPICR 0x34 /* RTC Periodic Interrupt Counter register */ 790 #define PIAR 0x38 /* RTC Periodic Interrupt Alarm register */ 791 792 #define TYPE_PXA2XX_RTC "pxa2xx_rtc" 793 #define PXA2XX_RTC(obj) \ 794 OBJECT_CHECK(PXA2xxRTCState, (obj), TYPE_PXA2XX_RTC) 795 796 typedef struct { 797 /*< private >*/ 798 SysBusDevice parent_obj; 799 /*< public >*/ 800 801 MemoryRegion iomem; 802 uint32_t rttr; 803 uint32_t rtsr; 804 uint32_t rtar; 805 uint32_t rdar1; 806 uint32_t rdar2; 807 uint32_t ryar1; 808 uint32_t ryar2; 809 uint32_t swar1; 810 uint32_t swar2; 811 uint32_t piar; 812 uint32_t last_rcnr; 813 uint32_t last_rdcr; 814 uint32_t last_rycr; 815 uint32_t last_swcr; 816 uint32_t last_rtcpicr; 817 int64_t last_hz; 818 int64_t last_sw; 819 int64_t last_pi; 820 QEMUTimer *rtc_hz; 821 QEMUTimer *rtc_rdal1; 822 QEMUTimer *rtc_rdal2; 823 QEMUTimer *rtc_swal1; 824 QEMUTimer *rtc_swal2; 825 QEMUTimer *rtc_pi; 826 qemu_irq rtc_irq; 827 } PXA2xxRTCState; 828 829 static inline void pxa2xx_rtc_int_update(PXA2xxRTCState *s) 830 { 831 qemu_set_irq(s->rtc_irq, !!(s->rtsr & 0x2553)); 832 } 833 834 static void pxa2xx_rtc_hzupdate(PXA2xxRTCState *s) 835 { 836 int64_t rt = qemu_clock_get_ms(rtc_clock); 837 s->last_rcnr += ((rt - s->last_hz) << 15) / 838 (1000 * ((s->rttr & 0xffff) + 1)); 839 s->last_rdcr += ((rt - s->last_hz) << 15) / 840 (1000 * ((s->rttr & 0xffff) + 1)); 841 s->last_hz = rt; 842 } 843 844 static void pxa2xx_rtc_swupdate(PXA2xxRTCState *s) 845 { 846 int64_t rt = qemu_clock_get_ms(rtc_clock); 847 if (s->rtsr & (1 << 12)) 848 s->last_swcr += (rt - s->last_sw) / 10; 849 s->last_sw = rt; 850 } 851 852 static void pxa2xx_rtc_piupdate(PXA2xxRTCState *s) 853 { 854 int64_t rt = qemu_clock_get_ms(rtc_clock); 855 if (s->rtsr & (1 << 15)) 856 s->last_swcr += rt - s->last_pi; 857 s->last_pi = rt; 858 } 859 860 static inline void pxa2xx_rtc_alarm_update(PXA2xxRTCState *s, 861 uint32_t rtsr) 862 { 863 if ((rtsr & (1 << 2)) && !(rtsr & (1 << 0))) 864 timer_mod(s->rtc_hz, s->last_hz + 865 (((s->rtar - s->last_rcnr) * 1000 * 866 ((s->rttr & 0xffff) + 1)) >> 15)); 867 else 868 timer_del(s->rtc_hz); 869 870 if ((rtsr & (1 << 5)) && !(rtsr & (1 << 4))) 871 timer_mod(s->rtc_rdal1, s->last_hz + 872 (((s->rdar1 - s->last_rdcr) * 1000 * 873 ((s->rttr & 0xffff) + 1)) >> 15)); /* TODO: fixup */ 874 else 875 timer_del(s->rtc_rdal1); 876 877 if ((rtsr & (1 << 7)) && !(rtsr & (1 << 6))) 878 timer_mod(s->rtc_rdal2, s->last_hz + 879 (((s->rdar2 - s->last_rdcr) * 1000 * 880 ((s->rttr & 0xffff) + 1)) >> 15)); /* TODO: fixup */ 881 else 882 timer_del(s->rtc_rdal2); 883 884 if ((rtsr & 0x1200) == 0x1200 && !(rtsr & (1 << 8))) 885 timer_mod(s->rtc_swal1, s->last_sw + 886 (s->swar1 - s->last_swcr) * 10); /* TODO: fixup */ 887 else 888 timer_del(s->rtc_swal1); 889 890 if ((rtsr & 0x1800) == 0x1800 && !(rtsr & (1 << 10))) 891 timer_mod(s->rtc_swal2, s->last_sw + 892 (s->swar2 - s->last_swcr) * 10); /* TODO: fixup */ 893 else 894 timer_del(s->rtc_swal2); 895 896 if ((rtsr & 0xc000) == 0xc000 && !(rtsr & (1 << 13))) 897 timer_mod(s->rtc_pi, s->last_pi + 898 (s->piar & 0xffff) - s->last_rtcpicr); 899 else 900 timer_del(s->rtc_pi); 901 } 902 903 static inline void pxa2xx_rtc_hz_tick(void *opaque) 904 { 905 PXA2xxRTCState *s = (PXA2xxRTCState *) opaque; 906 s->rtsr |= (1 << 0); 907 pxa2xx_rtc_alarm_update(s, s->rtsr); 908 pxa2xx_rtc_int_update(s); 909 } 910 911 static inline void pxa2xx_rtc_rdal1_tick(void *opaque) 912 { 913 PXA2xxRTCState *s = (PXA2xxRTCState *) opaque; 914 s->rtsr |= (1 << 4); 915 pxa2xx_rtc_alarm_update(s, s->rtsr); 916 pxa2xx_rtc_int_update(s); 917 } 918 919 static inline void pxa2xx_rtc_rdal2_tick(void *opaque) 920 { 921 PXA2xxRTCState *s = (PXA2xxRTCState *) opaque; 922 s->rtsr |= (1 << 6); 923 pxa2xx_rtc_alarm_update(s, s->rtsr); 924 pxa2xx_rtc_int_update(s); 925 } 926 927 static inline void pxa2xx_rtc_swal1_tick(void *opaque) 928 { 929 PXA2xxRTCState *s = (PXA2xxRTCState *) opaque; 930 s->rtsr |= (1 << 8); 931 pxa2xx_rtc_alarm_update(s, s->rtsr); 932 pxa2xx_rtc_int_update(s); 933 } 934 935 static inline void pxa2xx_rtc_swal2_tick(void *opaque) 936 { 937 PXA2xxRTCState *s = (PXA2xxRTCState *) opaque; 938 s->rtsr |= (1 << 10); 939 pxa2xx_rtc_alarm_update(s, s->rtsr); 940 pxa2xx_rtc_int_update(s); 941 } 942 943 static inline void pxa2xx_rtc_pi_tick(void *opaque) 944 { 945 PXA2xxRTCState *s = (PXA2xxRTCState *) opaque; 946 s->rtsr |= (1 << 13); 947 pxa2xx_rtc_piupdate(s); 948 s->last_rtcpicr = 0; 949 pxa2xx_rtc_alarm_update(s, s->rtsr); 950 pxa2xx_rtc_int_update(s); 951 } 952 953 static uint64_t pxa2xx_rtc_read(void *opaque, hwaddr addr, 954 unsigned size) 955 { 956 PXA2xxRTCState *s = (PXA2xxRTCState *) opaque; 957 958 switch (addr) { 959 case RTTR: 960 return s->rttr; 961 case RTSR: 962 return s->rtsr; 963 case RTAR: 964 return s->rtar; 965 case RDAR1: 966 return s->rdar1; 967 case RDAR2: 968 return s->rdar2; 969 case RYAR1: 970 return s->ryar1; 971 case RYAR2: 972 return s->ryar2; 973 case SWAR1: 974 return s->swar1; 975 case SWAR2: 976 return s->swar2; 977 case PIAR: 978 return s->piar; 979 case RCNR: 980 return s->last_rcnr + 981 ((qemu_clock_get_ms(rtc_clock) - s->last_hz) << 15) / 982 (1000 * ((s->rttr & 0xffff) + 1)); 983 case RDCR: 984 return s->last_rdcr + 985 ((qemu_clock_get_ms(rtc_clock) - s->last_hz) << 15) / 986 (1000 * ((s->rttr & 0xffff) + 1)); 987 case RYCR: 988 return s->last_rycr; 989 case SWCR: 990 if (s->rtsr & (1 << 12)) 991 return s->last_swcr + 992 (qemu_clock_get_ms(rtc_clock) - s->last_sw) / 10; 993 else 994 return s->last_swcr; 995 default: 996 printf("%s: Bad register " REG_FMT "\n", __FUNCTION__, addr); 997 break; 998 } 999 return 0; 1000 } 1001 1002 static void pxa2xx_rtc_write(void *opaque, hwaddr addr, 1003 uint64_t value64, unsigned size) 1004 { 1005 PXA2xxRTCState *s = (PXA2xxRTCState *) opaque; 1006 uint32_t value = value64; 1007 1008 switch (addr) { 1009 case RTTR: 1010 if (!(s->rttr & (1U << 31))) { 1011 pxa2xx_rtc_hzupdate(s); 1012 s->rttr = value; 1013 pxa2xx_rtc_alarm_update(s, s->rtsr); 1014 } 1015 break; 1016 1017 case RTSR: 1018 if ((s->rtsr ^ value) & (1 << 15)) 1019 pxa2xx_rtc_piupdate(s); 1020 1021 if ((s->rtsr ^ value) & (1 << 12)) 1022 pxa2xx_rtc_swupdate(s); 1023 1024 if (((s->rtsr ^ value) & 0x4aac) | (value & ~0xdaac)) 1025 pxa2xx_rtc_alarm_update(s, value); 1026 1027 s->rtsr = (value & 0xdaac) | (s->rtsr & ~(value & ~0xdaac)); 1028 pxa2xx_rtc_int_update(s); 1029 break; 1030 1031 case RTAR: 1032 s->rtar = value; 1033 pxa2xx_rtc_alarm_update(s, s->rtsr); 1034 break; 1035 1036 case RDAR1: 1037 s->rdar1 = value; 1038 pxa2xx_rtc_alarm_update(s, s->rtsr); 1039 break; 1040 1041 case RDAR2: 1042 s->rdar2 = value; 1043 pxa2xx_rtc_alarm_update(s, s->rtsr); 1044 break; 1045 1046 case RYAR1: 1047 s->ryar1 = value; 1048 pxa2xx_rtc_alarm_update(s, s->rtsr); 1049 break; 1050 1051 case RYAR2: 1052 s->ryar2 = value; 1053 pxa2xx_rtc_alarm_update(s, s->rtsr); 1054 break; 1055 1056 case SWAR1: 1057 pxa2xx_rtc_swupdate(s); 1058 s->swar1 = value; 1059 s->last_swcr = 0; 1060 pxa2xx_rtc_alarm_update(s, s->rtsr); 1061 break; 1062 1063 case SWAR2: 1064 s->swar2 = value; 1065 pxa2xx_rtc_alarm_update(s, s->rtsr); 1066 break; 1067 1068 case PIAR: 1069 s->piar = value; 1070 pxa2xx_rtc_alarm_update(s, s->rtsr); 1071 break; 1072 1073 case RCNR: 1074 pxa2xx_rtc_hzupdate(s); 1075 s->last_rcnr = value; 1076 pxa2xx_rtc_alarm_update(s, s->rtsr); 1077 break; 1078 1079 case RDCR: 1080 pxa2xx_rtc_hzupdate(s); 1081 s->last_rdcr = value; 1082 pxa2xx_rtc_alarm_update(s, s->rtsr); 1083 break; 1084 1085 case RYCR: 1086 s->last_rycr = value; 1087 break; 1088 1089 case SWCR: 1090 pxa2xx_rtc_swupdate(s); 1091 s->last_swcr = value; 1092 pxa2xx_rtc_alarm_update(s, s->rtsr); 1093 break; 1094 1095 case RTCPICR: 1096 pxa2xx_rtc_piupdate(s); 1097 s->last_rtcpicr = value & 0xffff; 1098 pxa2xx_rtc_alarm_update(s, s->rtsr); 1099 break; 1100 1101 default: 1102 printf("%s: Bad register " REG_FMT "\n", __FUNCTION__, addr); 1103 } 1104 } 1105 1106 static const MemoryRegionOps pxa2xx_rtc_ops = { 1107 .read = pxa2xx_rtc_read, 1108 .write = pxa2xx_rtc_write, 1109 .endianness = DEVICE_NATIVE_ENDIAN, 1110 }; 1111 1112 static int pxa2xx_rtc_init(SysBusDevice *dev) 1113 { 1114 PXA2xxRTCState *s = PXA2XX_RTC(dev); 1115 struct tm tm; 1116 int wom; 1117 1118 s->rttr = 0x7fff; 1119 s->rtsr = 0; 1120 1121 qemu_get_timedate(&tm, 0); 1122 wom = ((tm.tm_mday - 1) / 7) + 1; 1123 1124 s->last_rcnr = (uint32_t) mktimegm(&tm); 1125 s->last_rdcr = (wom << 20) | ((tm.tm_wday + 1) << 17) | 1126 (tm.tm_hour << 12) | (tm.tm_min << 6) | tm.tm_sec; 1127 s->last_rycr = ((tm.tm_year + 1900) << 9) | 1128 ((tm.tm_mon + 1) << 5) | tm.tm_mday; 1129 s->last_swcr = (tm.tm_hour << 19) | 1130 (tm.tm_min << 13) | (tm.tm_sec << 7); 1131 s->last_rtcpicr = 0; 1132 s->last_hz = s->last_sw = s->last_pi = qemu_clock_get_ms(rtc_clock); 1133 1134 s->rtc_hz = timer_new_ms(rtc_clock, pxa2xx_rtc_hz_tick, s); 1135 s->rtc_rdal1 = timer_new_ms(rtc_clock, pxa2xx_rtc_rdal1_tick, s); 1136 s->rtc_rdal2 = timer_new_ms(rtc_clock, pxa2xx_rtc_rdal2_tick, s); 1137 s->rtc_swal1 = timer_new_ms(rtc_clock, pxa2xx_rtc_swal1_tick, s); 1138 s->rtc_swal2 = timer_new_ms(rtc_clock, pxa2xx_rtc_swal2_tick, s); 1139 s->rtc_pi = timer_new_ms(rtc_clock, pxa2xx_rtc_pi_tick, s); 1140 1141 sysbus_init_irq(dev, &s->rtc_irq); 1142 1143 memory_region_init_io(&s->iomem, OBJECT(s), &pxa2xx_rtc_ops, s, 1144 "pxa2xx-rtc", 0x10000); 1145 sysbus_init_mmio(dev, &s->iomem); 1146 1147 return 0; 1148 } 1149 1150 static void pxa2xx_rtc_pre_save(void *opaque) 1151 { 1152 PXA2xxRTCState *s = (PXA2xxRTCState *) opaque; 1153 1154 pxa2xx_rtc_hzupdate(s); 1155 pxa2xx_rtc_piupdate(s); 1156 pxa2xx_rtc_swupdate(s); 1157 } 1158 1159 static int pxa2xx_rtc_post_load(void *opaque, int version_id) 1160 { 1161 PXA2xxRTCState *s = (PXA2xxRTCState *) opaque; 1162 1163 pxa2xx_rtc_alarm_update(s, s->rtsr); 1164 1165 return 0; 1166 } 1167 1168 static const VMStateDescription vmstate_pxa2xx_rtc_regs = { 1169 .name = "pxa2xx_rtc", 1170 .version_id = 0, 1171 .minimum_version_id = 0, 1172 .pre_save = pxa2xx_rtc_pre_save, 1173 .post_load = pxa2xx_rtc_post_load, 1174 .fields = (VMStateField[]) { 1175 VMSTATE_UINT32(rttr, PXA2xxRTCState), 1176 VMSTATE_UINT32(rtsr, PXA2xxRTCState), 1177 VMSTATE_UINT32(rtar, PXA2xxRTCState), 1178 VMSTATE_UINT32(rdar1, PXA2xxRTCState), 1179 VMSTATE_UINT32(rdar2, PXA2xxRTCState), 1180 VMSTATE_UINT32(ryar1, PXA2xxRTCState), 1181 VMSTATE_UINT32(ryar2, PXA2xxRTCState), 1182 VMSTATE_UINT32(swar1, PXA2xxRTCState), 1183 VMSTATE_UINT32(swar2, PXA2xxRTCState), 1184 VMSTATE_UINT32(piar, PXA2xxRTCState), 1185 VMSTATE_UINT32(last_rcnr, PXA2xxRTCState), 1186 VMSTATE_UINT32(last_rdcr, PXA2xxRTCState), 1187 VMSTATE_UINT32(last_rycr, PXA2xxRTCState), 1188 VMSTATE_UINT32(last_swcr, PXA2xxRTCState), 1189 VMSTATE_UINT32(last_rtcpicr, PXA2xxRTCState), 1190 VMSTATE_INT64(last_hz, PXA2xxRTCState), 1191 VMSTATE_INT64(last_sw, PXA2xxRTCState), 1192 VMSTATE_INT64(last_pi, PXA2xxRTCState), 1193 VMSTATE_END_OF_LIST(), 1194 }, 1195 }; 1196 1197 static void pxa2xx_rtc_sysbus_class_init(ObjectClass *klass, void *data) 1198 { 1199 DeviceClass *dc = DEVICE_CLASS(klass); 1200 SysBusDeviceClass *k = SYS_BUS_DEVICE_CLASS(klass); 1201 1202 k->init = pxa2xx_rtc_init; 1203 dc->desc = "PXA2xx RTC Controller"; 1204 dc->vmsd = &vmstate_pxa2xx_rtc_regs; 1205 } 1206 1207 static const TypeInfo pxa2xx_rtc_sysbus_info = { 1208 .name = TYPE_PXA2XX_RTC, 1209 .parent = TYPE_SYS_BUS_DEVICE, 1210 .instance_size = sizeof(PXA2xxRTCState), 1211 .class_init = pxa2xx_rtc_sysbus_class_init, 1212 }; 1213 1214 /* I2C Interface */ 1215 1216 #define TYPE_PXA2XX_I2C_SLAVE "pxa2xx-i2c-slave" 1217 #define PXA2XX_I2C_SLAVE(obj) \ 1218 OBJECT_CHECK(PXA2xxI2CSlaveState, (obj), TYPE_PXA2XX_I2C_SLAVE) 1219 1220 typedef struct PXA2xxI2CSlaveState { 1221 I2CSlave parent_obj; 1222 1223 PXA2xxI2CState *host; 1224 } PXA2xxI2CSlaveState; 1225 1226 #define TYPE_PXA2XX_I2C "pxa2xx_i2c" 1227 #define PXA2XX_I2C(obj) \ 1228 OBJECT_CHECK(PXA2xxI2CState, (obj), TYPE_PXA2XX_I2C) 1229 1230 struct PXA2xxI2CState { 1231 /*< private >*/ 1232 SysBusDevice parent_obj; 1233 /*< public >*/ 1234 1235 MemoryRegion iomem; 1236 PXA2xxI2CSlaveState *slave; 1237 I2CBus *bus; 1238 qemu_irq irq; 1239 uint32_t offset; 1240 uint32_t region_size; 1241 1242 uint16_t control; 1243 uint16_t status; 1244 uint8_t ibmr; 1245 uint8_t data; 1246 }; 1247 1248 #define IBMR 0x80 /* I2C Bus Monitor register */ 1249 #define IDBR 0x88 /* I2C Data Buffer register */ 1250 #define ICR 0x90 /* I2C Control register */ 1251 #define ISR 0x98 /* I2C Status register */ 1252 #define ISAR 0xa0 /* I2C Slave Address register */ 1253 1254 static void pxa2xx_i2c_update(PXA2xxI2CState *s) 1255 { 1256 uint16_t level = 0; 1257 level |= s->status & s->control & (1 << 10); /* BED */ 1258 level |= (s->status & (1 << 7)) && (s->control & (1 << 9)); /* IRF */ 1259 level |= (s->status & (1 << 6)) && (s->control & (1 << 8)); /* ITE */ 1260 level |= s->status & (1 << 9); /* SAD */ 1261 qemu_set_irq(s->irq, !!level); 1262 } 1263 1264 /* These are only stubs now. */ 1265 static void pxa2xx_i2c_event(I2CSlave *i2c, enum i2c_event event) 1266 { 1267 PXA2xxI2CSlaveState *slave = PXA2XX_I2C_SLAVE(i2c); 1268 PXA2xxI2CState *s = slave->host; 1269 1270 switch (event) { 1271 case I2C_START_SEND: 1272 s->status |= (1 << 9); /* set SAD */ 1273 s->status &= ~(1 << 0); /* clear RWM */ 1274 break; 1275 case I2C_START_RECV: 1276 s->status |= (1 << 9); /* set SAD */ 1277 s->status |= 1 << 0; /* set RWM */ 1278 break; 1279 case I2C_FINISH: 1280 s->status |= (1 << 4); /* set SSD */ 1281 break; 1282 case I2C_NACK: 1283 s->status |= 1 << 1; /* set ACKNAK */ 1284 break; 1285 } 1286 pxa2xx_i2c_update(s); 1287 } 1288 1289 static int pxa2xx_i2c_rx(I2CSlave *i2c) 1290 { 1291 PXA2xxI2CSlaveState *slave = PXA2XX_I2C_SLAVE(i2c); 1292 PXA2xxI2CState *s = slave->host; 1293 1294 if ((s->control & (1 << 14)) || !(s->control & (1 << 6))) { 1295 return 0; 1296 } 1297 1298 if (s->status & (1 << 0)) { /* RWM */ 1299 s->status |= 1 << 6; /* set ITE */ 1300 } 1301 pxa2xx_i2c_update(s); 1302 1303 return s->data; 1304 } 1305 1306 static int pxa2xx_i2c_tx(I2CSlave *i2c, uint8_t data) 1307 { 1308 PXA2xxI2CSlaveState *slave = PXA2XX_I2C_SLAVE(i2c); 1309 PXA2xxI2CState *s = slave->host; 1310 1311 if ((s->control & (1 << 14)) || !(s->control & (1 << 6))) { 1312 return 1; 1313 } 1314 1315 if (!(s->status & (1 << 0))) { /* RWM */ 1316 s->status |= 1 << 7; /* set IRF */ 1317 s->data = data; 1318 } 1319 pxa2xx_i2c_update(s); 1320 1321 return 1; 1322 } 1323 1324 static uint64_t pxa2xx_i2c_read(void *opaque, hwaddr addr, 1325 unsigned size) 1326 { 1327 PXA2xxI2CState *s = (PXA2xxI2CState *) opaque; 1328 I2CSlave *slave; 1329 1330 addr -= s->offset; 1331 switch (addr) { 1332 case ICR: 1333 return s->control; 1334 case ISR: 1335 return s->status | (i2c_bus_busy(s->bus) << 2); 1336 case ISAR: 1337 slave = I2C_SLAVE(s->slave); 1338 return slave->address; 1339 case IDBR: 1340 return s->data; 1341 case IBMR: 1342 if (s->status & (1 << 2)) 1343 s->ibmr ^= 3; /* Fake SCL and SDA pin changes */ 1344 else 1345 s->ibmr = 0; 1346 return s->ibmr; 1347 default: 1348 printf("%s: Bad register " REG_FMT "\n", __FUNCTION__, addr); 1349 break; 1350 } 1351 return 0; 1352 } 1353 1354 static void pxa2xx_i2c_write(void *opaque, hwaddr addr, 1355 uint64_t value64, unsigned size) 1356 { 1357 PXA2xxI2CState *s = (PXA2xxI2CState *) opaque; 1358 uint32_t value = value64; 1359 int ack; 1360 1361 addr -= s->offset; 1362 switch (addr) { 1363 case ICR: 1364 s->control = value & 0xfff7; 1365 if ((value & (1 << 3)) && (value & (1 << 6))) { /* TB and IUE */ 1366 /* TODO: slave mode */ 1367 if (value & (1 << 0)) { /* START condition */ 1368 if (s->data & 1) 1369 s->status |= 1 << 0; /* set RWM */ 1370 else 1371 s->status &= ~(1 << 0); /* clear RWM */ 1372 ack = !i2c_start_transfer(s->bus, s->data >> 1, s->data & 1); 1373 } else { 1374 if (s->status & (1 << 0)) { /* RWM */ 1375 s->data = i2c_recv(s->bus); 1376 if (value & (1 << 2)) /* ACKNAK */ 1377 i2c_nack(s->bus); 1378 ack = 1; 1379 } else 1380 ack = !i2c_send(s->bus, s->data); 1381 } 1382 1383 if (value & (1 << 1)) /* STOP condition */ 1384 i2c_end_transfer(s->bus); 1385 1386 if (ack) { 1387 if (value & (1 << 0)) /* START condition */ 1388 s->status |= 1 << 6; /* set ITE */ 1389 else 1390 if (s->status & (1 << 0)) /* RWM */ 1391 s->status |= 1 << 7; /* set IRF */ 1392 else 1393 s->status |= 1 << 6; /* set ITE */ 1394 s->status &= ~(1 << 1); /* clear ACKNAK */ 1395 } else { 1396 s->status |= 1 << 6; /* set ITE */ 1397 s->status |= 1 << 10; /* set BED */ 1398 s->status |= 1 << 1; /* set ACKNAK */ 1399 } 1400 } 1401 if (!(value & (1 << 3)) && (value & (1 << 6))) /* !TB and IUE */ 1402 if (value & (1 << 4)) /* MA */ 1403 i2c_end_transfer(s->bus); 1404 pxa2xx_i2c_update(s); 1405 break; 1406 1407 case ISR: 1408 s->status &= ~(value & 0x07f0); 1409 pxa2xx_i2c_update(s); 1410 break; 1411 1412 case ISAR: 1413 i2c_set_slave_address(I2C_SLAVE(s->slave), value & 0x7f); 1414 break; 1415 1416 case IDBR: 1417 s->data = value & 0xff; 1418 break; 1419 1420 default: 1421 printf("%s: Bad register " REG_FMT "\n", __FUNCTION__, addr); 1422 } 1423 } 1424 1425 static const MemoryRegionOps pxa2xx_i2c_ops = { 1426 .read = pxa2xx_i2c_read, 1427 .write = pxa2xx_i2c_write, 1428 .endianness = DEVICE_NATIVE_ENDIAN, 1429 }; 1430 1431 static const VMStateDescription vmstate_pxa2xx_i2c_slave = { 1432 .name = "pxa2xx_i2c_slave", 1433 .version_id = 1, 1434 .minimum_version_id = 1, 1435 .fields = (VMStateField[]) { 1436 VMSTATE_I2C_SLAVE(parent_obj, PXA2xxI2CSlaveState), 1437 VMSTATE_END_OF_LIST() 1438 } 1439 }; 1440 1441 static const VMStateDescription vmstate_pxa2xx_i2c = { 1442 .name = "pxa2xx_i2c", 1443 .version_id = 1, 1444 .minimum_version_id = 1, 1445 .fields = (VMStateField[]) { 1446 VMSTATE_UINT16(control, PXA2xxI2CState), 1447 VMSTATE_UINT16(status, PXA2xxI2CState), 1448 VMSTATE_UINT8(ibmr, PXA2xxI2CState), 1449 VMSTATE_UINT8(data, PXA2xxI2CState), 1450 VMSTATE_STRUCT_POINTER(slave, PXA2xxI2CState, 1451 vmstate_pxa2xx_i2c_slave, PXA2xxI2CSlaveState), 1452 VMSTATE_END_OF_LIST() 1453 } 1454 }; 1455 1456 static int pxa2xx_i2c_slave_init(I2CSlave *i2c) 1457 { 1458 /* Nothing to do. */ 1459 return 0; 1460 } 1461 1462 static void pxa2xx_i2c_slave_class_init(ObjectClass *klass, void *data) 1463 { 1464 I2CSlaveClass *k = I2C_SLAVE_CLASS(klass); 1465 1466 k->init = pxa2xx_i2c_slave_init; 1467 k->event = pxa2xx_i2c_event; 1468 k->recv = pxa2xx_i2c_rx; 1469 k->send = pxa2xx_i2c_tx; 1470 } 1471 1472 static const TypeInfo pxa2xx_i2c_slave_info = { 1473 .name = TYPE_PXA2XX_I2C_SLAVE, 1474 .parent = TYPE_I2C_SLAVE, 1475 .instance_size = sizeof(PXA2xxI2CSlaveState), 1476 .class_init = pxa2xx_i2c_slave_class_init, 1477 }; 1478 1479 PXA2xxI2CState *pxa2xx_i2c_init(hwaddr base, 1480 qemu_irq irq, uint32_t region_size) 1481 { 1482 DeviceState *dev; 1483 SysBusDevice *i2c_dev; 1484 PXA2xxI2CState *s; 1485 I2CBus *i2cbus; 1486 1487 dev = qdev_create(NULL, TYPE_PXA2XX_I2C); 1488 qdev_prop_set_uint32(dev, "size", region_size + 1); 1489 qdev_prop_set_uint32(dev, "offset", base & region_size); 1490 qdev_init_nofail(dev); 1491 1492 i2c_dev = SYS_BUS_DEVICE(dev); 1493 sysbus_mmio_map(i2c_dev, 0, base & ~region_size); 1494 sysbus_connect_irq(i2c_dev, 0, irq); 1495 1496 s = PXA2XX_I2C(i2c_dev); 1497 /* FIXME: Should the slave device really be on a separate bus? */ 1498 i2cbus = i2c_init_bus(dev, "dummy"); 1499 dev = i2c_create_slave(i2cbus, TYPE_PXA2XX_I2C_SLAVE, 0); 1500 s->slave = PXA2XX_I2C_SLAVE(dev); 1501 s->slave->host = s; 1502 1503 return s; 1504 } 1505 1506 static int pxa2xx_i2c_initfn(SysBusDevice *sbd) 1507 { 1508 DeviceState *dev = DEVICE(sbd); 1509 PXA2xxI2CState *s = PXA2XX_I2C(dev); 1510 1511 s->bus = i2c_init_bus(dev, "i2c"); 1512 1513 memory_region_init_io(&s->iomem, OBJECT(s), &pxa2xx_i2c_ops, s, 1514 "pxa2xx-i2c", s->region_size); 1515 sysbus_init_mmio(sbd, &s->iomem); 1516 sysbus_init_irq(sbd, &s->irq); 1517 1518 return 0; 1519 } 1520 1521 I2CBus *pxa2xx_i2c_bus(PXA2xxI2CState *s) 1522 { 1523 return s->bus; 1524 } 1525 1526 static Property pxa2xx_i2c_properties[] = { 1527 DEFINE_PROP_UINT32("size", PXA2xxI2CState, region_size, 0x10000), 1528 DEFINE_PROP_UINT32("offset", PXA2xxI2CState, offset, 0), 1529 DEFINE_PROP_END_OF_LIST(), 1530 }; 1531 1532 static void pxa2xx_i2c_class_init(ObjectClass *klass, void *data) 1533 { 1534 DeviceClass *dc = DEVICE_CLASS(klass); 1535 SysBusDeviceClass *k = SYS_BUS_DEVICE_CLASS(klass); 1536 1537 k->init = pxa2xx_i2c_initfn; 1538 dc->desc = "PXA2xx I2C Bus Controller"; 1539 dc->vmsd = &vmstate_pxa2xx_i2c; 1540 dc->props = pxa2xx_i2c_properties; 1541 } 1542 1543 static const TypeInfo pxa2xx_i2c_info = { 1544 .name = TYPE_PXA2XX_I2C, 1545 .parent = TYPE_SYS_BUS_DEVICE, 1546 .instance_size = sizeof(PXA2xxI2CState), 1547 .class_init = pxa2xx_i2c_class_init, 1548 }; 1549 1550 /* PXA Inter-IC Sound Controller */ 1551 static void pxa2xx_i2s_reset(PXA2xxI2SState *i2s) 1552 { 1553 i2s->rx_len = 0; 1554 i2s->tx_len = 0; 1555 i2s->fifo_len = 0; 1556 i2s->clk = 0x1a; 1557 i2s->control[0] = 0x00; 1558 i2s->control[1] = 0x00; 1559 i2s->status = 0x00; 1560 i2s->mask = 0x00; 1561 } 1562 1563 #define SACR_TFTH(val) ((val >> 8) & 0xf) 1564 #define SACR_RFTH(val) ((val >> 12) & 0xf) 1565 #define SACR_DREC(val) (val & (1 << 3)) 1566 #define SACR_DPRL(val) (val & (1 << 4)) 1567 1568 static inline void pxa2xx_i2s_update(PXA2xxI2SState *i2s) 1569 { 1570 int rfs, tfs; 1571 rfs = SACR_RFTH(i2s->control[0]) < i2s->rx_len && 1572 !SACR_DREC(i2s->control[1]); 1573 tfs = (i2s->tx_len || i2s->fifo_len < SACR_TFTH(i2s->control[0])) && 1574 i2s->enable && !SACR_DPRL(i2s->control[1]); 1575 1576 qemu_set_irq(i2s->rx_dma, rfs); 1577 qemu_set_irq(i2s->tx_dma, tfs); 1578 1579 i2s->status &= 0xe0; 1580 if (i2s->fifo_len < 16 || !i2s->enable) 1581 i2s->status |= 1 << 0; /* TNF */ 1582 if (i2s->rx_len) 1583 i2s->status |= 1 << 1; /* RNE */ 1584 if (i2s->enable) 1585 i2s->status |= 1 << 2; /* BSY */ 1586 if (tfs) 1587 i2s->status |= 1 << 3; /* TFS */ 1588 if (rfs) 1589 i2s->status |= 1 << 4; /* RFS */ 1590 if (!(i2s->tx_len && i2s->enable)) 1591 i2s->status |= i2s->fifo_len << 8; /* TFL */ 1592 i2s->status |= MAX(i2s->rx_len, 0xf) << 12; /* RFL */ 1593 1594 qemu_set_irq(i2s->irq, i2s->status & i2s->mask); 1595 } 1596 1597 #define SACR0 0x00 /* Serial Audio Global Control register */ 1598 #define SACR1 0x04 /* Serial Audio I2S/MSB-Justified Control register */ 1599 #define SASR0 0x0c /* Serial Audio Interface and FIFO Status register */ 1600 #define SAIMR 0x14 /* Serial Audio Interrupt Mask register */ 1601 #define SAICR 0x18 /* Serial Audio Interrupt Clear register */ 1602 #define SADIV 0x60 /* Serial Audio Clock Divider register */ 1603 #define SADR 0x80 /* Serial Audio Data register */ 1604 1605 static uint64_t pxa2xx_i2s_read(void *opaque, hwaddr addr, 1606 unsigned size) 1607 { 1608 PXA2xxI2SState *s = (PXA2xxI2SState *) opaque; 1609 1610 switch (addr) { 1611 case SACR0: 1612 return s->control[0]; 1613 case SACR1: 1614 return s->control[1]; 1615 case SASR0: 1616 return s->status; 1617 case SAIMR: 1618 return s->mask; 1619 case SAICR: 1620 return 0; 1621 case SADIV: 1622 return s->clk; 1623 case SADR: 1624 if (s->rx_len > 0) { 1625 s->rx_len --; 1626 pxa2xx_i2s_update(s); 1627 return s->codec_in(s->opaque); 1628 } 1629 return 0; 1630 default: 1631 printf("%s: Bad register " REG_FMT "\n", __FUNCTION__, addr); 1632 break; 1633 } 1634 return 0; 1635 } 1636 1637 static void pxa2xx_i2s_write(void *opaque, hwaddr addr, 1638 uint64_t value, unsigned size) 1639 { 1640 PXA2xxI2SState *s = (PXA2xxI2SState *) opaque; 1641 uint32_t *sample; 1642 1643 switch (addr) { 1644 case SACR0: 1645 if (value & (1 << 3)) /* RST */ 1646 pxa2xx_i2s_reset(s); 1647 s->control[0] = value & 0xff3d; 1648 if (!s->enable && (value & 1) && s->tx_len) { /* ENB */ 1649 for (sample = s->fifo; s->fifo_len > 0; s->fifo_len --, sample ++) 1650 s->codec_out(s->opaque, *sample); 1651 s->status &= ~(1 << 7); /* I2SOFF */ 1652 } 1653 if (value & (1 << 4)) /* EFWR */ 1654 printf("%s: Attempt to use special function\n", __FUNCTION__); 1655 s->enable = (value & 9) == 1; /* ENB && !RST*/ 1656 pxa2xx_i2s_update(s); 1657 break; 1658 case SACR1: 1659 s->control[1] = value & 0x0039; 1660 if (value & (1 << 5)) /* ENLBF */ 1661 printf("%s: Attempt to use loopback function\n", __FUNCTION__); 1662 if (value & (1 << 4)) /* DPRL */ 1663 s->fifo_len = 0; 1664 pxa2xx_i2s_update(s); 1665 break; 1666 case SAIMR: 1667 s->mask = value & 0x0078; 1668 pxa2xx_i2s_update(s); 1669 break; 1670 case SAICR: 1671 s->status &= ~(value & (3 << 5)); 1672 pxa2xx_i2s_update(s); 1673 break; 1674 case SADIV: 1675 s->clk = value & 0x007f; 1676 break; 1677 case SADR: 1678 if (s->tx_len && s->enable) { 1679 s->tx_len --; 1680 pxa2xx_i2s_update(s); 1681 s->codec_out(s->opaque, value); 1682 } else if (s->fifo_len < 16) { 1683 s->fifo[s->fifo_len ++] = value; 1684 pxa2xx_i2s_update(s); 1685 } 1686 break; 1687 default: 1688 printf("%s: Bad register " REG_FMT "\n", __FUNCTION__, addr); 1689 } 1690 } 1691 1692 static const MemoryRegionOps pxa2xx_i2s_ops = { 1693 .read = pxa2xx_i2s_read, 1694 .write = pxa2xx_i2s_write, 1695 .endianness = DEVICE_NATIVE_ENDIAN, 1696 }; 1697 1698 static const VMStateDescription vmstate_pxa2xx_i2s = { 1699 .name = "pxa2xx_i2s", 1700 .version_id = 0, 1701 .minimum_version_id = 0, 1702 .fields = (VMStateField[]) { 1703 VMSTATE_UINT32_ARRAY(control, PXA2xxI2SState, 2), 1704 VMSTATE_UINT32(status, PXA2xxI2SState), 1705 VMSTATE_UINT32(mask, PXA2xxI2SState), 1706 VMSTATE_UINT32(clk, PXA2xxI2SState), 1707 VMSTATE_INT32(enable, PXA2xxI2SState), 1708 VMSTATE_INT32(rx_len, PXA2xxI2SState), 1709 VMSTATE_INT32(tx_len, PXA2xxI2SState), 1710 VMSTATE_INT32(fifo_len, PXA2xxI2SState), 1711 VMSTATE_END_OF_LIST() 1712 } 1713 }; 1714 1715 static void pxa2xx_i2s_data_req(void *opaque, int tx, int rx) 1716 { 1717 PXA2xxI2SState *s = (PXA2xxI2SState *) opaque; 1718 uint32_t *sample; 1719 1720 /* Signal FIFO errors */ 1721 if (s->enable && s->tx_len) 1722 s->status |= 1 << 5; /* TUR */ 1723 if (s->enable && s->rx_len) 1724 s->status |= 1 << 6; /* ROR */ 1725 1726 /* Should be tx - MIN(tx, s->fifo_len) but we don't really need to 1727 * handle the cases where it makes a difference. */ 1728 s->tx_len = tx - s->fifo_len; 1729 s->rx_len = rx; 1730 /* Note that is s->codec_out wasn't set, we wouldn't get called. */ 1731 if (s->enable) 1732 for (sample = s->fifo; s->fifo_len; s->fifo_len --, sample ++) 1733 s->codec_out(s->opaque, *sample); 1734 pxa2xx_i2s_update(s); 1735 } 1736 1737 static PXA2xxI2SState *pxa2xx_i2s_init(MemoryRegion *sysmem, 1738 hwaddr base, 1739 qemu_irq irq, qemu_irq rx_dma, qemu_irq tx_dma) 1740 { 1741 PXA2xxI2SState *s = (PXA2xxI2SState *) 1742 g_malloc0(sizeof(PXA2xxI2SState)); 1743 1744 s->irq = irq; 1745 s->rx_dma = rx_dma; 1746 s->tx_dma = tx_dma; 1747 s->data_req = pxa2xx_i2s_data_req; 1748 1749 pxa2xx_i2s_reset(s); 1750 1751 memory_region_init_io(&s->iomem, NULL, &pxa2xx_i2s_ops, s, 1752 "pxa2xx-i2s", 0x100000); 1753 memory_region_add_subregion(sysmem, base, &s->iomem); 1754 1755 vmstate_register(NULL, base, &vmstate_pxa2xx_i2s, s); 1756 1757 return s; 1758 } 1759 1760 /* PXA Fast Infra-red Communications Port */ 1761 struct PXA2xxFIrState { 1762 MemoryRegion iomem; 1763 qemu_irq irq; 1764 qemu_irq rx_dma; 1765 qemu_irq tx_dma; 1766 int enable; 1767 CharDriverState *chr; 1768 1769 uint8_t control[3]; 1770 uint8_t status[2]; 1771 1772 int rx_len; 1773 int rx_start; 1774 uint8_t rx_fifo[64]; 1775 }; 1776 1777 static void pxa2xx_fir_reset(PXA2xxFIrState *s) 1778 { 1779 s->control[0] = 0x00; 1780 s->control[1] = 0x00; 1781 s->control[2] = 0x00; 1782 s->status[0] = 0x00; 1783 s->status[1] = 0x00; 1784 s->enable = 0; 1785 } 1786 1787 static inline void pxa2xx_fir_update(PXA2xxFIrState *s) 1788 { 1789 static const int tresh[4] = { 8, 16, 32, 0 }; 1790 int intr = 0; 1791 if ((s->control[0] & (1 << 4)) && /* RXE */ 1792 s->rx_len >= tresh[s->control[2] & 3]) /* TRIG */ 1793 s->status[0] |= 1 << 4; /* RFS */ 1794 else 1795 s->status[0] &= ~(1 << 4); /* RFS */ 1796 if (s->control[0] & (1 << 3)) /* TXE */ 1797 s->status[0] |= 1 << 3; /* TFS */ 1798 else 1799 s->status[0] &= ~(1 << 3); /* TFS */ 1800 if (s->rx_len) 1801 s->status[1] |= 1 << 2; /* RNE */ 1802 else 1803 s->status[1] &= ~(1 << 2); /* RNE */ 1804 if (s->control[0] & (1 << 4)) /* RXE */ 1805 s->status[1] |= 1 << 0; /* RSY */ 1806 else 1807 s->status[1] &= ~(1 << 0); /* RSY */ 1808 1809 intr |= (s->control[0] & (1 << 5)) && /* RIE */ 1810 (s->status[0] & (1 << 4)); /* RFS */ 1811 intr |= (s->control[0] & (1 << 6)) && /* TIE */ 1812 (s->status[0] & (1 << 3)); /* TFS */ 1813 intr |= (s->control[2] & (1 << 4)) && /* TRAIL */ 1814 (s->status[0] & (1 << 6)); /* EOC */ 1815 intr |= (s->control[0] & (1 << 2)) && /* TUS */ 1816 (s->status[0] & (1 << 1)); /* TUR */ 1817 intr |= s->status[0] & 0x25; /* FRE, RAB, EIF */ 1818 1819 qemu_set_irq(s->rx_dma, (s->status[0] >> 4) & 1); 1820 qemu_set_irq(s->tx_dma, (s->status[0] >> 3) & 1); 1821 1822 qemu_set_irq(s->irq, intr && s->enable); 1823 } 1824 1825 #define ICCR0 0x00 /* FICP Control register 0 */ 1826 #define ICCR1 0x04 /* FICP Control register 1 */ 1827 #define ICCR2 0x08 /* FICP Control register 2 */ 1828 #define ICDR 0x0c /* FICP Data register */ 1829 #define ICSR0 0x14 /* FICP Status register 0 */ 1830 #define ICSR1 0x18 /* FICP Status register 1 */ 1831 #define ICFOR 0x1c /* FICP FIFO Occupancy Status register */ 1832 1833 static uint64_t pxa2xx_fir_read(void *opaque, hwaddr addr, 1834 unsigned size) 1835 { 1836 PXA2xxFIrState *s = (PXA2xxFIrState *) opaque; 1837 uint8_t ret; 1838 1839 switch (addr) { 1840 case ICCR0: 1841 return s->control[0]; 1842 case ICCR1: 1843 return s->control[1]; 1844 case ICCR2: 1845 return s->control[2]; 1846 case ICDR: 1847 s->status[0] &= ~0x01; 1848 s->status[1] &= ~0x72; 1849 if (s->rx_len) { 1850 s->rx_len --; 1851 ret = s->rx_fifo[s->rx_start ++]; 1852 s->rx_start &= 63; 1853 pxa2xx_fir_update(s); 1854 return ret; 1855 } 1856 printf("%s: Rx FIFO underrun.\n", __FUNCTION__); 1857 break; 1858 case ICSR0: 1859 return s->status[0]; 1860 case ICSR1: 1861 return s->status[1] | (1 << 3); /* TNF */ 1862 case ICFOR: 1863 return s->rx_len; 1864 default: 1865 printf("%s: Bad register " REG_FMT "\n", __FUNCTION__, addr); 1866 break; 1867 } 1868 return 0; 1869 } 1870 1871 static void pxa2xx_fir_write(void *opaque, hwaddr addr, 1872 uint64_t value64, unsigned size) 1873 { 1874 PXA2xxFIrState *s = (PXA2xxFIrState *) opaque; 1875 uint32_t value = value64; 1876 uint8_t ch; 1877 1878 switch (addr) { 1879 case ICCR0: 1880 s->control[0] = value; 1881 if (!(value & (1 << 4))) /* RXE */ 1882 s->rx_len = s->rx_start = 0; 1883 if (!(value & (1 << 3))) { /* TXE */ 1884 /* Nop */ 1885 } 1886 s->enable = value & 1; /* ITR */ 1887 if (!s->enable) 1888 s->status[0] = 0; 1889 pxa2xx_fir_update(s); 1890 break; 1891 case ICCR1: 1892 s->control[1] = value; 1893 break; 1894 case ICCR2: 1895 s->control[2] = value & 0x3f; 1896 pxa2xx_fir_update(s); 1897 break; 1898 case ICDR: 1899 if (s->control[2] & (1 << 2)) /* TXP */ 1900 ch = value; 1901 else 1902 ch = ~value; 1903 if (s->chr && s->enable && (s->control[0] & (1 << 3))) /* TXE */ 1904 qemu_chr_fe_write(s->chr, &ch, 1); 1905 break; 1906 case ICSR0: 1907 s->status[0] &= ~(value & 0x66); 1908 pxa2xx_fir_update(s); 1909 break; 1910 case ICFOR: 1911 break; 1912 default: 1913 printf("%s: Bad register " REG_FMT "\n", __FUNCTION__, addr); 1914 } 1915 } 1916 1917 static const MemoryRegionOps pxa2xx_fir_ops = { 1918 .read = pxa2xx_fir_read, 1919 .write = pxa2xx_fir_write, 1920 .endianness = DEVICE_NATIVE_ENDIAN, 1921 }; 1922 1923 static int pxa2xx_fir_is_empty(void *opaque) 1924 { 1925 PXA2xxFIrState *s = (PXA2xxFIrState *) opaque; 1926 return (s->rx_len < 64); 1927 } 1928 1929 static void pxa2xx_fir_rx(void *opaque, const uint8_t *buf, int size) 1930 { 1931 PXA2xxFIrState *s = (PXA2xxFIrState *) opaque; 1932 if (!(s->control[0] & (1 << 4))) /* RXE */ 1933 return; 1934 1935 while (size --) { 1936 s->status[1] |= 1 << 4; /* EOF */ 1937 if (s->rx_len >= 64) { 1938 s->status[1] |= 1 << 6; /* ROR */ 1939 break; 1940 } 1941 1942 if (s->control[2] & (1 << 3)) /* RXP */ 1943 s->rx_fifo[(s->rx_start + s->rx_len ++) & 63] = *(buf ++); 1944 else 1945 s->rx_fifo[(s->rx_start + s->rx_len ++) & 63] = ~*(buf ++); 1946 } 1947 1948 pxa2xx_fir_update(s); 1949 } 1950 1951 static void pxa2xx_fir_event(void *opaque, int event) 1952 { 1953 } 1954 1955 static void pxa2xx_fir_save(QEMUFile *f, void *opaque) 1956 { 1957 PXA2xxFIrState *s = (PXA2xxFIrState *) opaque; 1958 int i; 1959 1960 qemu_put_be32(f, s->enable); 1961 1962 qemu_put_8s(f, &s->control[0]); 1963 qemu_put_8s(f, &s->control[1]); 1964 qemu_put_8s(f, &s->control[2]); 1965 qemu_put_8s(f, &s->status[0]); 1966 qemu_put_8s(f, &s->status[1]); 1967 1968 qemu_put_byte(f, s->rx_len); 1969 for (i = 0; i < s->rx_len; i ++) 1970 qemu_put_byte(f, s->rx_fifo[(s->rx_start + i) & 63]); 1971 } 1972 1973 static int pxa2xx_fir_load(QEMUFile *f, void *opaque, int version_id) 1974 { 1975 PXA2xxFIrState *s = (PXA2xxFIrState *) opaque; 1976 int i; 1977 1978 s->enable = qemu_get_be32(f); 1979 1980 qemu_get_8s(f, &s->control[0]); 1981 qemu_get_8s(f, &s->control[1]); 1982 qemu_get_8s(f, &s->control[2]); 1983 qemu_get_8s(f, &s->status[0]); 1984 qemu_get_8s(f, &s->status[1]); 1985 1986 s->rx_len = qemu_get_byte(f); 1987 s->rx_start = 0; 1988 for (i = 0; i < s->rx_len; i ++) 1989 s->rx_fifo[i] = qemu_get_byte(f); 1990 1991 return 0; 1992 } 1993 1994 static PXA2xxFIrState *pxa2xx_fir_init(MemoryRegion *sysmem, 1995 hwaddr base, 1996 qemu_irq irq, qemu_irq rx_dma, qemu_irq tx_dma, 1997 CharDriverState *chr) 1998 { 1999 PXA2xxFIrState *s = (PXA2xxFIrState *) 2000 g_malloc0(sizeof(PXA2xxFIrState)); 2001 2002 s->irq = irq; 2003 s->rx_dma = rx_dma; 2004 s->tx_dma = tx_dma; 2005 s->chr = chr; 2006 2007 pxa2xx_fir_reset(s); 2008 2009 memory_region_init_io(&s->iomem, NULL, &pxa2xx_fir_ops, s, "pxa2xx-fir", 0x1000); 2010 memory_region_add_subregion(sysmem, base, &s->iomem); 2011 2012 if (chr) { 2013 qemu_chr_fe_claim_no_fail(chr); 2014 qemu_chr_add_handlers(chr, pxa2xx_fir_is_empty, 2015 pxa2xx_fir_rx, pxa2xx_fir_event, s); 2016 } 2017 2018 register_savevm(NULL, "pxa2xx_fir", 0, 0, pxa2xx_fir_save, 2019 pxa2xx_fir_load, s); 2020 2021 return s; 2022 } 2023 2024 static void pxa2xx_reset(void *opaque, int line, int level) 2025 { 2026 PXA2xxState *s = (PXA2xxState *) opaque; 2027 2028 if (level && (s->pm_regs[PCFR >> 2] & 0x10)) { /* GPR_EN */ 2029 cpu_reset(CPU(s->cpu)); 2030 /* TODO: reset peripherals */ 2031 } 2032 } 2033 2034 /* Initialise a PXA270 integrated chip (ARM based core). */ 2035 PXA2xxState *pxa270_init(MemoryRegion *address_space, 2036 unsigned int sdram_size, const char *revision) 2037 { 2038 PXA2xxState *s; 2039 int i; 2040 DriveInfo *dinfo; 2041 s = (PXA2xxState *) g_malloc0(sizeof(PXA2xxState)); 2042 2043 if (revision && strncmp(revision, "pxa27", 5)) { 2044 fprintf(stderr, "Machine requires a PXA27x processor.\n"); 2045 exit(1); 2046 } 2047 if (!revision) 2048 revision = "pxa270"; 2049 2050 s->cpu = cpu_arm_init(revision); 2051 if (s->cpu == NULL) { 2052 fprintf(stderr, "Unable to find CPU definition\n"); 2053 exit(1); 2054 } 2055 s->reset = qemu_allocate_irq(pxa2xx_reset, s, 0); 2056 2057 /* SDRAM & Internal Memory Storage */ 2058 memory_region_init_ram(&s->sdram, NULL, "pxa270.sdram", sdram_size); 2059 vmstate_register_ram_global(&s->sdram); 2060 memory_region_add_subregion(address_space, PXA2XX_SDRAM_BASE, &s->sdram); 2061 memory_region_init_ram(&s->internal, NULL, "pxa270.internal", 0x40000); 2062 vmstate_register_ram_global(&s->internal); 2063 memory_region_add_subregion(address_space, PXA2XX_INTERNAL_BASE, 2064 &s->internal); 2065 2066 s->pic = pxa2xx_pic_init(0x40d00000, s->cpu); 2067 2068 s->dma = pxa27x_dma_init(0x40000000, 2069 qdev_get_gpio_in(s->pic, PXA2XX_PIC_DMA)); 2070 2071 sysbus_create_varargs("pxa27x-timer", 0x40a00000, 2072 qdev_get_gpio_in(s->pic, PXA2XX_PIC_OST_0 + 0), 2073 qdev_get_gpio_in(s->pic, PXA2XX_PIC_OST_0 + 1), 2074 qdev_get_gpio_in(s->pic, PXA2XX_PIC_OST_0 + 2), 2075 qdev_get_gpio_in(s->pic, PXA2XX_PIC_OST_0 + 3), 2076 qdev_get_gpio_in(s->pic, PXA27X_PIC_OST_4_11), 2077 NULL); 2078 2079 s->gpio = pxa2xx_gpio_init(0x40e00000, s->cpu, s->pic, 121); 2080 2081 dinfo = drive_get(IF_SD, 0, 0); 2082 if (!dinfo) { 2083 fprintf(stderr, "qemu: missing SecureDigital device\n"); 2084 exit(1); 2085 } 2086 s->mmc = pxa2xx_mmci_init(address_space, 0x41100000, dinfo->bdrv, 2087 qdev_get_gpio_in(s->pic, PXA2XX_PIC_MMC), 2088 qdev_get_gpio_in(s->dma, PXA2XX_RX_RQ_MMCI), 2089 qdev_get_gpio_in(s->dma, PXA2XX_TX_RQ_MMCI)); 2090 2091 for (i = 0; pxa270_serial[i].io_base; i++) { 2092 if (serial_hds[i]) { 2093 serial_mm_init(address_space, pxa270_serial[i].io_base, 2, 2094 qdev_get_gpio_in(s->pic, pxa270_serial[i].irqn), 2095 14857000 / 16, serial_hds[i], 2096 DEVICE_NATIVE_ENDIAN); 2097 } else { 2098 break; 2099 } 2100 } 2101 if (serial_hds[i]) 2102 s->fir = pxa2xx_fir_init(address_space, 0x40800000, 2103 qdev_get_gpio_in(s->pic, PXA2XX_PIC_ICP), 2104 qdev_get_gpio_in(s->dma, PXA2XX_RX_RQ_ICP), 2105 qdev_get_gpio_in(s->dma, PXA2XX_TX_RQ_ICP), 2106 serial_hds[i]); 2107 2108 s->lcd = pxa2xx_lcdc_init(address_space, 0x44000000, 2109 qdev_get_gpio_in(s->pic, PXA2XX_PIC_LCD)); 2110 2111 s->cm_base = 0x41300000; 2112 s->cm_regs[CCCR >> 2] = 0x02000210; /* 416.0 MHz */ 2113 s->clkcfg = 0x00000009; /* Turbo mode active */ 2114 memory_region_init_io(&s->cm_iomem, NULL, &pxa2xx_cm_ops, s, "pxa2xx-cm", 0x1000); 2115 memory_region_add_subregion(address_space, s->cm_base, &s->cm_iomem); 2116 vmstate_register(NULL, 0, &vmstate_pxa2xx_cm, s); 2117 2118 pxa2xx_setup_cp14(s); 2119 2120 s->mm_base = 0x48000000; 2121 s->mm_regs[MDMRS >> 2] = 0x00020002; 2122 s->mm_regs[MDREFR >> 2] = 0x03ca4000; 2123 s->mm_regs[MECR >> 2] = 0x00000001; /* Two PC Card sockets */ 2124 memory_region_init_io(&s->mm_iomem, NULL, &pxa2xx_mm_ops, s, "pxa2xx-mm", 0x1000); 2125 memory_region_add_subregion(address_space, s->mm_base, &s->mm_iomem); 2126 vmstate_register(NULL, 0, &vmstate_pxa2xx_mm, s); 2127 2128 s->pm_base = 0x40f00000; 2129 memory_region_init_io(&s->pm_iomem, NULL, &pxa2xx_pm_ops, s, "pxa2xx-pm", 0x100); 2130 memory_region_add_subregion(address_space, s->pm_base, &s->pm_iomem); 2131 vmstate_register(NULL, 0, &vmstate_pxa2xx_pm, s); 2132 2133 for (i = 0; pxa27x_ssp[i].io_base; i ++); 2134 s->ssp = (SSIBus **)g_malloc0(sizeof(SSIBus *) * i); 2135 for (i = 0; pxa27x_ssp[i].io_base; i ++) { 2136 DeviceState *dev; 2137 dev = sysbus_create_simple(TYPE_PXA2XX_SSP, pxa27x_ssp[i].io_base, 2138 qdev_get_gpio_in(s->pic, pxa27x_ssp[i].irqn)); 2139 s->ssp[i] = (SSIBus *)qdev_get_child_bus(dev, "ssi"); 2140 } 2141 2142 if (usb_enabled(false)) { 2143 sysbus_create_simple("sysbus-ohci", 0x4c000000, 2144 qdev_get_gpio_in(s->pic, PXA2XX_PIC_USBH1)); 2145 } 2146 2147 s->pcmcia[0] = pxa2xx_pcmcia_init(address_space, 0x20000000); 2148 s->pcmcia[1] = pxa2xx_pcmcia_init(address_space, 0x30000000); 2149 2150 sysbus_create_simple(TYPE_PXA2XX_RTC, 0x40900000, 2151 qdev_get_gpio_in(s->pic, PXA2XX_PIC_RTCALARM)); 2152 2153 s->i2c[0] = pxa2xx_i2c_init(0x40301600, 2154 qdev_get_gpio_in(s->pic, PXA2XX_PIC_I2C), 0xffff); 2155 s->i2c[1] = pxa2xx_i2c_init(0x40f00100, 2156 qdev_get_gpio_in(s->pic, PXA2XX_PIC_PWRI2C), 0xff); 2157 2158 s->i2s = pxa2xx_i2s_init(address_space, 0x40400000, 2159 qdev_get_gpio_in(s->pic, PXA2XX_PIC_I2S), 2160 qdev_get_gpio_in(s->dma, PXA2XX_RX_RQ_I2S), 2161 qdev_get_gpio_in(s->dma, PXA2XX_TX_RQ_I2S)); 2162 2163 s->kp = pxa27x_keypad_init(address_space, 0x41500000, 2164 qdev_get_gpio_in(s->pic, PXA2XX_PIC_KEYPAD)); 2165 2166 /* GPIO1 resets the processor */ 2167 /* The handler can be overridden by board-specific code */ 2168 qdev_connect_gpio_out(s->gpio, 1, s->reset); 2169 return s; 2170 } 2171 2172 /* Initialise a PXA255 integrated chip (ARM based core). */ 2173 PXA2xxState *pxa255_init(MemoryRegion *address_space, unsigned int sdram_size) 2174 { 2175 PXA2xxState *s; 2176 int i; 2177 DriveInfo *dinfo; 2178 2179 s = (PXA2xxState *) g_malloc0(sizeof(PXA2xxState)); 2180 2181 s->cpu = cpu_arm_init("pxa255"); 2182 if (s->cpu == NULL) { 2183 fprintf(stderr, "Unable to find CPU definition\n"); 2184 exit(1); 2185 } 2186 s->reset = qemu_allocate_irq(pxa2xx_reset, s, 0); 2187 2188 /* SDRAM & Internal Memory Storage */ 2189 memory_region_init_ram(&s->sdram, NULL, "pxa255.sdram", sdram_size); 2190 vmstate_register_ram_global(&s->sdram); 2191 memory_region_add_subregion(address_space, PXA2XX_SDRAM_BASE, &s->sdram); 2192 memory_region_init_ram(&s->internal, NULL, "pxa255.internal", 2193 PXA2XX_INTERNAL_SIZE); 2194 vmstate_register_ram_global(&s->internal); 2195 memory_region_add_subregion(address_space, PXA2XX_INTERNAL_BASE, 2196 &s->internal); 2197 2198 s->pic = pxa2xx_pic_init(0x40d00000, s->cpu); 2199 2200 s->dma = pxa255_dma_init(0x40000000, 2201 qdev_get_gpio_in(s->pic, PXA2XX_PIC_DMA)); 2202 2203 sysbus_create_varargs("pxa25x-timer", 0x40a00000, 2204 qdev_get_gpio_in(s->pic, PXA2XX_PIC_OST_0 + 0), 2205 qdev_get_gpio_in(s->pic, PXA2XX_PIC_OST_0 + 1), 2206 qdev_get_gpio_in(s->pic, PXA2XX_PIC_OST_0 + 2), 2207 qdev_get_gpio_in(s->pic, PXA2XX_PIC_OST_0 + 3), 2208 NULL); 2209 2210 s->gpio = pxa2xx_gpio_init(0x40e00000, s->cpu, s->pic, 85); 2211 2212 dinfo = drive_get(IF_SD, 0, 0); 2213 if (!dinfo) { 2214 fprintf(stderr, "qemu: missing SecureDigital device\n"); 2215 exit(1); 2216 } 2217 s->mmc = pxa2xx_mmci_init(address_space, 0x41100000, dinfo->bdrv, 2218 qdev_get_gpio_in(s->pic, PXA2XX_PIC_MMC), 2219 qdev_get_gpio_in(s->dma, PXA2XX_RX_RQ_MMCI), 2220 qdev_get_gpio_in(s->dma, PXA2XX_TX_RQ_MMCI)); 2221 2222 for (i = 0; pxa255_serial[i].io_base; i++) { 2223 if (serial_hds[i]) { 2224 serial_mm_init(address_space, pxa255_serial[i].io_base, 2, 2225 qdev_get_gpio_in(s->pic, pxa255_serial[i].irqn), 2226 14745600 / 16, serial_hds[i], 2227 DEVICE_NATIVE_ENDIAN); 2228 } else { 2229 break; 2230 } 2231 } 2232 if (serial_hds[i]) 2233 s->fir = pxa2xx_fir_init(address_space, 0x40800000, 2234 qdev_get_gpio_in(s->pic, PXA2XX_PIC_ICP), 2235 qdev_get_gpio_in(s->dma, PXA2XX_RX_RQ_ICP), 2236 qdev_get_gpio_in(s->dma, PXA2XX_TX_RQ_ICP), 2237 serial_hds[i]); 2238 2239 s->lcd = pxa2xx_lcdc_init(address_space, 0x44000000, 2240 qdev_get_gpio_in(s->pic, PXA2XX_PIC_LCD)); 2241 2242 s->cm_base = 0x41300000; 2243 s->cm_regs[CCCR >> 2] = 0x02000210; /* 416.0 MHz */ 2244 s->clkcfg = 0x00000009; /* Turbo mode active */ 2245 memory_region_init_io(&s->cm_iomem, NULL, &pxa2xx_cm_ops, s, "pxa2xx-cm", 0x1000); 2246 memory_region_add_subregion(address_space, s->cm_base, &s->cm_iomem); 2247 vmstate_register(NULL, 0, &vmstate_pxa2xx_cm, s); 2248 2249 pxa2xx_setup_cp14(s); 2250 2251 s->mm_base = 0x48000000; 2252 s->mm_regs[MDMRS >> 2] = 0x00020002; 2253 s->mm_regs[MDREFR >> 2] = 0x03ca4000; 2254 s->mm_regs[MECR >> 2] = 0x00000001; /* Two PC Card sockets */ 2255 memory_region_init_io(&s->mm_iomem, NULL, &pxa2xx_mm_ops, s, "pxa2xx-mm", 0x1000); 2256 memory_region_add_subregion(address_space, s->mm_base, &s->mm_iomem); 2257 vmstate_register(NULL, 0, &vmstate_pxa2xx_mm, s); 2258 2259 s->pm_base = 0x40f00000; 2260 memory_region_init_io(&s->pm_iomem, NULL, &pxa2xx_pm_ops, s, "pxa2xx-pm", 0x100); 2261 memory_region_add_subregion(address_space, s->pm_base, &s->pm_iomem); 2262 vmstate_register(NULL, 0, &vmstate_pxa2xx_pm, s); 2263 2264 for (i = 0; pxa255_ssp[i].io_base; i ++); 2265 s->ssp = (SSIBus **)g_malloc0(sizeof(SSIBus *) * i); 2266 for (i = 0; pxa255_ssp[i].io_base; i ++) { 2267 DeviceState *dev; 2268 dev = sysbus_create_simple(TYPE_PXA2XX_SSP, pxa255_ssp[i].io_base, 2269 qdev_get_gpio_in(s->pic, pxa255_ssp[i].irqn)); 2270 s->ssp[i] = (SSIBus *)qdev_get_child_bus(dev, "ssi"); 2271 } 2272 2273 if (usb_enabled(false)) { 2274 sysbus_create_simple("sysbus-ohci", 0x4c000000, 2275 qdev_get_gpio_in(s->pic, PXA2XX_PIC_USBH1)); 2276 } 2277 2278 s->pcmcia[0] = pxa2xx_pcmcia_init(address_space, 0x20000000); 2279 s->pcmcia[1] = pxa2xx_pcmcia_init(address_space, 0x30000000); 2280 2281 sysbus_create_simple(TYPE_PXA2XX_RTC, 0x40900000, 2282 qdev_get_gpio_in(s->pic, PXA2XX_PIC_RTCALARM)); 2283 2284 s->i2c[0] = pxa2xx_i2c_init(0x40301600, 2285 qdev_get_gpio_in(s->pic, PXA2XX_PIC_I2C), 0xffff); 2286 s->i2c[1] = pxa2xx_i2c_init(0x40f00100, 2287 qdev_get_gpio_in(s->pic, PXA2XX_PIC_PWRI2C), 0xff); 2288 2289 s->i2s = pxa2xx_i2s_init(address_space, 0x40400000, 2290 qdev_get_gpio_in(s->pic, PXA2XX_PIC_I2S), 2291 qdev_get_gpio_in(s->dma, PXA2XX_RX_RQ_I2S), 2292 qdev_get_gpio_in(s->dma, PXA2XX_TX_RQ_I2S)); 2293 2294 /* GPIO1 resets the processor */ 2295 /* The handler can be overridden by board-specific code */ 2296 qdev_connect_gpio_out(s->gpio, 1, s->reset); 2297 return s; 2298 } 2299 2300 static void pxa2xx_ssp_class_init(ObjectClass *klass, void *data) 2301 { 2302 SysBusDeviceClass *sdc = SYS_BUS_DEVICE_CLASS(klass); 2303 2304 sdc->init = pxa2xx_ssp_init; 2305 } 2306 2307 static const TypeInfo pxa2xx_ssp_info = { 2308 .name = TYPE_PXA2XX_SSP, 2309 .parent = TYPE_SYS_BUS_DEVICE, 2310 .instance_size = sizeof(PXA2xxSSPState), 2311 .class_init = pxa2xx_ssp_class_init, 2312 }; 2313 2314 static void pxa2xx_register_types(void) 2315 { 2316 type_register_static(&pxa2xx_i2c_slave_info); 2317 type_register_static(&pxa2xx_ssp_info); 2318 type_register_static(&pxa2xx_i2c_info); 2319 type_register_static(&pxa2xx_rtc_sysbus_info); 2320 } 2321 2322 type_init(pxa2xx_register_types) 2323