1 /* 2 * Intel XScale PXA255/270 GPIO controller emulation. 3 * 4 * Copyright (c) 2006 Openedhand Ltd. 5 * Written by Andrzej Zaborowski <balrog@zabor.org> 6 * 7 * This code is licensed under the GPL. 8 */ 9 10 #include "qemu/osdep.h" 11 #include "cpu.h" 12 #include "hw/hw.h" 13 #include "hw/sysbus.h" 14 #include "hw/arm/pxa.h" 15 #include "qemu/log.h" 16 17 #define PXA2XX_GPIO_BANKS 4 18 19 #define TYPE_PXA2XX_GPIO "pxa2xx-gpio" 20 #define PXA2XX_GPIO(obj) \ 21 OBJECT_CHECK(PXA2xxGPIOInfo, (obj), TYPE_PXA2XX_GPIO) 22 23 typedef struct PXA2xxGPIOInfo PXA2xxGPIOInfo; 24 struct PXA2xxGPIOInfo { 25 /*< private >*/ 26 SysBusDevice parent_obj; 27 /*< public >*/ 28 29 MemoryRegion iomem; 30 qemu_irq irq0, irq1, irqX; 31 int lines; 32 int ncpu; 33 ARMCPU *cpu; 34 35 /* XXX: GNU C vectors are more suitable */ 36 uint32_t ilevel[PXA2XX_GPIO_BANKS]; 37 uint32_t olevel[PXA2XX_GPIO_BANKS]; 38 uint32_t dir[PXA2XX_GPIO_BANKS]; 39 uint32_t rising[PXA2XX_GPIO_BANKS]; 40 uint32_t falling[PXA2XX_GPIO_BANKS]; 41 uint32_t status[PXA2XX_GPIO_BANKS]; 42 uint32_t gafr[PXA2XX_GPIO_BANKS * 2]; 43 44 uint32_t prev_level[PXA2XX_GPIO_BANKS]; 45 qemu_irq handler[PXA2XX_GPIO_BANKS * 32]; 46 qemu_irq read_notify; 47 }; 48 49 static struct { 50 enum { 51 GPIO_NONE, 52 GPLR, 53 GPSR, 54 GPCR, 55 GPDR, 56 GRER, 57 GFER, 58 GEDR, 59 GAFR_L, 60 GAFR_U, 61 } reg; 62 int bank; 63 } pxa2xx_gpio_regs[0x200] = { 64 [0 ... 0x1ff] = { GPIO_NONE, 0 }, 65 #define PXA2XX_REG(reg, a0, a1, a2, a3) \ 66 [a0] = { reg, 0 }, [a1] = { reg, 1 }, [a2] = { reg, 2 }, [a3] = { reg, 3 }, 67 68 PXA2XX_REG(GPLR, 0x000, 0x004, 0x008, 0x100) 69 PXA2XX_REG(GPSR, 0x018, 0x01c, 0x020, 0x118) 70 PXA2XX_REG(GPCR, 0x024, 0x028, 0x02c, 0x124) 71 PXA2XX_REG(GPDR, 0x00c, 0x010, 0x014, 0x10c) 72 PXA2XX_REG(GRER, 0x030, 0x034, 0x038, 0x130) 73 PXA2XX_REG(GFER, 0x03c, 0x040, 0x044, 0x13c) 74 PXA2XX_REG(GEDR, 0x048, 0x04c, 0x050, 0x148) 75 PXA2XX_REG(GAFR_L, 0x054, 0x05c, 0x064, 0x06c) 76 PXA2XX_REG(GAFR_U, 0x058, 0x060, 0x068, 0x070) 77 }; 78 79 static void pxa2xx_gpio_irq_update(PXA2xxGPIOInfo *s) 80 { 81 if (s->status[0] & (1 << 0)) 82 qemu_irq_raise(s->irq0); 83 else 84 qemu_irq_lower(s->irq0); 85 86 if (s->status[0] & (1 << 1)) 87 qemu_irq_raise(s->irq1); 88 else 89 qemu_irq_lower(s->irq1); 90 91 if ((s->status[0] & ~3) | s->status[1] | s->status[2] | s->status[3]) 92 qemu_irq_raise(s->irqX); 93 else 94 qemu_irq_lower(s->irqX); 95 } 96 97 /* Bitmap of pins used as standby and sleep wake-up sources. */ 98 static const int pxa2xx_gpio_wake[PXA2XX_GPIO_BANKS] = { 99 0x8003fe1b, 0x002001fc, 0xec080000, 0x0012007f, 100 }; 101 102 static void pxa2xx_gpio_set(void *opaque, int line, int level) 103 { 104 PXA2xxGPIOInfo *s = (PXA2xxGPIOInfo *) opaque; 105 CPUState *cpu = CPU(s->cpu); 106 int bank; 107 uint32_t mask; 108 109 if (line >= s->lines) { 110 printf("%s: No GPIO pin %i\n", __FUNCTION__, line); 111 return; 112 } 113 114 bank = line >> 5; 115 mask = 1U << (line & 31); 116 117 if (level) { 118 s->status[bank] |= s->rising[bank] & mask & 119 ~s->ilevel[bank] & ~s->dir[bank]; 120 s->ilevel[bank] |= mask; 121 } else { 122 s->status[bank] |= s->falling[bank] & mask & 123 s->ilevel[bank] & ~s->dir[bank]; 124 s->ilevel[bank] &= ~mask; 125 } 126 127 if (s->status[bank] & mask) 128 pxa2xx_gpio_irq_update(s); 129 130 /* Wake-up GPIOs */ 131 if (cpu->halted && (mask & ~s->dir[bank] & pxa2xx_gpio_wake[bank])) { 132 cpu_interrupt(cpu, CPU_INTERRUPT_EXITTB); 133 } 134 } 135 136 static void pxa2xx_gpio_handler_update(PXA2xxGPIOInfo *s) { 137 uint32_t level, diff; 138 int i, bit, line; 139 for (i = 0; i < PXA2XX_GPIO_BANKS; i ++) { 140 level = s->olevel[i] & s->dir[i]; 141 142 for (diff = s->prev_level[i] ^ level; diff; diff ^= 1 << bit) { 143 bit = ctz32(diff); 144 line = bit + 32 * i; 145 qemu_set_irq(s->handler[line], (level >> bit) & 1); 146 } 147 148 s->prev_level[i] = level; 149 } 150 } 151 152 static uint64_t pxa2xx_gpio_read(void *opaque, hwaddr offset, 153 unsigned size) 154 { 155 PXA2xxGPIOInfo *s = (PXA2xxGPIOInfo *) opaque; 156 uint32_t ret; 157 int bank; 158 if (offset >= 0x200) 159 return 0; 160 161 bank = pxa2xx_gpio_regs[offset].bank; 162 switch (pxa2xx_gpio_regs[offset].reg) { 163 case GPDR: /* GPIO Pin-Direction registers */ 164 return s->dir[bank]; 165 166 case GPSR: /* GPIO Pin-Output Set registers */ 167 qemu_log_mask(LOG_GUEST_ERROR, 168 "pxa2xx GPIO: read from write only register GPSR\n"); 169 return 0; 170 171 case GPCR: /* GPIO Pin-Output Clear registers */ 172 qemu_log_mask(LOG_GUEST_ERROR, 173 "pxa2xx GPIO: read from write only register GPCR\n"); 174 return 0; 175 176 case GRER: /* GPIO Rising-Edge Detect Enable registers */ 177 return s->rising[bank]; 178 179 case GFER: /* GPIO Falling-Edge Detect Enable registers */ 180 return s->falling[bank]; 181 182 case GAFR_L: /* GPIO Alternate Function registers */ 183 return s->gafr[bank * 2]; 184 185 case GAFR_U: /* GPIO Alternate Function registers */ 186 return s->gafr[bank * 2 + 1]; 187 188 case GPLR: /* GPIO Pin-Level registers */ 189 ret = (s->olevel[bank] & s->dir[bank]) | 190 (s->ilevel[bank] & ~s->dir[bank]); 191 qemu_irq_raise(s->read_notify); 192 return ret; 193 194 case GEDR: /* GPIO Edge Detect Status registers */ 195 return s->status[bank]; 196 197 default: 198 hw_error("%s: Bad offset " REG_FMT "\n", __FUNCTION__, offset); 199 } 200 201 return 0; 202 } 203 204 static void pxa2xx_gpio_write(void *opaque, hwaddr offset, 205 uint64_t value, unsigned size) 206 { 207 PXA2xxGPIOInfo *s = (PXA2xxGPIOInfo *) opaque; 208 int bank; 209 if (offset >= 0x200) 210 return; 211 212 bank = pxa2xx_gpio_regs[offset].bank; 213 switch (pxa2xx_gpio_regs[offset].reg) { 214 case GPDR: /* GPIO Pin-Direction registers */ 215 s->dir[bank] = value; 216 pxa2xx_gpio_handler_update(s); 217 break; 218 219 case GPSR: /* GPIO Pin-Output Set registers */ 220 s->olevel[bank] |= value; 221 pxa2xx_gpio_handler_update(s); 222 break; 223 224 case GPCR: /* GPIO Pin-Output Clear registers */ 225 s->olevel[bank] &= ~value; 226 pxa2xx_gpio_handler_update(s); 227 break; 228 229 case GRER: /* GPIO Rising-Edge Detect Enable registers */ 230 s->rising[bank] = value; 231 break; 232 233 case GFER: /* GPIO Falling-Edge Detect Enable registers */ 234 s->falling[bank] = value; 235 break; 236 237 case GAFR_L: /* GPIO Alternate Function registers */ 238 s->gafr[bank * 2] = value; 239 break; 240 241 case GAFR_U: /* GPIO Alternate Function registers */ 242 s->gafr[bank * 2 + 1] = value; 243 break; 244 245 case GEDR: /* GPIO Edge Detect Status registers */ 246 s->status[bank] &= ~value; 247 pxa2xx_gpio_irq_update(s); 248 break; 249 250 default: 251 hw_error("%s: Bad offset " REG_FMT "\n", __FUNCTION__, offset); 252 } 253 } 254 255 static const MemoryRegionOps pxa_gpio_ops = { 256 .read = pxa2xx_gpio_read, 257 .write = pxa2xx_gpio_write, 258 .endianness = DEVICE_NATIVE_ENDIAN, 259 }; 260 261 DeviceState *pxa2xx_gpio_init(hwaddr base, 262 ARMCPU *cpu, DeviceState *pic, int lines) 263 { 264 CPUState *cs = CPU(cpu); 265 DeviceState *dev; 266 267 dev = qdev_create(NULL, TYPE_PXA2XX_GPIO); 268 qdev_prop_set_int32(dev, "lines", lines); 269 qdev_prop_set_int32(dev, "ncpu", cs->cpu_index); 270 qdev_init_nofail(dev); 271 272 sysbus_mmio_map(SYS_BUS_DEVICE(dev), 0, base); 273 sysbus_connect_irq(SYS_BUS_DEVICE(dev), 0, 274 qdev_get_gpio_in(pic, PXA2XX_PIC_GPIO_0)); 275 sysbus_connect_irq(SYS_BUS_DEVICE(dev), 1, 276 qdev_get_gpio_in(pic, PXA2XX_PIC_GPIO_1)); 277 sysbus_connect_irq(SYS_BUS_DEVICE(dev), 2, 278 qdev_get_gpio_in(pic, PXA2XX_PIC_GPIO_X)); 279 280 return dev; 281 } 282 283 static int pxa2xx_gpio_initfn(SysBusDevice *sbd) 284 { 285 DeviceState *dev = DEVICE(sbd); 286 PXA2xxGPIOInfo *s = PXA2XX_GPIO(dev); 287 288 s->cpu = ARM_CPU(qemu_get_cpu(s->ncpu)); 289 290 qdev_init_gpio_in(dev, pxa2xx_gpio_set, s->lines); 291 qdev_init_gpio_out(dev, s->handler, s->lines); 292 293 memory_region_init_io(&s->iomem, OBJECT(s), &pxa_gpio_ops, s, "pxa2xx-gpio", 0x1000); 294 sysbus_init_mmio(sbd, &s->iomem); 295 sysbus_init_irq(sbd, &s->irq0); 296 sysbus_init_irq(sbd, &s->irq1); 297 sysbus_init_irq(sbd, &s->irqX); 298 299 return 0; 300 } 301 302 /* 303 * Registers a callback to notify on GPLR reads. This normally 304 * shouldn't be needed but it is used for the hack on Spitz machines. 305 */ 306 void pxa2xx_gpio_read_notifier(DeviceState *dev, qemu_irq handler) 307 { 308 PXA2xxGPIOInfo *s = PXA2XX_GPIO(dev); 309 310 s->read_notify = handler; 311 } 312 313 static const VMStateDescription vmstate_pxa2xx_gpio_regs = { 314 .name = "pxa2xx-gpio", 315 .version_id = 1, 316 .minimum_version_id = 1, 317 .fields = (VMStateField[]) { 318 VMSTATE_UINT32_ARRAY(ilevel, PXA2xxGPIOInfo, PXA2XX_GPIO_BANKS), 319 VMSTATE_UINT32_ARRAY(olevel, PXA2xxGPIOInfo, PXA2XX_GPIO_BANKS), 320 VMSTATE_UINT32_ARRAY(dir, PXA2xxGPIOInfo, PXA2XX_GPIO_BANKS), 321 VMSTATE_UINT32_ARRAY(rising, PXA2xxGPIOInfo, PXA2XX_GPIO_BANKS), 322 VMSTATE_UINT32_ARRAY(falling, PXA2xxGPIOInfo, PXA2XX_GPIO_BANKS), 323 VMSTATE_UINT32_ARRAY(status, PXA2xxGPIOInfo, PXA2XX_GPIO_BANKS), 324 VMSTATE_UINT32_ARRAY(gafr, PXA2xxGPIOInfo, PXA2XX_GPIO_BANKS * 2), 325 VMSTATE_UINT32_ARRAY(prev_level, PXA2xxGPIOInfo, PXA2XX_GPIO_BANKS), 326 VMSTATE_END_OF_LIST(), 327 }, 328 }; 329 330 static Property pxa2xx_gpio_properties[] = { 331 DEFINE_PROP_INT32("lines", PXA2xxGPIOInfo, lines, 0), 332 DEFINE_PROP_INT32("ncpu", PXA2xxGPIOInfo, ncpu, 0), 333 DEFINE_PROP_END_OF_LIST(), 334 }; 335 336 static void pxa2xx_gpio_class_init(ObjectClass *klass, void *data) 337 { 338 DeviceClass *dc = DEVICE_CLASS(klass); 339 SysBusDeviceClass *k = SYS_BUS_DEVICE_CLASS(klass); 340 341 k->init = pxa2xx_gpio_initfn; 342 dc->desc = "PXA2xx GPIO controller"; 343 dc->props = pxa2xx_gpio_properties; 344 dc->vmsd = &vmstate_pxa2xx_gpio_regs; 345 } 346 347 static const TypeInfo pxa2xx_gpio_info = { 348 .name = TYPE_PXA2XX_GPIO, 349 .parent = TYPE_SYS_BUS_DEVICE, 350 .instance_size = sizeof(PXA2xxGPIOInfo), 351 .class_init = pxa2xx_gpio_class_init, 352 }; 353 354 static void pxa2xx_gpio_register_types(void) 355 { 356 type_register_static(&pxa2xx_gpio_info); 357 } 358 359 type_init(pxa2xx_gpio_register_types) 360