1 /* 2 * Intel XScale PXA255/270 GPIO controller emulation. 3 * 4 * Copyright (c) 2006 Openedhand Ltd. 5 * Written by Andrzej Zaborowski <balrog@zabor.org> 6 * 7 * This code is licensed under the GPL. 8 */ 9 10 #include "qemu/osdep.h" 11 #include "cpu.h" 12 #include "hw/irq.h" 13 #include "hw/qdev-properties.h" 14 #include "hw/sysbus.h" 15 #include "migration/vmstate.h" 16 #include "hw/arm/pxa.h" 17 #include "qapi/error.h" 18 #include "qemu/log.h" 19 #include "qemu/module.h" 20 #include "qom/object.h" 21 22 #define PXA2XX_GPIO_BANKS 4 23 24 #define TYPE_PXA2XX_GPIO "pxa2xx-gpio" 25 typedef struct PXA2xxGPIOInfo PXA2xxGPIOInfo; 26 DECLARE_INSTANCE_CHECKER(PXA2xxGPIOInfo, PXA2XX_GPIO, 27 TYPE_PXA2XX_GPIO) 28 29 struct PXA2xxGPIOInfo { 30 /*< private >*/ 31 SysBusDevice parent_obj; 32 /*< public >*/ 33 34 MemoryRegion iomem; 35 qemu_irq irq0, irq1, irqX; 36 int lines; 37 int ncpu; 38 ARMCPU *cpu; 39 40 /* XXX: GNU C vectors are more suitable */ 41 uint32_t ilevel[PXA2XX_GPIO_BANKS]; 42 uint32_t olevel[PXA2XX_GPIO_BANKS]; 43 uint32_t dir[PXA2XX_GPIO_BANKS]; 44 uint32_t rising[PXA2XX_GPIO_BANKS]; 45 uint32_t falling[PXA2XX_GPIO_BANKS]; 46 uint32_t status[PXA2XX_GPIO_BANKS]; 47 uint32_t gafr[PXA2XX_GPIO_BANKS * 2]; 48 49 uint32_t prev_level[PXA2XX_GPIO_BANKS]; 50 qemu_irq handler[PXA2XX_GPIO_BANKS * 32]; 51 qemu_irq read_notify; 52 }; 53 54 static struct { 55 enum { 56 GPIO_NONE, 57 GPLR, 58 GPSR, 59 GPCR, 60 GPDR, 61 GRER, 62 GFER, 63 GEDR, 64 GAFR_L, 65 GAFR_U, 66 } reg; 67 int bank; 68 } pxa2xx_gpio_regs[0x200] = { 69 [0 ... 0x1ff] = { GPIO_NONE, 0 }, 70 #define PXA2XX_REG(reg, a0, a1, a2, a3) \ 71 [a0] = { reg, 0 }, [a1] = { reg, 1 }, [a2] = { reg, 2 }, [a3] = { reg, 3 }, 72 73 PXA2XX_REG(GPLR, 0x000, 0x004, 0x008, 0x100) 74 PXA2XX_REG(GPSR, 0x018, 0x01c, 0x020, 0x118) 75 PXA2XX_REG(GPCR, 0x024, 0x028, 0x02c, 0x124) 76 PXA2XX_REG(GPDR, 0x00c, 0x010, 0x014, 0x10c) 77 PXA2XX_REG(GRER, 0x030, 0x034, 0x038, 0x130) 78 PXA2XX_REG(GFER, 0x03c, 0x040, 0x044, 0x13c) 79 PXA2XX_REG(GEDR, 0x048, 0x04c, 0x050, 0x148) 80 PXA2XX_REG(GAFR_L, 0x054, 0x05c, 0x064, 0x06c) 81 PXA2XX_REG(GAFR_U, 0x058, 0x060, 0x068, 0x070) 82 }; 83 84 static void pxa2xx_gpio_irq_update(PXA2xxGPIOInfo *s) 85 { 86 if (s->status[0] & (1 << 0)) 87 qemu_irq_raise(s->irq0); 88 else 89 qemu_irq_lower(s->irq0); 90 91 if (s->status[0] & (1 << 1)) 92 qemu_irq_raise(s->irq1); 93 else 94 qemu_irq_lower(s->irq1); 95 96 if ((s->status[0] & ~3) | s->status[1] | s->status[2] | s->status[3]) 97 qemu_irq_raise(s->irqX); 98 else 99 qemu_irq_lower(s->irqX); 100 } 101 102 /* Bitmap of pins used as standby and sleep wake-up sources. */ 103 static const int pxa2xx_gpio_wake[PXA2XX_GPIO_BANKS] = { 104 0x8003fe1b, 0x002001fc, 0xec080000, 0x0012007f, 105 }; 106 107 static void pxa2xx_gpio_set(void *opaque, int line, int level) 108 { 109 PXA2xxGPIOInfo *s = (PXA2xxGPIOInfo *) opaque; 110 CPUState *cpu = CPU(s->cpu); 111 int bank; 112 uint32_t mask; 113 114 if (line >= s->lines) { 115 printf("%s: No GPIO pin %i\n", __func__, line); 116 return; 117 } 118 119 bank = line >> 5; 120 mask = 1U << (line & 31); 121 122 if (level) { 123 s->status[bank] |= s->rising[bank] & mask & 124 ~s->ilevel[bank] & ~s->dir[bank]; 125 s->ilevel[bank] |= mask; 126 } else { 127 s->status[bank] |= s->falling[bank] & mask & 128 s->ilevel[bank] & ~s->dir[bank]; 129 s->ilevel[bank] &= ~mask; 130 } 131 132 if (s->status[bank] & mask) 133 pxa2xx_gpio_irq_update(s); 134 135 /* Wake-up GPIOs */ 136 if (cpu->halted && (mask & ~s->dir[bank] & pxa2xx_gpio_wake[bank])) { 137 cpu_interrupt(cpu, CPU_INTERRUPT_EXITTB); 138 } 139 } 140 141 static void pxa2xx_gpio_handler_update(PXA2xxGPIOInfo *s) { 142 uint32_t level, diff; 143 int i, bit, line; 144 for (i = 0; i < PXA2XX_GPIO_BANKS; i ++) { 145 level = s->olevel[i] & s->dir[i]; 146 147 for (diff = s->prev_level[i] ^ level; diff; diff ^= 1 << bit) { 148 bit = ctz32(diff); 149 line = bit + 32 * i; 150 qemu_set_irq(s->handler[line], (level >> bit) & 1); 151 } 152 153 s->prev_level[i] = level; 154 } 155 } 156 157 static uint64_t pxa2xx_gpio_read(void *opaque, hwaddr offset, 158 unsigned size) 159 { 160 PXA2xxGPIOInfo *s = (PXA2xxGPIOInfo *) opaque; 161 uint32_t ret; 162 int bank; 163 if (offset >= 0x200) 164 return 0; 165 166 bank = pxa2xx_gpio_regs[offset].bank; 167 switch (pxa2xx_gpio_regs[offset].reg) { 168 case GPDR: /* GPIO Pin-Direction registers */ 169 return s->dir[bank]; 170 171 case GPSR: /* GPIO Pin-Output Set registers */ 172 qemu_log_mask(LOG_GUEST_ERROR, 173 "pxa2xx GPIO: read from write only register GPSR\n"); 174 return 0; 175 176 case GPCR: /* GPIO Pin-Output Clear registers */ 177 qemu_log_mask(LOG_GUEST_ERROR, 178 "pxa2xx GPIO: read from write only register GPCR\n"); 179 return 0; 180 181 case GRER: /* GPIO Rising-Edge Detect Enable registers */ 182 return s->rising[bank]; 183 184 case GFER: /* GPIO Falling-Edge Detect Enable registers */ 185 return s->falling[bank]; 186 187 case GAFR_L: /* GPIO Alternate Function registers */ 188 return s->gafr[bank * 2]; 189 190 case GAFR_U: /* GPIO Alternate Function registers */ 191 return s->gafr[bank * 2 + 1]; 192 193 case GPLR: /* GPIO Pin-Level registers */ 194 ret = (s->olevel[bank] & s->dir[bank]) | 195 (s->ilevel[bank] & ~s->dir[bank]); 196 qemu_irq_raise(s->read_notify); 197 return ret; 198 199 case GEDR: /* GPIO Edge Detect Status registers */ 200 return s->status[bank]; 201 202 default: 203 qemu_log_mask(LOG_GUEST_ERROR, "%s: Bad offset 0x%" HWADDR_PRIX "\n", 204 __func__, offset); 205 } 206 207 return 0; 208 } 209 210 static void pxa2xx_gpio_write(void *opaque, hwaddr offset, 211 uint64_t value, unsigned size) 212 { 213 PXA2xxGPIOInfo *s = (PXA2xxGPIOInfo *) opaque; 214 int bank; 215 if (offset >= 0x200) 216 return; 217 218 bank = pxa2xx_gpio_regs[offset].bank; 219 switch (pxa2xx_gpio_regs[offset].reg) { 220 case GPDR: /* GPIO Pin-Direction registers */ 221 s->dir[bank] = value; 222 pxa2xx_gpio_handler_update(s); 223 break; 224 225 case GPSR: /* GPIO Pin-Output Set registers */ 226 s->olevel[bank] |= value; 227 pxa2xx_gpio_handler_update(s); 228 break; 229 230 case GPCR: /* GPIO Pin-Output Clear registers */ 231 s->olevel[bank] &= ~value; 232 pxa2xx_gpio_handler_update(s); 233 break; 234 235 case GRER: /* GPIO Rising-Edge Detect Enable registers */ 236 s->rising[bank] = value; 237 break; 238 239 case GFER: /* GPIO Falling-Edge Detect Enable registers */ 240 s->falling[bank] = value; 241 break; 242 243 case GAFR_L: /* GPIO Alternate Function registers */ 244 s->gafr[bank * 2] = value; 245 break; 246 247 case GAFR_U: /* GPIO Alternate Function registers */ 248 s->gafr[bank * 2 + 1] = value; 249 break; 250 251 case GEDR: /* GPIO Edge Detect Status registers */ 252 s->status[bank] &= ~value; 253 pxa2xx_gpio_irq_update(s); 254 break; 255 256 default: 257 qemu_log_mask(LOG_GUEST_ERROR, "%s: Bad offset 0x%" HWADDR_PRIX "\n", 258 __func__, offset); 259 } 260 } 261 262 static const MemoryRegionOps pxa_gpio_ops = { 263 .read = pxa2xx_gpio_read, 264 .write = pxa2xx_gpio_write, 265 .endianness = DEVICE_NATIVE_ENDIAN, 266 }; 267 268 DeviceState *pxa2xx_gpio_init(hwaddr base, 269 ARMCPU *cpu, DeviceState *pic, int lines) 270 { 271 CPUState *cs = CPU(cpu); 272 DeviceState *dev; 273 274 dev = qdev_new(TYPE_PXA2XX_GPIO); 275 qdev_prop_set_int32(dev, "lines", lines); 276 qdev_prop_set_int32(dev, "ncpu", cs->cpu_index); 277 sysbus_realize_and_unref(SYS_BUS_DEVICE(dev), &error_fatal); 278 279 sysbus_mmio_map(SYS_BUS_DEVICE(dev), 0, base); 280 sysbus_connect_irq(SYS_BUS_DEVICE(dev), 0, 281 qdev_get_gpio_in(pic, PXA2XX_PIC_GPIO_0)); 282 sysbus_connect_irq(SYS_BUS_DEVICE(dev), 1, 283 qdev_get_gpio_in(pic, PXA2XX_PIC_GPIO_1)); 284 sysbus_connect_irq(SYS_BUS_DEVICE(dev), 2, 285 qdev_get_gpio_in(pic, PXA2XX_PIC_GPIO_X)); 286 287 return dev; 288 } 289 290 static void pxa2xx_gpio_initfn(Object *obj) 291 { 292 SysBusDevice *sbd = SYS_BUS_DEVICE(obj); 293 DeviceState *dev = DEVICE(sbd); 294 PXA2xxGPIOInfo *s = PXA2XX_GPIO(dev); 295 296 memory_region_init_io(&s->iomem, obj, &pxa_gpio_ops, 297 s, "pxa2xx-gpio", 0x1000); 298 sysbus_init_mmio(sbd, &s->iomem); 299 sysbus_init_irq(sbd, &s->irq0); 300 sysbus_init_irq(sbd, &s->irq1); 301 sysbus_init_irq(sbd, &s->irqX); 302 } 303 304 static void pxa2xx_gpio_realize(DeviceState *dev, Error **errp) 305 { 306 PXA2xxGPIOInfo *s = PXA2XX_GPIO(dev); 307 308 s->cpu = ARM_CPU(qemu_get_cpu(s->ncpu)); 309 310 qdev_init_gpio_in(dev, pxa2xx_gpio_set, s->lines); 311 qdev_init_gpio_out(dev, s->handler, s->lines); 312 } 313 314 /* 315 * Registers a callback to notify on GPLR reads. This normally 316 * shouldn't be needed but it is used for the hack on Spitz machines. 317 */ 318 void pxa2xx_gpio_read_notifier(DeviceState *dev, qemu_irq handler) 319 { 320 PXA2xxGPIOInfo *s = PXA2XX_GPIO(dev); 321 322 s->read_notify = handler; 323 } 324 325 static const VMStateDescription vmstate_pxa2xx_gpio_regs = { 326 .name = "pxa2xx-gpio", 327 .version_id = 1, 328 .minimum_version_id = 1, 329 .fields = (VMStateField[]) { 330 VMSTATE_UINT32_ARRAY(ilevel, PXA2xxGPIOInfo, PXA2XX_GPIO_BANKS), 331 VMSTATE_UINT32_ARRAY(olevel, PXA2xxGPIOInfo, PXA2XX_GPIO_BANKS), 332 VMSTATE_UINT32_ARRAY(dir, PXA2xxGPIOInfo, PXA2XX_GPIO_BANKS), 333 VMSTATE_UINT32_ARRAY(rising, PXA2xxGPIOInfo, PXA2XX_GPIO_BANKS), 334 VMSTATE_UINT32_ARRAY(falling, PXA2xxGPIOInfo, PXA2XX_GPIO_BANKS), 335 VMSTATE_UINT32_ARRAY(status, PXA2xxGPIOInfo, PXA2XX_GPIO_BANKS), 336 VMSTATE_UINT32_ARRAY(gafr, PXA2xxGPIOInfo, PXA2XX_GPIO_BANKS * 2), 337 VMSTATE_UINT32_ARRAY(prev_level, PXA2xxGPIOInfo, PXA2XX_GPIO_BANKS), 338 VMSTATE_END_OF_LIST(), 339 }, 340 }; 341 342 static Property pxa2xx_gpio_properties[] = { 343 DEFINE_PROP_INT32("lines", PXA2xxGPIOInfo, lines, 0), 344 DEFINE_PROP_INT32("ncpu", PXA2xxGPIOInfo, ncpu, 0), 345 DEFINE_PROP_END_OF_LIST(), 346 }; 347 348 static void pxa2xx_gpio_class_init(ObjectClass *klass, void *data) 349 { 350 DeviceClass *dc = DEVICE_CLASS(klass); 351 352 dc->desc = "PXA2xx GPIO controller"; 353 device_class_set_props(dc, pxa2xx_gpio_properties); 354 dc->vmsd = &vmstate_pxa2xx_gpio_regs; 355 dc->realize = pxa2xx_gpio_realize; 356 } 357 358 static const TypeInfo pxa2xx_gpio_info = { 359 .name = TYPE_PXA2XX_GPIO, 360 .parent = TYPE_SYS_BUS_DEVICE, 361 .instance_size = sizeof(PXA2xxGPIOInfo), 362 .instance_init = pxa2xx_gpio_initfn, 363 .class_init = pxa2xx_gpio_class_init, 364 }; 365 366 static void pxa2xx_gpio_register_types(void) 367 { 368 type_register_static(&pxa2xx_gpio_info); 369 } 370 371 type_init(pxa2xx_gpio_register_types) 372