1 /* 2 * ARM RealView Baseboard System emulation. 3 * 4 * Copyright (c) 2006-2007 CodeSourcery. 5 * Written by Paul Brook 6 * 7 * This code is licensed under the GPL. 8 */ 9 10 #include "hw/sysbus.h" 11 #include "hw/arm/arm.h" 12 #include "hw/arm/primecell.h" 13 #include "hw/devices.h" 14 #include "hw/pci/pci.h" 15 #include "net/net.h" 16 #include "sysemu/sysemu.h" 17 #include "hw/boards.h" 18 #include "hw/i2c/i2c.h" 19 #include "sysemu/blockdev.h" 20 #include "exec/address-spaces.h" 21 #include "qemu/error-report.h" 22 23 #define SMP_BOOT_ADDR 0xe0000000 24 #define SMP_BOOTREG_ADDR 0x10000030 25 26 /* Board init. */ 27 28 static struct arm_boot_info realview_binfo = { 29 .smp_loader_start = SMP_BOOT_ADDR, 30 .smp_bootreg_addr = SMP_BOOTREG_ADDR, 31 }; 32 33 /* The following two lists must be consistent. */ 34 enum realview_board_type { 35 BOARD_EB, 36 BOARD_EB_MPCORE, 37 BOARD_PB_A8, 38 BOARD_PBX_A9, 39 }; 40 41 static const int realview_board_id[] = { 42 0x33b, 43 0x33b, 44 0x769, 45 0x76d 46 }; 47 48 static void realview_init(MachineState *machine, 49 enum realview_board_type board_type) 50 { 51 ARMCPU *cpu = NULL; 52 CPUARMState *env; 53 ObjectClass *cpu_oc; 54 MemoryRegion *sysmem = get_system_memory(); 55 MemoryRegion *ram_lo = g_new(MemoryRegion, 1); 56 MemoryRegion *ram_hi = g_new(MemoryRegion, 1); 57 MemoryRegion *ram_alias = g_new(MemoryRegion, 1); 58 MemoryRegion *ram_hack = g_new(MemoryRegion, 1); 59 DeviceState *dev, *sysctl, *gpio2, *pl041; 60 SysBusDevice *busdev; 61 qemu_irq pic[64]; 62 qemu_irq mmc_irq[2]; 63 PCIBus *pci_bus = NULL; 64 NICInfo *nd; 65 I2CBus *i2c; 66 int n; 67 int done_nic = 0; 68 qemu_irq cpu_irq[4]; 69 int is_mpcore = 0; 70 int is_pb = 0; 71 uint32_t proc_id = 0; 72 uint32_t sys_id; 73 ram_addr_t low_ram_size; 74 ram_addr_t ram_size = machine->ram_size; 75 hwaddr periphbase = 0; 76 77 switch (board_type) { 78 case BOARD_EB: 79 break; 80 case BOARD_EB_MPCORE: 81 is_mpcore = 1; 82 periphbase = 0x10100000; 83 break; 84 case BOARD_PB_A8: 85 is_pb = 1; 86 break; 87 case BOARD_PBX_A9: 88 is_mpcore = 1; 89 is_pb = 1; 90 periphbase = 0x1f000000; 91 break; 92 } 93 94 cpu_oc = cpu_class_by_name(TYPE_ARM_CPU, machine->cpu_model); 95 if (!cpu_oc) { 96 fprintf(stderr, "Unable to find CPU definition\n"); 97 exit(1); 98 } 99 100 for (n = 0; n < smp_cpus; n++) { 101 Object *cpuobj = object_new(object_class_get_name(cpu_oc)); 102 Error *err = NULL; 103 104 if (is_pb && is_mpcore) { 105 object_property_set_int(cpuobj, periphbase, "reset-cbar", &err); 106 if (err) { 107 error_report("%s", error_get_pretty(err)); 108 exit(1); 109 } 110 } 111 112 object_property_set_bool(cpuobj, true, "realized", &err); 113 if (err) { 114 error_report("%s", error_get_pretty(err)); 115 exit(1); 116 } 117 118 cpu_irq[n] = qdev_get_gpio_in(DEVICE(cpuobj), ARM_CPU_IRQ); 119 } 120 cpu = ARM_CPU(first_cpu); 121 env = &cpu->env; 122 if (arm_feature(env, ARM_FEATURE_V7)) { 123 if (is_mpcore) { 124 proc_id = 0x0c000000; 125 } else { 126 proc_id = 0x0e000000; 127 } 128 } else if (arm_feature(env, ARM_FEATURE_V6K)) { 129 proc_id = 0x06000000; 130 } else if (arm_feature(env, ARM_FEATURE_V6)) { 131 proc_id = 0x04000000; 132 } else { 133 proc_id = 0x02000000; 134 } 135 136 if (is_pb && ram_size > 0x20000000) { 137 /* Core tile RAM. */ 138 low_ram_size = ram_size - 0x20000000; 139 ram_size = 0x20000000; 140 memory_region_init_ram(ram_lo, NULL, "realview.lowmem", low_ram_size, 141 &error_abort); 142 vmstate_register_ram_global(ram_lo); 143 memory_region_add_subregion(sysmem, 0x20000000, ram_lo); 144 } 145 146 memory_region_init_ram(ram_hi, NULL, "realview.highmem", ram_size, 147 &error_abort); 148 vmstate_register_ram_global(ram_hi); 149 low_ram_size = ram_size; 150 if (low_ram_size > 0x10000000) 151 low_ram_size = 0x10000000; 152 /* SDRAM at address zero. */ 153 memory_region_init_alias(ram_alias, NULL, "realview.alias", 154 ram_hi, 0, low_ram_size); 155 memory_region_add_subregion(sysmem, 0, ram_alias); 156 if (is_pb) { 157 /* And again at a high address. */ 158 memory_region_add_subregion(sysmem, 0x70000000, ram_hi); 159 } else { 160 ram_size = low_ram_size; 161 } 162 163 sys_id = is_pb ? 0x01780500 : 0xc1400400; 164 sysctl = qdev_create(NULL, "realview_sysctl"); 165 qdev_prop_set_uint32(sysctl, "sys_id", sys_id); 166 qdev_prop_set_uint32(sysctl, "proc_id", proc_id); 167 qdev_init_nofail(sysctl); 168 sysbus_mmio_map(SYS_BUS_DEVICE(sysctl), 0, 0x10000000); 169 170 if (is_mpcore) { 171 dev = qdev_create(NULL, is_pb ? "a9mpcore_priv": "realview_mpcore"); 172 qdev_prop_set_uint32(dev, "num-cpu", smp_cpus); 173 qdev_init_nofail(dev); 174 busdev = SYS_BUS_DEVICE(dev); 175 sysbus_mmio_map(busdev, 0, periphbase); 176 for (n = 0; n < smp_cpus; n++) { 177 sysbus_connect_irq(busdev, n, cpu_irq[n]); 178 } 179 sysbus_create_varargs("l2x0", periphbase + 0x2000, NULL); 180 /* Both A9 and 11MPCore put the GIC CPU i/f at base + 0x100 */ 181 realview_binfo.gic_cpu_if_addr = periphbase + 0x100; 182 } else { 183 uint32_t gic_addr = is_pb ? 0x1e000000 : 0x10040000; 184 /* For now just create the nIRQ GIC, and ignore the others. */ 185 dev = sysbus_create_simple("realview_gic", gic_addr, cpu_irq[0]); 186 } 187 for (n = 0; n < 64; n++) { 188 pic[n] = qdev_get_gpio_in(dev, n); 189 } 190 191 pl041 = qdev_create(NULL, "pl041"); 192 qdev_prop_set_uint32(pl041, "nc_fifo_depth", 512); 193 qdev_init_nofail(pl041); 194 sysbus_mmio_map(SYS_BUS_DEVICE(pl041), 0, 0x10004000); 195 sysbus_connect_irq(SYS_BUS_DEVICE(pl041), 0, pic[19]); 196 197 sysbus_create_simple("pl050_keyboard", 0x10006000, pic[20]); 198 sysbus_create_simple("pl050_mouse", 0x10007000, pic[21]); 199 200 sysbus_create_simple("pl011", 0x10009000, pic[12]); 201 sysbus_create_simple("pl011", 0x1000a000, pic[13]); 202 sysbus_create_simple("pl011", 0x1000b000, pic[14]); 203 sysbus_create_simple("pl011", 0x1000c000, pic[15]); 204 205 /* DMA controller is optional, apparently. */ 206 sysbus_create_simple("pl081", 0x10030000, pic[24]); 207 208 sysbus_create_simple("sp804", 0x10011000, pic[4]); 209 sysbus_create_simple("sp804", 0x10012000, pic[5]); 210 211 sysbus_create_simple("pl061", 0x10013000, pic[6]); 212 sysbus_create_simple("pl061", 0x10014000, pic[7]); 213 gpio2 = sysbus_create_simple("pl061", 0x10015000, pic[8]); 214 215 sysbus_create_simple("pl111", 0x10020000, pic[23]); 216 217 dev = sysbus_create_varargs("pl181", 0x10005000, pic[17], pic[18], NULL); 218 /* Wire up MMC card detect and read-only signals. These have 219 * to go to both the PL061 GPIO and the sysctl register. 220 * Note that the PL181 orders these lines (readonly,inserted) 221 * and the PL061 has them the other way about. Also the card 222 * detect line is inverted. 223 */ 224 mmc_irq[0] = qemu_irq_split( 225 qdev_get_gpio_in(sysctl, ARM_SYSCTL_GPIO_MMC_WPROT), 226 qdev_get_gpio_in(gpio2, 1)); 227 mmc_irq[1] = qemu_irq_split( 228 qdev_get_gpio_in(sysctl, ARM_SYSCTL_GPIO_MMC_CARDIN), 229 qemu_irq_invert(qdev_get_gpio_in(gpio2, 0))); 230 qdev_connect_gpio_out(dev, 0, mmc_irq[0]); 231 qdev_connect_gpio_out(dev, 1, mmc_irq[1]); 232 233 sysbus_create_simple("pl031", 0x10017000, pic[10]); 234 235 if (!is_pb) { 236 dev = qdev_create(NULL, "realview_pci"); 237 busdev = SYS_BUS_DEVICE(dev); 238 qdev_init_nofail(dev); 239 sysbus_mmio_map(busdev, 0, 0x10019000); /* PCI controller registers */ 240 sysbus_mmio_map(busdev, 1, 0x60000000); /* PCI self-config */ 241 sysbus_mmio_map(busdev, 2, 0x61000000); /* PCI config */ 242 sysbus_mmio_map(busdev, 3, 0x62000000); /* PCI I/O */ 243 sysbus_mmio_map(busdev, 4, 0x63000000); /* PCI memory window 1 */ 244 sysbus_mmio_map(busdev, 5, 0x64000000); /* PCI memory window 2 */ 245 sysbus_mmio_map(busdev, 6, 0x68000000); /* PCI memory window 3 */ 246 sysbus_connect_irq(busdev, 0, pic[48]); 247 sysbus_connect_irq(busdev, 1, pic[49]); 248 sysbus_connect_irq(busdev, 2, pic[50]); 249 sysbus_connect_irq(busdev, 3, pic[51]); 250 pci_bus = (PCIBus *)qdev_get_child_bus(dev, "pci"); 251 if (usb_enabled(false)) { 252 pci_create_simple(pci_bus, -1, "pci-ohci"); 253 } 254 n = drive_get_max_bus(IF_SCSI); 255 while (n >= 0) { 256 pci_create_simple(pci_bus, -1, "lsi53c895a"); 257 n--; 258 } 259 } 260 for(n = 0; n < nb_nics; n++) { 261 nd = &nd_table[n]; 262 263 if (!done_nic && (!nd->model || 264 strcmp(nd->model, is_pb ? "lan9118" : "smc91c111") == 0)) { 265 if (is_pb) { 266 lan9118_init(nd, 0x4e000000, pic[28]); 267 } else { 268 smc91c111_init(nd, 0x4e000000, pic[28]); 269 } 270 done_nic = 1; 271 } else { 272 if (pci_bus) { 273 pci_nic_init_nofail(nd, pci_bus, "rtl8139", NULL); 274 } 275 } 276 } 277 278 dev = sysbus_create_simple("versatile_i2c", 0x10002000, NULL); 279 i2c = (I2CBus *)qdev_get_child_bus(dev, "i2c"); 280 i2c_create_slave(i2c, "ds1338", 0x68); 281 282 /* Memory map for RealView Emulation Baseboard: */ 283 /* 0x10000000 System registers. */ 284 /* 0x10001000 System controller. */ 285 /* 0x10002000 Two-Wire Serial Bus. */ 286 /* 0x10003000 Reserved. */ 287 /* 0x10004000 AACI. */ 288 /* 0x10005000 MCI. */ 289 /* 0x10006000 KMI0. */ 290 /* 0x10007000 KMI1. */ 291 /* 0x10008000 Character LCD. (EB) */ 292 /* 0x10009000 UART0. */ 293 /* 0x1000a000 UART1. */ 294 /* 0x1000b000 UART2. */ 295 /* 0x1000c000 UART3. */ 296 /* 0x1000d000 SSPI. */ 297 /* 0x1000e000 SCI. */ 298 /* 0x1000f000 Reserved. */ 299 /* 0x10010000 Watchdog. */ 300 /* 0x10011000 Timer 0+1. */ 301 /* 0x10012000 Timer 2+3. */ 302 /* 0x10013000 GPIO 0. */ 303 /* 0x10014000 GPIO 1. */ 304 /* 0x10015000 GPIO 2. */ 305 /* 0x10002000 Two-Wire Serial Bus - DVI. (PB) */ 306 /* 0x10017000 RTC. */ 307 /* 0x10018000 DMC. */ 308 /* 0x10019000 PCI controller config. */ 309 /* 0x10020000 CLCD. */ 310 /* 0x10030000 DMA Controller. */ 311 /* 0x10040000 GIC1. (EB) */ 312 /* 0x10050000 GIC2. (EB) */ 313 /* 0x10060000 GIC3. (EB) */ 314 /* 0x10070000 GIC4. (EB) */ 315 /* 0x10080000 SMC. */ 316 /* 0x1e000000 GIC1. (PB) */ 317 /* 0x1e001000 GIC2. (PB) */ 318 /* 0x1e002000 GIC3. (PB) */ 319 /* 0x1e003000 GIC4. (PB) */ 320 /* 0x40000000 NOR flash. */ 321 /* 0x44000000 DoC flash. */ 322 /* 0x48000000 SRAM. */ 323 /* 0x4c000000 Configuration flash. */ 324 /* 0x4e000000 Ethernet. */ 325 /* 0x4f000000 USB. */ 326 /* 0x50000000 PISMO. */ 327 /* 0x54000000 PISMO. */ 328 /* 0x58000000 PISMO. */ 329 /* 0x5c000000 PISMO. */ 330 /* 0x60000000 PCI. */ 331 /* 0x60000000 PCI Self Config. */ 332 /* 0x61000000 PCI Config. */ 333 /* 0x62000000 PCI IO. */ 334 /* 0x63000000 PCI mem 0. */ 335 /* 0x64000000 PCI mem 1. */ 336 /* 0x68000000 PCI mem 2. */ 337 338 /* ??? Hack to map an additional page of ram for the secondary CPU 339 startup code. I guess this works on real hardware because the 340 BootROM happens to be in ROM/flash or in memory that isn't clobbered 341 until after Linux boots the secondary CPUs. */ 342 memory_region_init_ram(ram_hack, NULL, "realview.hack", 0x1000, 343 &error_abort); 344 vmstate_register_ram_global(ram_hack); 345 memory_region_add_subregion(sysmem, SMP_BOOT_ADDR, ram_hack); 346 347 realview_binfo.ram_size = ram_size; 348 realview_binfo.kernel_filename = machine->kernel_filename; 349 realview_binfo.kernel_cmdline = machine->kernel_cmdline; 350 realview_binfo.initrd_filename = machine->initrd_filename; 351 realview_binfo.nb_cpus = smp_cpus; 352 realview_binfo.board_id = realview_board_id[board_type]; 353 realview_binfo.loader_start = (board_type == BOARD_PB_A8 ? 0x70000000 : 0); 354 arm_load_kernel(ARM_CPU(first_cpu), &realview_binfo); 355 } 356 357 static void realview_eb_init(MachineState *machine) 358 { 359 if (!machine->cpu_model) { 360 machine->cpu_model = "arm926"; 361 } 362 realview_init(machine, BOARD_EB); 363 } 364 365 static void realview_eb_mpcore_init(MachineState *machine) 366 { 367 if (!machine->cpu_model) { 368 machine->cpu_model = "arm11mpcore"; 369 } 370 realview_init(machine, BOARD_EB_MPCORE); 371 } 372 373 static void realview_pb_a8_init(MachineState *machine) 374 { 375 if (!machine->cpu_model) { 376 machine->cpu_model = "cortex-a8"; 377 } 378 realview_init(machine, BOARD_PB_A8); 379 } 380 381 static void realview_pbx_a9_init(MachineState *machine) 382 { 383 if (!machine->cpu_model) { 384 machine->cpu_model = "cortex-a9"; 385 } 386 realview_init(machine, BOARD_PBX_A9); 387 } 388 389 static QEMUMachine realview_eb_machine = { 390 .name = "realview-eb", 391 .desc = "ARM RealView Emulation Baseboard (ARM926EJ-S)", 392 .init = realview_eb_init, 393 .block_default_type = IF_SCSI, 394 }; 395 396 static QEMUMachine realview_eb_mpcore_machine = { 397 .name = "realview-eb-mpcore", 398 .desc = "ARM RealView Emulation Baseboard (ARM11MPCore)", 399 .init = realview_eb_mpcore_init, 400 .block_default_type = IF_SCSI, 401 .max_cpus = 4, 402 }; 403 404 static QEMUMachine realview_pb_a8_machine = { 405 .name = "realview-pb-a8", 406 .desc = "ARM RealView Platform Baseboard for Cortex-A8", 407 .init = realview_pb_a8_init, 408 }; 409 410 static QEMUMachine realview_pbx_a9_machine = { 411 .name = "realview-pbx-a9", 412 .desc = "ARM RealView Platform Baseboard Explore for Cortex-A9", 413 .init = realview_pbx_a9_init, 414 .block_default_type = IF_SCSI, 415 .max_cpus = 4, 416 }; 417 418 static void realview_machine_init(void) 419 { 420 qemu_register_machine(&realview_eb_machine); 421 qemu_register_machine(&realview_eb_mpcore_machine); 422 qemu_register_machine(&realview_pb_a8_machine); 423 qemu_register_machine(&realview_pbx_a9_machine); 424 } 425 426 machine_init(realview_machine_init); 427