1 /* 2 * ARM SBSA Reference Platform emulation 3 * 4 * Copyright (c) 2018 Linaro Limited 5 * Copyright (c) 2023 Qualcomm Innovation Center, Inc. All rights reserved. 6 * Written by Hongbo Zhang <hongbo.zhang@linaro.org> 7 * 8 * This program is free software; you can redistribute it and/or modify it 9 * under the terms and conditions of the GNU General Public License, 10 * version 2 or later, as published by the Free Software Foundation. 11 * 12 * This program is distributed in the hope it will be useful, but WITHOUT 13 * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or 14 * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for 15 * more details. 16 * 17 * You should have received a copy of the GNU General Public License along with 18 * this program. If not, see <http://www.gnu.org/licenses/>. 19 */ 20 21 #include "qemu/osdep.h" 22 #include "qemu/datadir.h" 23 #include "qapi/error.h" 24 #include "qemu/error-report.h" 25 #include "qemu/units.h" 26 #include "sysemu/device_tree.h" 27 #include "sysemu/kvm.h" 28 #include "sysemu/numa.h" 29 #include "sysemu/runstate.h" 30 #include "sysemu/sysemu.h" 31 #include "exec/hwaddr.h" 32 #include "kvm_arm.h" 33 #include "hw/arm/boot.h" 34 #include "hw/arm/bsa.h" 35 #include "hw/arm/fdt.h" 36 #include "hw/arm/smmuv3.h" 37 #include "hw/block/flash.h" 38 #include "hw/boards.h" 39 #include "hw/ide/internal.h" 40 #include "hw/ide/ahci_internal.h" 41 #include "hw/intc/arm_gicv3_common.h" 42 #include "hw/intc/arm_gicv3_its_common.h" 43 #include "hw/loader.h" 44 #include "hw/pci-host/gpex.h" 45 #include "hw/qdev-properties.h" 46 #include "hw/usb.h" 47 #include "hw/usb/xhci.h" 48 #include "hw/char/pl011.h" 49 #include "hw/watchdog/sbsa_gwdt.h" 50 #include "net/net.h" 51 #include "qapi/qmp/qlist.h" 52 #include "qom/object.h" 53 54 #define RAMLIMIT_GB 8192 55 #define RAMLIMIT_BYTES (RAMLIMIT_GB * GiB) 56 57 #define NUM_IRQS 256 58 #define NUM_SMMU_IRQS 4 59 #define NUM_SATA_PORTS 6 60 61 enum { 62 SBSA_FLASH, 63 SBSA_MEM, 64 SBSA_CPUPERIPHS, 65 SBSA_GIC_DIST, 66 SBSA_GIC_REDIST, 67 SBSA_GIC_ITS, 68 SBSA_SECURE_EC, 69 SBSA_GWDT_WS0, 70 SBSA_GWDT_REFRESH, 71 SBSA_GWDT_CONTROL, 72 SBSA_SMMU, 73 SBSA_UART, 74 SBSA_RTC, 75 SBSA_PCIE, 76 SBSA_PCIE_MMIO, 77 SBSA_PCIE_MMIO_HIGH, 78 SBSA_PCIE_PIO, 79 SBSA_PCIE_ECAM, 80 SBSA_GPIO, 81 SBSA_SECURE_UART, 82 SBSA_SECURE_UART_MM, 83 SBSA_SECURE_MEM, 84 SBSA_AHCI, 85 SBSA_XHCI, 86 }; 87 88 struct SBSAMachineState { 89 MachineState parent; 90 struct arm_boot_info bootinfo; 91 int smp_cpus; 92 void *fdt; 93 int fdt_size; 94 int psci_conduit; 95 DeviceState *gic; 96 PFlashCFI01 *flash[2]; 97 }; 98 99 #define TYPE_SBSA_MACHINE MACHINE_TYPE_NAME("sbsa-ref") 100 OBJECT_DECLARE_SIMPLE_TYPE(SBSAMachineState, SBSA_MACHINE) 101 102 static const MemMapEntry sbsa_ref_memmap[] = { 103 /* 512M boot ROM */ 104 [SBSA_FLASH] = { 0, 0x20000000 }, 105 /* 512M secure memory */ 106 [SBSA_SECURE_MEM] = { 0x20000000, 0x20000000 }, 107 /* Space reserved for CPU peripheral devices */ 108 [SBSA_CPUPERIPHS] = { 0x40000000, 0x00040000 }, 109 [SBSA_GIC_DIST] = { 0x40060000, 0x00010000 }, 110 [SBSA_GIC_REDIST] = { 0x40080000, 0x04000000 }, 111 [SBSA_GIC_ITS] = { 0x44081000, 0x00020000 }, 112 [SBSA_SECURE_EC] = { 0x50000000, 0x00001000 }, 113 [SBSA_GWDT_REFRESH] = { 0x50010000, 0x00001000 }, 114 [SBSA_GWDT_CONTROL] = { 0x50011000, 0x00001000 }, 115 [SBSA_UART] = { 0x60000000, 0x00001000 }, 116 [SBSA_RTC] = { 0x60010000, 0x00001000 }, 117 [SBSA_GPIO] = { 0x60020000, 0x00001000 }, 118 [SBSA_SECURE_UART] = { 0x60030000, 0x00001000 }, 119 [SBSA_SECURE_UART_MM] = { 0x60040000, 0x00001000 }, 120 [SBSA_SMMU] = { 0x60050000, 0x00020000 }, 121 /* Space here reserved for more SMMUs */ 122 [SBSA_AHCI] = { 0x60100000, 0x00010000 }, 123 [SBSA_XHCI] = { 0x60110000, 0x00010000 }, 124 /* Space here reserved for other devices */ 125 [SBSA_PCIE_PIO] = { 0x7fff0000, 0x00010000 }, 126 /* 32-bit address PCIE MMIO space */ 127 [SBSA_PCIE_MMIO] = { 0x80000000, 0x70000000 }, 128 /* 256M PCIE ECAM space */ 129 [SBSA_PCIE_ECAM] = { 0xf0000000, 0x10000000 }, 130 /* ~1TB PCIE MMIO space (4GB to 1024GB boundary) */ 131 [SBSA_PCIE_MMIO_HIGH] = { 0x100000000ULL, 0xFF00000000ULL }, 132 [SBSA_MEM] = { 0x10000000000ULL, RAMLIMIT_BYTES }, 133 }; 134 135 static const int sbsa_ref_irqmap[] = { 136 [SBSA_UART] = 1, 137 [SBSA_RTC] = 2, 138 [SBSA_PCIE] = 3, /* ... to 6 */ 139 [SBSA_GPIO] = 7, 140 [SBSA_SECURE_UART] = 8, 141 [SBSA_SECURE_UART_MM] = 9, 142 [SBSA_AHCI] = 10, 143 [SBSA_XHCI] = 11, 144 [SBSA_SMMU] = 12, /* ... to 15 */ 145 [SBSA_GWDT_WS0] = 16, 146 }; 147 148 static uint64_t sbsa_ref_cpu_mp_affinity(SBSAMachineState *sms, int idx) 149 { 150 uint8_t clustersz = ARM_DEFAULT_CPUS_PER_CLUSTER; 151 return arm_cpu_mp_affinity(idx, clustersz); 152 } 153 154 static void sbsa_fdt_add_gic_node(SBSAMachineState *sms) 155 { 156 char *nodename; 157 158 nodename = g_strdup_printf("/intc"); 159 qemu_fdt_add_subnode(sms->fdt, nodename); 160 qemu_fdt_setprop_sized_cells(sms->fdt, nodename, "reg", 161 2, sbsa_ref_memmap[SBSA_GIC_DIST].base, 162 2, sbsa_ref_memmap[SBSA_GIC_DIST].size, 163 2, sbsa_ref_memmap[SBSA_GIC_REDIST].base, 164 2, sbsa_ref_memmap[SBSA_GIC_REDIST].size); 165 166 nodename = g_strdup_printf("/intc/its"); 167 qemu_fdt_add_subnode(sms->fdt, nodename); 168 qemu_fdt_setprop_sized_cells(sms->fdt, nodename, "reg", 169 2, sbsa_ref_memmap[SBSA_GIC_ITS].base, 170 2, sbsa_ref_memmap[SBSA_GIC_ITS].size); 171 172 g_free(nodename); 173 } 174 175 /* 176 * Firmware on this machine only uses ACPI table to load OS, these limited 177 * device tree nodes are just to let firmware know the info which varies from 178 * command line parameters, so it is not necessary to be fully compatible 179 * with the kernel CPU and NUMA binding rules. 180 */ 181 static void create_fdt(SBSAMachineState *sms) 182 { 183 void *fdt = create_device_tree(&sms->fdt_size); 184 const MachineState *ms = MACHINE(sms); 185 int nb_numa_nodes = ms->numa_state->num_nodes; 186 int cpu; 187 188 if (!fdt) { 189 error_report("create_device_tree() failed"); 190 exit(1); 191 } 192 193 sms->fdt = fdt; 194 195 qemu_fdt_setprop_string(fdt, "/", "compatible", "linux,sbsa-ref"); 196 qemu_fdt_setprop_cell(fdt, "/", "#address-cells", 0x2); 197 qemu_fdt_setprop_cell(fdt, "/", "#size-cells", 0x2); 198 199 /* 200 * This versioning scheme is for informing platform fw only. It is neither: 201 * - A QEMU versioned machine type; a given version of QEMU will emulate 202 * a given version of the platform. 203 * - A reflection of level of SBSA (now SystemReady SR) support provided. 204 * 205 * machine-version-major: updated when changes breaking fw compatibility 206 * are introduced. 207 * machine-version-minor: updated when features are added that don't break 208 * fw compatibility. 209 */ 210 qemu_fdt_setprop_cell(fdt, "/", "machine-version-major", 0); 211 qemu_fdt_setprop_cell(fdt, "/", "machine-version-minor", 3); 212 213 if (ms->numa_state->have_numa_distance) { 214 int size = nb_numa_nodes * nb_numa_nodes * 3 * sizeof(uint32_t); 215 uint32_t *matrix = g_malloc0(size); 216 int idx, i, j; 217 218 for (i = 0; i < nb_numa_nodes; i++) { 219 for (j = 0; j < nb_numa_nodes; j++) { 220 idx = (i * nb_numa_nodes + j) * 3; 221 matrix[idx + 0] = cpu_to_be32(i); 222 matrix[idx + 1] = cpu_to_be32(j); 223 matrix[idx + 2] = 224 cpu_to_be32(ms->numa_state->nodes[i].distance[j]); 225 } 226 } 227 228 qemu_fdt_add_subnode(fdt, "/distance-map"); 229 qemu_fdt_setprop(fdt, "/distance-map", "distance-matrix", 230 matrix, size); 231 g_free(matrix); 232 } 233 234 /* 235 * From Documentation/devicetree/bindings/arm/cpus.yaml 236 * On ARM v8 64-bit systems this property is required 237 * and matches the MPIDR_EL1 register affinity bits. 238 * 239 * * If cpus node's #address-cells property is set to 2 240 * 241 * The first reg cell bits [7:0] must be set to 242 * bits [39:32] of MPIDR_EL1. 243 * 244 * The second reg cell bits [23:0] must be set to 245 * bits [23:0] of MPIDR_EL1. 246 */ 247 qemu_fdt_add_subnode(sms->fdt, "/cpus"); 248 qemu_fdt_setprop_cell(sms->fdt, "/cpus", "#address-cells", 2); 249 qemu_fdt_setprop_cell(sms->fdt, "/cpus", "#size-cells", 0x0); 250 251 for (cpu = sms->smp_cpus - 1; cpu >= 0; cpu--) { 252 char *nodename = g_strdup_printf("/cpus/cpu@%d", cpu); 253 ARMCPU *armcpu = ARM_CPU(qemu_get_cpu(cpu)); 254 CPUState *cs = CPU(armcpu); 255 uint64_t mpidr = sbsa_ref_cpu_mp_affinity(sms, cpu); 256 257 qemu_fdt_add_subnode(sms->fdt, nodename); 258 qemu_fdt_setprop_u64(sms->fdt, nodename, "reg", mpidr); 259 260 if (ms->possible_cpus->cpus[cs->cpu_index].props.has_node_id) { 261 qemu_fdt_setprop_cell(sms->fdt, nodename, "numa-node-id", 262 ms->possible_cpus->cpus[cs->cpu_index].props.node_id); 263 } 264 265 g_free(nodename); 266 } 267 268 sbsa_fdt_add_gic_node(sms); 269 } 270 271 #define SBSA_FLASH_SECTOR_SIZE (256 * KiB) 272 273 static PFlashCFI01 *sbsa_flash_create1(SBSAMachineState *sms, 274 const char *name, 275 const char *alias_prop_name) 276 { 277 /* 278 * Create a single flash device. We use the same parameters as 279 * the flash devices on the Versatile Express board. 280 */ 281 DeviceState *dev = qdev_new(TYPE_PFLASH_CFI01); 282 283 qdev_prop_set_uint64(dev, "sector-length", SBSA_FLASH_SECTOR_SIZE); 284 qdev_prop_set_uint8(dev, "width", 4); 285 qdev_prop_set_uint8(dev, "device-width", 2); 286 qdev_prop_set_bit(dev, "big-endian", false); 287 qdev_prop_set_uint16(dev, "id0", 0x89); 288 qdev_prop_set_uint16(dev, "id1", 0x18); 289 qdev_prop_set_uint16(dev, "id2", 0x00); 290 qdev_prop_set_uint16(dev, "id3", 0x00); 291 qdev_prop_set_string(dev, "name", name); 292 object_property_add_child(OBJECT(sms), name, OBJECT(dev)); 293 object_property_add_alias(OBJECT(sms), alias_prop_name, 294 OBJECT(dev), "drive"); 295 return PFLASH_CFI01(dev); 296 } 297 298 static void sbsa_flash_create(SBSAMachineState *sms) 299 { 300 sms->flash[0] = sbsa_flash_create1(sms, "sbsa.flash0", "pflash0"); 301 sms->flash[1] = sbsa_flash_create1(sms, "sbsa.flash1", "pflash1"); 302 } 303 304 static void sbsa_flash_map1(PFlashCFI01 *flash, 305 hwaddr base, hwaddr size, 306 MemoryRegion *sysmem) 307 { 308 DeviceState *dev = DEVICE(flash); 309 310 assert(QEMU_IS_ALIGNED(size, SBSA_FLASH_SECTOR_SIZE)); 311 assert(size / SBSA_FLASH_SECTOR_SIZE <= UINT32_MAX); 312 qdev_prop_set_uint32(dev, "num-blocks", size / SBSA_FLASH_SECTOR_SIZE); 313 sysbus_realize_and_unref(SYS_BUS_DEVICE(dev), &error_fatal); 314 315 memory_region_add_subregion(sysmem, base, 316 sysbus_mmio_get_region(SYS_BUS_DEVICE(dev), 317 0)); 318 } 319 320 static void sbsa_flash_map(SBSAMachineState *sms, 321 MemoryRegion *sysmem, 322 MemoryRegion *secure_sysmem) 323 { 324 /* 325 * Map two flash devices to fill the SBSA_FLASH space in the memmap. 326 * sysmem is the system memory space. secure_sysmem is the secure view 327 * of the system, and the first flash device should be made visible only 328 * there. The second flash device is visible to both secure and nonsecure. 329 */ 330 hwaddr flashsize = sbsa_ref_memmap[SBSA_FLASH].size / 2; 331 hwaddr flashbase = sbsa_ref_memmap[SBSA_FLASH].base; 332 333 sbsa_flash_map1(sms->flash[0], flashbase, flashsize, 334 secure_sysmem); 335 sbsa_flash_map1(sms->flash[1], flashbase + flashsize, flashsize, 336 sysmem); 337 } 338 339 static bool sbsa_firmware_init(SBSAMachineState *sms, 340 MemoryRegion *sysmem, 341 MemoryRegion *secure_sysmem) 342 { 343 const char *bios_name; 344 int i; 345 BlockBackend *pflash_blk0; 346 347 /* Map legacy -drive if=pflash to machine properties */ 348 for (i = 0; i < ARRAY_SIZE(sms->flash); i++) { 349 pflash_cfi01_legacy_drive(sms->flash[i], 350 drive_get(IF_PFLASH, 0, i)); 351 } 352 353 sbsa_flash_map(sms, sysmem, secure_sysmem); 354 355 pflash_blk0 = pflash_cfi01_get_blk(sms->flash[0]); 356 357 bios_name = MACHINE(sms)->firmware; 358 if (bios_name) { 359 char *fname; 360 MemoryRegion *mr; 361 int image_size; 362 363 if (pflash_blk0) { 364 error_report("The contents of the first flash device may be " 365 "specified with -bios or with -drive if=pflash... " 366 "but you cannot use both options at once"); 367 exit(1); 368 } 369 370 /* Fall back to -bios */ 371 372 fname = qemu_find_file(QEMU_FILE_TYPE_BIOS, bios_name); 373 if (!fname) { 374 error_report("Could not find ROM image '%s'", bios_name); 375 exit(1); 376 } 377 mr = sysbus_mmio_get_region(SYS_BUS_DEVICE(sms->flash[0]), 0); 378 image_size = load_image_mr(fname, mr); 379 g_free(fname); 380 if (image_size < 0) { 381 error_report("Could not load ROM image '%s'", bios_name); 382 exit(1); 383 } 384 } 385 386 return pflash_blk0 || bios_name; 387 } 388 389 static void create_secure_ram(SBSAMachineState *sms, 390 MemoryRegion *secure_sysmem) 391 { 392 MemoryRegion *secram = g_new(MemoryRegion, 1); 393 hwaddr base = sbsa_ref_memmap[SBSA_SECURE_MEM].base; 394 hwaddr size = sbsa_ref_memmap[SBSA_SECURE_MEM].size; 395 396 memory_region_init_ram(secram, NULL, "sbsa-ref.secure-ram", size, 397 &error_fatal); 398 memory_region_add_subregion(secure_sysmem, base, secram); 399 } 400 401 static void create_its(SBSAMachineState *sms) 402 { 403 const char *itsclass = its_class_name(); 404 DeviceState *dev; 405 406 dev = qdev_new(itsclass); 407 408 object_property_set_link(OBJECT(dev), "parent-gicv3", OBJECT(sms->gic), 409 &error_abort); 410 sysbus_realize_and_unref(SYS_BUS_DEVICE(dev), &error_fatal); 411 sysbus_mmio_map(SYS_BUS_DEVICE(dev), 0, sbsa_ref_memmap[SBSA_GIC_ITS].base); 412 } 413 414 static void create_gic(SBSAMachineState *sms, MemoryRegion *mem) 415 { 416 unsigned int smp_cpus = MACHINE(sms)->smp.cpus; 417 SysBusDevice *gicbusdev; 418 const char *gictype; 419 uint32_t redist0_capacity, redist0_count; 420 QList *redist_region_count; 421 int i; 422 423 gictype = gicv3_class_name(); 424 425 sms->gic = qdev_new(gictype); 426 qdev_prop_set_uint32(sms->gic, "revision", 3); 427 qdev_prop_set_uint32(sms->gic, "num-cpu", smp_cpus); 428 /* 429 * Note that the num-irq property counts both internal and external 430 * interrupts; there are always 32 of the former (mandated by GIC spec). 431 */ 432 qdev_prop_set_uint32(sms->gic, "num-irq", NUM_IRQS + 32); 433 qdev_prop_set_bit(sms->gic, "has-security-extensions", true); 434 435 redist0_capacity = 436 sbsa_ref_memmap[SBSA_GIC_REDIST].size / GICV3_REDIST_SIZE; 437 redist0_count = MIN(smp_cpus, redist0_capacity); 438 439 redist_region_count = qlist_new(); 440 qlist_append_int(redist_region_count, redist0_count); 441 qdev_prop_set_array(sms->gic, "redist-region-count", redist_region_count); 442 443 object_property_set_link(OBJECT(sms->gic), "sysmem", 444 OBJECT(mem), &error_fatal); 445 qdev_prop_set_bit(sms->gic, "has-lpi", true); 446 447 gicbusdev = SYS_BUS_DEVICE(sms->gic); 448 sysbus_realize_and_unref(gicbusdev, &error_fatal); 449 sysbus_mmio_map(gicbusdev, 0, sbsa_ref_memmap[SBSA_GIC_DIST].base); 450 sysbus_mmio_map(gicbusdev, 1, sbsa_ref_memmap[SBSA_GIC_REDIST].base); 451 452 /* 453 * Wire the outputs from each CPU's generic timer and the GICv3 454 * maintenance interrupt signal to the appropriate GIC PPI inputs, 455 * and the GIC's IRQ/FIQ/VIRQ/VFIQ interrupt outputs to the CPU's inputs. 456 */ 457 for (i = 0; i < smp_cpus; i++) { 458 DeviceState *cpudev = DEVICE(qemu_get_cpu(i)); 459 int intidbase = NUM_IRQS + i * GIC_INTERNAL; 460 int irq; 461 /* 462 * Mapping from the output timer irq lines from the CPU to the 463 * GIC PPI inputs used for this board. 464 */ 465 const int timer_irq[] = { 466 [GTIMER_PHYS] = ARCH_TIMER_NS_EL1_IRQ, 467 [GTIMER_VIRT] = ARCH_TIMER_VIRT_IRQ, 468 [GTIMER_HYP] = ARCH_TIMER_NS_EL2_IRQ, 469 [GTIMER_SEC] = ARCH_TIMER_S_EL1_IRQ, 470 [GTIMER_HYPVIRT] = ARCH_TIMER_NS_EL2_VIRT_IRQ, 471 }; 472 473 for (irq = 0; irq < ARRAY_SIZE(timer_irq); irq++) { 474 qdev_connect_gpio_out(cpudev, irq, 475 qdev_get_gpio_in(sms->gic, 476 intidbase + timer_irq[irq])); 477 } 478 479 qdev_connect_gpio_out_named(cpudev, "gicv3-maintenance-interrupt", 0, 480 qdev_get_gpio_in(sms->gic, 481 intidbase 482 + ARCH_GIC_MAINT_IRQ)); 483 484 qdev_connect_gpio_out_named(cpudev, "pmu-interrupt", 0, 485 qdev_get_gpio_in(sms->gic, 486 intidbase 487 + VIRTUAL_PMU_IRQ)); 488 489 sysbus_connect_irq(gicbusdev, i, qdev_get_gpio_in(cpudev, ARM_CPU_IRQ)); 490 sysbus_connect_irq(gicbusdev, i + smp_cpus, 491 qdev_get_gpio_in(cpudev, ARM_CPU_FIQ)); 492 sysbus_connect_irq(gicbusdev, i + 2 * smp_cpus, 493 qdev_get_gpio_in(cpudev, ARM_CPU_VIRQ)); 494 sysbus_connect_irq(gicbusdev, i + 3 * smp_cpus, 495 qdev_get_gpio_in(cpudev, ARM_CPU_VFIQ)); 496 } 497 create_its(sms); 498 } 499 500 static void create_uart(const SBSAMachineState *sms, int uart, 501 MemoryRegion *mem, Chardev *chr) 502 { 503 hwaddr base = sbsa_ref_memmap[uart].base; 504 int irq = sbsa_ref_irqmap[uart]; 505 DeviceState *dev = qdev_new(TYPE_PL011); 506 SysBusDevice *s = SYS_BUS_DEVICE(dev); 507 508 qdev_prop_set_chr(dev, "chardev", chr); 509 sysbus_realize_and_unref(SYS_BUS_DEVICE(dev), &error_fatal); 510 memory_region_add_subregion(mem, base, 511 sysbus_mmio_get_region(s, 0)); 512 sysbus_connect_irq(s, 0, qdev_get_gpio_in(sms->gic, irq)); 513 } 514 515 static void create_rtc(const SBSAMachineState *sms) 516 { 517 hwaddr base = sbsa_ref_memmap[SBSA_RTC].base; 518 int irq = sbsa_ref_irqmap[SBSA_RTC]; 519 520 sysbus_create_simple("pl031", base, qdev_get_gpio_in(sms->gic, irq)); 521 } 522 523 static void create_wdt(const SBSAMachineState *sms) 524 { 525 hwaddr rbase = sbsa_ref_memmap[SBSA_GWDT_REFRESH].base; 526 hwaddr cbase = sbsa_ref_memmap[SBSA_GWDT_CONTROL].base; 527 DeviceState *dev = qdev_new(TYPE_WDT_SBSA); 528 SysBusDevice *s = SYS_BUS_DEVICE(dev); 529 int irq = sbsa_ref_irqmap[SBSA_GWDT_WS0]; 530 531 sysbus_realize_and_unref(s, &error_fatal); 532 sysbus_mmio_map(s, 0, rbase); 533 sysbus_mmio_map(s, 1, cbase); 534 sysbus_connect_irq(s, 0, qdev_get_gpio_in(sms->gic, irq)); 535 } 536 537 static DeviceState *gpio_key_dev; 538 static void sbsa_ref_powerdown_req(Notifier *n, void *opaque) 539 { 540 /* use gpio Pin 3 for power button event */ 541 qemu_set_irq(qdev_get_gpio_in(gpio_key_dev, 0), 1); 542 } 543 544 static Notifier sbsa_ref_powerdown_notifier = { 545 .notify = sbsa_ref_powerdown_req 546 }; 547 548 static void create_gpio(const SBSAMachineState *sms) 549 { 550 DeviceState *pl061_dev; 551 hwaddr base = sbsa_ref_memmap[SBSA_GPIO].base; 552 int irq = sbsa_ref_irqmap[SBSA_GPIO]; 553 554 pl061_dev = sysbus_create_simple("pl061", base, 555 qdev_get_gpio_in(sms->gic, irq)); 556 557 gpio_key_dev = sysbus_create_simple("gpio-key", -1, 558 qdev_get_gpio_in(pl061_dev, 3)); 559 560 /* connect powerdown request */ 561 qemu_register_powerdown_notifier(&sbsa_ref_powerdown_notifier); 562 } 563 564 static void create_ahci(const SBSAMachineState *sms) 565 { 566 hwaddr base = sbsa_ref_memmap[SBSA_AHCI].base; 567 int irq = sbsa_ref_irqmap[SBSA_AHCI]; 568 DeviceState *dev; 569 DriveInfo *hd[NUM_SATA_PORTS]; 570 SysbusAHCIState *sysahci; 571 AHCIState *ahci; 572 int i; 573 574 dev = qdev_new("sysbus-ahci"); 575 qdev_prop_set_uint32(dev, "num-ports", NUM_SATA_PORTS); 576 sysbus_realize_and_unref(SYS_BUS_DEVICE(dev), &error_fatal); 577 sysbus_mmio_map(SYS_BUS_DEVICE(dev), 0, base); 578 sysbus_connect_irq(SYS_BUS_DEVICE(dev), 0, qdev_get_gpio_in(sms->gic, irq)); 579 580 sysahci = SYSBUS_AHCI(dev); 581 ahci = &sysahci->ahci; 582 ide_drive_get(hd, ARRAY_SIZE(hd)); 583 for (i = 0; i < ahci->ports; i++) { 584 if (hd[i] == NULL) { 585 continue; 586 } 587 ide_bus_create_drive(&ahci->dev[i].port, 0, hd[i]); 588 } 589 } 590 591 static void create_xhci(const SBSAMachineState *sms) 592 { 593 hwaddr base = sbsa_ref_memmap[SBSA_XHCI].base; 594 int irq = sbsa_ref_irqmap[SBSA_XHCI]; 595 DeviceState *dev = qdev_new(TYPE_XHCI_SYSBUS); 596 qdev_prop_set_uint32(dev, "slots", XHCI_MAXSLOTS); 597 598 sysbus_realize_and_unref(SYS_BUS_DEVICE(dev), &error_fatal); 599 sysbus_mmio_map(SYS_BUS_DEVICE(dev), 0, base); 600 sysbus_connect_irq(SYS_BUS_DEVICE(dev), 0, qdev_get_gpio_in(sms->gic, irq)); 601 } 602 603 static void create_smmu(const SBSAMachineState *sms, PCIBus *bus) 604 { 605 hwaddr base = sbsa_ref_memmap[SBSA_SMMU].base; 606 int irq = sbsa_ref_irqmap[SBSA_SMMU]; 607 DeviceState *dev; 608 int i; 609 610 dev = qdev_new(TYPE_ARM_SMMUV3); 611 612 object_property_set_link(OBJECT(dev), "primary-bus", OBJECT(bus), 613 &error_abort); 614 sysbus_realize_and_unref(SYS_BUS_DEVICE(dev), &error_fatal); 615 sysbus_mmio_map(SYS_BUS_DEVICE(dev), 0, base); 616 for (i = 0; i < NUM_SMMU_IRQS; i++) { 617 sysbus_connect_irq(SYS_BUS_DEVICE(dev), i, 618 qdev_get_gpio_in(sms->gic, irq + i)); 619 } 620 } 621 622 static void create_pcie(SBSAMachineState *sms) 623 { 624 hwaddr base_ecam = sbsa_ref_memmap[SBSA_PCIE_ECAM].base; 625 hwaddr size_ecam = sbsa_ref_memmap[SBSA_PCIE_ECAM].size; 626 hwaddr base_mmio = sbsa_ref_memmap[SBSA_PCIE_MMIO].base; 627 hwaddr size_mmio = sbsa_ref_memmap[SBSA_PCIE_MMIO].size; 628 hwaddr base_mmio_high = sbsa_ref_memmap[SBSA_PCIE_MMIO_HIGH].base; 629 hwaddr size_mmio_high = sbsa_ref_memmap[SBSA_PCIE_MMIO_HIGH].size; 630 hwaddr base_pio = sbsa_ref_memmap[SBSA_PCIE_PIO].base; 631 int irq = sbsa_ref_irqmap[SBSA_PCIE]; 632 MachineClass *mc = MACHINE_GET_CLASS(sms); 633 MemoryRegion *mmio_alias, *mmio_alias_high, *mmio_reg; 634 MemoryRegion *ecam_alias, *ecam_reg; 635 DeviceState *dev; 636 PCIHostState *pci; 637 int i; 638 639 dev = qdev_new(TYPE_GPEX_HOST); 640 sysbus_realize_and_unref(SYS_BUS_DEVICE(dev), &error_fatal); 641 642 /* Map ECAM space */ 643 ecam_alias = g_new0(MemoryRegion, 1); 644 ecam_reg = sysbus_mmio_get_region(SYS_BUS_DEVICE(dev), 0); 645 memory_region_init_alias(ecam_alias, OBJECT(dev), "pcie-ecam", 646 ecam_reg, 0, size_ecam); 647 memory_region_add_subregion(get_system_memory(), base_ecam, ecam_alias); 648 649 /* Map the MMIO space */ 650 mmio_alias = g_new0(MemoryRegion, 1); 651 mmio_reg = sysbus_mmio_get_region(SYS_BUS_DEVICE(dev), 1); 652 memory_region_init_alias(mmio_alias, OBJECT(dev), "pcie-mmio", 653 mmio_reg, base_mmio, size_mmio); 654 memory_region_add_subregion(get_system_memory(), base_mmio, mmio_alias); 655 656 /* Map the MMIO_HIGH space */ 657 mmio_alias_high = g_new0(MemoryRegion, 1); 658 memory_region_init_alias(mmio_alias_high, OBJECT(dev), "pcie-mmio-high", 659 mmio_reg, base_mmio_high, size_mmio_high); 660 memory_region_add_subregion(get_system_memory(), base_mmio_high, 661 mmio_alias_high); 662 663 /* Map IO port space */ 664 sysbus_mmio_map(SYS_BUS_DEVICE(dev), 2, base_pio); 665 666 for (i = 0; i < GPEX_NUM_IRQS; i++) { 667 sysbus_connect_irq(SYS_BUS_DEVICE(dev), i, 668 qdev_get_gpio_in(sms->gic, irq + i)); 669 gpex_set_irq_num(GPEX_HOST(dev), i, irq + i); 670 } 671 672 pci = PCI_HOST_BRIDGE(dev); 673 if (pci->bus) { 674 for (i = 0; i < nb_nics; i++) { 675 pci_nic_init_nofail(&nd_table[i], pci->bus, mc->default_nic, NULL); 676 } 677 } 678 679 pci_create_simple(pci->bus, -1, "bochs-display"); 680 681 create_smmu(sms, pci->bus); 682 } 683 684 static void *sbsa_ref_dtb(const struct arm_boot_info *binfo, int *fdt_size) 685 { 686 const SBSAMachineState *board = container_of(binfo, SBSAMachineState, 687 bootinfo); 688 689 *fdt_size = board->fdt_size; 690 return board->fdt; 691 } 692 693 static void create_secure_ec(MemoryRegion *mem) 694 { 695 hwaddr base = sbsa_ref_memmap[SBSA_SECURE_EC].base; 696 DeviceState *dev = qdev_new("sbsa-ec"); 697 SysBusDevice *s = SYS_BUS_DEVICE(dev); 698 699 memory_region_add_subregion(mem, base, 700 sysbus_mmio_get_region(s, 0)); 701 } 702 703 static void sbsa_ref_init(MachineState *machine) 704 { 705 unsigned int smp_cpus = machine->smp.cpus; 706 unsigned int max_cpus = machine->smp.max_cpus; 707 SBSAMachineState *sms = SBSA_MACHINE(machine); 708 MachineClass *mc = MACHINE_GET_CLASS(machine); 709 MemoryRegion *sysmem = get_system_memory(); 710 MemoryRegion *secure_sysmem = g_new(MemoryRegion, 1); 711 bool firmware_loaded; 712 const CPUArchIdList *possible_cpus; 713 int n, sbsa_max_cpus; 714 715 if (kvm_enabled()) { 716 error_report("sbsa-ref: KVM is not supported for this machine"); 717 exit(1); 718 } 719 720 /* 721 * The Secure view of the world is the same as the NonSecure, 722 * but with a few extra devices. Create it as a container region 723 * containing the system memory at low priority; any secure-only 724 * devices go in at higher priority and take precedence. 725 */ 726 memory_region_init(secure_sysmem, OBJECT(machine), "secure-memory", 727 UINT64_MAX); 728 memory_region_add_subregion_overlap(secure_sysmem, 0, sysmem, -1); 729 730 firmware_loaded = sbsa_firmware_init(sms, sysmem, secure_sysmem); 731 732 /* 733 * This machine has EL3 enabled, external firmware should supply PSCI 734 * implementation, so the QEMU's internal PSCI is disabled. 735 */ 736 sms->psci_conduit = QEMU_PSCI_CONDUIT_DISABLED; 737 738 sbsa_max_cpus = sbsa_ref_memmap[SBSA_GIC_REDIST].size / GICV3_REDIST_SIZE; 739 740 if (max_cpus > sbsa_max_cpus) { 741 error_report("Number of SMP CPUs requested (%d) exceeds max CPUs " 742 "supported by machine 'sbsa-ref' (%d)", 743 max_cpus, sbsa_max_cpus); 744 exit(1); 745 } 746 747 sms->smp_cpus = smp_cpus; 748 749 if (machine->ram_size > sbsa_ref_memmap[SBSA_MEM].size) { 750 error_report("sbsa-ref: cannot model more than %dGB RAM", RAMLIMIT_GB); 751 exit(1); 752 } 753 754 possible_cpus = mc->possible_cpu_arch_ids(machine); 755 for (n = 0; n < possible_cpus->len; n++) { 756 Object *cpuobj; 757 CPUState *cs; 758 759 if (n >= smp_cpus) { 760 break; 761 } 762 763 cpuobj = object_new(possible_cpus->cpus[n].type); 764 object_property_set_int(cpuobj, "mp-affinity", 765 possible_cpus->cpus[n].arch_id, NULL); 766 767 cs = CPU(cpuobj); 768 cs->cpu_index = n; 769 770 numa_cpu_pre_plug(&possible_cpus->cpus[cs->cpu_index], DEVICE(cpuobj), 771 &error_fatal); 772 773 if (object_property_find(cpuobj, "reset-cbar")) { 774 object_property_set_int(cpuobj, "reset-cbar", 775 sbsa_ref_memmap[SBSA_CPUPERIPHS].base, 776 &error_abort); 777 } 778 779 object_property_set_link(cpuobj, "memory", OBJECT(sysmem), 780 &error_abort); 781 782 object_property_set_link(cpuobj, "secure-memory", 783 OBJECT(secure_sysmem), &error_abort); 784 785 qdev_realize(DEVICE(cpuobj), NULL, &error_fatal); 786 object_unref(cpuobj); 787 } 788 789 memory_region_add_subregion(sysmem, sbsa_ref_memmap[SBSA_MEM].base, 790 machine->ram); 791 792 create_fdt(sms); 793 794 create_secure_ram(sms, secure_sysmem); 795 796 create_gic(sms, sysmem); 797 798 create_uart(sms, SBSA_UART, sysmem, serial_hd(0)); 799 create_uart(sms, SBSA_SECURE_UART, secure_sysmem, serial_hd(1)); 800 /* Second secure UART for RAS and MM from EL0 */ 801 create_uart(sms, SBSA_SECURE_UART_MM, secure_sysmem, serial_hd(2)); 802 803 create_rtc(sms); 804 805 create_wdt(sms); 806 807 create_gpio(sms); 808 809 create_ahci(sms); 810 811 create_xhci(sms); 812 813 create_pcie(sms); 814 815 create_secure_ec(secure_sysmem); 816 817 sms->bootinfo.ram_size = machine->ram_size; 818 sms->bootinfo.board_id = -1; 819 sms->bootinfo.loader_start = sbsa_ref_memmap[SBSA_MEM].base; 820 sms->bootinfo.get_dtb = sbsa_ref_dtb; 821 sms->bootinfo.firmware_loaded = firmware_loaded; 822 arm_load_kernel(ARM_CPU(first_cpu), machine, &sms->bootinfo); 823 } 824 825 static const CPUArchIdList *sbsa_ref_possible_cpu_arch_ids(MachineState *ms) 826 { 827 unsigned int max_cpus = ms->smp.max_cpus; 828 SBSAMachineState *sms = SBSA_MACHINE(ms); 829 int n; 830 831 if (ms->possible_cpus) { 832 assert(ms->possible_cpus->len == max_cpus); 833 return ms->possible_cpus; 834 } 835 836 ms->possible_cpus = g_malloc0(sizeof(CPUArchIdList) + 837 sizeof(CPUArchId) * max_cpus); 838 ms->possible_cpus->len = max_cpus; 839 for (n = 0; n < ms->possible_cpus->len; n++) { 840 ms->possible_cpus->cpus[n].type = ms->cpu_type; 841 ms->possible_cpus->cpus[n].arch_id = 842 sbsa_ref_cpu_mp_affinity(sms, n); 843 ms->possible_cpus->cpus[n].props.has_thread_id = true; 844 ms->possible_cpus->cpus[n].props.thread_id = n; 845 } 846 return ms->possible_cpus; 847 } 848 849 static CpuInstanceProperties 850 sbsa_ref_cpu_index_to_props(MachineState *ms, unsigned cpu_index) 851 { 852 MachineClass *mc = MACHINE_GET_CLASS(ms); 853 const CPUArchIdList *possible_cpus = mc->possible_cpu_arch_ids(ms); 854 855 assert(cpu_index < possible_cpus->len); 856 return possible_cpus->cpus[cpu_index].props; 857 } 858 859 static int64_t 860 sbsa_ref_get_default_cpu_node_id(const MachineState *ms, int idx) 861 { 862 return idx % ms->numa_state->num_nodes; 863 } 864 865 static void sbsa_ref_instance_init(Object *obj) 866 { 867 SBSAMachineState *sms = SBSA_MACHINE(obj); 868 869 sbsa_flash_create(sms); 870 } 871 872 static void sbsa_ref_class_init(ObjectClass *oc, void *data) 873 { 874 MachineClass *mc = MACHINE_CLASS(oc); 875 static const char * const valid_cpu_types[] = { 876 ARM_CPU_TYPE_NAME("cortex-a57"), 877 ARM_CPU_TYPE_NAME("cortex-a72"), 878 ARM_CPU_TYPE_NAME("neoverse-n1"), 879 ARM_CPU_TYPE_NAME("neoverse-v1"), 880 ARM_CPU_TYPE_NAME("neoverse-n2"), 881 ARM_CPU_TYPE_NAME("max"), 882 NULL, 883 }; 884 885 mc->init = sbsa_ref_init; 886 mc->desc = "QEMU 'SBSA Reference' ARM Virtual Machine"; 887 mc->default_cpu_type = ARM_CPU_TYPE_NAME("neoverse-n1"); 888 mc->valid_cpu_types = valid_cpu_types; 889 mc->max_cpus = 512; 890 mc->pci_allow_0_address = true; 891 mc->minimum_page_bits = 12; 892 mc->block_default_type = IF_IDE; 893 mc->no_cdrom = 1; 894 mc->default_nic = "e1000e"; 895 mc->default_ram_size = 1 * GiB; 896 mc->default_ram_id = "sbsa-ref.ram"; 897 mc->default_cpus = 4; 898 mc->possible_cpu_arch_ids = sbsa_ref_possible_cpu_arch_ids; 899 mc->cpu_index_to_instance_props = sbsa_ref_cpu_index_to_props; 900 mc->get_default_cpu_node_id = sbsa_ref_get_default_cpu_node_id; 901 /* platform instead of architectural choice */ 902 mc->cpu_cluster_has_numa_boundary = true; 903 } 904 905 static const TypeInfo sbsa_ref_info = { 906 .name = TYPE_SBSA_MACHINE, 907 .parent = TYPE_MACHINE, 908 .instance_init = sbsa_ref_instance_init, 909 .class_init = sbsa_ref_class_init, 910 .instance_size = sizeof(SBSAMachineState), 911 }; 912 913 static void sbsa_ref_machine_init(void) 914 { 915 type_register_static(&sbsa_ref_info); 916 } 917 918 type_init(sbsa_ref_machine_init); 919