1 /* 2 * ARM SBSA Reference Platform emulation 3 * 4 * Copyright (c) 2018 Linaro Limited 5 * Written by Hongbo Zhang <hongbo.zhang@linaro.org> 6 * 7 * This program is free software; you can redistribute it and/or modify it 8 * under the terms and conditions of the GNU General Public License, 9 * version 2 or later, as published by the Free Software Foundation. 10 * 11 * This program is distributed in the hope it will be useful, but WITHOUT 12 * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or 13 * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for 14 * more details. 15 * 16 * You should have received a copy of the GNU General Public License along with 17 * this program. If not, see <http://www.gnu.org/licenses/>. 18 */ 19 20 #include "qemu/osdep.h" 21 #include "qemu-common.h" 22 #include "qemu/datadir.h" 23 #include "qapi/error.h" 24 #include "qemu/error-report.h" 25 #include "qemu/units.h" 26 #include "sysemu/device_tree.h" 27 #include "sysemu/numa.h" 28 #include "sysemu/runstate.h" 29 #include "sysemu/sysemu.h" 30 #include "exec/hwaddr.h" 31 #include "kvm_arm.h" 32 #include "hw/arm/boot.h" 33 #include "hw/block/flash.h" 34 #include "hw/boards.h" 35 #include "hw/ide/internal.h" 36 #include "hw/ide/ahci_internal.h" 37 #include "hw/intc/arm_gicv3_common.h" 38 #include "hw/loader.h" 39 #include "hw/pci-host/gpex.h" 40 #include "hw/qdev-properties.h" 41 #include "hw/usb.h" 42 #include "hw/char/pl011.h" 43 #include "hw/watchdog/sbsa_gwdt.h" 44 #include "net/net.h" 45 #include "qom/object.h" 46 47 #define RAMLIMIT_GB 8192 48 #define RAMLIMIT_BYTES (RAMLIMIT_GB * GiB) 49 50 #define NUM_IRQS 256 51 #define NUM_SMMU_IRQS 4 52 #define NUM_SATA_PORTS 6 53 54 #define VIRTUAL_PMU_IRQ 7 55 #define ARCH_GIC_MAINT_IRQ 9 56 #define ARCH_TIMER_VIRT_IRQ 11 57 #define ARCH_TIMER_S_EL1_IRQ 13 58 #define ARCH_TIMER_NS_EL1_IRQ 14 59 #define ARCH_TIMER_NS_EL2_IRQ 10 60 61 enum { 62 SBSA_FLASH, 63 SBSA_MEM, 64 SBSA_CPUPERIPHS, 65 SBSA_GIC_DIST, 66 SBSA_GIC_REDIST, 67 SBSA_SECURE_EC, 68 SBSA_GWDT_WS0, 69 SBSA_GWDT_REFRESH, 70 SBSA_GWDT_CONTROL, 71 SBSA_SMMU, 72 SBSA_UART, 73 SBSA_RTC, 74 SBSA_PCIE, 75 SBSA_PCIE_MMIO, 76 SBSA_PCIE_MMIO_HIGH, 77 SBSA_PCIE_PIO, 78 SBSA_PCIE_ECAM, 79 SBSA_GPIO, 80 SBSA_SECURE_UART, 81 SBSA_SECURE_UART_MM, 82 SBSA_SECURE_MEM, 83 SBSA_AHCI, 84 SBSA_EHCI, 85 }; 86 87 struct SBSAMachineState { 88 MachineState parent; 89 struct arm_boot_info bootinfo; 90 int smp_cpus; 91 void *fdt; 92 int fdt_size; 93 int psci_conduit; 94 DeviceState *gic; 95 PFlashCFI01 *flash[2]; 96 }; 97 98 #define TYPE_SBSA_MACHINE MACHINE_TYPE_NAME("sbsa-ref") 99 OBJECT_DECLARE_SIMPLE_TYPE(SBSAMachineState, SBSA_MACHINE) 100 101 static const MemMapEntry sbsa_ref_memmap[] = { 102 /* 512M boot ROM */ 103 [SBSA_FLASH] = { 0, 0x20000000 }, 104 /* 512M secure memory */ 105 [SBSA_SECURE_MEM] = { 0x20000000, 0x20000000 }, 106 /* Space reserved for CPU peripheral devices */ 107 [SBSA_CPUPERIPHS] = { 0x40000000, 0x00040000 }, 108 [SBSA_GIC_DIST] = { 0x40060000, 0x00010000 }, 109 [SBSA_GIC_REDIST] = { 0x40080000, 0x04000000 }, 110 [SBSA_SECURE_EC] = { 0x50000000, 0x00001000 }, 111 [SBSA_GWDT_REFRESH] = { 0x50010000, 0x00001000 }, 112 [SBSA_GWDT_CONTROL] = { 0x50011000, 0x00001000 }, 113 [SBSA_UART] = { 0x60000000, 0x00001000 }, 114 [SBSA_RTC] = { 0x60010000, 0x00001000 }, 115 [SBSA_GPIO] = { 0x60020000, 0x00001000 }, 116 [SBSA_SECURE_UART] = { 0x60030000, 0x00001000 }, 117 [SBSA_SECURE_UART_MM] = { 0x60040000, 0x00001000 }, 118 [SBSA_SMMU] = { 0x60050000, 0x00020000 }, 119 /* Space here reserved for more SMMUs */ 120 [SBSA_AHCI] = { 0x60100000, 0x00010000 }, 121 [SBSA_EHCI] = { 0x60110000, 0x00010000 }, 122 /* Space here reserved for other devices */ 123 [SBSA_PCIE_PIO] = { 0x7fff0000, 0x00010000 }, 124 /* 32-bit address PCIE MMIO space */ 125 [SBSA_PCIE_MMIO] = { 0x80000000, 0x70000000 }, 126 /* 256M PCIE ECAM space */ 127 [SBSA_PCIE_ECAM] = { 0xf0000000, 0x10000000 }, 128 /* ~1TB PCIE MMIO space (4GB to 1024GB boundary) */ 129 [SBSA_PCIE_MMIO_HIGH] = { 0x100000000ULL, 0xFF00000000ULL }, 130 [SBSA_MEM] = { 0x10000000000ULL, RAMLIMIT_BYTES }, 131 }; 132 133 static const int sbsa_ref_irqmap[] = { 134 [SBSA_UART] = 1, 135 [SBSA_RTC] = 2, 136 [SBSA_PCIE] = 3, /* ... to 6 */ 137 [SBSA_GPIO] = 7, 138 [SBSA_SECURE_UART] = 8, 139 [SBSA_SECURE_UART_MM] = 9, 140 [SBSA_AHCI] = 10, 141 [SBSA_EHCI] = 11, 142 [SBSA_SMMU] = 12, /* ... to 15 */ 143 [SBSA_GWDT_WS0] = 16, 144 }; 145 146 static const char * const valid_cpus[] = { 147 ARM_CPU_TYPE_NAME("cortex-a57"), 148 ARM_CPU_TYPE_NAME("cortex-a72"), 149 ARM_CPU_TYPE_NAME("max"), 150 }; 151 152 static bool cpu_type_valid(const char *cpu) 153 { 154 int i; 155 156 for (i = 0; i < ARRAY_SIZE(valid_cpus); i++) { 157 if (strcmp(cpu, valid_cpus[i]) == 0) { 158 return true; 159 } 160 } 161 return false; 162 } 163 164 static uint64_t sbsa_ref_cpu_mp_affinity(SBSAMachineState *sms, int idx) 165 { 166 uint8_t clustersz = ARM_DEFAULT_CPUS_PER_CLUSTER; 167 return arm_cpu_mp_affinity(idx, clustersz); 168 } 169 170 /* 171 * Firmware on this machine only uses ACPI table to load OS, these limited 172 * device tree nodes are just to let firmware know the info which varies from 173 * command line parameters, so it is not necessary to be fully compatible 174 * with the kernel CPU and NUMA binding rules. 175 */ 176 static void create_fdt(SBSAMachineState *sms) 177 { 178 void *fdt = create_device_tree(&sms->fdt_size); 179 const MachineState *ms = MACHINE(sms); 180 int nb_numa_nodes = ms->numa_state->num_nodes; 181 int cpu; 182 183 if (!fdt) { 184 error_report("create_device_tree() failed"); 185 exit(1); 186 } 187 188 sms->fdt = fdt; 189 190 qemu_fdt_setprop_string(fdt, "/", "compatible", "linux,sbsa-ref"); 191 qemu_fdt_setprop_cell(fdt, "/", "#address-cells", 0x2); 192 qemu_fdt_setprop_cell(fdt, "/", "#size-cells", 0x2); 193 194 if (ms->numa_state->have_numa_distance) { 195 int size = nb_numa_nodes * nb_numa_nodes * 3 * sizeof(uint32_t); 196 uint32_t *matrix = g_malloc0(size); 197 int idx, i, j; 198 199 for (i = 0; i < nb_numa_nodes; i++) { 200 for (j = 0; j < nb_numa_nodes; j++) { 201 idx = (i * nb_numa_nodes + j) * 3; 202 matrix[idx + 0] = cpu_to_be32(i); 203 matrix[idx + 1] = cpu_to_be32(j); 204 matrix[idx + 2] = 205 cpu_to_be32(ms->numa_state->nodes[i].distance[j]); 206 } 207 } 208 209 qemu_fdt_add_subnode(fdt, "/distance-map"); 210 qemu_fdt_setprop(fdt, "/distance-map", "distance-matrix", 211 matrix, size); 212 g_free(matrix); 213 } 214 215 /* 216 * From Documentation/devicetree/bindings/arm/cpus.yaml 217 * On ARM v8 64-bit systems this property is required 218 * and matches the MPIDR_EL1 register affinity bits. 219 * 220 * * If cpus node's #address-cells property is set to 2 221 * 222 * The first reg cell bits [7:0] must be set to 223 * bits [39:32] of MPIDR_EL1. 224 * 225 * The second reg cell bits [23:0] must be set to 226 * bits [23:0] of MPIDR_EL1. 227 */ 228 qemu_fdt_add_subnode(sms->fdt, "/cpus"); 229 qemu_fdt_setprop_cell(sms->fdt, "/cpus", "#address-cells", 2); 230 qemu_fdt_setprop_cell(sms->fdt, "/cpus", "#size-cells", 0x0); 231 232 for (cpu = sms->smp_cpus - 1; cpu >= 0; cpu--) { 233 char *nodename = g_strdup_printf("/cpus/cpu@%d", cpu); 234 ARMCPU *armcpu = ARM_CPU(qemu_get_cpu(cpu)); 235 CPUState *cs = CPU(armcpu); 236 uint64_t mpidr = sbsa_ref_cpu_mp_affinity(sms, cpu); 237 238 qemu_fdt_add_subnode(sms->fdt, nodename); 239 qemu_fdt_setprop_u64(sms->fdt, nodename, "reg", mpidr); 240 241 if (ms->possible_cpus->cpus[cs->cpu_index].props.has_node_id) { 242 qemu_fdt_setprop_cell(sms->fdt, nodename, "numa-node-id", 243 ms->possible_cpus->cpus[cs->cpu_index].props.node_id); 244 } 245 246 g_free(nodename); 247 } 248 } 249 250 #define SBSA_FLASH_SECTOR_SIZE (256 * KiB) 251 252 static PFlashCFI01 *sbsa_flash_create1(SBSAMachineState *sms, 253 const char *name, 254 const char *alias_prop_name) 255 { 256 /* 257 * Create a single flash device. We use the same parameters as 258 * the flash devices on the Versatile Express board. 259 */ 260 DeviceState *dev = qdev_new(TYPE_PFLASH_CFI01); 261 262 qdev_prop_set_uint64(dev, "sector-length", SBSA_FLASH_SECTOR_SIZE); 263 qdev_prop_set_uint8(dev, "width", 4); 264 qdev_prop_set_uint8(dev, "device-width", 2); 265 qdev_prop_set_bit(dev, "big-endian", false); 266 qdev_prop_set_uint16(dev, "id0", 0x89); 267 qdev_prop_set_uint16(dev, "id1", 0x18); 268 qdev_prop_set_uint16(dev, "id2", 0x00); 269 qdev_prop_set_uint16(dev, "id3", 0x00); 270 qdev_prop_set_string(dev, "name", name); 271 object_property_add_child(OBJECT(sms), name, OBJECT(dev)); 272 object_property_add_alias(OBJECT(sms), alias_prop_name, 273 OBJECT(dev), "drive"); 274 return PFLASH_CFI01(dev); 275 } 276 277 static void sbsa_flash_create(SBSAMachineState *sms) 278 { 279 sms->flash[0] = sbsa_flash_create1(sms, "sbsa.flash0", "pflash0"); 280 sms->flash[1] = sbsa_flash_create1(sms, "sbsa.flash1", "pflash1"); 281 } 282 283 static void sbsa_flash_map1(PFlashCFI01 *flash, 284 hwaddr base, hwaddr size, 285 MemoryRegion *sysmem) 286 { 287 DeviceState *dev = DEVICE(flash); 288 289 assert(QEMU_IS_ALIGNED(size, SBSA_FLASH_SECTOR_SIZE)); 290 assert(size / SBSA_FLASH_SECTOR_SIZE <= UINT32_MAX); 291 qdev_prop_set_uint32(dev, "num-blocks", size / SBSA_FLASH_SECTOR_SIZE); 292 sysbus_realize_and_unref(SYS_BUS_DEVICE(dev), &error_fatal); 293 294 memory_region_add_subregion(sysmem, base, 295 sysbus_mmio_get_region(SYS_BUS_DEVICE(dev), 296 0)); 297 } 298 299 static void sbsa_flash_map(SBSAMachineState *sms, 300 MemoryRegion *sysmem, 301 MemoryRegion *secure_sysmem) 302 { 303 /* 304 * Map two flash devices to fill the SBSA_FLASH space in the memmap. 305 * sysmem is the system memory space. secure_sysmem is the secure view 306 * of the system, and the first flash device should be made visible only 307 * there. The second flash device is visible to both secure and nonsecure. 308 */ 309 hwaddr flashsize = sbsa_ref_memmap[SBSA_FLASH].size / 2; 310 hwaddr flashbase = sbsa_ref_memmap[SBSA_FLASH].base; 311 312 sbsa_flash_map1(sms->flash[0], flashbase, flashsize, 313 secure_sysmem); 314 sbsa_flash_map1(sms->flash[1], flashbase + flashsize, flashsize, 315 sysmem); 316 } 317 318 static bool sbsa_firmware_init(SBSAMachineState *sms, 319 MemoryRegion *sysmem, 320 MemoryRegion *secure_sysmem) 321 { 322 const char *bios_name; 323 int i; 324 BlockBackend *pflash_blk0; 325 326 /* Map legacy -drive if=pflash to machine properties */ 327 for (i = 0; i < ARRAY_SIZE(sms->flash); i++) { 328 pflash_cfi01_legacy_drive(sms->flash[i], 329 drive_get(IF_PFLASH, 0, i)); 330 } 331 332 sbsa_flash_map(sms, sysmem, secure_sysmem); 333 334 pflash_blk0 = pflash_cfi01_get_blk(sms->flash[0]); 335 336 bios_name = MACHINE(sms)->firmware; 337 if (bios_name) { 338 char *fname; 339 MemoryRegion *mr; 340 int image_size; 341 342 if (pflash_blk0) { 343 error_report("The contents of the first flash device may be " 344 "specified with -bios or with -drive if=pflash... " 345 "but you cannot use both options at once"); 346 exit(1); 347 } 348 349 /* Fall back to -bios */ 350 351 fname = qemu_find_file(QEMU_FILE_TYPE_BIOS, bios_name); 352 if (!fname) { 353 error_report("Could not find ROM image '%s'", bios_name); 354 exit(1); 355 } 356 mr = sysbus_mmio_get_region(SYS_BUS_DEVICE(sms->flash[0]), 0); 357 image_size = load_image_mr(fname, mr); 358 g_free(fname); 359 if (image_size < 0) { 360 error_report("Could not load ROM image '%s'", bios_name); 361 exit(1); 362 } 363 } 364 365 return pflash_blk0 || bios_name; 366 } 367 368 static void create_secure_ram(SBSAMachineState *sms, 369 MemoryRegion *secure_sysmem) 370 { 371 MemoryRegion *secram = g_new(MemoryRegion, 1); 372 hwaddr base = sbsa_ref_memmap[SBSA_SECURE_MEM].base; 373 hwaddr size = sbsa_ref_memmap[SBSA_SECURE_MEM].size; 374 375 memory_region_init_ram(secram, NULL, "sbsa-ref.secure-ram", size, 376 &error_fatal); 377 memory_region_add_subregion(secure_sysmem, base, secram); 378 } 379 380 static void create_gic(SBSAMachineState *sms) 381 { 382 unsigned int smp_cpus = MACHINE(sms)->smp.cpus; 383 SysBusDevice *gicbusdev; 384 const char *gictype; 385 uint32_t redist0_capacity, redist0_count; 386 int i; 387 388 gictype = gicv3_class_name(); 389 390 sms->gic = qdev_new(gictype); 391 qdev_prop_set_uint32(sms->gic, "revision", 3); 392 qdev_prop_set_uint32(sms->gic, "num-cpu", smp_cpus); 393 /* 394 * Note that the num-irq property counts both internal and external 395 * interrupts; there are always 32 of the former (mandated by GIC spec). 396 */ 397 qdev_prop_set_uint32(sms->gic, "num-irq", NUM_IRQS + 32); 398 qdev_prop_set_bit(sms->gic, "has-security-extensions", true); 399 400 redist0_capacity = 401 sbsa_ref_memmap[SBSA_GIC_REDIST].size / GICV3_REDIST_SIZE; 402 redist0_count = MIN(smp_cpus, redist0_capacity); 403 404 qdev_prop_set_uint32(sms->gic, "len-redist-region-count", 1); 405 qdev_prop_set_uint32(sms->gic, "redist-region-count[0]", redist0_count); 406 407 gicbusdev = SYS_BUS_DEVICE(sms->gic); 408 sysbus_realize_and_unref(gicbusdev, &error_fatal); 409 sysbus_mmio_map(gicbusdev, 0, sbsa_ref_memmap[SBSA_GIC_DIST].base); 410 sysbus_mmio_map(gicbusdev, 1, sbsa_ref_memmap[SBSA_GIC_REDIST].base); 411 412 /* 413 * Wire the outputs from each CPU's generic timer and the GICv3 414 * maintenance interrupt signal to the appropriate GIC PPI inputs, 415 * and the GIC's IRQ/FIQ/VIRQ/VFIQ interrupt outputs to the CPU's inputs. 416 */ 417 for (i = 0; i < smp_cpus; i++) { 418 DeviceState *cpudev = DEVICE(qemu_get_cpu(i)); 419 int ppibase = NUM_IRQS + i * GIC_INTERNAL + GIC_NR_SGIS; 420 int irq; 421 /* 422 * Mapping from the output timer irq lines from the CPU to the 423 * GIC PPI inputs used for this board. 424 */ 425 const int timer_irq[] = { 426 [GTIMER_PHYS] = ARCH_TIMER_NS_EL1_IRQ, 427 [GTIMER_VIRT] = ARCH_TIMER_VIRT_IRQ, 428 [GTIMER_HYP] = ARCH_TIMER_NS_EL2_IRQ, 429 [GTIMER_SEC] = ARCH_TIMER_S_EL1_IRQ, 430 }; 431 432 for (irq = 0; irq < ARRAY_SIZE(timer_irq); irq++) { 433 qdev_connect_gpio_out(cpudev, irq, 434 qdev_get_gpio_in(sms->gic, 435 ppibase + timer_irq[irq])); 436 } 437 438 qdev_connect_gpio_out_named(cpudev, "gicv3-maintenance-interrupt", 0, 439 qdev_get_gpio_in(sms->gic, ppibase 440 + ARCH_GIC_MAINT_IRQ)); 441 qdev_connect_gpio_out_named(cpudev, "pmu-interrupt", 0, 442 qdev_get_gpio_in(sms->gic, ppibase 443 + VIRTUAL_PMU_IRQ)); 444 445 sysbus_connect_irq(gicbusdev, i, qdev_get_gpio_in(cpudev, ARM_CPU_IRQ)); 446 sysbus_connect_irq(gicbusdev, i + smp_cpus, 447 qdev_get_gpio_in(cpudev, ARM_CPU_FIQ)); 448 sysbus_connect_irq(gicbusdev, i + 2 * smp_cpus, 449 qdev_get_gpio_in(cpudev, ARM_CPU_VIRQ)); 450 sysbus_connect_irq(gicbusdev, i + 3 * smp_cpus, 451 qdev_get_gpio_in(cpudev, ARM_CPU_VFIQ)); 452 } 453 } 454 455 static void create_uart(const SBSAMachineState *sms, int uart, 456 MemoryRegion *mem, Chardev *chr) 457 { 458 hwaddr base = sbsa_ref_memmap[uart].base; 459 int irq = sbsa_ref_irqmap[uart]; 460 DeviceState *dev = qdev_new(TYPE_PL011); 461 SysBusDevice *s = SYS_BUS_DEVICE(dev); 462 463 qdev_prop_set_chr(dev, "chardev", chr); 464 sysbus_realize_and_unref(SYS_BUS_DEVICE(dev), &error_fatal); 465 memory_region_add_subregion(mem, base, 466 sysbus_mmio_get_region(s, 0)); 467 sysbus_connect_irq(s, 0, qdev_get_gpio_in(sms->gic, irq)); 468 } 469 470 static void create_rtc(const SBSAMachineState *sms) 471 { 472 hwaddr base = sbsa_ref_memmap[SBSA_RTC].base; 473 int irq = sbsa_ref_irqmap[SBSA_RTC]; 474 475 sysbus_create_simple("pl031", base, qdev_get_gpio_in(sms->gic, irq)); 476 } 477 478 static void create_wdt(const SBSAMachineState *sms) 479 { 480 hwaddr rbase = sbsa_ref_memmap[SBSA_GWDT_REFRESH].base; 481 hwaddr cbase = sbsa_ref_memmap[SBSA_GWDT_CONTROL].base; 482 DeviceState *dev = qdev_new(TYPE_WDT_SBSA); 483 SysBusDevice *s = SYS_BUS_DEVICE(dev); 484 int irq = sbsa_ref_irqmap[SBSA_GWDT_WS0]; 485 486 sysbus_realize_and_unref(s, &error_fatal); 487 sysbus_mmio_map(s, 0, rbase); 488 sysbus_mmio_map(s, 1, cbase); 489 sysbus_connect_irq(s, 0, qdev_get_gpio_in(sms->gic, irq)); 490 } 491 492 static DeviceState *gpio_key_dev; 493 static void sbsa_ref_powerdown_req(Notifier *n, void *opaque) 494 { 495 /* use gpio Pin 3 for power button event */ 496 qemu_set_irq(qdev_get_gpio_in(gpio_key_dev, 0), 1); 497 } 498 499 static Notifier sbsa_ref_powerdown_notifier = { 500 .notify = sbsa_ref_powerdown_req 501 }; 502 503 static void create_gpio(const SBSAMachineState *sms) 504 { 505 DeviceState *pl061_dev; 506 hwaddr base = sbsa_ref_memmap[SBSA_GPIO].base; 507 int irq = sbsa_ref_irqmap[SBSA_GPIO]; 508 509 pl061_dev = sysbus_create_simple("pl061", base, 510 qdev_get_gpio_in(sms->gic, irq)); 511 512 gpio_key_dev = sysbus_create_simple("gpio-key", -1, 513 qdev_get_gpio_in(pl061_dev, 3)); 514 515 /* connect powerdown request */ 516 qemu_register_powerdown_notifier(&sbsa_ref_powerdown_notifier); 517 } 518 519 static void create_ahci(const SBSAMachineState *sms) 520 { 521 hwaddr base = sbsa_ref_memmap[SBSA_AHCI].base; 522 int irq = sbsa_ref_irqmap[SBSA_AHCI]; 523 DeviceState *dev; 524 DriveInfo *hd[NUM_SATA_PORTS]; 525 SysbusAHCIState *sysahci; 526 AHCIState *ahci; 527 int i; 528 529 dev = qdev_new("sysbus-ahci"); 530 qdev_prop_set_uint32(dev, "num-ports", NUM_SATA_PORTS); 531 sysbus_realize_and_unref(SYS_BUS_DEVICE(dev), &error_fatal); 532 sysbus_mmio_map(SYS_BUS_DEVICE(dev), 0, base); 533 sysbus_connect_irq(SYS_BUS_DEVICE(dev), 0, qdev_get_gpio_in(sms->gic, irq)); 534 535 sysahci = SYSBUS_AHCI(dev); 536 ahci = &sysahci->ahci; 537 ide_drive_get(hd, ARRAY_SIZE(hd)); 538 for (i = 0; i < ahci->ports; i++) { 539 if (hd[i] == NULL) { 540 continue; 541 } 542 ide_create_drive(&ahci->dev[i].port, 0, hd[i]); 543 } 544 } 545 546 static void create_ehci(const SBSAMachineState *sms) 547 { 548 hwaddr base = sbsa_ref_memmap[SBSA_EHCI].base; 549 int irq = sbsa_ref_irqmap[SBSA_EHCI]; 550 551 sysbus_create_simple("platform-ehci-usb", base, 552 qdev_get_gpio_in(sms->gic, irq)); 553 } 554 555 static void create_smmu(const SBSAMachineState *sms, PCIBus *bus) 556 { 557 hwaddr base = sbsa_ref_memmap[SBSA_SMMU].base; 558 int irq = sbsa_ref_irqmap[SBSA_SMMU]; 559 DeviceState *dev; 560 int i; 561 562 dev = qdev_new("arm-smmuv3"); 563 564 object_property_set_link(OBJECT(dev), "primary-bus", OBJECT(bus), 565 &error_abort); 566 sysbus_realize_and_unref(SYS_BUS_DEVICE(dev), &error_fatal); 567 sysbus_mmio_map(SYS_BUS_DEVICE(dev), 0, base); 568 for (i = 0; i < NUM_SMMU_IRQS; i++) { 569 sysbus_connect_irq(SYS_BUS_DEVICE(dev), i, 570 qdev_get_gpio_in(sms->gic, irq + i)); 571 } 572 } 573 574 static void create_pcie(SBSAMachineState *sms) 575 { 576 hwaddr base_ecam = sbsa_ref_memmap[SBSA_PCIE_ECAM].base; 577 hwaddr size_ecam = sbsa_ref_memmap[SBSA_PCIE_ECAM].size; 578 hwaddr base_mmio = sbsa_ref_memmap[SBSA_PCIE_MMIO].base; 579 hwaddr size_mmio = sbsa_ref_memmap[SBSA_PCIE_MMIO].size; 580 hwaddr base_mmio_high = sbsa_ref_memmap[SBSA_PCIE_MMIO_HIGH].base; 581 hwaddr size_mmio_high = sbsa_ref_memmap[SBSA_PCIE_MMIO_HIGH].size; 582 hwaddr base_pio = sbsa_ref_memmap[SBSA_PCIE_PIO].base; 583 int irq = sbsa_ref_irqmap[SBSA_PCIE]; 584 MemoryRegion *mmio_alias, *mmio_alias_high, *mmio_reg; 585 MemoryRegion *ecam_alias, *ecam_reg; 586 DeviceState *dev; 587 PCIHostState *pci; 588 int i; 589 590 dev = qdev_new(TYPE_GPEX_HOST); 591 sysbus_realize_and_unref(SYS_BUS_DEVICE(dev), &error_fatal); 592 593 /* Map ECAM space */ 594 ecam_alias = g_new0(MemoryRegion, 1); 595 ecam_reg = sysbus_mmio_get_region(SYS_BUS_DEVICE(dev), 0); 596 memory_region_init_alias(ecam_alias, OBJECT(dev), "pcie-ecam", 597 ecam_reg, 0, size_ecam); 598 memory_region_add_subregion(get_system_memory(), base_ecam, ecam_alias); 599 600 /* Map the MMIO space */ 601 mmio_alias = g_new0(MemoryRegion, 1); 602 mmio_reg = sysbus_mmio_get_region(SYS_BUS_DEVICE(dev), 1); 603 memory_region_init_alias(mmio_alias, OBJECT(dev), "pcie-mmio", 604 mmio_reg, base_mmio, size_mmio); 605 memory_region_add_subregion(get_system_memory(), base_mmio, mmio_alias); 606 607 /* Map the MMIO_HIGH space */ 608 mmio_alias_high = g_new0(MemoryRegion, 1); 609 memory_region_init_alias(mmio_alias_high, OBJECT(dev), "pcie-mmio-high", 610 mmio_reg, base_mmio_high, size_mmio_high); 611 memory_region_add_subregion(get_system_memory(), base_mmio_high, 612 mmio_alias_high); 613 614 /* Map IO port space */ 615 sysbus_mmio_map(SYS_BUS_DEVICE(dev), 2, base_pio); 616 617 for (i = 0; i < GPEX_NUM_IRQS; i++) { 618 sysbus_connect_irq(SYS_BUS_DEVICE(dev), i, 619 qdev_get_gpio_in(sms->gic, irq + i)); 620 gpex_set_irq_num(GPEX_HOST(dev), i, irq + i); 621 } 622 623 pci = PCI_HOST_BRIDGE(dev); 624 if (pci->bus) { 625 for (i = 0; i < nb_nics; i++) { 626 NICInfo *nd = &nd_table[i]; 627 628 if (!nd->model) { 629 nd->model = g_strdup("e1000e"); 630 } 631 632 pci_nic_init_nofail(nd, pci->bus, nd->model, NULL); 633 } 634 } 635 636 pci_create_simple(pci->bus, -1, "VGA"); 637 638 create_smmu(sms, pci->bus); 639 } 640 641 static void *sbsa_ref_dtb(const struct arm_boot_info *binfo, int *fdt_size) 642 { 643 const SBSAMachineState *board = container_of(binfo, SBSAMachineState, 644 bootinfo); 645 646 *fdt_size = board->fdt_size; 647 return board->fdt; 648 } 649 650 static void create_secure_ec(MemoryRegion *mem) 651 { 652 hwaddr base = sbsa_ref_memmap[SBSA_SECURE_EC].base; 653 DeviceState *dev = qdev_new("sbsa-ec"); 654 SysBusDevice *s = SYS_BUS_DEVICE(dev); 655 656 memory_region_add_subregion(mem, base, 657 sysbus_mmio_get_region(s, 0)); 658 } 659 660 static void sbsa_ref_init(MachineState *machine) 661 { 662 unsigned int smp_cpus = machine->smp.cpus; 663 unsigned int max_cpus = machine->smp.max_cpus; 664 SBSAMachineState *sms = SBSA_MACHINE(machine); 665 MachineClass *mc = MACHINE_GET_CLASS(machine); 666 MemoryRegion *sysmem = get_system_memory(); 667 MemoryRegion *secure_sysmem = g_new(MemoryRegion, 1); 668 bool firmware_loaded; 669 const CPUArchIdList *possible_cpus; 670 int n, sbsa_max_cpus; 671 672 if (!cpu_type_valid(machine->cpu_type)) { 673 error_report("sbsa-ref: CPU type %s not supported", machine->cpu_type); 674 exit(1); 675 } 676 677 if (kvm_enabled()) { 678 error_report("sbsa-ref: KVM is not supported for this machine"); 679 exit(1); 680 } 681 682 /* 683 * The Secure view of the world is the same as the NonSecure, 684 * but with a few extra devices. Create it as a container region 685 * containing the system memory at low priority; any secure-only 686 * devices go in at higher priority and take precedence. 687 */ 688 memory_region_init(secure_sysmem, OBJECT(machine), "secure-memory", 689 UINT64_MAX); 690 memory_region_add_subregion_overlap(secure_sysmem, 0, sysmem, -1); 691 692 firmware_loaded = sbsa_firmware_init(sms, sysmem, secure_sysmem); 693 694 /* 695 * This machine has EL3 enabled, external firmware should supply PSCI 696 * implementation, so the QEMU's internal PSCI is disabled. 697 */ 698 sms->psci_conduit = QEMU_PSCI_CONDUIT_DISABLED; 699 700 sbsa_max_cpus = sbsa_ref_memmap[SBSA_GIC_REDIST].size / GICV3_REDIST_SIZE; 701 702 if (max_cpus > sbsa_max_cpus) { 703 error_report("Number of SMP CPUs requested (%d) exceeds max CPUs " 704 "supported by machine 'sbsa-ref' (%d)", 705 max_cpus, sbsa_max_cpus); 706 exit(1); 707 } 708 709 sms->smp_cpus = smp_cpus; 710 711 if (machine->ram_size > sbsa_ref_memmap[SBSA_MEM].size) { 712 error_report("sbsa-ref: cannot model more than %dGB RAM", RAMLIMIT_GB); 713 exit(1); 714 } 715 716 possible_cpus = mc->possible_cpu_arch_ids(machine); 717 for (n = 0; n < possible_cpus->len; n++) { 718 Object *cpuobj; 719 CPUState *cs; 720 721 if (n >= smp_cpus) { 722 break; 723 } 724 725 cpuobj = object_new(possible_cpus->cpus[n].type); 726 object_property_set_int(cpuobj, "mp-affinity", 727 possible_cpus->cpus[n].arch_id, NULL); 728 729 cs = CPU(cpuobj); 730 cs->cpu_index = n; 731 732 numa_cpu_pre_plug(&possible_cpus->cpus[cs->cpu_index], DEVICE(cpuobj), 733 &error_fatal); 734 735 if (object_property_find(cpuobj, "reset-cbar")) { 736 object_property_set_int(cpuobj, "reset-cbar", 737 sbsa_ref_memmap[SBSA_CPUPERIPHS].base, 738 &error_abort); 739 } 740 741 object_property_set_link(cpuobj, "memory", OBJECT(sysmem), 742 &error_abort); 743 744 object_property_set_link(cpuobj, "secure-memory", 745 OBJECT(secure_sysmem), &error_abort); 746 747 qdev_realize(DEVICE(cpuobj), NULL, &error_fatal); 748 object_unref(cpuobj); 749 } 750 751 memory_region_add_subregion(sysmem, sbsa_ref_memmap[SBSA_MEM].base, 752 machine->ram); 753 754 create_fdt(sms); 755 756 create_secure_ram(sms, secure_sysmem); 757 758 create_gic(sms); 759 760 create_uart(sms, SBSA_UART, sysmem, serial_hd(0)); 761 create_uart(sms, SBSA_SECURE_UART, secure_sysmem, serial_hd(1)); 762 /* Second secure UART for RAS and MM from EL0 */ 763 create_uart(sms, SBSA_SECURE_UART_MM, secure_sysmem, serial_hd(2)); 764 765 create_rtc(sms); 766 767 create_wdt(sms); 768 769 create_gpio(sms); 770 771 create_ahci(sms); 772 773 create_ehci(sms); 774 775 create_pcie(sms); 776 777 create_secure_ec(secure_sysmem); 778 779 sms->bootinfo.ram_size = machine->ram_size; 780 sms->bootinfo.nb_cpus = smp_cpus; 781 sms->bootinfo.board_id = -1; 782 sms->bootinfo.loader_start = sbsa_ref_memmap[SBSA_MEM].base; 783 sms->bootinfo.get_dtb = sbsa_ref_dtb; 784 sms->bootinfo.firmware_loaded = firmware_loaded; 785 arm_load_kernel(ARM_CPU(first_cpu), machine, &sms->bootinfo); 786 } 787 788 static const CPUArchIdList *sbsa_ref_possible_cpu_arch_ids(MachineState *ms) 789 { 790 unsigned int max_cpus = ms->smp.max_cpus; 791 SBSAMachineState *sms = SBSA_MACHINE(ms); 792 int n; 793 794 if (ms->possible_cpus) { 795 assert(ms->possible_cpus->len == max_cpus); 796 return ms->possible_cpus; 797 } 798 799 ms->possible_cpus = g_malloc0(sizeof(CPUArchIdList) + 800 sizeof(CPUArchId) * max_cpus); 801 ms->possible_cpus->len = max_cpus; 802 for (n = 0; n < ms->possible_cpus->len; n++) { 803 ms->possible_cpus->cpus[n].type = ms->cpu_type; 804 ms->possible_cpus->cpus[n].arch_id = 805 sbsa_ref_cpu_mp_affinity(sms, n); 806 ms->possible_cpus->cpus[n].props.has_thread_id = true; 807 ms->possible_cpus->cpus[n].props.thread_id = n; 808 } 809 return ms->possible_cpus; 810 } 811 812 static CpuInstanceProperties 813 sbsa_ref_cpu_index_to_props(MachineState *ms, unsigned cpu_index) 814 { 815 MachineClass *mc = MACHINE_GET_CLASS(ms); 816 const CPUArchIdList *possible_cpus = mc->possible_cpu_arch_ids(ms); 817 818 assert(cpu_index < possible_cpus->len); 819 return possible_cpus->cpus[cpu_index].props; 820 } 821 822 static int64_t 823 sbsa_ref_get_default_cpu_node_id(const MachineState *ms, int idx) 824 { 825 return idx % ms->numa_state->num_nodes; 826 } 827 828 static void sbsa_ref_instance_init(Object *obj) 829 { 830 SBSAMachineState *sms = SBSA_MACHINE(obj); 831 832 sbsa_flash_create(sms); 833 } 834 835 static void sbsa_ref_class_init(ObjectClass *oc, void *data) 836 { 837 MachineClass *mc = MACHINE_CLASS(oc); 838 839 mc->init = sbsa_ref_init; 840 mc->desc = "QEMU 'SBSA Reference' ARM Virtual Machine"; 841 mc->default_cpu_type = ARM_CPU_TYPE_NAME("cortex-a57"); 842 mc->max_cpus = 512; 843 mc->pci_allow_0_address = true; 844 mc->minimum_page_bits = 12; 845 mc->block_default_type = IF_IDE; 846 mc->no_cdrom = 1; 847 mc->default_ram_size = 1 * GiB; 848 mc->default_ram_id = "sbsa-ref.ram"; 849 mc->default_cpus = 4; 850 mc->possible_cpu_arch_ids = sbsa_ref_possible_cpu_arch_ids; 851 mc->cpu_index_to_instance_props = sbsa_ref_cpu_index_to_props; 852 mc->get_default_cpu_node_id = sbsa_ref_get_default_cpu_node_id; 853 } 854 855 static const TypeInfo sbsa_ref_info = { 856 .name = TYPE_SBSA_MACHINE, 857 .parent = TYPE_MACHINE, 858 .instance_init = sbsa_ref_instance_init, 859 .class_init = sbsa_ref_class_init, 860 .instance_size = sizeof(SBSAMachineState), 861 }; 862 863 static void sbsa_ref_machine_init(void) 864 { 865 type_register_static(&sbsa_ref_info); 866 } 867 868 type_init(sbsa_ref_machine_init); 869