1 /* 2 * ARM SBSA Reference Platform emulation 3 * 4 * Copyright (c) 2018 Linaro Limited 5 * Copyright (c) 2023 Qualcomm Innovation Center, Inc. All rights reserved. 6 * Written by Hongbo Zhang <hongbo.zhang@linaro.org> 7 * 8 * This program is free software; you can redistribute it and/or modify it 9 * under the terms and conditions of the GNU General Public License, 10 * version 2 or later, as published by the Free Software Foundation. 11 * 12 * This program is distributed in the hope it will be useful, but WITHOUT 13 * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or 14 * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for 15 * more details. 16 * 17 * You should have received a copy of the GNU General Public License along with 18 * this program. If not, see <http://www.gnu.org/licenses/>. 19 */ 20 21 #include "qemu/osdep.h" 22 #include "qemu/datadir.h" 23 #include "qapi/error.h" 24 #include "qemu/error-report.h" 25 #include "qemu/units.h" 26 #include "sysemu/device_tree.h" 27 #include "sysemu/kvm.h" 28 #include "sysemu/numa.h" 29 #include "sysemu/runstate.h" 30 #include "sysemu/sysemu.h" 31 #include "exec/hwaddr.h" 32 #include "kvm_arm.h" 33 #include "hw/arm/boot.h" 34 #include "hw/arm/bsa.h" 35 #include "hw/arm/fdt.h" 36 #include "hw/arm/smmuv3.h" 37 #include "hw/block/flash.h" 38 #include "hw/boards.h" 39 #include "hw/ide/internal.h" 40 #include "hw/ide/ahci_internal.h" 41 #include "hw/ide/ahci-sysbus.h" 42 #include "hw/intc/arm_gicv3_common.h" 43 #include "hw/intc/arm_gicv3_its_common.h" 44 #include "hw/loader.h" 45 #include "hw/pci-host/gpex.h" 46 #include "hw/qdev-properties.h" 47 #include "hw/usb.h" 48 #include "hw/usb/xhci.h" 49 #include "hw/char/pl011.h" 50 #include "hw/watchdog/sbsa_gwdt.h" 51 #include "net/net.h" 52 #include "qapi/qmp/qlist.h" 53 #include "qom/object.h" 54 #include "target/arm/cpu-qom.h" 55 #include "target/arm/gtimer.h" 56 57 #define RAMLIMIT_GB 8192 58 #define RAMLIMIT_BYTES (RAMLIMIT_GB * GiB) 59 60 #define NUM_IRQS 256 61 #define NUM_SMMU_IRQS 4 62 #define NUM_SATA_PORTS 6 63 64 enum { 65 SBSA_FLASH, 66 SBSA_MEM, 67 SBSA_CPUPERIPHS, 68 SBSA_GIC_DIST, 69 SBSA_GIC_REDIST, 70 SBSA_GIC_ITS, 71 SBSA_SECURE_EC, 72 SBSA_GWDT_WS0, 73 SBSA_GWDT_REFRESH, 74 SBSA_GWDT_CONTROL, 75 SBSA_SMMU, 76 SBSA_UART, 77 SBSA_RTC, 78 SBSA_PCIE, 79 SBSA_PCIE_MMIO, 80 SBSA_PCIE_MMIO_HIGH, 81 SBSA_PCIE_PIO, 82 SBSA_PCIE_ECAM, 83 SBSA_GPIO, 84 SBSA_SECURE_UART, 85 SBSA_SECURE_UART_MM, 86 SBSA_SECURE_MEM, 87 SBSA_AHCI, 88 SBSA_XHCI, 89 }; 90 91 struct SBSAMachineState { 92 MachineState parent; 93 struct arm_boot_info bootinfo; 94 int smp_cpus; 95 void *fdt; 96 int fdt_size; 97 int psci_conduit; 98 DeviceState *gic; 99 PFlashCFI01 *flash[2]; 100 }; 101 102 #define TYPE_SBSA_MACHINE MACHINE_TYPE_NAME("sbsa-ref") 103 OBJECT_DECLARE_SIMPLE_TYPE(SBSAMachineState, SBSA_MACHINE) 104 105 static const MemMapEntry sbsa_ref_memmap[] = { 106 /* 512M boot ROM */ 107 [SBSA_FLASH] = { 0, 0x20000000 }, 108 /* 512M secure memory */ 109 [SBSA_SECURE_MEM] = { 0x20000000, 0x20000000 }, 110 /* Space reserved for CPU peripheral devices */ 111 [SBSA_CPUPERIPHS] = { 0x40000000, 0x00040000 }, 112 [SBSA_GIC_DIST] = { 0x40060000, 0x00010000 }, 113 [SBSA_GIC_REDIST] = { 0x40080000, 0x04000000 }, 114 [SBSA_GIC_ITS] = { 0x44081000, 0x00020000 }, 115 [SBSA_SECURE_EC] = { 0x50000000, 0x00001000 }, 116 [SBSA_GWDT_REFRESH] = { 0x50010000, 0x00001000 }, 117 [SBSA_GWDT_CONTROL] = { 0x50011000, 0x00001000 }, 118 [SBSA_UART] = { 0x60000000, 0x00001000 }, 119 [SBSA_RTC] = { 0x60010000, 0x00001000 }, 120 [SBSA_GPIO] = { 0x60020000, 0x00001000 }, 121 [SBSA_SECURE_UART] = { 0x60030000, 0x00001000 }, 122 [SBSA_SECURE_UART_MM] = { 0x60040000, 0x00001000 }, 123 [SBSA_SMMU] = { 0x60050000, 0x00020000 }, 124 /* Space here reserved for more SMMUs */ 125 [SBSA_AHCI] = { 0x60100000, 0x00010000 }, 126 [SBSA_XHCI] = { 0x60110000, 0x00010000 }, 127 /* Space here reserved for other devices */ 128 [SBSA_PCIE_PIO] = { 0x7fff0000, 0x00010000 }, 129 /* 32-bit address PCIE MMIO space */ 130 [SBSA_PCIE_MMIO] = { 0x80000000, 0x70000000 }, 131 /* 256M PCIE ECAM space */ 132 [SBSA_PCIE_ECAM] = { 0xf0000000, 0x10000000 }, 133 /* ~1TB PCIE MMIO space (4GB to 1024GB boundary) */ 134 [SBSA_PCIE_MMIO_HIGH] = { 0x100000000ULL, 0xFF00000000ULL }, 135 [SBSA_MEM] = { 0x10000000000ULL, RAMLIMIT_BYTES }, 136 }; 137 138 static const int sbsa_ref_irqmap[] = { 139 [SBSA_UART] = 1, 140 [SBSA_RTC] = 2, 141 [SBSA_PCIE] = 3, /* ... to 6 */ 142 [SBSA_GPIO] = 7, 143 [SBSA_SECURE_UART] = 8, 144 [SBSA_SECURE_UART_MM] = 9, 145 [SBSA_AHCI] = 10, 146 [SBSA_XHCI] = 11, 147 [SBSA_SMMU] = 12, /* ... to 15 */ 148 [SBSA_GWDT_WS0] = 16, 149 }; 150 151 static uint64_t sbsa_ref_cpu_mp_affinity(SBSAMachineState *sms, int idx) 152 { 153 uint8_t clustersz = ARM_DEFAULT_CPUS_PER_CLUSTER; 154 return arm_build_mp_affinity(idx, clustersz); 155 } 156 157 static void sbsa_fdt_add_gic_node(SBSAMachineState *sms) 158 { 159 char *nodename; 160 161 nodename = g_strdup_printf("/intc"); 162 qemu_fdt_add_subnode(sms->fdt, nodename); 163 qemu_fdt_setprop_sized_cells(sms->fdt, nodename, "reg", 164 2, sbsa_ref_memmap[SBSA_GIC_DIST].base, 165 2, sbsa_ref_memmap[SBSA_GIC_DIST].size, 166 2, sbsa_ref_memmap[SBSA_GIC_REDIST].base, 167 2, sbsa_ref_memmap[SBSA_GIC_REDIST].size); 168 169 nodename = g_strdup_printf("/intc/its"); 170 qemu_fdt_add_subnode(sms->fdt, nodename); 171 qemu_fdt_setprop_sized_cells(sms->fdt, nodename, "reg", 172 2, sbsa_ref_memmap[SBSA_GIC_ITS].base, 173 2, sbsa_ref_memmap[SBSA_GIC_ITS].size); 174 175 g_free(nodename); 176 } 177 178 /* 179 * Firmware on this machine only uses ACPI table to load OS, these limited 180 * device tree nodes are just to let firmware know the info which varies from 181 * command line parameters, so it is not necessary to be fully compatible 182 * with the kernel CPU and NUMA binding rules. 183 */ 184 static void create_fdt(SBSAMachineState *sms) 185 { 186 void *fdt = create_device_tree(&sms->fdt_size); 187 const MachineState *ms = MACHINE(sms); 188 int nb_numa_nodes = ms->numa_state->num_nodes; 189 int cpu; 190 191 if (!fdt) { 192 error_report("create_device_tree() failed"); 193 exit(1); 194 } 195 196 sms->fdt = fdt; 197 198 qemu_fdt_setprop_string(fdt, "/", "compatible", "linux,sbsa-ref"); 199 qemu_fdt_setprop_cell(fdt, "/", "#address-cells", 0x2); 200 qemu_fdt_setprop_cell(fdt, "/", "#size-cells", 0x2); 201 202 /* 203 * This versioning scheme is for informing platform fw only. It is neither: 204 * - A QEMU versioned machine type; a given version of QEMU will emulate 205 * a given version of the platform. 206 * - A reflection of level of SBSA (now SystemReady SR) support provided. 207 * 208 * machine-version-major: updated when changes breaking fw compatibility 209 * are introduced. 210 * machine-version-minor: updated when features are added that don't break 211 * fw compatibility. 212 */ 213 qemu_fdt_setprop_cell(fdt, "/", "machine-version-major", 0); 214 qemu_fdt_setprop_cell(fdt, "/", "machine-version-minor", 3); 215 216 if (ms->numa_state->have_numa_distance) { 217 int size = nb_numa_nodes * nb_numa_nodes * 3 * sizeof(uint32_t); 218 uint32_t *matrix = g_malloc0(size); 219 int idx, i, j; 220 221 for (i = 0; i < nb_numa_nodes; i++) { 222 for (j = 0; j < nb_numa_nodes; j++) { 223 idx = (i * nb_numa_nodes + j) * 3; 224 matrix[idx + 0] = cpu_to_be32(i); 225 matrix[idx + 1] = cpu_to_be32(j); 226 matrix[idx + 2] = 227 cpu_to_be32(ms->numa_state->nodes[i].distance[j]); 228 } 229 } 230 231 qemu_fdt_add_subnode(fdt, "/distance-map"); 232 qemu_fdt_setprop(fdt, "/distance-map", "distance-matrix", 233 matrix, size); 234 g_free(matrix); 235 } 236 237 /* 238 * From Documentation/devicetree/bindings/arm/cpus.yaml 239 * On ARM v8 64-bit systems this property is required 240 * and matches the MPIDR_EL1 register affinity bits. 241 * 242 * * If cpus node's #address-cells property is set to 2 243 * 244 * The first reg cell bits [7:0] must be set to 245 * bits [39:32] of MPIDR_EL1. 246 * 247 * The second reg cell bits [23:0] must be set to 248 * bits [23:0] of MPIDR_EL1. 249 */ 250 qemu_fdt_add_subnode(sms->fdt, "/cpus"); 251 qemu_fdt_setprop_cell(sms->fdt, "/cpus", "#address-cells", 2); 252 qemu_fdt_setprop_cell(sms->fdt, "/cpus", "#size-cells", 0x0); 253 254 for (cpu = sms->smp_cpus - 1; cpu >= 0; cpu--) { 255 char *nodename = g_strdup_printf("/cpus/cpu@%d", cpu); 256 ARMCPU *armcpu = ARM_CPU(qemu_get_cpu(cpu)); 257 CPUState *cs = CPU(armcpu); 258 uint64_t mpidr = sbsa_ref_cpu_mp_affinity(sms, cpu); 259 260 qemu_fdt_add_subnode(sms->fdt, nodename); 261 qemu_fdt_setprop_u64(sms->fdt, nodename, "reg", mpidr); 262 263 if (ms->possible_cpus->cpus[cs->cpu_index].props.has_node_id) { 264 qemu_fdt_setprop_cell(sms->fdt, nodename, "numa-node-id", 265 ms->possible_cpus->cpus[cs->cpu_index].props.node_id); 266 } 267 268 g_free(nodename); 269 } 270 271 sbsa_fdt_add_gic_node(sms); 272 } 273 274 #define SBSA_FLASH_SECTOR_SIZE (256 * KiB) 275 276 static PFlashCFI01 *sbsa_flash_create1(SBSAMachineState *sms, 277 const char *name, 278 const char *alias_prop_name) 279 { 280 /* 281 * Create a single flash device. We use the same parameters as 282 * the flash devices on the Versatile Express board. 283 */ 284 DeviceState *dev = qdev_new(TYPE_PFLASH_CFI01); 285 286 qdev_prop_set_uint64(dev, "sector-length", SBSA_FLASH_SECTOR_SIZE); 287 qdev_prop_set_uint8(dev, "width", 4); 288 qdev_prop_set_uint8(dev, "device-width", 2); 289 qdev_prop_set_bit(dev, "big-endian", false); 290 qdev_prop_set_uint16(dev, "id0", 0x89); 291 qdev_prop_set_uint16(dev, "id1", 0x18); 292 qdev_prop_set_uint16(dev, "id2", 0x00); 293 qdev_prop_set_uint16(dev, "id3", 0x00); 294 qdev_prop_set_string(dev, "name", name); 295 object_property_add_child(OBJECT(sms), name, OBJECT(dev)); 296 object_property_add_alias(OBJECT(sms), alias_prop_name, 297 OBJECT(dev), "drive"); 298 return PFLASH_CFI01(dev); 299 } 300 301 static void sbsa_flash_create(SBSAMachineState *sms) 302 { 303 sms->flash[0] = sbsa_flash_create1(sms, "sbsa.flash0", "pflash0"); 304 sms->flash[1] = sbsa_flash_create1(sms, "sbsa.flash1", "pflash1"); 305 } 306 307 static void sbsa_flash_map1(PFlashCFI01 *flash, 308 hwaddr base, hwaddr size, 309 MemoryRegion *sysmem) 310 { 311 DeviceState *dev = DEVICE(flash); 312 313 assert(QEMU_IS_ALIGNED(size, SBSA_FLASH_SECTOR_SIZE)); 314 assert(size / SBSA_FLASH_SECTOR_SIZE <= UINT32_MAX); 315 qdev_prop_set_uint32(dev, "num-blocks", size / SBSA_FLASH_SECTOR_SIZE); 316 sysbus_realize_and_unref(SYS_BUS_DEVICE(dev), &error_fatal); 317 318 memory_region_add_subregion(sysmem, base, 319 sysbus_mmio_get_region(SYS_BUS_DEVICE(dev), 320 0)); 321 } 322 323 static void sbsa_flash_map(SBSAMachineState *sms, 324 MemoryRegion *sysmem, 325 MemoryRegion *secure_sysmem) 326 { 327 /* 328 * Map two flash devices to fill the SBSA_FLASH space in the memmap. 329 * sysmem is the system memory space. secure_sysmem is the secure view 330 * of the system, and the first flash device should be made visible only 331 * there. The second flash device is visible to both secure and nonsecure. 332 */ 333 hwaddr flashsize = sbsa_ref_memmap[SBSA_FLASH].size / 2; 334 hwaddr flashbase = sbsa_ref_memmap[SBSA_FLASH].base; 335 336 sbsa_flash_map1(sms->flash[0], flashbase, flashsize, 337 secure_sysmem); 338 sbsa_flash_map1(sms->flash[1], flashbase + flashsize, flashsize, 339 sysmem); 340 } 341 342 static bool sbsa_firmware_init(SBSAMachineState *sms, 343 MemoryRegion *sysmem, 344 MemoryRegion *secure_sysmem) 345 { 346 const char *bios_name; 347 int i; 348 BlockBackend *pflash_blk0; 349 350 /* Map legacy -drive if=pflash to machine properties */ 351 for (i = 0; i < ARRAY_SIZE(sms->flash); i++) { 352 pflash_cfi01_legacy_drive(sms->flash[i], 353 drive_get(IF_PFLASH, 0, i)); 354 } 355 356 sbsa_flash_map(sms, sysmem, secure_sysmem); 357 358 pflash_blk0 = pflash_cfi01_get_blk(sms->flash[0]); 359 360 bios_name = MACHINE(sms)->firmware; 361 if (bios_name) { 362 char *fname; 363 MemoryRegion *mr; 364 int image_size; 365 366 if (pflash_blk0) { 367 error_report("The contents of the first flash device may be " 368 "specified with -bios or with -drive if=pflash... " 369 "but you cannot use both options at once"); 370 exit(1); 371 } 372 373 /* Fall back to -bios */ 374 375 fname = qemu_find_file(QEMU_FILE_TYPE_BIOS, bios_name); 376 if (!fname) { 377 error_report("Could not find ROM image '%s'", bios_name); 378 exit(1); 379 } 380 mr = sysbus_mmio_get_region(SYS_BUS_DEVICE(sms->flash[0]), 0); 381 image_size = load_image_mr(fname, mr); 382 g_free(fname); 383 if (image_size < 0) { 384 error_report("Could not load ROM image '%s'", bios_name); 385 exit(1); 386 } 387 } 388 389 return pflash_blk0 || bios_name; 390 } 391 392 static void create_secure_ram(SBSAMachineState *sms, 393 MemoryRegion *secure_sysmem) 394 { 395 MemoryRegion *secram = g_new(MemoryRegion, 1); 396 hwaddr base = sbsa_ref_memmap[SBSA_SECURE_MEM].base; 397 hwaddr size = sbsa_ref_memmap[SBSA_SECURE_MEM].size; 398 399 memory_region_init_ram(secram, NULL, "sbsa-ref.secure-ram", size, 400 &error_fatal); 401 memory_region_add_subregion(secure_sysmem, base, secram); 402 } 403 404 static void create_its(SBSAMachineState *sms) 405 { 406 const char *itsclass = its_class_name(); 407 DeviceState *dev; 408 409 dev = qdev_new(itsclass); 410 411 object_property_set_link(OBJECT(dev), "parent-gicv3", OBJECT(sms->gic), 412 &error_abort); 413 sysbus_realize_and_unref(SYS_BUS_DEVICE(dev), &error_fatal); 414 sysbus_mmio_map(SYS_BUS_DEVICE(dev), 0, sbsa_ref_memmap[SBSA_GIC_ITS].base); 415 } 416 417 static void create_gic(SBSAMachineState *sms, MemoryRegion *mem) 418 { 419 unsigned int smp_cpus = MACHINE(sms)->smp.cpus; 420 SysBusDevice *gicbusdev; 421 const char *gictype; 422 uint32_t redist0_capacity, redist0_count; 423 QList *redist_region_count; 424 int i; 425 426 gictype = gicv3_class_name(); 427 428 sms->gic = qdev_new(gictype); 429 qdev_prop_set_uint32(sms->gic, "revision", 3); 430 qdev_prop_set_uint32(sms->gic, "num-cpu", smp_cpus); 431 /* 432 * Note that the num-irq property counts both internal and external 433 * interrupts; there are always 32 of the former (mandated by GIC spec). 434 */ 435 qdev_prop_set_uint32(sms->gic, "num-irq", NUM_IRQS + 32); 436 qdev_prop_set_bit(sms->gic, "has-security-extensions", true); 437 438 redist0_capacity = 439 sbsa_ref_memmap[SBSA_GIC_REDIST].size / GICV3_REDIST_SIZE; 440 redist0_count = MIN(smp_cpus, redist0_capacity); 441 442 redist_region_count = qlist_new(); 443 qlist_append_int(redist_region_count, redist0_count); 444 qdev_prop_set_array(sms->gic, "redist-region-count", redist_region_count); 445 446 object_property_set_link(OBJECT(sms->gic), "sysmem", 447 OBJECT(mem), &error_fatal); 448 qdev_prop_set_bit(sms->gic, "has-lpi", true); 449 450 gicbusdev = SYS_BUS_DEVICE(sms->gic); 451 sysbus_realize_and_unref(gicbusdev, &error_fatal); 452 sysbus_mmio_map(gicbusdev, 0, sbsa_ref_memmap[SBSA_GIC_DIST].base); 453 sysbus_mmio_map(gicbusdev, 1, sbsa_ref_memmap[SBSA_GIC_REDIST].base); 454 455 /* 456 * Wire the outputs from each CPU's generic timer and the GICv3 457 * maintenance interrupt signal to the appropriate GIC PPI inputs, 458 * and the GIC's IRQ/FIQ/VIRQ/VFIQ interrupt outputs to the CPU's inputs. 459 */ 460 for (i = 0; i < smp_cpus; i++) { 461 DeviceState *cpudev = DEVICE(qemu_get_cpu(i)); 462 int intidbase = NUM_IRQS + i * GIC_INTERNAL; 463 int irq; 464 /* 465 * Mapping from the output timer irq lines from the CPU to the 466 * GIC PPI inputs used for this board. 467 */ 468 const int timer_irq[] = { 469 [GTIMER_PHYS] = ARCH_TIMER_NS_EL1_IRQ, 470 [GTIMER_VIRT] = ARCH_TIMER_VIRT_IRQ, 471 [GTIMER_HYP] = ARCH_TIMER_NS_EL2_IRQ, 472 [GTIMER_SEC] = ARCH_TIMER_S_EL1_IRQ, 473 [GTIMER_HYPVIRT] = ARCH_TIMER_NS_EL2_VIRT_IRQ, 474 }; 475 476 for (irq = 0; irq < ARRAY_SIZE(timer_irq); irq++) { 477 qdev_connect_gpio_out(cpudev, irq, 478 qdev_get_gpio_in(sms->gic, 479 intidbase + timer_irq[irq])); 480 } 481 482 qdev_connect_gpio_out_named(cpudev, "gicv3-maintenance-interrupt", 0, 483 qdev_get_gpio_in(sms->gic, 484 intidbase 485 + ARCH_GIC_MAINT_IRQ)); 486 487 qdev_connect_gpio_out_named(cpudev, "pmu-interrupt", 0, 488 qdev_get_gpio_in(sms->gic, 489 intidbase 490 + VIRTUAL_PMU_IRQ)); 491 492 sysbus_connect_irq(gicbusdev, i, qdev_get_gpio_in(cpudev, ARM_CPU_IRQ)); 493 sysbus_connect_irq(gicbusdev, i + smp_cpus, 494 qdev_get_gpio_in(cpudev, ARM_CPU_FIQ)); 495 sysbus_connect_irq(gicbusdev, i + 2 * smp_cpus, 496 qdev_get_gpio_in(cpudev, ARM_CPU_VIRQ)); 497 sysbus_connect_irq(gicbusdev, i + 3 * smp_cpus, 498 qdev_get_gpio_in(cpudev, ARM_CPU_VFIQ)); 499 } 500 create_its(sms); 501 } 502 503 static void create_uart(const SBSAMachineState *sms, int uart, 504 MemoryRegion *mem, Chardev *chr) 505 { 506 hwaddr base = sbsa_ref_memmap[uart].base; 507 int irq = sbsa_ref_irqmap[uart]; 508 DeviceState *dev = qdev_new(TYPE_PL011); 509 SysBusDevice *s = SYS_BUS_DEVICE(dev); 510 511 qdev_prop_set_chr(dev, "chardev", chr); 512 sysbus_realize_and_unref(SYS_BUS_DEVICE(dev), &error_fatal); 513 memory_region_add_subregion(mem, base, 514 sysbus_mmio_get_region(s, 0)); 515 sysbus_connect_irq(s, 0, qdev_get_gpio_in(sms->gic, irq)); 516 } 517 518 static void create_rtc(const SBSAMachineState *sms) 519 { 520 hwaddr base = sbsa_ref_memmap[SBSA_RTC].base; 521 int irq = sbsa_ref_irqmap[SBSA_RTC]; 522 523 sysbus_create_simple("pl031", base, qdev_get_gpio_in(sms->gic, irq)); 524 } 525 526 static void create_wdt(const SBSAMachineState *sms) 527 { 528 hwaddr rbase = sbsa_ref_memmap[SBSA_GWDT_REFRESH].base; 529 hwaddr cbase = sbsa_ref_memmap[SBSA_GWDT_CONTROL].base; 530 DeviceState *dev = qdev_new(TYPE_WDT_SBSA); 531 SysBusDevice *s = SYS_BUS_DEVICE(dev); 532 int irq = sbsa_ref_irqmap[SBSA_GWDT_WS0]; 533 534 sysbus_realize_and_unref(s, &error_fatal); 535 sysbus_mmio_map(s, 0, rbase); 536 sysbus_mmio_map(s, 1, cbase); 537 sysbus_connect_irq(s, 0, qdev_get_gpio_in(sms->gic, irq)); 538 } 539 540 static DeviceState *gpio_key_dev; 541 static void sbsa_ref_powerdown_req(Notifier *n, void *opaque) 542 { 543 /* use gpio Pin 3 for power button event */ 544 qemu_set_irq(qdev_get_gpio_in(gpio_key_dev, 0), 1); 545 } 546 547 static Notifier sbsa_ref_powerdown_notifier = { 548 .notify = sbsa_ref_powerdown_req 549 }; 550 551 static void create_gpio(const SBSAMachineState *sms) 552 { 553 DeviceState *pl061_dev; 554 hwaddr base = sbsa_ref_memmap[SBSA_GPIO].base; 555 int irq = sbsa_ref_irqmap[SBSA_GPIO]; 556 557 pl061_dev = sysbus_create_simple("pl061", base, 558 qdev_get_gpio_in(sms->gic, irq)); 559 560 gpio_key_dev = sysbus_create_simple("gpio-key", -1, 561 qdev_get_gpio_in(pl061_dev, 3)); 562 563 /* connect powerdown request */ 564 qemu_register_powerdown_notifier(&sbsa_ref_powerdown_notifier); 565 } 566 567 static void create_ahci(const SBSAMachineState *sms) 568 { 569 hwaddr base = sbsa_ref_memmap[SBSA_AHCI].base; 570 int irq = sbsa_ref_irqmap[SBSA_AHCI]; 571 DeviceState *dev; 572 DriveInfo *hd[NUM_SATA_PORTS]; 573 SysbusAHCIState *sysahci; 574 AHCIState *ahci; 575 int i; 576 577 dev = qdev_new("sysbus-ahci"); 578 qdev_prop_set_uint32(dev, "num-ports", NUM_SATA_PORTS); 579 sysbus_realize_and_unref(SYS_BUS_DEVICE(dev), &error_fatal); 580 sysbus_mmio_map(SYS_BUS_DEVICE(dev), 0, base); 581 sysbus_connect_irq(SYS_BUS_DEVICE(dev), 0, qdev_get_gpio_in(sms->gic, irq)); 582 583 sysahci = SYSBUS_AHCI(dev); 584 ahci = &sysahci->ahci; 585 ide_drive_get(hd, ARRAY_SIZE(hd)); 586 for (i = 0; i < ahci->ports; i++) { 587 if (hd[i] == NULL) { 588 continue; 589 } 590 ide_bus_create_drive(&ahci->dev[i].port, 0, hd[i]); 591 } 592 } 593 594 static void create_xhci(const SBSAMachineState *sms) 595 { 596 hwaddr base = sbsa_ref_memmap[SBSA_XHCI].base; 597 int irq = sbsa_ref_irqmap[SBSA_XHCI]; 598 DeviceState *dev = qdev_new(TYPE_XHCI_SYSBUS); 599 qdev_prop_set_uint32(dev, "slots", XHCI_MAXSLOTS); 600 601 sysbus_realize_and_unref(SYS_BUS_DEVICE(dev), &error_fatal); 602 sysbus_mmio_map(SYS_BUS_DEVICE(dev), 0, base); 603 sysbus_connect_irq(SYS_BUS_DEVICE(dev), 0, qdev_get_gpio_in(sms->gic, irq)); 604 } 605 606 static void create_smmu(const SBSAMachineState *sms, PCIBus *bus) 607 { 608 hwaddr base = sbsa_ref_memmap[SBSA_SMMU].base; 609 int irq = sbsa_ref_irqmap[SBSA_SMMU]; 610 DeviceState *dev; 611 int i; 612 613 dev = qdev_new(TYPE_ARM_SMMUV3); 614 615 object_property_set_link(OBJECT(dev), "primary-bus", OBJECT(bus), 616 &error_abort); 617 sysbus_realize_and_unref(SYS_BUS_DEVICE(dev), &error_fatal); 618 sysbus_mmio_map(SYS_BUS_DEVICE(dev), 0, base); 619 for (i = 0; i < NUM_SMMU_IRQS; i++) { 620 sysbus_connect_irq(SYS_BUS_DEVICE(dev), i, 621 qdev_get_gpio_in(sms->gic, irq + i)); 622 } 623 } 624 625 static void create_pcie(SBSAMachineState *sms) 626 { 627 hwaddr base_ecam = sbsa_ref_memmap[SBSA_PCIE_ECAM].base; 628 hwaddr size_ecam = sbsa_ref_memmap[SBSA_PCIE_ECAM].size; 629 hwaddr base_mmio = sbsa_ref_memmap[SBSA_PCIE_MMIO].base; 630 hwaddr size_mmio = sbsa_ref_memmap[SBSA_PCIE_MMIO].size; 631 hwaddr base_mmio_high = sbsa_ref_memmap[SBSA_PCIE_MMIO_HIGH].base; 632 hwaddr size_mmio_high = sbsa_ref_memmap[SBSA_PCIE_MMIO_HIGH].size; 633 hwaddr base_pio = sbsa_ref_memmap[SBSA_PCIE_PIO].base; 634 int irq = sbsa_ref_irqmap[SBSA_PCIE]; 635 MachineClass *mc = MACHINE_GET_CLASS(sms); 636 MemoryRegion *mmio_alias, *mmio_alias_high, *mmio_reg; 637 MemoryRegion *ecam_alias, *ecam_reg; 638 DeviceState *dev; 639 PCIHostState *pci; 640 int i; 641 642 dev = qdev_new(TYPE_GPEX_HOST); 643 sysbus_realize_and_unref(SYS_BUS_DEVICE(dev), &error_fatal); 644 645 /* Map ECAM space */ 646 ecam_alias = g_new0(MemoryRegion, 1); 647 ecam_reg = sysbus_mmio_get_region(SYS_BUS_DEVICE(dev), 0); 648 memory_region_init_alias(ecam_alias, OBJECT(dev), "pcie-ecam", 649 ecam_reg, 0, size_ecam); 650 memory_region_add_subregion(get_system_memory(), base_ecam, ecam_alias); 651 652 /* Map the MMIO space */ 653 mmio_alias = g_new0(MemoryRegion, 1); 654 mmio_reg = sysbus_mmio_get_region(SYS_BUS_DEVICE(dev), 1); 655 memory_region_init_alias(mmio_alias, OBJECT(dev), "pcie-mmio", 656 mmio_reg, base_mmio, size_mmio); 657 memory_region_add_subregion(get_system_memory(), base_mmio, mmio_alias); 658 659 /* Map the MMIO_HIGH space */ 660 mmio_alias_high = g_new0(MemoryRegion, 1); 661 memory_region_init_alias(mmio_alias_high, OBJECT(dev), "pcie-mmio-high", 662 mmio_reg, base_mmio_high, size_mmio_high); 663 memory_region_add_subregion(get_system_memory(), base_mmio_high, 664 mmio_alias_high); 665 666 /* Map IO port space */ 667 sysbus_mmio_map(SYS_BUS_DEVICE(dev), 2, base_pio); 668 669 for (i = 0; i < GPEX_NUM_IRQS; i++) { 670 sysbus_connect_irq(SYS_BUS_DEVICE(dev), i, 671 qdev_get_gpio_in(sms->gic, irq + i)); 672 gpex_set_irq_num(GPEX_HOST(dev), i, irq + i); 673 } 674 675 pci = PCI_HOST_BRIDGE(dev); 676 if (pci->bus) { 677 pci_init_nic_devices(pci->bus, mc->default_nic); 678 } 679 680 pci_create_simple(pci->bus, -1, "bochs-display"); 681 682 create_smmu(sms, pci->bus); 683 } 684 685 static void *sbsa_ref_dtb(const struct arm_boot_info *binfo, int *fdt_size) 686 { 687 const SBSAMachineState *board = container_of(binfo, SBSAMachineState, 688 bootinfo); 689 690 *fdt_size = board->fdt_size; 691 return board->fdt; 692 } 693 694 static void create_secure_ec(MemoryRegion *mem) 695 { 696 hwaddr base = sbsa_ref_memmap[SBSA_SECURE_EC].base; 697 DeviceState *dev = qdev_new("sbsa-ec"); 698 SysBusDevice *s = SYS_BUS_DEVICE(dev); 699 700 memory_region_add_subregion(mem, base, 701 sysbus_mmio_get_region(s, 0)); 702 } 703 704 static void sbsa_ref_init(MachineState *machine) 705 { 706 unsigned int smp_cpus = machine->smp.cpus; 707 unsigned int max_cpus = machine->smp.max_cpus; 708 SBSAMachineState *sms = SBSA_MACHINE(machine); 709 MachineClass *mc = MACHINE_GET_CLASS(machine); 710 MemoryRegion *sysmem = get_system_memory(); 711 MemoryRegion *secure_sysmem = g_new(MemoryRegion, 1); 712 bool firmware_loaded; 713 const CPUArchIdList *possible_cpus; 714 int n, sbsa_max_cpus; 715 716 if (kvm_enabled()) { 717 error_report("sbsa-ref: KVM is not supported for this machine"); 718 exit(1); 719 } 720 721 /* 722 * The Secure view of the world is the same as the NonSecure, 723 * but with a few extra devices. Create it as a container region 724 * containing the system memory at low priority; any secure-only 725 * devices go in at higher priority and take precedence. 726 */ 727 memory_region_init(secure_sysmem, OBJECT(machine), "secure-memory", 728 UINT64_MAX); 729 memory_region_add_subregion_overlap(secure_sysmem, 0, sysmem, -1); 730 731 firmware_loaded = sbsa_firmware_init(sms, sysmem, secure_sysmem); 732 733 /* 734 * This machine has EL3 enabled, external firmware should supply PSCI 735 * implementation, so the QEMU's internal PSCI is disabled. 736 */ 737 sms->psci_conduit = QEMU_PSCI_CONDUIT_DISABLED; 738 739 sbsa_max_cpus = sbsa_ref_memmap[SBSA_GIC_REDIST].size / GICV3_REDIST_SIZE; 740 741 if (max_cpus > sbsa_max_cpus) { 742 error_report("Number of SMP CPUs requested (%d) exceeds max CPUs " 743 "supported by machine 'sbsa-ref' (%d)", 744 max_cpus, sbsa_max_cpus); 745 exit(1); 746 } 747 748 sms->smp_cpus = smp_cpus; 749 750 if (machine->ram_size > sbsa_ref_memmap[SBSA_MEM].size) { 751 error_report("sbsa-ref: cannot model more than %dGB RAM", RAMLIMIT_GB); 752 exit(1); 753 } 754 755 possible_cpus = mc->possible_cpu_arch_ids(machine); 756 for (n = 0; n < possible_cpus->len; n++) { 757 Object *cpuobj; 758 CPUState *cs; 759 760 if (n >= smp_cpus) { 761 break; 762 } 763 764 cpuobj = object_new(possible_cpus->cpus[n].type); 765 object_property_set_int(cpuobj, "mp-affinity", 766 possible_cpus->cpus[n].arch_id, NULL); 767 768 cs = CPU(cpuobj); 769 cs->cpu_index = n; 770 771 numa_cpu_pre_plug(&possible_cpus->cpus[cs->cpu_index], DEVICE(cpuobj), 772 &error_fatal); 773 774 if (object_property_find(cpuobj, "reset-cbar")) { 775 object_property_set_int(cpuobj, "reset-cbar", 776 sbsa_ref_memmap[SBSA_CPUPERIPHS].base, 777 &error_abort); 778 } 779 780 object_property_set_link(cpuobj, "memory", OBJECT(sysmem), 781 &error_abort); 782 783 object_property_set_link(cpuobj, "secure-memory", 784 OBJECT(secure_sysmem), &error_abort); 785 786 qdev_realize(DEVICE(cpuobj), NULL, &error_fatal); 787 object_unref(cpuobj); 788 } 789 790 memory_region_add_subregion(sysmem, sbsa_ref_memmap[SBSA_MEM].base, 791 machine->ram); 792 793 create_fdt(sms); 794 795 create_secure_ram(sms, secure_sysmem); 796 797 create_gic(sms, sysmem); 798 799 create_uart(sms, SBSA_UART, sysmem, serial_hd(0)); 800 create_uart(sms, SBSA_SECURE_UART, secure_sysmem, serial_hd(1)); 801 /* Second secure UART for RAS and MM from EL0 */ 802 create_uart(sms, SBSA_SECURE_UART_MM, secure_sysmem, serial_hd(2)); 803 804 create_rtc(sms); 805 806 create_wdt(sms); 807 808 create_gpio(sms); 809 810 create_ahci(sms); 811 812 create_xhci(sms); 813 814 create_pcie(sms); 815 816 create_secure_ec(secure_sysmem); 817 818 sms->bootinfo.ram_size = machine->ram_size; 819 sms->bootinfo.board_id = -1; 820 sms->bootinfo.loader_start = sbsa_ref_memmap[SBSA_MEM].base; 821 sms->bootinfo.get_dtb = sbsa_ref_dtb; 822 sms->bootinfo.firmware_loaded = firmware_loaded; 823 arm_load_kernel(ARM_CPU(first_cpu), machine, &sms->bootinfo); 824 } 825 826 static const CPUArchIdList *sbsa_ref_possible_cpu_arch_ids(MachineState *ms) 827 { 828 unsigned int max_cpus = ms->smp.max_cpus; 829 SBSAMachineState *sms = SBSA_MACHINE(ms); 830 int n; 831 832 if (ms->possible_cpus) { 833 assert(ms->possible_cpus->len == max_cpus); 834 return ms->possible_cpus; 835 } 836 837 ms->possible_cpus = g_malloc0(sizeof(CPUArchIdList) + 838 sizeof(CPUArchId) * max_cpus); 839 ms->possible_cpus->len = max_cpus; 840 for (n = 0; n < ms->possible_cpus->len; n++) { 841 ms->possible_cpus->cpus[n].type = ms->cpu_type; 842 ms->possible_cpus->cpus[n].arch_id = 843 sbsa_ref_cpu_mp_affinity(sms, n); 844 ms->possible_cpus->cpus[n].props.has_thread_id = true; 845 ms->possible_cpus->cpus[n].props.thread_id = n; 846 } 847 return ms->possible_cpus; 848 } 849 850 static CpuInstanceProperties 851 sbsa_ref_cpu_index_to_props(MachineState *ms, unsigned cpu_index) 852 { 853 MachineClass *mc = MACHINE_GET_CLASS(ms); 854 const CPUArchIdList *possible_cpus = mc->possible_cpu_arch_ids(ms); 855 856 assert(cpu_index < possible_cpus->len); 857 return possible_cpus->cpus[cpu_index].props; 858 } 859 860 static int64_t 861 sbsa_ref_get_default_cpu_node_id(const MachineState *ms, int idx) 862 { 863 return idx % ms->numa_state->num_nodes; 864 } 865 866 static void sbsa_ref_instance_init(Object *obj) 867 { 868 SBSAMachineState *sms = SBSA_MACHINE(obj); 869 870 sbsa_flash_create(sms); 871 } 872 873 static void sbsa_ref_class_init(ObjectClass *oc, void *data) 874 { 875 MachineClass *mc = MACHINE_CLASS(oc); 876 static const char * const valid_cpu_types[] = { 877 ARM_CPU_TYPE_NAME("cortex-a57"), 878 ARM_CPU_TYPE_NAME("cortex-a72"), 879 ARM_CPU_TYPE_NAME("neoverse-n1"), 880 ARM_CPU_TYPE_NAME("neoverse-v1"), 881 ARM_CPU_TYPE_NAME("neoverse-n2"), 882 ARM_CPU_TYPE_NAME("max"), 883 NULL, 884 }; 885 886 mc->init = sbsa_ref_init; 887 mc->desc = "QEMU 'SBSA Reference' ARM Virtual Machine"; 888 mc->default_cpu_type = ARM_CPU_TYPE_NAME("neoverse-n1"); 889 mc->valid_cpu_types = valid_cpu_types; 890 mc->max_cpus = 512; 891 mc->pci_allow_0_address = true; 892 mc->minimum_page_bits = 12; 893 mc->block_default_type = IF_IDE; 894 mc->no_cdrom = 1; 895 mc->default_nic = "e1000e"; 896 mc->default_ram_size = 1 * GiB; 897 mc->default_ram_id = "sbsa-ref.ram"; 898 mc->default_cpus = 4; 899 mc->possible_cpu_arch_ids = sbsa_ref_possible_cpu_arch_ids; 900 mc->cpu_index_to_instance_props = sbsa_ref_cpu_index_to_props; 901 mc->get_default_cpu_node_id = sbsa_ref_get_default_cpu_node_id; 902 /* platform instead of architectural choice */ 903 mc->cpu_cluster_has_numa_boundary = true; 904 } 905 906 static const TypeInfo sbsa_ref_info = { 907 .name = TYPE_SBSA_MACHINE, 908 .parent = TYPE_MACHINE, 909 .instance_init = sbsa_ref_instance_init, 910 .class_init = sbsa_ref_class_init, 911 .instance_size = sizeof(SBSAMachineState), 912 }; 913 914 static void sbsa_ref_machine_init(void) 915 { 916 type_register_static(&sbsa_ref_info); 917 } 918 919 type_init(sbsa_ref_machine_init); 920