1 /* 2 * ARM SBSA Reference Platform emulation 3 * 4 * Copyright (c) 2018 Linaro Limited 5 * Copyright (c) 2023 Qualcomm Innovation Center, Inc. All rights reserved. 6 * Written by Hongbo Zhang <hongbo.zhang@linaro.org> 7 * 8 * This program is free software; you can redistribute it and/or modify it 9 * under the terms and conditions of the GNU General Public License, 10 * version 2 or later, as published by the Free Software Foundation. 11 * 12 * This program is distributed in the hope it will be useful, but WITHOUT 13 * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or 14 * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for 15 * more details. 16 * 17 * You should have received a copy of the GNU General Public License along with 18 * this program. If not, see <http://www.gnu.org/licenses/>. 19 */ 20 21 #include "qemu/osdep.h" 22 #include "qemu/datadir.h" 23 #include "qapi/error.h" 24 #include "qemu/error-report.h" 25 #include "qemu/units.h" 26 #include "sysemu/device_tree.h" 27 #include "sysemu/kvm.h" 28 #include "sysemu/numa.h" 29 #include "sysemu/runstate.h" 30 #include "sysemu/sysemu.h" 31 #include "exec/hwaddr.h" 32 #include "kvm_arm.h" 33 #include "hw/arm/boot.h" 34 #include "hw/arm/bsa.h" 35 #include "hw/arm/fdt.h" 36 #include "hw/arm/smmuv3.h" 37 #include "hw/block/flash.h" 38 #include "hw/boards.h" 39 #include "hw/ide/internal.h" 40 #include "hw/ide/ahci_internal.h" 41 #include "hw/intc/arm_gicv3_common.h" 42 #include "hw/intc/arm_gicv3_its_common.h" 43 #include "hw/loader.h" 44 #include "hw/pci-host/gpex.h" 45 #include "hw/qdev-properties.h" 46 #include "hw/usb.h" 47 #include "hw/usb/xhci.h" 48 #include "hw/char/pl011.h" 49 #include "hw/watchdog/sbsa_gwdt.h" 50 #include "net/net.h" 51 #include "qom/object.h" 52 53 #define RAMLIMIT_GB 8192 54 #define RAMLIMIT_BYTES (RAMLIMIT_GB * GiB) 55 56 #define NUM_IRQS 256 57 #define NUM_SMMU_IRQS 4 58 #define NUM_SATA_PORTS 6 59 60 enum { 61 SBSA_FLASH, 62 SBSA_MEM, 63 SBSA_CPUPERIPHS, 64 SBSA_GIC_DIST, 65 SBSA_GIC_REDIST, 66 SBSA_GIC_ITS, 67 SBSA_SECURE_EC, 68 SBSA_GWDT_WS0, 69 SBSA_GWDT_REFRESH, 70 SBSA_GWDT_CONTROL, 71 SBSA_SMMU, 72 SBSA_UART, 73 SBSA_RTC, 74 SBSA_PCIE, 75 SBSA_PCIE_MMIO, 76 SBSA_PCIE_MMIO_HIGH, 77 SBSA_PCIE_PIO, 78 SBSA_PCIE_ECAM, 79 SBSA_GPIO, 80 SBSA_SECURE_UART, 81 SBSA_SECURE_UART_MM, 82 SBSA_SECURE_MEM, 83 SBSA_AHCI, 84 SBSA_XHCI, 85 }; 86 87 struct SBSAMachineState { 88 MachineState parent; 89 struct arm_boot_info bootinfo; 90 int smp_cpus; 91 void *fdt; 92 int fdt_size; 93 int psci_conduit; 94 DeviceState *gic; 95 PFlashCFI01 *flash[2]; 96 }; 97 98 #define TYPE_SBSA_MACHINE MACHINE_TYPE_NAME("sbsa-ref") 99 OBJECT_DECLARE_SIMPLE_TYPE(SBSAMachineState, SBSA_MACHINE) 100 101 static const MemMapEntry sbsa_ref_memmap[] = { 102 /* 512M boot ROM */ 103 [SBSA_FLASH] = { 0, 0x20000000 }, 104 /* 512M secure memory */ 105 [SBSA_SECURE_MEM] = { 0x20000000, 0x20000000 }, 106 /* Space reserved for CPU peripheral devices */ 107 [SBSA_CPUPERIPHS] = { 0x40000000, 0x00040000 }, 108 [SBSA_GIC_DIST] = { 0x40060000, 0x00010000 }, 109 [SBSA_GIC_REDIST] = { 0x40080000, 0x04000000 }, 110 [SBSA_GIC_ITS] = { 0x44081000, 0x00020000 }, 111 [SBSA_SECURE_EC] = { 0x50000000, 0x00001000 }, 112 [SBSA_GWDT_REFRESH] = { 0x50010000, 0x00001000 }, 113 [SBSA_GWDT_CONTROL] = { 0x50011000, 0x00001000 }, 114 [SBSA_UART] = { 0x60000000, 0x00001000 }, 115 [SBSA_RTC] = { 0x60010000, 0x00001000 }, 116 [SBSA_GPIO] = { 0x60020000, 0x00001000 }, 117 [SBSA_SECURE_UART] = { 0x60030000, 0x00001000 }, 118 [SBSA_SECURE_UART_MM] = { 0x60040000, 0x00001000 }, 119 [SBSA_SMMU] = { 0x60050000, 0x00020000 }, 120 /* Space here reserved for more SMMUs */ 121 [SBSA_AHCI] = { 0x60100000, 0x00010000 }, 122 [SBSA_XHCI] = { 0x60110000, 0x00010000 }, 123 /* Space here reserved for other devices */ 124 [SBSA_PCIE_PIO] = { 0x7fff0000, 0x00010000 }, 125 /* 32-bit address PCIE MMIO space */ 126 [SBSA_PCIE_MMIO] = { 0x80000000, 0x70000000 }, 127 /* 256M PCIE ECAM space */ 128 [SBSA_PCIE_ECAM] = { 0xf0000000, 0x10000000 }, 129 /* ~1TB PCIE MMIO space (4GB to 1024GB boundary) */ 130 [SBSA_PCIE_MMIO_HIGH] = { 0x100000000ULL, 0xFF00000000ULL }, 131 [SBSA_MEM] = { 0x10000000000ULL, RAMLIMIT_BYTES }, 132 }; 133 134 static const int sbsa_ref_irqmap[] = { 135 [SBSA_UART] = 1, 136 [SBSA_RTC] = 2, 137 [SBSA_PCIE] = 3, /* ... to 6 */ 138 [SBSA_GPIO] = 7, 139 [SBSA_SECURE_UART] = 8, 140 [SBSA_SECURE_UART_MM] = 9, 141 [SBSA_AHCI] = 10, 142 [SBSA_XHCI] = 11, 143 [SBSA_SMMU] = 12, /* ... to 15 */ 144 [SBSA_GWDT_WS0] = 16, 145 }; 146 147 static const char * const valid_cpus[] = { 148 ARM_CPU_TYPE_NAME("cortex-a57"), 149 ARM_CPU_TYPE_NAME("cortex-a72"), 150 ARM_CPU_TYPE_NAME("neoverse-n1"), 151 ARM_CPU_TYPE_NAME("neoverse-v1"), 152 ARM_CPU_TYPE_NAME("max"), 153 }; 154 155 static bool cpu_type_valid(const char *cpu) 156 { 157 int i; 158 159 for (i = 0; i < ARRAY_SIZE(valid_cpus); i++) { 160 if (strcmp(cpu, valid_cpus[i]) == 0) { 161 return true; 162 } 163 } 164 return false; 165 } 166 167 static uint64_t sbsa_ref_cpu_mp_affinity(SBSAMachineState *sms, int idx) 168 { 169 uint8_t clustersz = ARM_DEFAULT_CPUS_PER_CLUSTER; 170 return arm_cpu_mp_affinity(idx, clustersz); 171 } 172 173 static void sbsa_fdt_add_gic_node(SBSAMachineState *sms) 174 { 175 char *nodename; 176 177 nodename = g_strdup_printf("/intc"); 178 qemu_fdt_add_subnode(sms->fdt, nodename); 179 qemu_fdt_setprop_sized_cells(sms->fdt, nodename, "reg", 180 2, sbsa_ref_memmap[SBSA_GIC_DIST].base, 181 2, sbsa_ref_memmap[SBSA_GIC_DIST].size, 182 2, sbsa_ref_memmap[SBSA_GIC_REDIST].base, 183 2, sbsa_ref_memmap[SBSA_GIC_REDIST].size); 184 185 nodename = g_strdup_printf("/intc/its"); 186 qemu_fdt_add_subnode(sms->fdt, nodename); 187 qemu_fdt_setprop_sized_cells(sms->fdt, nodename, "reg", 188 2, sbsa_ref_memmap[SBSA_GIC_ITS].base, 189 2, sbsa_ref_memmap[SBSA_GIC_ITS].size); 190 191 g_free(nodename); 192 } 193 194 /* 195 * Firmware on this machine only uses ACPI table to load OS, these limited 196 * device tree nodes are just to let firmware know the info which varies from 197 * command line parameters, so it is not necessary to be fully compatible 198 * with the kernel CPU and NUMA binding rules. 199 */ 200 static void create_fdt(SBSAMachineState *sms) 201 { 202 void *fdt = create_device_tree(&sms->fdt_size); 203 const MachineState *ms = MACHINE(sms); 204 int nb_numa_nodes = ms->numa_state->num_nodes; 205 int cpu; 206 207 if (!fdt) { 208 error_report("create_device_tree() failed"); 209 exit(1); 210 } 211 212 sms->fdt = fdt; 213 214 qemu_fdt_setprop_string(fdt, "/", "compatible", "linux,sbsa-ref"); 215 qemu_fdt_setprop_cell(fdt, "/", "#address-cells", 0x2); 216 qemu_fdt_setprop_cell(fdt, "/", "#size-cells", 0x2); 217 218 /* 219 * This versioning scheme is for informing platform fw only. It is neither: 220 * - A QEMU versioned machine type; a given version of QEMU will emulate 221 * a given version of the platform. 222 * - A reflection of level of SBSA (now SystemReady SR) support provided. 223 * 224 * machine-version-major: updated when changes breaking fw compatibility 225 * are introduced. 226 * machine-version-minor: updated when features are added that don't break 227 * fw compatibility. 228 */ 229 qemu_fdt_setprop_cell(fdt, "/", "machine-version-major", 0); 230 qemu_fdt_setprop_cell(fdt, "/", "machine-version-minor", 3); 231 232 if (ms->numa_state->have_numa_distance) { 233 int size = nb_numa_nodes * nb_numa_nodes * 3 * sizeof(uint32_t); 234 uint32_t *matrix = g_malloc0(size); 235 int idx, i, j; 236 237 for (i = 0; i < nb_numa_nodes; i++) { 238 for (j = 0; j < nb_numa_nodes; j++) { 239 idx = (i * nb_numa_nodes + j) * 3; 240 matrix[idx + 0] = cpu_to_be32(i); 241 matrix[idx + 1] = cpu_to_be32(j); 242 matrix[idx + 2] = 243 cpu_to_be32(ms->numa_state->nodes[i].distance[j]); 244 } 245 } 246 247 qemu_fdt_add_subnode(fdt, "/distance-map"); 248 qemu_fdt_setprop(fdt, "/distance-map", "distance-matrix", 249 matrix, size); 250 g_free(matrix); 251 } 252 253 /* 254 * From Documentation/devicetree/bindings/arm/cpus.yaml 255 * On ARM v8 64-bit systems this property is required 256 * and matches the MPIDR_EL1 register affinity bits. 257 * 258 * * If cpus node's #address-cells property is set to 2 259 * 260 * The first reg cell bits [7:0] must be set to 261 * bits [39:32] of MPIDR_EL1. 262 * 263 * The second reg cell bits [23:0] must be set to 264 * bits [23:0] of MPIDR_EL1. 265 */ 266 qemu_fdt_add_subnode(sms->fdt, "/cpus"); 267 qemu_fdt_setprop_cell(sms->fdt, "/cpus", "#address-cells", 2); 268 qemu_fdt_setprop_cell(sms->fdt, "/cpus", "#size-cells", 0x0); 269 270 for (cpu = sms->smp_cpus - 1; cpu >= 0; cpu--) { 271 char *nodename = g_strdup_printf("/cpus/cpu@%d", cpu); 272 ARMCPU *armcpu = ARM_CPU(qemu_get_cpu(cpu)); 273 CPUState *cs = CPU(armcpu); 274 uint64_t mpidr = sbsa_ref_cpu_mp_affinity(sms, cpu); 275 276 qemu_fdt_add_subnode(sms->fdt, nodename); 277 qemu_fdt_setprop_u64(sms->fdt, nodename, "reg", mpidr); 278 279 if (ms->possible_cpus->cpus[cs->cpu_index].props.has_node_id) { 280 qemu_fdt_setprop_cell(sms->fdt, nodename, "numa-node-id", 281 ms->possible_cpus->cpus[cs->cpu_index].props.node_id); 282 } 283 284 g_free(nodename); 285 } 286 287 sbsa_fdt_add_gic_node(sms); 288 } 289 290 #define SBSA_FLASH_SECTOR_SIZE (256 * KiB) 291 292 static PFlashCFI01 *sbsa_flash_create1(SBSAMachineState *sms, 293 const char *name, 294 const char *alias_prop_name) 295 { 296 /* 297 * Create a single flash device. We use the same parameters as 298 * the flash devices on the Versatile Express board. 299 */ 300 DeviceState *dev = qdev_new(TYPE_PFLASH_CFI01); 301 302 qdev_prop_set_uint64(dev, "sector-length", SBSA_FLASH_SECTOR_SIZE); 303 qdev_prop_set_uint8(dev, "width", 4); 304 qdev_prop_set_uint8(dev, "device-width", 2); 305 qdev_prop_set_bit(dev, "big-endian", false); 306 qdev_prop_set_uint16(dev, "id0", 0x89); 307 qdev_prop_set_uint16(dev, "id1", 0x18); 308 qdev_prop_set_uint16(dev, "id2", 0x00); 309 qdev_prop_set_uint16(dev, "id3", 0x00); 310 qdev_prop_set_string(dev, "name", name); 311 object_property_add_child(OBJECT(sms), name, OBJECT(dev)); 312 object_property_add_alias(OBJECT(sms), alias_prop_name, 313 OBJECT(dev), "drive"); 314 return PFLASH_CFI01(dev); 315 } 316 317 static void sbsa_flash_create(SBSAMachineState *sms) 318 { 319 sms->flash[0] = sbsa_flash_create1(sms, "sbsa.flash0", "pflash0"); 320 sms->flash[1] = sbsa_flash_create1(sms, "sbsa.flash1", "pflash1"); 321 } 322 323 static void sbsa_flash_map1(PFlashCFI01 *flash, 324 hwaddr base, hwaddr size, 325 MemoryRegion *sysmem) 326 { 327 DeviceState *dev = DEVICE(flash); 328 329 assert(QEMU_IS_ALIGNED(size, SBSA_FLASH_SECTOR_SIZE)); 330 assert(size / SBSA_FLASH_SECTOR_SIZE <= UINT32_MAX); 331 qdev_prop_set_uint32(dev, "num-blocks", size / SBSA_FLASH_SECTOR_SIZE); 332 sysbus_realize_and_unref(SYS_BUS_DEVICE(dev), &error_fatal); 333 334 memory_region_add_subregion(sysmem, base, 335 sysbus_mmio_get_region(SYS_BUS_DEVICE(dev), 336 0)); 337 } 338 339 static void sbsa_flash_map(SBSAMachineState *sms, 340 MemoryRegion *sysmem, 341 MemoryRegion *secure_sysmem) 342 { 343 /* 344 * Map two flash devices to fill the SBSA_FLASH space in the memmap. 345 * sysmem is the system memory space. secure_sysmem is the secure view 346 * of the system, and the first flash device should be made visible only 347 * there. The second flash device is visible to both secure and nonsecure. 348 */ 349 hwaddr flashsize = sbsa_ref_memmap[SBSA_FLASH].size / 2; 350 hwaddr flashbase = sbsa_ref_memmap[SBSA_FLASH].base; 351 352 sbsa_flash_map1(sms->flash[0], flashbase, flashsize, 353 secure_sysmem); 354 sbsa_flash_map1(sms->flash[1], flashbase + flashsize, flashsize, 355 sysmem); 356 } 357 358 static bool sbsa_firmware_init(SBSAMachineState *sms, 359 MemoryRegion *sysmem, 360 MemoryRegion *secure_sysmem) 361 { 362 const char *bios_name; 363 int i; 364 BlockBackend *pflash_blk0; 365 366 /* Map legacy -drive if=pflash to machine properties */ 367 for (i = 0; i < ARRAY_SIZE(sms->flash); i++) { 368 pflash_cfi01_legacy_drive(sms->flash[i], 369 drive_get(IF_PFLASH, 0, i)); 370 } 371 372 sbsa_flash_map(sms, sysmem, secure_sysmem); 373 374 pflash_blk0 = pflash_cfi01_get_blk(sms->flash[0]); 375 376 bios_name = MACHINE(sms)->firmware; 377 if (bios_name) { 378 char *fname; 379 MemoryRegion *mr; 380 int image_size; 381 382 if (pflash_blk0) { 383 error_report("The contents of the first flash device may be " 384 "specified with -bios or with -drive if=pflash... " 385 "but you cannot use both options at once"); 386 exit(1); 387 } 388 389 /* Fall back to -bios */ 390 391 fname = qemu_find_file(QEMU_FILE_TYPE_BIOS, bios_name); 392 if (!fname) { 393 error_report("Could not find ROM image '%s'", bios_name); 394 exit(1); 395 } 396 mr = sysbus_mmio_get_region(SYS_BUS_DEVICE(sms->flash[0]), 0); 397 image_size = load_image_mr(fname, mr); 398 g_free(fname); 399 if (image_size < 0) { 400 error_report("Could not load ROM image '%s'", bios_name); 401 exit(1); 402 } 403 } 404 405 return pflash_blk0 || bios_name; 406 } 407 408 static void create_secure_ram(SBSAMachineState *sms, 409 MemoryRegion *secure_sysmem) 410 { 411 MemoryRegion *secram = g_new(MemoryRegion, 1); 412 hwaddr base = sbsa_ref_memmap[SBSA_SECURE_MEM].base; 413 hwaddr size = sbsa_ref_memmap[SBSA_SECURE_MEM].size; 414 415 memory_region_init_ram(secram, NULL, "sbsa-ref.secure-ram", size, 416 &error_fatal); 417 memory_region_add_subregion(secure_sysmem, base, secram); 418 } 419 420 static void create_its(SBSAMachineState *sms) 421 { 422 const char *itsclass = its_class_name(); 423 DeviceState *dev; 424 425 dev = qdev_new(itsclass); 426 427 object_property_set_link(OBJECT(dev), "parent-gicv3", OBJECT(sms->gic), 428 &error_abort); 429 sysbus_realize_and_unref(SYS_BUS_DEVICE(dev), &error_fatal); 430 sysbus_mmio_map(SYS_BUS_DEVICE(dev), 0, sbsa_ref_memmap[SBSA_GIC_ITS].base); 431 } 432 433 static void create_gic(SBSAMachineState *sms, MemoryRegion *mem) 434 { 435 unsigned int smp_cpus = MACHINE(sms)->smp.cpus; 436 SysBusDevice *gicbusdev; 437 const char *gictype; 438 uint32_t redist0_capacity, redist0_count; 439 int i; 440 441 gictype = gicv3_class_name(); 442 443 sms->gic = qdev_new(gictype); 444 qdev_prop_set_uint32(sms->gic, "revision", 3); 445 qdev_prop_set_uint32(sms->gic, "num-cpu", smp_cpus); 446 /* 447 * Note that the num-irq property counts both internal and external 448 * interrupts; there are always 32 of the former (mandated by GIC spec). 449 */ 450 qdev_prop_set_uint32(sms->gic, "num-irq", NUM_IRQS + 32); 451 qdev_prop_set_bit(sms->gic, "has-security-extensions", true); 452 453 redist0_capacity = 454 sbsa_ref_memmap[SBSA_GIC_REDIST].size / GICV3_REDIST_SIZE; 455 redist0_count = MIN(smp_cpus, redist0_capacity); 456 457 qdev_prop_set_uint32(sms->gic, "len-redist-region-count", 1); 458 qdev_prop_set_uint32(sms->gic, "redist-region-count[0]", redist0_count); 459 460 object_property_set_link(OBJECT(sms->gic), "sysmem", 461 OBJECT(mem), &error_fatal); 462 qdev_prop_set_bit(sms->gic, "has-lpi", true); 463 464 gicbusdev = SYS_BUS_DEVICE(sms->gic); 465 sysbus_realize_and_unref(gicbusdev, &error_fatal); 466 sysbus_mmio_map(gicbusdev, 0, sbsa_ref_memmap[SBSA_GIC_DIST].base); 467 sysbus_mmio_map(gicbusdev, 1, sbsa_ref_memmap[SBSA_GIC_REDIST].base); 468 469 /* 470 * Wire the outputs from each CPU's generic timer and the GICv3 471 * maintenance interrupt signal to the appropriate GIC PPI inputs, 472 * and the GIC's IRQ/FIQ/VIRQ/VFIQ interrupt outputs to the CPU's inputs. 473 */ 474 for (i = 0; i < smp_cpus; i++) { 475 DeviceState *cpudev = DEVICE(qemu_get_cpu(i)); 476 int intidbase = NUM_IRQS + i * GIC_INTERNAL; 477 int irq; 478 /* 479 * Mapping from the output timer irq lines from the CPU to the 480 * GIC PPI inputs used for this board. 481 */ 482 const int timer_irq[] = { 483 [GTIMER_PHYS] = ARCH_TIMER_NS_EL1_IRQ, 484 [GTIMER_VIRT] = ARCH_TIMER_VIRT_IRQ, 485 [GTIMER_HYP] = ARCH_TIMER_NS_EL2_IRQ, 486 [GTIMER_SEC] = ARCH_TIMER_S_EL1_IRQ, 487 [GTIMER_HYPVIRT] = ARCH_TIMER_NS_EL2_VIRT_IRQ, 488 }; 489 490 for (irq = 0; irq < ARRAY_SIZE(timer_irq); irq++) { 491 qdev_connect_gpio_out(cpudev, irq, 492 qdev_get_gpio_in(sms->gic, 493 intidbase + timer_irq[irq])); 494 } 495 496 qdev_connect_gpio_out_named(cpudev, "gicv3-maintenance-interrupt", 0, 497 qdev_get_gpio_in(sms->gic, 498 intidbase 499 + ARCH_GIC_MAINT_IRQ)); 500 501 qdev_connect_gpio_out_named(cpudev, "pmu-interrupt", 0, 502 qdev_get_gpio_in(sms->gic, 503 intidbase 504 + VIRTUAL_PMU_IRQ)); 505 506 sysbus_connect_irq(gicbusdev, i, qdev_get_gpio_in(cpudev, ARM_CPU_IRQ)); 507 sysbus_connect_irq(gicbusdev, i + smp_cpus, 508 qdev_get_gpio_in(cpudev, ARM_CPU_FIQ)); 509 sysbus_connect_irq(gicbusdev, i + 2 * smp_cpus, 510 qdev_get_gpio_in(cpudev, ARM_CPU_VIRQ)); 511 sysbus_connect_irq(gicbusdev, i + 3 * smp_cpus, 512 qdev_get_gpio_in(cpudev, ARM_CPU_VFIQ)); 513 } 514 create_its(sms); 515 } 516 517 static void create_uart(const SBSAMachineState *sms, int uart, 518 MemoryRegion *mem, Chardev *chr) 519 { 520 hwaddr base = sbsa_ref_memmap[uart].base; 521 int irq = sbsa_ref_irqmap[uart]; 522 DeviceState *dev = qdev_new(TYPE_PL011); 523 SysBusDevice *s = SYS_BUS_DEVICE(dev); 524 525 qdev_prop_set_chr(dev, "chardev", chr); 526 sysbus_realize_and_unref(SYS_BUS_DEVICE(dev), &error_fatal); 527 memory_region_add_subregion(mem, base, 528 sysbus_mmio_get_region(s, 0)); 529 sysbus_connect_irq(s, 0, qdev_get_gpio_in(sms->gic, irq)); 530 } 531 532 static void create_rtc(const SBSAMachineState *sms) 533 { 534 hwaddr base = sbsa_ref_memmap[SBSA_RTC].base; 535 int irq = sbsa_ref_irqmap[SBSA_RTC]; 536 537 sysbus_create_simple("pl031", base, qdev_get_gpio_in(sms->gic, irq)); 538 } 539 540 static void create_wdt(const SBSAMachineState *sms) 541 { 542 hwaddr rbase = sbsa_ref_memmap[SBSA_GWDT_REFRESH].base; 543 hwaddr cbase = sbsa_ref_memmap[SBSA_GWDT_CONTROL].base; 544 DeviceState *dev = qdev_new(TYPE_WDT_SBSA); 545 SysBusDevice *s = SYS_BUS_DEVICE(dev); 546 int irq = sbsa_ref_irqmap[SBSA_GWDT_WS0]; 547 548 sysbus_realize_and_unref(s, &error_fatal); 549 sysbus_mmio_map(s, 0, rbase); 550 sysbus_mmio_map(s, 1, cbase); 551 sysbus_connect_irq(s, 0, qdev_get_gpio_in(sms->gic, irq)); 552 } 553 554 static DeviceState *gpio_key_dev; 555 static void sbsa_ref_powerdown_req(Notifier *n, void *opaque) 556 { 557 /* use gpio Pin 3 for power button event */ 558 qemu_set_irq(qdev_get_gpio_in(gpio_key_dev, 0), 1); 559 } 560 561 static Notifier sbsa_ref_powerdown_notifier = { 562 .notify = sbsa_ref_powerdown_req 563 }; 564 565 static void create_gpio(const SBSAMachineState *sms) 566 { 567 DeviceState *pl061_dev; 568 hwaddr base = sbsa_ref_memmap[SBSA_GPIO].base; 569 int irq = sbsa_ref_irqmap[SBSA_GPIO]; 570 571 pl061_dev = sysbus_create_simple("pl061", base, 572 qdev_get_gpio_in(sms->gic, irq)); 573 574 gpio_key_dev = sysbus_create_simple("gpio-key", -1, 575 qdev_get_gpio_in(pl061_dev, 3)); 576 577 /* connect powerdown request */ 578 qemu_register_powerdown_notifier(&sbsa_ref_powerdown_notifier); 579 } 580 581 static void create_ahci(const SBSAMachineState *sms) 582 { 583 hwaddr base = sbsa_ref_memmap[SBSA_AHCI].base; 584 int irq = sbsa_ref_irqmap[SBSA_AHCI]; 585 DeviceState *dev; 586 DriveInfo *hd[NUM_SATA_PORTS]; 587 SysbusAHCIState *sysahci; 588 AHCIState *ahci; 589 int i; 590 591 dev = qdev_new("sysbus-ahci"); 592 qdev_prop_set_uint32(dev, "num-ports", NUM_SATA_PORTS); 593 sysbus_realize_and_unref(SYS_BUS_DEVICE(dev), &error_fatal); 594 sysbus_mmio_map(SYS_BUS_DEVICE(dev), 0, base); 595 sysbus_connect_irq(SYS_BUS_DEVICE(dev), 0, qdev_get_gpio_in(sms->gic, irq)); 596 597 sysahci = SYSBUS_AHCI(dev); 598 ahci = &sysahci->ahci; 599 ide_drive_get(hd, ARRAY_SIZE(hd)); 600 for (i = 0; i < ahci->ports; i++) { 601 if (hd[i] == NULL) { 602 continue; 603 } 604 ide_bus_create_drive(&ahci->dev[i].port, 0, hd[i]); 605 } 606 } 607 608 static void create_xhci(const SBSAMachineState *sms) 609 { 610 hwaddr base = sbsa_ref_memmap[SBSA_XHCI].base; 611 int irq = sbsa_ref_irqmap[SBSA_XHCI]; 612 DeviceState *dev = qdev_new(TYPE_XHCI_SYSBUS); 613 qdev_prop_set_uint32(dev, "slots", XHCI_MAXSLOTS); 614 615 sysbus_realize_and_unref(SYS_BUS_DEVICE(dev), &error_fatal); 616 sysbus_mmio_map(SYS_BUS_DEVICE(dev), 0, base); 617 sysbus_connect_irq(SYS_BUS_DEVICE(dev), 0, qdev_get_gpio_in(sms->gic, irq)); 618 } 619 620 static void create_smmu(const SBSAMachineState *sms, PCIBus *bus) 621 { 622 hwaddr base = sbsa_ref_memmap[SBSA_SMMU].base; 623 int irq = sbsa_ref_irqmap[SBSA_SMMU]; 624 DeviceState *dev; 625 int i; 626 627 dev = qdev_new(TYPE_ARM_SMMUV3); 628 629 object_property_set_link(OBJECT(dev), "primary-bus", OBJECT(bus), 630 &error_abort); 631 sysbus_realize_and_unref(SYS_BUS_DEVICE(dev), &error_fatal); 632 sysbus_mmio_map(SYS_BUS_DEVICE(dev), 0, base); 633 for (i = 0; i < NUM_SMMU_IRQS; i++) { 634 sysbus_connect_irq(SYS_BUS_DEVICE(dev), i, 635 qdev_get_gpio_in(sms->gic, irq + i)); 636 } 637 } 638 639 static void create_pcie(SBSAMachineState *sms) 640 { 641 hwaddr base_ecam = sbsa_ref_memmap[SBSA_PCIE_ECAM].base; 642 hwaddr size_ecam = sbsa_ref_memmap[SBSA_PCIE_ECAM].size; 643 hwaddr base_mmio = sbsa_ref_memmap[SBSA_PCIE_MMIO].base; 644 hwaddr size_mmio = sbsa_ref_memmap[SBSA_PCIE_MMIO].size; 645 hwaddr base_mmio_high = sbsa_ref_memmap[SBSA_PCIE_MMIO_HIGH].base; 646 hwaddr size_mmio_high = sbsa_ref_memmap[SBSA_PCIE_MMIO_HIGH].size; 647 hwaddr base_pio = sbsa_ref_memmap[SBSA_PCIE_PIO].base; 648 int irq = sbsa_ref_irqmap[SBSA_PCIE]; 649 MachineClass *mc = MACHINE_GET_CLASS(sms); 650 MemoryRegion *mmio_alias, *mmio_alias_high, *mmio_reg; 651 MemoryRegion *ecam_alias, *ecam_reg; 652 DeviceState *dev; 653 PCIHostState *pci; 654 int i; 655 656 dev = qdev_new(TYPE_GPEX_HOST); 657 sysbus_realize_and_unref(SYS_BUS_DEVICE(dev), &error_fatal); 658 659 /* Map ECAM space */ 660 ecam_alias = g_new0(MemoryRegion, 1); 661 ecam_reg = sysbus_mmio_get_region(SYS_BUS_DEVICE(dev), 0); 662 memory_region_init_alias(ecam_alias, OBJECT(dev), "pcie-ecam", 663 ecam_reg, 0, size_ecam); 664 memory_region_add_subregion(get_system_memory(), base_ecam, ecam_alias); 665 666 /* Map the MMIO space */ 667 mmio_alias = g_new0(MemoryRegion, 1); 668 mmio_reg = sysbus_mmio_get_region(SYS_BUS_DEVICE(dev), 1); 669 memory_region_init_alias(mmio_alias, OBJECT(dev), "pcie-mmio", 670 mmio_reg, base_mmio, size_mmio); 671 memory_region_add_subregion(get_system_memory(), base_mmio, mmio_alias); 672 673 /* Map the MMIO_HIGH space */ 674 mmio_alias_high = g_new0(MemoryRegion, 1); 675 memory_region_init_alias(mmio_alias_high, OBJECT(dev), "pcie-mmio-high", 676 mmio_reg, base_mmio_high, size_mmio_high); 677 memory_region_add_subregion(get_system_memory(), base_mmio_high, 678 mmio_alias_high); 679 680 /* Map IO port space */ 681 sysbus_mmio_map(SYS_BUS_DEVICE(dev), 2, base_pio); 682 683 for (i = 0; i < GPEX_NUM_IRQS; i++) { 684 sysbus_connect_irq(SYS_BUS_DEVICE(dev), i, 685 qdev_get_gpio_in(sms->gic, irq + i)); 686 gpex_set_irq_num(GPEX_HOST(dev), i, irq + i); 687 } 688 689 pci = PCI_HOST_BRIDGE(dev); 690 if (pci->bus) { 691 for (i = 0; i < nb_nics; i++) { 692 pci_nic_init_nofail(&nd_table[i], pci->bus, mc->default_nic, NULL); 693 } 694 } 695 696 pci_create_simple(pci->bus, -1, "bochs-display"); 697 698 create_smmu(sms, pci->bus); 699 } 700 701 static void *sbsa_ref_dtb(const struct arm_boot_info *binfo, int *fdt_size) 702 { 703 const SBSAMachineState *board = container_of(binfo, SBSAMachineState, 704 bootinfo); 705 706 *fdt_size = board->fdt_size; 707 return board->fdt; 708 } 709 710 static void create_secure_ec(MemoryRegion *mem) 711 { 712 hwaddr base = sbsa_ref_memmap[SBSA_SECURE_EC].base; 713 DeviceState *dev = qdev_new("sbsa-ec"); 714 SysBusDevice *s = SYS_BUS_DEVICE(dev); 715 716 memory_region_add_subregion(mem, base, 717 sysbus_mmio_get_region(s, 0)); 718 } 719 720 static void sbsa_ref_init(MachineState *machine) 721 { 722 unsigned int smp_cpus = machine->smp.cpus; 723 unsigned int max_cpus = machine->smp.max_cpus; 724 SBSAMachineState *sms = SBSA_MACHINE(machine); 725 MachineClass *mc = MACHINE_GET_CLASS(machine); 726 MemoryRegion *sysmem = get_system_memory(); 727 MemoryRegion *secure_sysmem = g_new(MemoryRegion, 1); 728 bool firmware_loaded; 729 const CPUArchIdList *possible_cpus; 730 int n, sbsa_max_cpus; 731 732 if (!cpu_type_valid(machine->cpu_type)) { 733 error_report("sbsa-ref: CPU type %s not supported", machine->cpu_type); 734 exit(1); 735 } 736 737 if (kvm_enabled()) { 738 error_report("sbsa-ref: KVM is not supported for this machine"); 739 exit(1); 740 } 741 742 /* 743 * The Secure view of the world is the same as the NonSecure, 744 * but with a few extra devices. Create it as a container region 745 * containing the system memory at low priority; any secure-only 746 * devices go in at higher priority and take precedence. 747 */ 748 memory_region_init(secure_sysmem, OBJECT(machine), "secure-memory", 749 UINT64_MAX); 750 memory_region_add_subregion_overlap(secure_sysmem, 0, sysmem, -1); 751 752 firmware_loaded = sbsa_firmware_init(sms, sysmem, secure_sysmem); 753 754 /* 755 * This machine has EL3 enabled, external firmware should supply PSCI 756 * implementation, so the QEMU's internal PSCI is disabled. 757 */ 758 sms->psci_conduit = QEMU_PSCI_CONDUIT_DISABLED; 759 760 sbsa_max_cpus = sbsa_ref_memmap[SBSA_GIC_REDIST].size / GICV3_REDIST_SIZE; 761 762 if (max_cpus > sbsa_max_cpus) { 763 error_report("Number of SMP CPUs requested (%d) exceeds max CPUs " 764 "supported by machine 'sbsa-ref' (%d)", 765 max_cpus, sbsa_max_cpus); 766 exit(1); 767 } 768 769 sms->smp_cpus = smp_cpus; 770 771 if (machine->ram_size > sbsa_ref_memmap[SBSA_MEM].size) { 772 error_report("sbsa-ref: cannot model more than %dGB RAM", RAMLIMIT_GB); 773 exit(1); 774 } 775 776 possible_cpus = mc->possible_cpu_arch_ids(machine); 777 for (n = 0; n < possible_cpus->len; n++) { 778 Object *cpuobj; 779 CPUState *cs; 780 781 if (n >= smp_cpus) { 782 break; 783 } 784 785 cpuobj = object_new(possible_cpus->cpus[n].type); 786 object_property_set_int(cpuobj, "mp-affinity", 787 possible_cpus->cpus[n].arch_id, NULL); 788 789 cs = CPU(cpuobj); 790 cs->cpu_index = n; 791 792 numa_cpu_pre_plug(&possible_cpus->cpus[cs->cpu_index], DEVICE(cpuobj), 793 &error_fatal); 794 795 if (object_property_find(cpuobj, "reset-cbar")) { 796 object_property_set_int(cpuobj, "reset-cbar", 797 sbsa_ref_memmap[SBSA_CPUPERIPHS].base, 798 &error_abort); 799 } 800 801 object_property_set_link(cpuobj, "memory", OBJECT(sysmem), 802 &error_abort); 803 804 object_property_set_link(cpuobj, "secure-memory", 805 OBJECT(secure_sysmem), &error_abort); 806 807 qdev_realize(DEVICE(cpuobj), NULL, &error_fatal); 808 object_unref(cpuobj); 809 } 810 811 memory_region_add_subregion(sysmem, sbsa_ref_memmap[SBSA_MEM].base, 812 machine->ram); 813 814 create_fdt(sms); 815 816 create_secure_ram(sms, secure_sysmem); 817 818 create_gic(sms, sysmem); 819 820 create_uart(sms, SBSA_UART, sysmem, serial_hd(0)); 821 create_uart(sms, SBSA_SECURE_UART, secure_sysmem, serial_hd(1)); 822 /* Second secure UART for RAS and MM from EL0 */ 823 create_uart(sms, SBSA_SECURE_UART_MM, secure_sysmem, serial_hd(2)); 824 825 create_rtc(sms); 826 827 create_wdt(sms); 828 829 create_gpio(sms); 830 831 create_ahci(sms); 832 833 create_xhci(sms); 834 835 create_pcie(sms); 836 837 create_secure_ec(secure_sysmem); 838 839 sms->bootinfo.ram_size = machine->ram_size; 840 sms->bootinfo.board_id = -1; 841 sms->bootinfo.loader_start = sbsa_ref_memmap[SBSA_MEM].base; 842 sms->bootinfo.get_dtb = sbsa_ref_dtb; 843 sms->bootinfo.firmware_loaded = firmware_loaded; 844 arm_load_kernel(ARM_CPU(first_cpu), machine, &sms->bootinfo); 845 } 846 847 static const CPUArchIdList *sbsa_ref_possible_cpu_arch_ids(MachineState *ms) 848 { 849 unsigned int max_cpus = ms->smp.max_cpus; 850 SBSAMachineState *sms = SBSA_MACHINE(ms); 851 int n; 852 853 if (ms->possible_cpus) { 854 assert(ms->possible_cpus->len == max_cpus); 855 return ms->possible_cpus; 856 } 857 858 ms->possible_cpus = g_malloc0(sizeof(CPUArchIdList) + 859 sizeof(CPUArchId) * max_cpus); 860 ms->possible_cpus->len = max_cpus; 861 for (n = 0; n < ms->possible_cpus->len; n++) { 862 ms->possible_cpus->cpus[n].type = ms->cpu_type; 863 ms->possible_cpus->cpus[n].arch_id = 864 sbsa_ref_cpu_mp_affinity(sms, n); 865 ms->possible_cpus->cpus[n].props.has_thread_id = true; 866 ms->possible_cpus->cpus[n].props.thread_id = n; 867 } 868 return ms->possible_cpus; 869 } 870 871 static CpuInstanceProperties 872 sbsa_ref_cpu_index_to_props(MachineState *ms, unsigned cpu_index) 873 { 874 MachineClass *mc = MACHINE_GET_CLASS(ms); 875 const CPUArchIdList *possible_cpus = mc->possible_cpu_arch_ids(ms); 876 877 assert(cpu_index < possible_cpus->len); 878 return possible_cpus->cpus[cpu_index].props; 879 } 880 881 static int64_t 882 sbsa_ref_get_default_cpu_node_id(const MachineState *ms, int idx) 883 { 884 return idx % ms->numa_state->num_nodes; 885 } 886 887 static void sbsa_ref_instance_init(Object *obj) 888 { 889 SBSAMachineState *sms = SBSA_MACHINE(obj); 890 891 sbsa_flash_create(sms); 892 } 893 894 static void sbsa_ref_class_init(ObjectClass *oc, void *data) 895 { 896 MachineClass *mc = MACHINE_CLASS(oc); 897 898 mc->init = sbsa_ref_init; 899 mc->desc = "QEMU 'SBSA Reference' ARM Virtual Machine"; 900 mc->default_cpu_type = ARM_CPU_TYPE_NAME("neoverse-n1"); 901 mc->max_cpus = 512; 902 mc->pci_allow_0_address = true; 903 mc->minimum_page_bits = 12; 904 mc->block_default_type = IF_IDE; 905 mc->no_cdrom = 1; 906 mc->default_nic = "e1000e"; 907 mc->default_ram_size = 1 * GiB; 908 mc->default_ram_id = "sbsa-ref.ram"; 909 mc->default_cpus = 4; 910 mc->possible_cpu_arch_ids = sbsa_ref_possible_cpu_arch_ids; 911 mc->cpu_index_to_instance_props = sbsa_ref_cpu_index_to_props; 912 mc->get_default_cpu_node_id = sbsa_ref_get_default_cpu_node_id; 913 /* platform instead of architectural choice */ 914 mc->cpu_cluster_has_numa_boundary = true; 915 } 916 917 static const TypeInfo sbsa_ref_info = { 918 .name = TYPE_SBSA_MACHINE, 919 .parent = TYPE_MACHINE, 920 .instance_init = sbsa_ref_instance_init, 921 .class_init = sbsa_ref_class_init, 922 .instance_size = sizeof(SBSAMachineState), 923 }; 924 925 static void sbsa_ref_machine_init(void) 926 { 927 type_register_static(&sbsa_ref_info); 928 } 929 930 type_init(sbsa_ref_machine_init); 931