xref: /qemu/hw/arm/smmu-internal.h (revision 10be627d)
1 /*
2  * ARM SMMU support - Internal API
3  *
4  * Copyright (c) 2017 Red Hat, Inc.
5  * Copyright (C) 2014-2016 Broadcom Corporation
6  * Written by Prem Mallappa, Eric Auger
7  *
8  * This program is free software; you can redistribute it and/or modify
9  * it under the terms of the GNU General Public License version 2 as
10  * published by the Free Software Foundation.
11  *
12  * This program is distributed in the hope that it will be useful,
13  * but WITHOUT ANY WARRANTY; without even the implied warranty of
14  * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
15  * General Public License for more details.
16  *
17  * You should have received a copy of the GNU General Public License along
18  * with this program; if not, see <http://www.gnu.org/licenses/>.
19  */
20 
21 #ifndef HW_ARM_SMMU_INTERNAL_H
22 #define HW_ARM_SMMU_INTERNAL_H
23 
24 #define TBI0(tbi) ((tbi) & 0x1)
25 #define TBI1(tbi) ((tbi) & 0x2 >> 1)
26 
27 /* PTE Manipulation */
28 
29 #define ARM_LPAE_PTE_TYPE_SHIFT         0
30 #define ARM_LPAE_PTE_TYPE_MASK          0x3
31 
32 #define ARM_LPAE_PTE_TYPE_BLOCK         1
33 #define ARM_LPAE_PTE_TYPE_TABLE         3
34 
35 #define ARM_LPAE_L3_PTE_TYPE_RESERVED   1
36 #define ARM_LPAE_L3_PTE_TYPE_PAGE       3
37 
38 #define ARM_LPAE_PTE_VALID              (1 << 0)
39 
40 #define PTE_ADDRESS(pte, shift) \
41     (extract64(pte, shift, 47 - shift + 1) << shift)
42 
43 #define is_invalid_pte(pte) (!(pte & ARM_LPAE_PTE_VALID))
44 
45 #define is_reserved_pte(pte, level)                                      \
46     ((level == 3) &&                                                     \
47      ((pte & ARM_LPAE_PTE_TYPE_MASK) == ARM_LPAE_L3_PTE_TYPE_RESERVED))
48 
49 #define is_block_pte(pte, level)                                         \
50     ((level < 3) &&                                                      \
51      ((pte & ARM_LPAE_PTE_TYPE_MASK) == ARM_LPAE_PTE_TYPE_BLOCK))
52 
53 #define is_table_pte(pte, level)                                        \
54     ((level < 3) &&                                                     \
55      ((pte & ARM_LPAE_PTE_TYPE_MASK) == ARM_LPAE_PTE_TYPE_TABLE))
56 
57 #define is_page_pte(pte, level)                                         \
58     ((level == 3) &&                                                    \
59      ((pte & ARM_LPAE_PTE_TYPE_MASK) == ARM_LPAE_L3_PTE_TYPE_PAGE))
60 
61 /* access permissions */
62 
63 #define PTE_AP(pte) \
64     (extract64(pte, 6, 2))
65 
66 #define PTE_APTABLE(pte) \
67     (extract64(pte, 61, 2))
68 
69 #define PTE_AF(pte) \
70     (extract64(pte, 10, 1))
71 /*
72  * TODO: At the moment all transactions are considered as privileged (EL1)
73  * as IOMMU translation callback does not pass user/priv attributes.
74  */
75 #define is_permission_fault(ap, perm) \
76     (((perm) & IOMMU_WO) && ((ap) & 0x2))
77 
78 #define is_permission_fault_s2(s2ap, perm) \
79     (!(((s2ap) & (perm)) == (perm)))
80 
81 #define PTE_AP_TO_PERM(ap) \
82     (IOMMU_ACCESS_FLAG(true, !((ap) & 0x2)))
83 
84 /* Level Indexing */
85 
86 static inline int level_shift(int level, int granule_sz)
87 {
88     return granule_sz + (3 - level) * (granule_sz - 3);
89 }
90 
91 static inline uint64_t level_page_mask(int level, int granule_sz)
92 {
93     return ~(MAKE_64BIT_MASK(0, level_shift(level, granule_sz)));
94 }
95 
96 static inline
97 uint64_t iova_level_offset(uint64_t iova, int inputsize,
98                            int level, int gsz)
99 {
100     return ((iova & MAKE_64BIT_MASK(0, inputsize)) >> level_shift(level, gsz)) &
101             MAKE_64BIT_MASK(0, gsz - 3);
102 }
103 
104 /* FEAT_LPA2 and FEAT_TTST are not implemented. */
105 static inline int get_start_level(int sl0 , int granule_sz)
106 {
107     /* ARM DDI0487I.a: Table D8-12. */
108     if (granule_sz == 12) {
109         return 2 - sl0;
110     }
111     /* ARM DDI0487I.a: Table D8-22 and Table D8-31. */
112     return 3 - sl0;
113 }
114 
115 /*
116  * Index in a concatenated first level stage-2 page table.
117  * ARM DDI0487I.a: D8.2.2 Concatenated translation tables.
118  */
119 static inline int pgd_concat_idx(int start_level, int granule_sz,
120                                  dma_addr_t ipa)
121 {
122     uint64_t ret;
123     /*
124      * Get the number of bits handled by next levels, then any extra bits in
125      * the address should index the concatenated tables. This relation can be
126      * deduced from tables in ARM DDI0487I.a: D8.2.7-9
127      */
128     int shift =  level_shift(start_level - 1, granule_sz);
129 
130     ret = ipa >> shift;
131     return ret;
132 }
133 
134 #define SMMU_IOTLB_ASID(key) ((key).asid)
135 #define SMMU_IOTLB_VMID(key) ((key).vmid)
136 
137 typedef struct SMMUIOTLBPageInvInfo {
138     int asid;
139     int vmid;
140     uint64_t iova;
141     uint64_t mask;
142 } SMMUIOTLBPageInvInfo;
143 
144 typedef struct SMMUSIDRange {
145     uint32_t start;
146     uint32_t end;
147 } SMMUSIDRange;
148 
149 #endif
150