153018216SPaolo Bonzini /* 253018216SPaolo Bonzini * Luminary Micro Stellaris peripherals 353018216SPaolo Bonzini * 453018216SPaolo Bonzini * Copyright (c) 2006 CodeSourcery. 553018216SPaolo Bonzini * Written by Paul Brook 653018216SPaolo Bonzini * 753018216SPaolo Bonzini * This code is licensed under the GPL. 853018216SPaolo Bonzini */ 953018216SPaolo Bonzini 1012b16722SPeter Maydell #include "qemu/osdep.h" 11da34e65cSMarkus Armbruster #include "qapi/error.h" 1253018216SPaolo Bonzini #include "hw/sysbus.h" 138fd06719SAlistair Francis #include "hw/ssi/ssi.h" 14bd2be150SPeter Maydell #include "hw/arm/arm.h" 15bd2be150SPeter Maydell #include "hw/devices.h" 1653018216SPaolo Bonzini #include "qemu/timer.h" 170d09e41aSPaolo Bonzini #include "hw/i2c/i2c.h" 1853018216SPaolo Bonzini #include "net/net.h" 1953018216SPaolo Bonzini #include "hw/boards.h" 20*03dd024fSPaolo Bonzini #include "qemu/log.h" 2153018216SPaolo Bonzini #include "exec/address-spaces.h" 22d69ffb5bSMichael Davidsaver #include "sysemu/sysemu.h" 2353018216SPaolo Bonzini 2453018216SPaolo Bonzini #define GPIO_A 0 2553018216SPaolo Bonzini #define GPIO_B 1 2653018216SPaolo Bonzini #define GPIO_C 2 2753018216SPaolo Bonzini #define GPIO_D 3 2853018216SPaolo Bonzini #define GPIO_E 4 2953018216SPaolo Bonzini #define GPIO_F 5 3053018216SPaolo Bonzini #define GPIO_G 6 3153018216SPaolo Bonzini 3253018216SPaolo Bonzini #define BP_OLED_I2C 0x01 3353018216SPaolo Bonzini #define BP_OLED_SSI 0x02 3453018216SPaolo Bonzini #define BP_GAMEPAD 0x04 3553018216SPaolo Bonzini 368b47b7daSAlistair Francis #define NUM_IRQ_LINES 64 378b47b7daSAlistair Francis 3853018216SPaolo Bonzini typedef const struct { 3953018216SPaolo Bonzini const char *name; 4053018216SPaolo Bonzini uint32_t did0; 4153018216SPaolo Bonzini uint32_t did1; 4253018216SPaolo Bonzini uint32_t dc0; 4353018216SPaolo Bonzini uint32_t dc1; 4453018216SPaolo Bonzini uint32_t dc2; 4553018216SPaolo Bonzini uint32_t dc3; 4653018216SPaolo Bonzini uint32_t dc4; 4753018216SPaolo Bonzini uint32_t peripherals; 4853018216SPaolo Bonzini } stellaris_board_info; 4953018216SPaolo Bonzini 5053018216SPaolo Bonzini /* General purpose timer module. */ 5153018216SPaolo Bonzini 528ef1d394SAndreas Färber #define TYPE_STELLARIS_GPTM "stellaris-gptm" 538ef1d394SAndreas Färber #define STELLARIS_GPTM(obj) \ 548ef1d394SAndreas Färber OBJECT_CHECK(gptm_state, (obj), TYPE_STELLARIS_GPTM) 558ef1d394SAndreas Färber 5653018216SPaolo Bonzini typedef struct gptm_state { 578ef1d394SAndreas Färber SysBusDevice parent_obj; 588ef1d394SAndreas Färber 5953018216SPaolo Bonzini MemoryRegion iomem; 6053018216SPaolo Bonzini uint32_t config; 6153018216SPaolo Bonzini uint32_t mode[2]; 6253018216SPaolo Bonzini uint32_t control; 6353018216SPaolo Bonzini uint32_t state; 6453018216SPaolo Bonzini uint32_t mask; 6553018216SPaolo Bonzini uint32_t load[2]; 6653018216SPaolo Bonzini uint32_t match[2]; 6753018216SPaolo Bonzini uint32_t prescale[2]; 6853018216SPaolo Bonzini uint32_t match_prescale[2]; 6953018216SPaolo Bonzini uint32_t rtc; 7053018216SPaolo Bonzini int64_t tick[2]; 7153018216SPaolo Bonzini struct gptm_state *opaque[2]; 7253018216SPaolo Bonzini QEMUTimer *timer[2]; 7353018216SPaolo Bonzini /* The timers have an alternate output used to trigger the ADC. */ 7453018216SPaolo Bonzini qemu_irq trigger; 7553018216SPaolo Bonzini qemu_irq irq; 7653018216SPaolo Bonzini } gptm_state; 7753018216SPaolo Bonzini 7853018216SPaolo Bonzini static void gptm_update_irq(gptm_state *s) 7953018216SPaolo Bonzini { 8053018216SPaolo Bonzini int level; 8153018216SPaolo Bonzini level = (s->state & s->mask) != 0; 8253018216SPaolo Bonzini qemu_set_irq(s->irq, level); 8353018216SPaolo Bonzini } 8453018216SPaolo Bonzini 8553018216SPaolo Bonzini static void gptm_stop(gptm_state *s, int n) 8653018216SPaolo Bonzini { 87bc72ad67SAlex Bligh timer_del(s->timer[n]); 8853018216SPaolo Bonzini } 8953018216SPaolo Bonzini 9053018216SPaolo Bonzini static void gptm_reload(gptm_state *s, int n, int reset) 9153018216SPaolo Bonzini { 9253018216SPaolo Bonzini int64_t tick; 9353018216SPaolo Bonzini if (reset) 94bc72ad67SAlex Bligh tick = qemu_clock_get_ns(QEMU_CLOCK_VIRTUAL); 9553018216SPaolo Bonzini else 9653018216SPaolo Bonzini tick = s->tick[n]; 9753018216SPaolo Bonzini 9853018216SPaolo Bonzini if (s->config == 0) { 9953018216SPaolo Bonzini /* 32-bit CountDown. */ 10053018216SPaolo Bonzini uint32_t count; 10153018216SPaolo Bonzini count = s->load[0] | (s->load[1] << 16); 10253018216SPaolo Bonzini tick += (int64_t)count * system_clock_scale; 10353018216SPaolo Bonzini } else if (s->config == 1) { 10453018216SPaolo Bonzini /* 32-bit RTC. 1Hz tick. */ 10573bcb24dSRutuja Shah tick += NANOSECONDS_PER_SECOND; 10653018216SPaolo Bonzini } else if (s->mode[n] == 0xa) { 10753018216SPaolo Bonzini /* PWM mode. Not implemented. */ 10853018216SPaolo Bonzini } else { 10953018216SPaolo Bonzini hw_error("TODO: 16-bit timer mode 0x%x\n", s->mode[n]); 11053018216SPaolo Bonzini } 11153018216SPaolo Bonzini s->tick[n] = tick; 112bc72ad67SAlex Bligh timer_mod(s->timer[n], tick); 11353018216SPaolo Bonzini } 11453018216SPaolo Bonzini 11553018216SPaolo Bonzini static void gptm_tick(void *opaque) 11653018216SPaolo Bonzini { 11753018216SPaolo Bonzini gptm_state **p = (gptm_state **)opaque; 11853018216SPaolo Bonzini gptm_state *s; 11953018216SPaolo Bonzini int n; 12053018216SPaolo Bonzini 12153018216SPaolo Bonzini s = *p; 12253018216SPaolo Bonzini n = p - s->opaque; 12353018216SPaolo Bonzini if (s->config == 0) { 12453018216SPaolo Bonzini s->state |= 1; 12553018216SPaolo Bonzini if ((s->control & 0x20)) { 12653018216SPaolo Bonzini /* Output trigger. */ 12753018216SPaolo Bonzini qemu_irq_pulse(s->trigger); 12853018216SPaolo Bonzini } 12953018216SPaolo Bonzini if (s->mode[0] & 1) { 13053018216SPaolo Bonzini /* One-shot. */ 13153018216SPaolo Bonzini s->control &= ~1; 13253018216SPaolo Bonzini } else { 13353018216SPaolo Bonzini /* Periodic. */ 13453018216SPaolo Bonzini gptm_reload(s, 0, 0); 13553018216SPaolo Bonzini } 13653018216SPaolo Bonzini } else if (s->config == 1) { 13753018216SPaolo Bonzini /* RTC. */ 13853018216SPaolo Bonzini uint32_t match; 13953018216SPaolo Bonzini s->rtc++; 14053018216SPaolo Bonzini match = s->match[0] | (s->match[1] << 16); 14153018216SPaolo Bonzini if (s->rtc > match) 14253018216SPaolo Bonzini s->rtc = 0; 14353018216SPaolo Bonzini if (s->rtc == 0) { 14453018216SPaolo Bonzini s->state |= 8; 14553018216SPaolo Bonzini } 14653018216SPaolo Bonzini gptm_reload(s, 0, 0); 14753018216SPaolo Bonzini } else if (s->mode[n] == 0xa) { 14853018216SPaolo Bonzini /* PWM mode. Not implemented. */ 14953018216SPaolo Bonzini } else { 15053018216SPaolo Bonzini hw_error("TODO: 16-bit timer mode 0x%x\n", s->mode[n]); 15153018216SPaolo Bonzini } 15253018216SPaolo Bonzini gptm_update_irq(s); 15353018216SPaolo Bonzini } 15453018216SPaolo Bonzini 15553018216SPaolo Bonzini static uint64_t gptm_read(void *opaque, hwaddr offset, 15653018216SPaolo Bonzini unsigned size) 15753018216SPaolo Bonzini { 15853018216SPaolo Bonzini gptm_state *s = (gptm_state *)opaque; 15953018216SPaolo Bonzini 16053018216SPaolo Bonzini switch (offset) { 16153018216SPaolo Bonzini case 0x00: /* CFG */ 16253018216SPaolo Bonzini return s->config; 16353018216SPaolo Bonzini case 0x04: /* TAMR */ 16453018216SPaolo Bonzini return s->mode[0]; 16553018216SPaolo Bonzini case 0x08: /* TBMR */ 16653018216SPaolo Bonzini return s->mode[1]; 16753018216SPaolo Bonzini case 0x0c: /* CTL */ 16853018216SPaolo Bonzini return s->control; 16953018216SPaolo Bonzini case 0x18: /* IMR */ 17053018216SPaolo Bonzini return s->mask; 17153018216SPaolo Bonzini case 0x1c: /* RIS */ 17253018216SPaolo Bonzini return s->state; 17353018216SPaolo Bonzini case 0x20: /* MIS */ 17453018216SPaolo Bonzini return s->state & s->mask; 17553018216SPaolo Bonzini case 0x24: /* CR */ 17653018216SPaolo Bonzini return 0; 17753018216SPaolo Bonzini case 0x28: /* TAILR */ 17853018216SPaolo Bonzini return s->load[0] | ((s->config < 4) ? (s->load[1] << 16) : 0); 17953018216SPaolo Bonzini case 0x2c: /* TBILR */ 18053018216SPaolo Bonzini return s->load[1]; 18153018216SPaolo Bonzini case 0x30: /* TAMARCHR */ 18253018216SPaolo Bonzini return s->match[0] | ((s->config < 4) ? (s->match[1] << 16) : 0); 18353018216SPaolo Bonzini case 0x34: /* TBMATCHR */ 18453018216SPaolo Bonzini return s->match[1]; 18553018216SPaolo Bonzini case 0x38: /* TAPR */ 18653018216SPaolo Bonzini return s->prescale[0]; 18753018216SPaolo Bonzini case 0x3c: /* TBPR */ 18853018216SPaolo Bonzini return s->prescale[1]; 18953018216SPaolo Bonzini case 0x40: /* TAPMR */ 19053018216SPaolo Bonzini return s->match_prescale[0]; 19153018216SPaolo Bonzini case 0x44: /* TBPMR */ 19253018216SPaolo Bonzini return s->match_prescale[1]; 19353018216SPaolo Bonzini case 0x48: /* TAR */ 1941a791721SPeter Maydell if (s->config == 1) { 19553018216SPaolo Bonzini return s->rtc; 1961a791721SPeter Maydell } 1971a791721SPeter Maydell qemu_log_mask(LOG_UNIMP, 1981a791721SPeter Maydell "GPTM: read of TAR but timer read not supported"); 1991a791721SPeter Maydell return 0; 20053018216SPaolo Bonzini case 0x4c: /* TBR */ 2011a791721SPeter Maydell qemu_log_mask(LOG_UNIMP, 2021a791721SPeter Maydell "GPTM: read of TBR but timer read not supported"); 2031a791721SPeter Maydell return 0; 20453018216SPaolo Bonzini default: 2051a791721SPeter Maydell qemu_log_mask(LOG_GUEST_ERROR, 2061a791721SPeter Maydell "GPTM: read at bad offset 0x%x\n", (int)offset); 20753018216SPaolo Bonzini return 0; 20853018216SPaolo Bonzini } 20953018216SPaolo Bonzini } 21053018216SPaolo Bonzini 21153018216SPaolo Bonzini static void gptm_write(void *opaque, hwaddr offset, 21253018216SPaolo Bonzini uint64_t value, unsigned size) 21353018216SPaolo Bonzini { 21453018216SPaolo Bonzini gptm_state *s = (gptm_state *)opaque; 21553018216SPaolo Bonzini uint32_t oldval; 21653018216SPaolo Bonzini 21753018216SPaolo Bonzini /* The timers should be disabled before changing the configuration. 21853018216SPaolo Bonzini We take advantage of this and defer everything until the timer 21953018216SPaolo Bonzini is enabled. */ 22053018216SPaolo Bonzini switch (offset) { 22153018216SPaolo Bonzini case 0x00: /* CFG */ 22253018216SPaolo Bonzini s->config = value; 22353018216SPaolo Bonzini break; 22453018216SPaolo Bonzini case 0x04: /* TAMR */ 22553018216SPaolo Bonzini s->mode[0] = value; 22653018216SPaolo Bonzini break; 22753018216SPaolo Bonzini case 0x08: /* TBMR */ 22853018216SPaolo Bonzini s->mode[1] = value; 22953018216SPaolo Bonzini break; 23053018216SPaolo Bonzini case 0x0c: /* CTL */ 23153018216SPaolo Bonzini oldval = s->control; 23253018216SPaolo Bonzini s->control = value; 23353018216SPaolo Bonzini /* TODO: Implement pause. */ 23453018216SPaolo Bonzini if ((oldval ^ value) & 1) { 23553018216SPaolo Bonzini if (value & 1) { 23653018216SPaolo Bonzini gptm_reload(s, 0, 1); 23753018216SPaolo Bonzini } else { 23853018216SPaolo Bonzini gptm_stop(s, 0); 23953018216SPaolo Bonzini } 24053018216SPaolo Bonzini } 24153018216SPaolo Bonzini if (((oldval ^ value) & 0x100) && s->config >= 4) { 24253018216SPaolo Bonzini if (value & 0x100) { 24353018216SPaolo Bonzini gptm_reload(s, 1, 1); 24453018216SPaolo Bonzini } else { 24553018216SPaolo Bonzini gptm_stop(s, 1); 24653018216SPaolo Bonzini } 24753018216SPaolo Bonzini } 24853018216SPaolo Bonzini break; 24953018216SPaolo Bonzini case 0x18: /* IMR */ 25053018216SPaolo Bonzini s->mask = value & 0x77; 25153018216SPaolo Bonzini gptm_update_irq(s); 25253018216SPaolo Bonzini break; 25353018216SPaolo Bonzini case 0x24: /* CR */ 25453018216SPaolo Bonzini s->state &= ~value; 25553018216SPaolo Bonzini break; 25653018216SPaolo Bonzini case 0x28: /* TAILR */ 25753018216SPaolo Bonzini s->load[0] = value & 0xffff; 25853018216SPaolo Bonzini if (s->config < 4) { 25953018216SPaolo Bonzini s->load[1] = value >> 16; 26053018216SPaolo Bonzini } 26153018216SPaolo Bonzini break; 26253018216SPaolo Bonzini case 0x2c: /* TBILR */ 26353018216SPaolo Bonzini s->load[1] = value & 0xffff; 26453018216SPaolo Bonzini break; 26553018216SPaolo Bonzini case 0x30: /* TAMARCHR */ 26653018216SPaolo Bonzini s->match[0] = value & 0xffff; 26753018216SPaolo Bonzini if (s->config < 4) { 26853018216SPaolo Bonzini s->match[1] = value >> 16; 26953018216SPaolo Bonzini } 27053018216SPaolo Bonzini break; 27153018216SPaolo Bonzini case 0x34: /* TBMATCHR */ 27253018216SPaolo Bonzini s->match[1] = value >> 16; 27353018216SPaolo Bonzini break; 27453018216SPaolo Bonzini case 0x38: /* TAPR */ 27553018216SPaolo Bonzini s->prescale[0] = value; 27653018216SPaolo Bonzini break; 27753018216SPaolo Bonzini case 0x3c: /* TBPR */ 27853018216SPaolo Bonzini s->prescale[1] = value; 27953018216SPaolo Bonzini break; 28053018216SPaolo Bonzini case 0x40: /* TAPMR */ 28153018216SPaolo Bonzini s->match_prescale[0] = value; 28253018216SPaolo Bonzini break; 28353018216SPaolo Bonzini case 0x44: /* TBPMR */ 28453018216SPaolo Bonzini s->match_prescale[0] = value; 28553018216SPaolo Bonzini break; 28653018216SPaolo Bonzini default: 28753018216SPaolo Bonzini hw_error("gptm_write: Bad offset 0x%x\n", (int)offset); 28853018216SPaolo Bonzini } 28953018216SPaolo Bonzini gptm_update_irq(s); 29053018216SPaolo Bonzini } 29153018216SPaolo Bonzini 29253018216SPaolo Bonzini static const MemoryRegionOps gptm_ops = { 29353018216SPaolo Bonzini .read = gptm_read, 29453018216SPaolo Bonzini .write = gptm_write, 29553018216SPaolo Bonzini .endianness = DEVICE_NATIVE_ENDIAN, 29653018216SPaolo Bonzini }; 29753018216SPaolo Bonzini 29853018216SPaolo Bonzini static const VMStateDescription vmstate_stellaris_gptm = { 29953018216SPaolo Bonzini .name = "stellaris_gptm", 30053018216SPaolo Bonzini .version_id = 1, 30153018216SPaolo Bonzini .minimum_version_id = 1, 30253018216SPaolo Bonzini .fields = (VMStateField[]) { 30353018216SPaolo Bonzini VMSTATE_UINT32(config, gptm_state), 30453018216SPaolo Bonzini VMSTATE_UINT32_ARRAY(mode, gptm_state, 2), 30553018216SPaolo Bonzini VMSTATE_UINT32(control, gptm_state), 30653018216SPaolo Bonzini VMSTATE_UINT32(state, gptm_state), 30753018216SPaolo Bonzini VMSTATE_UINT32(mask, gptm_state), 30853018216SPaolo Bonzini VMSTATE_UNUSED(8), 30953018216SPaolo Bonzini VMSTATE_UINT32_ARRAY(load, gptm_state, 2), 31053018216SPaolo Bonzini VMSTATE_UINT32_ARRAY(match, gptm_state, 2), 31153018216SPaolo Bonzini VMSTATE_UINT32_ARRAY(prescale, gptm_state, 2), 31253018216SPaolo Bonzini VMSTATE_UINT32_ARRAY(match_prescale, gptm_state, 2), 31353018216SPaolo Bonzini VMSTATE_UINT32(rtc, gptm_state), 31453018216SPaolo Bonzini VMSTATE_INT64_ARRAY(tick, gptm_state, 2), 315e720677eSPaolo Bonzini VMSTATE_TIMER_PTR_ARRAY(timer, gptm_state, 2), 31653018216SPaolo Bonzini VMSTATE_END_OF_LIST() 31753018216SPaolo Bonzini } 31853018216SPaolo Bonzini }; 31953018216SPaolo Bonzini 32015c4fff5Sxiaoqiang.zhao static void stellaris_gptm_init(Object *obj) 32153018216SPaolo Bonzini { 32215c4fff5Sxiaoqiang.zhao DeviceState *dev = DEVICE(obj); 32315c4fff5Sxiaoqiang.zhao gptm_state *s = STELLARIS_GPTM(obj); 32415c4fff5Sxiaoqiang.zhao SysBusDevice *sbd = SYS_BUS_DEVICE(obj); 32553018216SPaolo Bonzini 3268ef1d394SAndreas Färber sysbus_init_irq(sbd, &s->irq); 3278ef1d394SAndreas Färber qdev_init_gpio_out(dev, &s->trigger, 1); 32853018216SPaolo Bonzini 32915c4fff5Sxiaoqiang.zhao memory_region_init_io(&s->iomem, obj, &gptm_ops, s, 33053018216SPaolo Bonzini "gptm", 0x1000); 3318ef1d394SAndreas Färber sysbus_init_mmio(sbd, &s->iomem); 33253018216SPaolo Bonzini 33353018216SPaolo Bonzini s->opaque[0] = s->opaque[1] = s; 334bc72ad67SAlex Bligh s->timer[0] = timer_new_ns(QEMU_CLOCK_VIRTUAL, gptm_tick, &s->opaque[0]); 335bc72ad67SAlex Bligh s->timer[1] = timer_new_ns(QEMU_CLOCK_VIRTUAL, gptm_tick, &s->opaque[1]); 33653018216SPaolo Bonzini } 33753018216SPaolo Bonzini 33853018216SPaolo Bonzini 33953018216SPaolo Bonzini /* System controller. */ 34053018216SPaolo Bonzini 34153018216SPaolo Bonzini typedef struct { 34253018216SPaolo Bonzini MemoryRegion iomem; 34353018216SPaolo Bonzini uint32_t pborctl; 34453018216SPaolo Bonzini uint32_t ldopctl; 34553018216SPaolo Bonzini uint32_t int_status; 34653018216SPaolo Bonzini uint32_t int_mask; 34753018216SPaolo Bonzini uint32_t resc; 34853018216SPaolo Bonzini uint32_t rcc; 34953018216SPaolo Bonzini uint32_t rcc2; 35053018216SPaolo Bonzini uint32_t rcgc[3]; 35153018216SPaolo Bonzini uint32_t scgc[3]; 35253018216SPaolo Bonzini uint32_t dcgc[3]; 35353018216SPaolo Bonzini uint32_t clkvclr; 35453018216SPaolo Bonzini uint32_t ldoarst; 35553018216SPaolo Bonzini uint32_t user0; 35653018216SPaolo Bonzini uint32_t user1; 35753018216SPaolo Bonzini qemu_irq irq; 35853018216SPaolo Bonzini stellaris_board_info *board; 35953018216SPaolo Bonzini } ssys_state; 36053018216SPaolo Bonzini 36153018216SPaolo Bonzini static void ssys_update(ssys_state *s) 36253018216SPaolo Bonzini { 36353018216SPaolo Bonzini qemu_set_irq(s->irq, (s->int_status & s->int_mask) != 0); 36453018216SPaolo Bonzini } 36553018216SPaolo Bonzini 36653018216SPaolo Bonzini static uint32_t pllcfg_sandstorm[16] = { 36753018216SPaolo Bonzini 0x31c0, /* 1 Mhz */ 36853018216SPaolo Bonzini 0x1ae0, /* 1.8432 Mhz */ 36953018216SPaolo Bonzini 0x18c0, /* 2 Mhz */ 37053018216SPaolo Bonzini 0xd573, /* 2.4576 Mhz */ 37153018216SPaolo Bonzini 0x37a6, /* 3.57954 Mhz */ 37253018216SPaolo Bonzini 0x1ae2, /* 3.6864 Mhz */ 37353018216SPaolo Bonzini 0x0c40, /* 4 Mhz */ 37453018216SPaolo Bonzini 0x98bc, /* 4.906 Mhz */ 37553018216SPaolo Bonzini 0x935b, /* 4.9152 Mhz */ 37653018216SPaolo Bonzini 0x09c0, /* 5 Mhz */ 37753018216SPaolo Bonzini 0x4dee, /* 5.12 Mhz */ 37853018216SPaolo Bonzini 0x0c41, /* 6 Mhz */ 37953018216SPaolo Bonzini 0x75db, /* 6.144 Mhz */ 38053018216SPaolo Bonzini 0x1ae6, /* 7.3728 Mhz */ 38153018216SPaolo Bonzini 0x0600, /* 8 Mhz */ 38253018216SPaolo Bonzini 0x585b /* 8.192 Mhz */ 38353018216SPaolo Bonzini }; 38453018216SPaolo Bonzini 38553018216SPaolo Bonzini static uint32_t pllcfg_fury[16] = { 38653018216SPaolo Bonzini 0x3200, /* 1 Mhz */ 38753018216SPaolo Bonzini 0x1b20, /* 1.8432 Mhz */ 38853018216SPaolo Bonzini 0x1900, /* 2 Mhz */ 38953018216SPaolo Bonzini 0xf42b, /* 2.4576 Mhz */ 39053018216SPaolo Bonzini 0x37e3, /* 3.57954 Mhz */ 39153018216SPaolo Bonzini 0x1b21, /* 3.6864 Mhz */ 39253018216SPaolo Bonzini 0x0c80, /* 4 Mhz */ 39353018216SPaolo Bonzini 0x98ee, /* 4.906 Mhz */ 39453018216SPaolo Bonzini 0xd5b4, /* 4.9152 Mhz */ 39553018216SPaolo Bonzini 0x0a00, /* 5 Mhz */ 39653018216SPaolo Bonzini 0x4e27, /* 5.12 Mhz */ 39753018216SPaolo Bonzini 0x1902, /* 6 Mhz */ 39853018216SPaolo Bonzini 0xec1c, /* 6.144 Mhz */ 39953018216SPaolo Bonzini 0x1b23, /* 7.3728 Mhz */ 40053018216SPaolo Bonzini 0x0640, /* 8 Mhz */ 40153018216SPaolo Bonzini 0xb11c /* 8.192 Mhz */ 40253018216SPaolo Bonzini }; 40353018216SPaolo Bonzini 40453018216SPaolo Bonzini #define DID0_VER_MASK 0x70000000 40553018216SPaolo Bonzini #define DID0_VER_0 0x00000000 40653018216SPaolo Bonzini #define DID0_VER_1 0x10000000 40753018216SPaolo Bonzini 40853018216SPaolo Bonzini #define DID0_CLASS_MASK 0x00FF0000 40953018216SPaolo Bonzini #define DID0_CLASS_SANDSTORM 0x00000000 41053018216SPaolo Bonzini #define DID0_CLASS_FURY 0x00010000 41153018216SPaolo Bonzini 41253018216SPaolo Bonzini static int ssys_board_class(const ssys_state *s) 41353018216SPaolo Bonzini { 41453018216SPaolo Bonzini uint32_t did0 = s->board->did0; 41553018216SPaolo Bonzini switch (did0 & DID0_VER_MASK) { 41653018216SPaolo Bonzini case DID0_VER_0: 41753018216SPaolo Bonzini return DID0_CLASS_SANDSTORM; 41853018216SPaolo Bonzini case DID0_VER_1: 41953018216SPaolo Bonzini switch (did0 & DID0_CLASS_MASK) { 42053018216SPaolo Bonzini case DID0_CLASS_SANDSTORM: 42153018216SPaolo Bonzini case DID0_CLASS_FURY: 42253018216SPaolo Bonzini return did0 & DID0_CLASS_MASK; 42353018216SPaolo Bonzini } 42453018216SPaolo Bonzini /* for unknown classes, fall through */ 42553018216SPaolo Bonzini default: 42653018216SPaolo Bonzini hw_error("ssys_board_class: Unknown class 0x%08x\n", did0); 42753018216SPaolo Bonzini } 42853018216SPaolo Bonzini } 42953018216SPaolo Bonzini 43053018216SPaolo Bonzini static uint64_t ssys_read(void *opaque, hwaddr offset, 43153018216SPaolo Bonzini unsigned size) 43253018216SPaolo Bonzini { 43353018216SPaolo Bonzini ssys_state *s = (ssys_state *)opaque; 43453018216SPaolo Bonzini 43553018216SPaolo Bonzini switch (offset) { 43653018216SPaolo Bonzini case 0x000: /* DID0 */ 43753018216SPaolo Bonzini return s->board->did0; 43853018216SPaolo Bonzini case 0x004: /* DID1 */ 43953018216SPaolo Bonzini return s->board->did1; 44053018216SPaolo Bonzini case 0x008: /* DC0 */ 44153018216SPaolo Bonzini return s->board->dc0; 44253018216SPaolo Bonzini case 0x010: /* DC1 */ 44353018216SPaolo Bonzini return s->board->dc1; 44453018216SPaolo Bonzini case 0x014: /* DC2 */ 44553018216SPaolo Bonzini return s->board->dc2; 44653018216SPaolo Bonzini case 0x018: /* DC3 */ 44753018216SPaolo Bonzini return s->board->dc3; 44853018216SPaolo Bonzini case 0x01c: /* DC4 */ 44953018216SPaolo Bonzini return s->board->dc4; 45053018216SPaolo Bonzini case 0x030: /* PBORCTL */ 45153018216SPaolo Bonzini return s->pborctl; 45253018216SPaolo Bonzini case 0x034: /* LDOPCTL */ 45353018216SPaolo Bonzini return s->ldopctl; 45453018216SPaolo Bonzini case 0x040: /* SRCR0 */ 45553018216SPaolo Bonzini return 0; 45653018216SPaolo Bonzini case 0x044: /* SRCR1 */ 45753018216SPaolo Bonzini return 0; 45853018216SPaolo Bonzini case 0x048: /* SRCR2 */ 45953018216SPaolo Bonzini return 0; 46053018216SPaolo Bonzini case 0x050: /* RIS */ 46153018216SPaolo Bonzini return s->int_status; 46253018216SPaolo Bonzini case 0x054: /* IMC */ 46353018216SPaolo Bonzini return s->int_mask; 46453018216SPaolo Bonzini case 0x058: /* MISC */ 46553018216SPaolo Bonzini return s->int_status & s->int_mask; 46653018216SPaolo Bonzini case 0x05c: /* RESC */ 46753018216SPaolo Bonzini return s->resc; 46853018216SPaolo Bonzini case 0x060: /* RCC */ 46953018216SPaolo Bonzini return s->rcc; 47053018216SPaolo Bonzini case 0x064: /* PLLCFG */ 47153018216SPaolo Bonzini { 47253018216SPaolo Bonzini int xtal; 47353018216SPaolo Bonzini xtal = (s->rcc >> 6) & 0xf; 47453018216SPaolo Bonzini switch (ssys_board_class(s)) { 47553018216SPaolo Bonzini case DID0_CLASS_FURY: 47653018216SPaolo Bonzini return pllcfg_fury[xtal]; 47753018216SPaolo Bonzini case DID0_CLASS_SANDSTORM: 47853018216SPaolo Bonzini return pllcfg_sandstorm[xtal]; 47953018216SPaolo Bonzini default: 48053018216SPaolo Bonzini hw_error("ssys_read: Unhandled class for PLLCFG read.\n"); 48153018216SPaolo Bonzini return 0; 48253018216SPaolo Bonzini } 48353018216SPaolo Bonzini } 48453018216SPaolo Bonzini case 0x070: /* RCC2 */ 48553018216SPaolo Bonzini return s->rcc2; 48653018216SPaolo Bonzini case 0x100: /* RCGC0 */ 48753018216SPaolo Bonzini return s->rcgc[0]; 48853018216SPaolo Bonzini case 0x104: /* RCGC1 */ 48953018216SPaolo Bonzini return s->rcgc[1]; 49053018216SPaolo Bonzini case 0x108: /* RCGC2 */ 49153018216SPaolo Bonzini return s->rcgc[2]; 49253018216SPaolo Bonzini case 0x110: /* SCGC0 */ 49353018216SPaolo Bonzini return s->scgc[0]; 49453018216SPaolo Bonzini case 0x114: /* SCGC1 */ 49553018216SPaolo Bonzini return s->scgc[1]; 49653018216SPaolo Bonzini case 0x118: /* SCGC2 */ 49753018216SPaolo Bonzini return s->scgc[2]; 49853018216SPaolo Bonzini case 0x120: /* DCGC0 */ 49953018216SPaolo Bonzini return s->dcgc[0]; 50053018216SPaolo Bonzini case 0x124: /* DCGC1 */ 50153018216SPaolo Bonzini return s->dcgc[1]; 50253018216SPaolo Bonzini case 0x128: /* DCGC2 */ 50353018216SPaolo Bonzini return s->dcgc[2]; 50453018216SPaolo Bonzini case 0x150: /* CLKVCLR */ 50553018216SPaolo Bonzini return s->clkvclr; 50653018216SPaolo Bonzini case 0x160: /* LDOARST */ 50753018216SPaolo Bonzini return s->ldoarst; 50853018216SPaolo Bonzini case 0x1e0: /* USER0 */ 50953018216SPaolo Bonzini return s->user0; 51053018216SPaolo Bonzini case 0x1e4: /* USER1 */ 51153018216SPaolo Bonzini return s->user1; 51253018216SPaolo Bonzini default: 51353018216SPaolo Bonzini hw_error("ssys_read: Bad offset 0x%x\n", (int)offset); 51453018216SPaolo Bonzini return 0; 51553018216SPaolo Bonzini } 51653018216SPaolo Bonzini } 51753018216SPaolo Bonzini 51853018216SPaolo Bonzini static bool ssys_use_rcc2(ssys_state *s) 51953018216SPaolo Bonzini { 52053018216SPaolo Bonzini return (s->rcc2 >> 31) & 0x1; 52153018216SPaolo Bonzini } 52253018216SPaolo Bonzini 52353018216SPaolo Bonzini /* 52453018216SPaolo Bonzini * Caculate the sys. clock period in ms. 52553018216SPaolo Bonzini */ 52653018216SPaolo Bonzini static void ssys_calculate_system_clock(ssys_state *s) 52753018216SPaolo Bonzini { 52853018216SPaolo Bonzini if (ssys_use_rcc2(s)) { 52953018216SPaolo Bonzini system_clock_scale = 5 * (((s->rcc2 >> 23) & 0x3f) + 1); 53053018216SPaolo Bonzini } else { 53153018216SPaolo Bonzini system_clock_scale = 5 * (((s->rcc >> 23) & 0xf) + 1); 53253018216SPaolo Bonzini } 53353018216SPaolo Bonzini } 53453018216SPaolo Bonzini 53553018216SPaolo Bonzini static void ssys_write(void *opaque, hwaddr offset, 53653018216SPaolo Bonzini uint64_t value, unsigned size) 53753018216SPaolo Bonzini { 53853018216SPaolo Bonzini ssys_state *s = (ssys_state *)opaque; 53953018216SPaolo Bonzini 54053018216SPaolo Bonzini switch (offset) { 54153018216SPaolo Bonzini case 0x030: /* PBORCTL */ 54253018216SPaolo Bonzini s->pborctl = value & 0xffff; 54353018216SPaolo Bonzini break; 54453018216SPaolo Bonzini case 0x034: /* LDOPCTL */ 54553018216SPaolo Bonzini s->ldopctl = value & 0x1f; 54653018216SPaolo Bonzini break; 54753018216SPaolo Bonzini case 0x040: /* SRCR0 */ 54853018216SPaolo Bonzini case 0x044: /* SRCR1 */ 54953018216SPaolo Bonzini case 0x048: /* SRCR2 */ 55053018216SPaolo Bonzini fprintf(stderr, "Peripheral reset not implemented\n"); 55153018216SPaolo Bonzini break; 55253018216SPaolo Bonzini case 0x054: /* IMC */ 55353018216SPaolo Bonzini s->int_mask = value & 0x7f; 55453018216SPaolo Bonzini break; 55553018216SPaolo Bonzini case 0x058: /* MISC */ 55653018216SPaolo Bonzini s->int_status &= ~value; 55753018216SPaolo Bonzini break; 55853018216SPaolo Bonzini case 0x05c: /* RESC */ 55953018216SPaolo Bonzini s->resc = value & 0x3f; 56053018216SPaolo Bonzini break; 56153018216SPaolo Bonzini case 0x060: /* RCC */ 56253018216SPaolo Bonzini if ((s->rcc & (1 << 13)) != 0 && (value & (1 << 13)) == 0) { 56353018216SPaolo Bonzini /* PLL enable. */ 56453018216SPaolo Bonzini s->int_status |= (1 << 6); 56553018216SPaolo Bonzini } 56653018216SPaolo Bonzini s->rcc = value; 56753018216SPaolo Bonzini ssys_calculate_system_clock(s); 56853018216SPaolo Bonzini break; 56953018216SPaolo Bonzini case 0x070: /* RCC2 */ 57053018216SPaolo Bonzini if (ssys_board_class(s) == DID0_CLASS_SANDSTORM) { 57153018216SPaolo Bonzini break; 57253018216SPaolo Bonzini } 57353018216SPaolo Bonzini 57453018216SPaolo Bonzini if ((s->rcc2 & (1 << 13)) != 0 && (value & (1 << 13)) == 0) { 57553018216SPaolo Bonzini /* PLL enable. */ 57653018216SPaolo Bonzini s->int_status |= (1 << 6); 57753018216SPaolo Bonzini } 57853018216SPaolo Bonzini s->rcc2 = value; 57953018216SPaolo Bonzini ssys_calculate_system_clock(s); 58053018216SPaolo Bonzini break; 58153018216SPaolo Bonzini case 0x100: /* RCGC0 */ 58253018216SPaolo Bonzini s->rcgc[0] = value; 58353018216SPaolo Bonzini break; 58453018216SPaolo Bonzini case 0x104: /* RCGC1 */ 58553018216SPaolo Bonzini s->rcgc[1] = value; 58653018216SPaolo Bonzini break; 58753018216SPaolo Bonzini case 0x108: /* RCGC2 */ 58853018216SPaolo Bonzini s->rcgc[2] = value; 58953018216SPaolo Bonzini break; 59053018216SPaolo Bonzini case 0x110: /* SCGC0 */ 59153018216SPaolo Bonzini s->scgc[0] = value; 59253018216SPaolo Bonzini break; 59353018216SPaolo Bonzini case 0x114: /* SCGC1 */ 59453018216SPaolo Bonzini s->scgc[1] = value; 59553018216SPaolo Bonzini break; 59653018216SPaolo Bonzini case 0x118: /* SCGC2 */ 59753018216SPaolo Bonzini s->scgc[2] = value; 59853018216SPaolo Bonzini break; 59953018216SPaolo Bonzini case 0x120: /* DCGC0 */ 60053018216SPaolo Bonzini s->dcgc[0] = value; 60153018216SPaolo Bonzini break; 60253018216SPaolo Bonzini case 0x124: /* DCGC1 */ 60353018216SPaolo Bonzini s->dcgc[1] = value; 60453018216SPaolo Bonzini break; 60553018216SPaolo Bonzini case 0x128: /* DCGC2 */ 60653018216SPaolo Bonzini s->dcgc[2] = value; 60753018216SPaolo Bonzini break; 60853018216SPaolo Bonzini case 0x150: /* CLKVCLR */ 60953018216SPaolo Bonzini s->clkvclr = value; 61053018216SPaolo Bonzini break; 61153018216SPaolo Bonzini case 0x160: /* LDOARST */ 61253018216SPaolo Bonzini s->ldoarst = value; 61353018216SPaolo Bonzini break; 61453018216SPaolo Bonzini default: 61553018216SPaolo Bonzini hw_error("ssys_write: Bad offset 0x%x\n", (int)offset); 61653018216SPaolo Bonzini } 61753018216SPaolo Bonzini ssys_update(s); 61853018216SPaolo Bonzini } 61953018216SPaolo Bonzini 62053018216SPaolo Bonzini static const MemoryRegionOps ssys_ops = { 62153018216SPaolo Bonzini .read = ssys_read, 62253018216SPaolo Bonzini .write = ssys_write, 62353018216SPaolo Bonzini .endianness = DEVICE_NATIVE_ENDIAN, 62453018216SPaolo Bonzini }; 62553018216SPaolo Bonzini 62653018216SPaolo Bonzini static void ssys_reset(void *opaque) 62753018216SPaolo Bonzini { 62853018216SPaolo Bonzini ssys_state *s = (ssys_state *)opaque; 62953018216SPaolo Bonzini 63053018216SPaolo Bonzini s->pborctl = 0x7ffd; 63153018216SPaolo Bonzini s->rcc = 0x078e3ac0; 63253018216SPaolo Bonzini 63353018216SPaolo Bonzini if (ssys_board_class(s) == DID0_CLASS_SANDSTORM) { 63453018216SPaolo Bonzini s->rcc2 = 0; 63553018216SPaolo Bonzini } else { 63653018216SPaolo Bonzini s->rcc2 = 0x07802810; 63753018216SPaolo Bonzini } 63853018216SPaolo Bonzini s->rcgc[0] = 1; 63953018216SPaolo Bonzini s->scgc[0] = 1; 64053018216SPaolo Bonzini s->dcgc[0] = 1; 64153018216SPaolo Bonzini ssys_calculate_system_clock(s); 64253018216SPaolo Bonzini } 64353018216SPaolo Bonzini 64453018216SPaolo Bonzini static int stellaris_sys_post_load(void *opaque, int version_id) 64553018216SPaolo Bonzini { 64653018216SPaolo Bonzini ssys_state *s = opaque; 64753018216SPaolo Bonzini 64853018216SPaolo Bonzini ssys_calculate_system_clock(s); 64953018216SPaolo Bonzini 65053018216SPaolo Bonzini return 0; 65153018216SPaolo Bonzini } 65253018216SPaolo Bonzini 65353018216SPaolo Bonzini static const VMStateDescription vmstate_stellaris_sys = { 65453018216SPaolo Bonzini .name = "stellaris_sys", 65553018216SPaolo Bonzini .version_id = 2, 65653018216SPaolo Bonzini .minimum_version_id = 1, 65753018216SPaolo Bonzini .post_load = stellaris_sys_post_load, 65853018216SPaolo Bonzini .fields = (VMStateField[]) { 65953018216SPaolo Bonzini VMSTATE_UINT32(pborctl, ssys_state), 66053018216SPaolo Bonzini VMSTATE_UINT32(ldopctl, ssys_state), 66153018216SPaolo Bonzini VMSTATE_UINT32(int_mask, ssys_state), 66253018216SPaolo Bonzini VMSTATE_UINT32(int_status, ssys_state), 66353018216SPaolo Bonzini VMSTATE_UINT32(resc, ssys_state), 66453018216SPaolo Bonzini VMSTATE_UINT32(rcc, ssys_state), 66553018216SPaolo Bonzini VMSTATE_UINT32_V(rcc2, ssys_state, 2), 66653018216SPaolo Bonzini VMSTATE_UINT32_ARRAY(rcgc, ssys_state, 3), 66753018216SPaolo Bonzini VMSTATE_UINT32_ARRAY(scgc, ssys_state, 3), 66853018216SPaolo Bonzini VMSTATE_UINT32_ARRAY(dcgc, ssys_state, 3), 66953018216SPaolo Bonzini VMSTATE_UINT32(clkvclr, ssys_state), 67053018216SPaolo Bonzini VMSTATE_UINT32(ldoarst, ssys_state), 67153018216SPaolo Bonzini VMSTATE_END_OF_LIST() 67253018216SPaolo Bonzini } 67353018216SPaolo Bonzini }; 67453018216SPaolo Bonzini 67553018216SPaolo Bonzini static int stellaris_sys_init(uint32_t base, qemu_irq irq, 67653018216SPaolo Bonzini stellaris_board_info * board, 67753018216SPaolo Bonzini uint8_t *macaddr) 67853018216SPaolo Bonzini { 67953018216SPaolo Bonzini ssys_state *s; 68053018216SPaolo Bonzini 681b45c03f5SMarkus Armbruster s = g_new0(ssys_state, 1); 68253018216SPaolo Bonzini s->irq = irq; 68353018216SPaolo Bonzini s->board = board; 68453018216SPaolo Bonzini /* Most devices come preprogrammed with a MAC address in the user data. */ 68553018216SPaolo Bonzini s->user0 = macaddr[0] | (macaddr[1] << 8) | (macaddr[2] << 16); 68653018216SPaolo Bonzini s->user1 = macaddr[3] | (macaddr[4] << 8) | (macaddr[5] << 16); 68753018216SPaolo Bonzini 6882c9b15caSPaolo Bonzini memory_region_init_io(&s->iomem, NULL, &ssys_ops, s, "ssys", 0x00001000); 68953018216SPaolo Bonzini memory_region_add_subregion(get_system_memory(), base, &s->iomem); 69053018216SPaolo Bonzini ssys_reset(s); 69153018216SPaolo Bonzini vmstate_register(NULL, -1, &vmstate_stellaris_sys, s); 69253018216SPaolo Bonzini return 0; 69353018216SPaolo Bonzini } 69453018216SPaolo Bonzini 69553018216SPaolo Bonzini 69653018216SPaolo Bonzini /* I2C controller. */ 69753018216SPaolo Bonzini 698d94a4015SAndreas Färber #define TYPE_STELLARIS_I2C "stellaris-i2c" 699d94a4015SAndreas Färber #define STELLARIS_I2C(obj) \ 700d94a4015SAndreas Färber OBJECT_CHECK(stellaris_i2c_state, (obj), TYPE_STELLARIS_I2C) 701d94a4015SAndreas Färber 70253018216SPaolo Bonzini typedef struct { 703d94a4015SAndreas Färber SysBusDevice parent_obj; 704d94a4015SAndreas Färber 705a5c82852SAndreas Färber I2CBus *bus; 70653018216SPaolo Bonzini qemu_irq irq; 70753018216SPaolo Bonzini MemoryRegion iomem; 70853018216SPaolo Bonzini uint32_t msa; 70953018216SPaolo Bonzini uint32_t mcs; 71053018216SPaolo Bonzini uint32_t mdr; 71153018216SPaolo Bonzini uint32_t mtpr; 71253018216SPaolo Bonzini uint32_t mimr; 71353018216SPaolo Bonzini uint32_t mris; 71453018216SPaolo Bonzini uint32_t mcr; 71553018216SPaolo Bonzini } stellaris_i2c_state; 71653018216SPaolo Bonzini 71753018216SPaolo Bonzini #define STELLARIS_I2C_MCS_BUSY 0x01 71853018216SPaolo Bonzini #define STELLARIS_I2C_MCS_ERROR 0x02 71953018216SPaolo Bonzini #define STELLARIS_I2C_MCS_ADRACK 0x04 72053018216SPaolo Bonzini #define STELLARIS_I2C_MCS_DATACK 0x08 72153018216SPaolo Bonzini #define STELLARIS_I2C_MCS_ARBLST 0x10 72253018216SPaolo Bonzini #define STELLARIS_I2C_MCS_IDLE 0x20 72353018216SPaolo Bonzini #define STELLARIS_I2C_MCS_BUSBSY 0x40 72453018216SPaolo Bonzini 72553018216SPaolo Bonzini static uint64_t stellaris_i2c_read(void *opaque, hwaddr offset, 72653018216SPaolo Bonzini unsigned size) 72753018216SPaolo Bonzini { 72853018216SPaolo Bonzini stellaris_i2c_state *s = (stellaris_i2c_state *)opaque; 72953018216SPaolo Bonzini 73053018216SPaolo Bonzini switch (offset) { 73153018216SPaolo Bonzini case 0x00: /* MSA */ 73253018216SPaolo Bonzini return s->msa; 73353018216SPaolo Bonzini case 0x04: /* MCS */ 73453018216SPaolo Bonzini /* We don't emulate timing, so the controller is never busy. */ 73553018216SPaolo Bonzini return s->mcs | STELLARIS_I2C_MCS_IDLE; 73653018216SPaolo Bonzini case 0x08: /* MDR */ 73753018216SPaolo Bonzini return s->mdr; 73853018216SPaolo Bonzini case 0x0c: /* MTPR */ 73953018216SPaolo Bonzini return s->mtpr; 74053018216SPaolo Bonzini case 0x10: /* MIMR */ 74153018216SPaolo Bonzini return s->mimr; 74253018216SPaolo Bonzini case 0x14: /* MRIS */ 74353018216SPaolo Bonzini return s->mris; 74453018216SPaolo Bonzini case 0x18: /* MMIS */ 74553018216SPaolo Bonzini return s->mris & s->mimr; 74653018216SPaolo Bonzini case 0x20: /* MCR */ 74753018216SPaolo Bonzini return s->mcr; 74853018216SPaolo Bonzini default: 74953018216SPaolo Bonzini hw_error("strllaris_i2c_read: Bad offset 0x%x\n", (int)offset); 75053018216SPaolo Bonzini return 0; 75153018216SPaolo Bonzini } 75253018216SPaolo Bonzini } 75353018216SPaolo Bonzini 75453018216SPaolo Bonzini static void stellaris_i2c_update(stellaris_i2c_state *s) 75553018216SPaolo Bonzini { 75653018216SPaolo Bonzini int level; 75753018216SPaolo Bonzini 75853018216SPaolo Bonzini level = (s->mris & s->mimr) != 0; 75953018216SPaolo Bonzini qemu_set_irq(s->irq, level); 76053018216SPaolo Bonzini } 76153018216SPaolo Bonzini 76253018216SPaolo Bonzini static void stellaris_i2c_write(void *opaque, hwaddr offset, 76353018216SPaolo Bonzini uint64_t value, unsigned size) 76453018216SPaolo Bonzini { 76553018216SPaolo Bonzini stellaris_i2c_state *s = (stellaris_i2c_state *)opaque; 76653018216SPaolo Bonzini 76753018216SPaolo Bonzini switch (offset) { 76853018216SPaolo Bonzini case 0x00: /* MSA */ 76953018216SPaolo Bonzini s->msa = value & 0xff; 77053018216SPaolo Bonzini break; 77153018216SPaolo Bonzini case 0x04: /* MCS */ 77253018216SPaolo Bonzini if ((s->mcr & 0x10) == 0) { 77353018216SPaolo Bonzini /* Disabled. Do nothing. */ 77453018216SPaolo Bonzini break; 77553018216SPaolo Bonzini } 77653018216SPaolo Bonzini /* Grab the bus if this is starting a transfer. */ 77753018216SPaolo Bonzini if ((value & 2) && (s->mcs & STELLARIS_I2C_MCS_BUSBSY) == 0) { 77853018216SPaolo Bonzini if (i2c_start_transfer(s->bus, s->msa >> 1, s->msa & 1)) { 77953018216SPaolo Bonzini s->mcs |= STELLARIS_I2C_MCS_ARBLST; 78053018216SPaolo Bonzini } else { 78153018216SPaolo Bonzini s->mcs &= ~STELLARIS_I2C_MCS_ARBLST; 78253018216SPaolo Bonzini s->mcs |= STELLARIS_I2C_MCS_BUSBSY; 78353018216SPaolo Bonzini } 78453018216SPaolo Bonzini } 78553018216SPaolo Bonzini /* If we don't have the bus then indicate an error. */ 78653018216SPaolo Bonzini if (!i2c_bus_busy(s->bus) 78753018216SPaolo Bonzini || (s->mcs & STELLARIS_I2C_MCS_BUSBSY) == 0) { 78853018216SPaolo Bonzini s->mcs |= STELLARIS_I2C_MCS_ERROR; 78953018216SPaolo Bonzini break; 79053018216SPaolo Bonzini } 79153018216SPaolo Bonzini s->mcs &= ~STELLARIS_I2C_MCS_ERROR; 79253018216SPaolo Bonzini if (value & 1) { 79353018216SPaolo Bonzini /* Transfer a byte. */ 79453018216SPaolo Bonzini /* TODO: Handle errors. */ 79553018216SPaolo Bonzini if (s->msa & 1) { 79653018216SPaolo Bonzini /* Recv */ 79753018216SPaolo Bonzini s->mdr = i2c_recv(s->bus) & 0xff; 79853018216SPaolo Bonzini } else { 79953018216SPaolo Bonzini /* Send */ 80053018216SPaolo Bonzini i2c_send(s->bus, s->mdr); 80153018216SPaolo Bonzini } 80253018216SPaolo Bonzini /* Raise an interrupt. */ 80353018216SPaolo Bonzini s->mris |= 1; 80453018216SPaolo Bonzini } 80553018216SPaolo Bonzini if (value & 4) { 80653018216SPaolo Bonzini /* Finish transfer. */ 80753018216SPaolo Bonzini i2c_end_transfer(s->bus); 80853018216SPaolo Bonzini s->mcs &= ~STELLARIS_I2C_MCS_BUSBSY; 80953018216SPaolo Bonzini } 81053018216SPaolo Bonzini break; 81153018216SPaolo Bonzini case 0x08: /* MDR */ 81253018216SPaolo Bonzini s->mdr = value & 0xff; 81353018216SPaolo Bonzini break; 81453018216SPaolo Bonzini case 0x0c: /* MTPR */ 81553018216SPaolo Bonzini s->mtpr = value & 0xff; 81653018216SPaolo Bonzini break; 81753018216SPaolo Bonzini case 0x10: /* MIMR */ 81853018216SPaolo Bonzini s->mimr = 1; 81953018216SPaolo Bonzini break; 82053018216SPaolo Bonzini case 0x1c: /* MICR */ 82153018216SPaolo Bonzini s->mris &= ~value; 82253018216SPaolo Bonzini break; 82353018216SPaolo Bonzini case 0x20: /* MCR */ 82453018216SPaolo Bonzini if (value & 1) 82553018216SPaolo Bonzini hw_error( 82653018216SPaolo Bonzini "stellaris_i2c_write: Loopback not implemented\n"); 82753018216SPaolo Bonzini if (value & 0x20) 82853018216SPaolo Bonzini hw_error( 82953018216SPaolo Bonzini "stellaris_i2c_write: Slave mode not implemented\n"); 83053018216SPaolo Bonzini s->mcr = value & 0x31; 83153018216SPaolo Bonzini break; 83253018216SPaolo Bonzini default: 83353018216SPaolo Bonzini hw_error("stellaris_i2c_write: Bad offset 0x%x\n", 83453018216SPaolo Bonzini (int)offset); 83553018216SPaolo Bonzini } 83653018216SPaolo Bonzini stellaris_i2c_update(s); 83753018216SPaolo Bonzini } 83853018216SPaolo Bonzini 83953018216SPaolo Bonzini static void stellaris_i2c_reset(stellaris_i2c_state *s) 84053018216SPaolo Bonzini { 84153018216SPaolo Bonzini if (s->mcs & STELLARIS_I2C_MCS_BUSBSY) 84253018216SPaolo Bonzini i2c_end_transfer(s->bus); 84353018216SPaolo Bonzini 84453018216SPaolo Bonzini s->msa = 0; 84553018216SPaolo Bonzini s->mcs = 0; 84653018216SPaolo Bonzini s->mdr = 0; 84753018216SPaolo Bonzini s->mtpr = 1; 84853018216SPaolo Bonzini s->mimr = 0; 84953018216SPaolo Bonzini s->mris = 0; 85053018216SPaolo Bonzini s->mcr = 0; 85153018216SPaolo Bonzini stellaris_i2c_update(s); 85253018216SPaolo Bonzini } 85353018216SPaolo Bonzini 85453018216SPaolo Bonzini static const MemoryRegionOps stellaris_i2c_ops = { 85553018216SPaolo Bonzini .read = stellaris_i2c_read, 85653018216SPaolo Bonzini .write = stellaris_i2c_write, 85753018216SPaolo Bonzini .endianness = DEVICE_NATIVE_ENDIAN, 85853018216SPaolo Bonzini }; 85953018216SPaolo Bonzini 86053018216SPaolo Bonzini static const VMStateDescription vmstate_stellaris_i2c = { 86153018216SPaolo Bonzini .name = "stellaris_i2c", 86253018216SPaolo Bonzini .version_id = 1, 86353018216SPaolo Bonzini .minimum_version_id = 1, 86453018216SPaolo Bonzini .fields = (VMStateField[]) { 86553018216SPaolo Bonzini VMSTATE_UINT32(msa, stellaris_i2c_state), 86653018216SPaolo Bonzini VMSTATE_UINT32(mcs, stellaris_i2c_state), 86753018216SPaolo Bonzini VMSTATE_UINT32(mdr, stellaris_i2c_state), 86853018216SPaolo Bonzini VMSTATE_UINT32(mtpr, stellaris_i2c_state), 86953018216SPaolo Bonzini VMSTATE_UINT32(mimr, stellaris_i2c_state), 87053018216SPaolo Bonzini VMSTATE_UINT32(mris, stellaris_i2c_state), 87153018216SPaolo Bonzini VMSTATE_UINT32(mcr, stellaris_i2c_state), 87253018216SPaolo Bonzini VMSTATE_END_OF_LIST() 87353018216SPaolo Bonzini } 87453018216SPaolo Bonzini }; 87553018216SPaolo Bonzini 87615c4fff5Sxiaoqiang.zhao static void stellaris_i2c_init(Object *obj) 87753018216SPaolo Bonzini { 87815c4fff5Sxiaoqiang.zhao DeviceState *dev = DEVICE(obj); 87915c4fff5Sxiaoqiang.zhao stellaris_i2c_state *s = STELLARIS_I2C(obj); 88015c4fff5Sxiaoqiang.zhao SysBusDevice *sbd = SYS_BUS_DEVICE(obj); 881a5c82852SAndreas Färber I2CBus *bus; 88253018216SPaolo Bonzini 883d94a4015SAndreas Färber sysbus_init_irq(sbd, &s->irq); 884d94a4015SAndreas Färber bus = i2c_init_bus(dev, "i2c"); 88553018216SPaolo Bonzini s->bus = bus; 88653018216SPaolo Bonzini 88715c4fff5Sxiaoqiang.zhao memory_region_init_io(&s->iomem, obj, &stellaris_i2c_ops, s, 88853018216SPaolo Bonzini "i2c", 0x1000); 889d94a4015SAndreas Färber sysbus_init_mmio(sbd, &s->iomem); 89053018216SPaolo Bonzini /* ??? For now we only implement the master interface. */ 89153018216SPaolo Bonzini stellaris_i2c_reset(s); 89253018216SPaolo Bonzini } 89353018216SPaolo Bonzini 89453018216SPaolo Bonzini /* Analogue to Digital Converter. This is only partially implemented, 89553018216SPaolo Bonzini enough for applications that use a combined ADC and timer tick. */ 89653018216SPaolo Bonzini 89753018216SPaolo Bonzini #define STELLARIS_ADC_EM_CONTROLLER 0 89853018216SPaolo Bonzini #define STELLARIS_ADC_EM_COMP 1 89953018216SPaolo Bonzini #define STELLARIS_ADC_EM_EXTERNAL 4 90053018216SPaolo Bonzini #define STELLARIS_ADC_EM_TIMER 5 90153018216SPaolo Bonzini #define STELLARIS_ADC_EM_PWM0 6 90253018216SPaolo Bonzini #define STELLARIS_ADC_EM_PWM1 7 90353018216SPaolo Bonzini #define STELLARIS_ADC_EM_PWM2 8 90453018216SPaolo Bonzini 90553018216SPaolo Bonzini #define STELLARIS_ADC_FIFO_EMPTY 0x0100 90653018216SPaolo Bonzini #define STELLARIS_ADC_FIFO_FULL 0x1000 90753018216SPaolo Bonzini 9087df7f67aSAndreas Färber #define TYPE_STELLARIS_ADC "stellaris-adc" 9097df7f67aSAndreas Färber #define STELLARIS_ADC(obj) \ 9107df7f67aSAndreas Färber OBJECT_CHECK(stellaris_adc_state, (obj), TYPE_STELLARIS_ADC) 9117df7f67aSAndreas Färber 9127df7f67aSAndreas Färber typedef struct StellarisADCState { 9137df7f67aSAndreas Färber SysBusDevice parent_obj; 9147df7f67aSAndreas Färber 91553018216SPaolo Bonzini MemoryRegion iomem; 91653018216SPaolo Bonzini uint32_t actss; 91753018216SPaolo Bonzini uint32_t ris; 91853018216SPaolo Bonzini uint32_t im; 91953018216SPaolo Bonzini uint32_t emux; 92053018216SPaolo Bonzini uint32_t ostat; 92153018216SPaolo Bonzini uint32_t ustat; 92253018216SPaolo Bonzini uint32_t sspri; 92353018216SPaolo Bonzini uint32_t sac; 92453018216SPaolo Bonzini struct { 92553018216SPaolo Bonzini uint32_t state; 92653018216SPaolo Bonzini uint32_t data[16]; 92753018216SPaolo Bonzini } fifo[4]; 92853018216SPaolo Bonzini uint32_t ssmux[4]; 92953018216SPaolo Bonzini uint32_t ssctl[4]; 93053018216SPaolo Bonzini uint32_t noise; 93153018216SPaolo Bonzini qemu_irq irq[4]; 93253018216SPaolo Bonzini } stellaris_adc_state; 93353018216SPaolo Bonzini 93453018216SPaolo Bonzini static uint32_t stellaris_adc_fifo_read(stellaris_adc_state *s, int n) 93553018216SPaolo Bonzini { 93653018216SPaolo Bonzini int tail; 93753018216SPaolo Bonzini 93853018216SPaolo Bonzini tail = s->fifo[n].state & 0xf; 93953018216SPaolo Bonzini if (s->fifo[n].state & STELLARIS_ADC_FIFO_EMPTY) { 94053018216SPaolo Bonzini s->ustat |= 1 << n; 94153018216SPaolo Bonzini } else { 94253018216SPaolo Bonzini s->fifo[n].state = (s->fifo[n].state & ~0xf) | ((tail + 1) & 0xf); 94353018216SPaolo Bonzini s->fifo[n].state &= ~STELLARIS_ADC_FIFO_FULL; 94453018216SPaolo Bonzini if (tail + 1 == ((s->fifo[n].state >> 4) & 0xf)) 94553018216SPaolo Bonzini s->fifo[n].state |= STELLARIS_ADC_FIFO_EMPTY; 94653018216SPaolo Bonzini } 94753018216SPaolo Bonzini return s->fifo[n].data[tail]; 94853018216SPaolo Bonzini } 94953018216SPaolo Bonzini 95053018216SPaolo Bonzini static void stellaris_adc_fifo_write(stellaris_adc_state *s, int n, 95153018216SPaolo Bonzini uint32_t value) 95253018216SPaolo Bonzini { 95353018216SPaolo Bonzini int head; 95453018216SPaolo Bonzini 95553018216SPaolo Bonzini /* TODO: Real hardware has limited size FIFOs. We have a full 16 entry 95653018216SPaolo Bonzini FIFO fir each sequencer. */ 95753018216SPaolo Bonzini head = (s->fifo[n].state >> 4) & 0xf; 95853018216SPaolo Bonzini if (s->fifo[n].state & STELLARIS_ADC_FIFO_FULL) { 95953018216SPaolo Bonzini s->ostat |= 1 << n; 96053018216SPaolo Bonzini return; 96153018216SPaolo Bonzini } 96253018216SPaolo Bonzini s->fifo[n].data[head] = value; 96353018216SPaolo Bonzini head = (head + 1) & 0xf; 96453018216SPaolo Bonzini s->fifo[n].state &= ~STELLARIS_ADC_FIFO_EMPTY; 96553018216SPaolo Bonzini s->fifo[n].state = (s->fifo[n].state & ~0xf0) | (head << 4); 96653018216SPaolo Bonzini if ((s->fifo[n].state & 0xf) == head) 96753018216SPaolo Bonzini s->fifo[n].state |= STELLARIS_ADC_FIFO_FULL; 96853018216SPaolo Bonzini } 96953018216SPaolo Bonzini 97053018216SPaolo Bonzini static void stellaris_adc_update(stellaris_adc_state *s) 97153018216SPaolo Bonzini { 97253018216SPaolo Bonzini int level; 97353018216SPaolo Bonzini int n; 97453018216SPaolo Bonzini 97553018216SPaolo Bonzini for (n = 0; n < 4; n++) { 97653018216SPaolo Bonzini level = (s->ris & s->im & (1 << n)) != 0; 97753018216SPaolo Bonzini qemu_set_irq(s->irq[n], level); 97853018216SPaolo Bonzini } 97953018216SPaolo Bonzini } 98053018216SPaolo Bonzini 98153018216SPaolo Bonzini static void stellaris_adc_trigger(void *opaque, int irq, int level) 98253018216SPaolo Bonzini { 98353018216SPaolo Bonzini stellaris_adc_state *s = (stellaris_adc_state *)opaque; 98453018216SPaolo Bonzini int n; 98553018216SPaolo Bonzini 98653018216SPaolo Bonzini for (n = 0; n < 4; n++) { 98753018216SPaolo Bonzini if ((s->actss & (1 << n)) == 0) { 98853018216SPaolo Bonzini continue; 98953018216SPaolo Bonzini } 99053018216SPaolo Bonzini 99153018216SPaolo Bonzini if (((s->emux >> (n * 4)) & 0xff) != 5) { 99253018216SPaolo Bonzini continue; 99353018216SPaolo Bonzini } 99453018216SPaolo Bonzini 99553018216SPaolo Bonzini /* Some applications use the ADC as a random number source, so introduce 99653018216SPaolo Bonzini some variation into the signal. */ 99753018216SPaolo Bonzini s->noise = s->noise * 314159 + 1; 99853018216SPaolo Bonzini /* ??? actual inputs not implemented. Return an arbitrary value. */ 99953018216SPaolo Bonzini stellaris_adc_fifo_write(s, n, 0x200 + ((s->noise >> 16) & 7)); 100053018216SPaolo Bonzini s->ris |= (1 << n); 100153018216SPaolo Bonzini stellaris_adc_update(s); 100253018216SPaolo Bonzini } 100353018216SPaolo Bonzini } 100453018216SPaolo Bonzini 100553018216SPaolo Bonzini static void stellaris_adc_reset(stellaris_adc_state *s) 100653018216SPaolo Bonzini { 100753018216SPaolo Bonzini int n; 100853018216SPaolo Bonzini 100953018216SPaolo Bonzini for (n = 0; n < 4; n++) { 101053018216SPaolo Bonzini s->ssmux[n] = 0; 101153018216SPaolo Bonzini s->ssctl[n] = 0; 101253018216SPaolo Bonzini s->fifo[n].state = STELLARIS_ADC_FIFO_EMPTY; 101353018216SPaolo Bonzini } 101453018216SPaolo Bonzini } 101553018216SPaolo Bonzini 101653018216SPaolo Bonzini static uint64_t stellaris_adc_read(void *opaque, hwaddr offset, 101753018216SPaolo Bonzini unsigned size) 101853018216SPaolo Bonzini { 101953018216SPaolo Bonzini stellaris_adc_state *s = (stellaris_adc_state *)opaque; 102053018216SPaolo Bonzini 102153018216SPaolo Bonzini /* TODO: Implement this. */ 102253018216SPaolo Bonzini if (offset >= 0x40 && offset < 0xc0) { 102353018216SPaolo Bonzini int n; 102453018216SPaolo Bonzini n = (offset - 0x40) >> 5; 102553018216SPaolo Bonzini switch (offset & 0x1f) { 102653018216SPaolo Bonzini case 0x00: /* SSMUX */ 102753018216SPaolo Bonzini return s->ssmux[n]; 102853018216SPaolo Bonzini case 0x04: /* SSCTL */ 102953018216SPaolo Bonzini return s->ssctl[n]; 103053018216SPaolo Bonzini case 0x08: /* SSFIFO */ 103153018216SPaolo Bonzini return stellaris_adc_fifo_read(s, n); 103253018216SPaolo Bonzini case 0x0c: /* SSFSTAT */ 103353018216SPaolo Bonzini return s->fifo[n].state; 103453018216SPaolo Bonzini default: 103553018216SPaolo Bonzini break; 103653018216SPaolo Bonzini } 103753018216SPaolo Bonzini } 103853018216SPaolo Bonzini switch (offset) { 103953018216SPaolo Bonzini case 0x00: /* ACTSS */ 104053018216SPaolo Bonzini return s->actss; 104153018216SPaolo Bonzini case 0x04: /* RIS */ 104253018216SPaolo Bonzini return s->ris; 104353018216SPaolo Bonzini case 0x08: /* IM */ 104453018216SPaolo Bonzini return s->im; 104553018216SPaolo Bonzini case 0x0c: /* ISC */ 104653018216SPaolo Bonzini return s->ris & s->im; 104753018216SPaolo Bonzini case 0x10: /* OSTAT */ 104853018216SPaolo Bonzini return s->ostat; 104953018216SPaolo Bonzini case 0x14: /* EMUX */ 105053018216SPaolo Bonzini return s->emux; 105153018216SPaolo Bonzini case 0x18: /* USTAT */ 105253018216SPaolo Bonzini return s->ustat; 105353018216SPaolo Bonzini case 0x20: /* SSPRI */ 105453018216SPaolo Bonzini return s->sspri; 105553018216SPaolo Bonzini case 0x30: /* SAC */ 105653018216SPaolo Bonzini return s->sac; 105753018216SPaolo Bonzini default: 105853018216SPaolo Bonzini hw_error("strllaris_adc_read: Bad offset 0x%x\n", 105953018216SPaolo Bonzini (int)offset); 106053018216SPaolo Bonzini return 0; 106153018216SPaolo Bonzini } 106253018216SPaolo Bonzini } 106353018216SPaolo Bonzini 106453018216SPaolo Bonzini static void stellaris_adc_write(void *opaque, hwaddr offset, 106553018216SPaolo Bonzini uint64_t value, unsigned size) 106653018216SPaolo Bonzini { 106753018216SPaolo Bonzini stellaris_adc_state *s = (stellaris_adc_state *)opaque; 106853018216SPaolo Bonzini 106953018216SPaolo Bonzini /* TODO: Implement this. */ 107053018216SPaolo Bonzini if (offset >= 0x40 && offset < 0xc0) { 107153018216SPaolo Bonzini int n; 107253018216SPaolo Bonzini n = (offset - 0x40) >> 5; 107353018216SPaolo Bonzini switch (offset & 0x1f) { 107453018216SPaolo Bonzini case 0x00: /* SSMUX */ 107553018216SPaolo Bonzini s->ssmux[n] = value & 0x33333333; 107653018216SPaolo Bonzini return; 107753018216SPaolo Bonzini case 0x04: /* SSCTL */ 107853018216SPaolo Bonzini if (value != 6) { 107953018216SPaolo Bonzini hw_error("ADC: Unimplemented sequence %" PRIx64 "\n", 108053018216SPaolo Bonzini value); 108153018216SPaolo Bonzini } 108253018216SPaolo Bonzini s->ssctl[n] = value; 108353018216SPaolo Bonzini return; 108453018216SPaolo Bonzini default: 108553018216SPaolo Bonzini break; 108653018216SPaolo Bonzini } 108753018216SPaolo Bonzini } 108853018216SPaolo Bonzini switch (offset) { 108953018216SPaolo Bonzini case 0x00: /* ACTSS */ 109053018216SPaolo Bonzini s->actss = value & 0xf; 109153018216SPaolo Bonzini break; 109253018216SPaolo Bonzini case 0x08: /* IM */ 109353018216SPaolo Bonzini s->im = value; 109453018216SPaolo Bonzini break; 109553018216SPaolo Bonzini case 0x0c: /* ISC */ 109653018216SPaolo Bonzini s->ris &= ~value; 109753018216SPaolo Bonzini break; 109853018216SPaolo Bonzini case 0x10: /* OSTAT */ 109953018216SPaolo Bonzini s->ostat &= ~value; 110053018216SPaolo Bonzini break; 110153018216SPaolo Bonzini case 0x14: /* EMUX */ 110253018216SPaolo Bonzini s->emux = value; 110353018216SPaolo Bonzini break; 110453018216SPaolo Bonzini case 0x18: /* USTAT */ 110553018216SPaolo Bonzini s->ustat &= ~value; 110653018216SPaolo Bonzini break; 110753018216SPaolo Bonzini case 0x20: /* SSPRI */ 110853018216SPaolo Bonzini s->sspri = value; 110953018216SPaolo Bonzini break; 111053018216SPaolo Bonzini case 0x28: /* PSSI */ 111153018216SPaolo Bonzini hw_error("Not implemented: ADC sample initiate\n"); 111253018216SPaolo Bonzini break; 111353018216SPaolo Bonzini case 0x30: /* SAC */ 111453018216SPaolo Bonzini s->sac = value; 111553018216SPaolo Bonzini break; 111653018216SPaolo Bonzini default: 111753018216SPaolo Bonzini hw_error("stellaris_adc_write: Bad offset 0x%x\n", (int)offset); 111853018216SPaolo Bonzini } 111953018216SPaolo Bonzini stellaris_adc_update(s); 112053018216SPaolo Bonzini } 112153018216SPaolo Bonzini 112253018216SPaolo Bonzini static const MemoryRegionOps stellaris_adc_ops = { 112353018216SPaolo Bonzini .read = stellaris_adc_read, 112453018216SPaolo Bonzini .write = stellaris_adc_write, 112553018216SPaolo Bonzini .endianness = DEVICE_NATIVE_ENDIAN, 112653018216SPaolo Bonzini }; 112753018216SPaolo Bonzini 112853018216SPaolo Bonzini static const VMStateDescription vmstate_stellaris_adc = { 112953018216SPaolo Bonzini .name = "stellaris_adc", 113053018216SPaolo Bonzini .version_id = 1, 113153018216SPaolo Bonzini .minimum_version_id = 1, 113253018216SPaolo Bonzini .fields = (VMStateField[]) { 113353018216SPaolo Bonzini VMSTATE_UINT32(actss, stellaris_adc_state), 113453018216SPaolo Bonzini VMSTATE_UINT32(ris, stellaris_adc_state), 113553018216SPaolo Bonzini VMSTATE_UINT32(im, stellaris_adc_state), 113653018216SPaolo Bonzini VMSTATE_UINT32(emux, stellaris_adc_state), 113753018216SPaolo Bonzini VMSTATE_UINT32(ostat, stellaris_adc_state), 113853018216SPaolo Bonzini VMSTATE_UINT32(ustat, stellaris_adc_state), 113953018216SPaolo Bonzini VMSTATE_UINT32(sspri, stellaris_adc_state), 114053018216SPaolo Bonzini VMSTATE_UINT32(sac, stellaris_adc_state), 114153018216SPaolo Bonzini VMSTATE_UINT32(fifo[0].state, stellaris_adc_state), 114253018216SPaolo Bonzini VMSTATE_UINT32_ARRAY(fifo[0].data, stellaris_adc_state, 16), 114353018216SPaolo Bonzini VMSTATE_UINT32(ssmux[0], stellaris_adc_state), 114453018216SPaolo Bonzini VMSTATE_UINT32(ssctl[0], stellaris_adc_state), 114553018216SPaolo Bonzini VMSTATE_UINT32(fifo[1].state, stellaris_adc_state), 114653018216SPaolo Bonzini VMSTATE_UINT32_ARRAY(fifo[1].data, stellaris_adc_state, 16), 114753018216SPaolo Bonzini VMSTATE_UINT32(ssmux[1], stellaris_adc_state), 114853018216SPaolo Bonzini VMSTATE_UINT32(ssctl[1], stellaris_adc_state), 114953018216SPaolo Bonzini VMSTATE_UINT32(fifo[2].state, stellaris_adc_state), 115053018216SPaolo Bonzini VMSTATE_UINT32_ARRAY(fifo[2].data, stellaris_adc_state, 16), 115153018216SPaolo Bonzini VMSTATE_UINT32(ssmux[2], stellaris_adc_state), 115253018216SPaolo Bonzini VMSTATE_UINT32(ssctl[2], stellaris_adc_state), 115353018216SPaolo Bonzini VMSTATE_UINT32(fifo[3].state, stellaris_adc_state), 115453018216SPaolo Bonzini VMSTATE_UINT32_ARRAY(fifo[3].data, stellaris_adc_state, 16), 115553018216SPaolo Bonzini VMSTATE_UINT32(ssmux[3], stellaris_adc_state), 115653018216SPaolo Bonzini VMSTATE_UINT32(ssctl[3], stellaris_adc_state), 115753018216SPaolo Bonzini VMSTATE_UINT32(noise, stellaris_adc_state), 115853018216SPaolo Bonzini VMSTATE_END_OF_LIST() 115953018216SPaolo Bonzini } 116053018216SPaolo Bonzini }; 116153018216SPaolo Bonzini 116215c4fff5Sxiaoqiang.zhao static void stellaris_adc_init(Object *obj) 116353018216SPaolo Bonzini { 116415c4fff5Sxiaoqiang.zhao DeviceState *dev = DEVICE(obj); 116515c4fff5Sxiaoqiang.zhao stellaris_adc_state *s = STELLARIS_ADC(obj); 116615c4fff5Sxiaoqiang.zhao SysBusDevice *sbd = SYS_BUS_DEVICE(obj); 116753018216SPaolo Bonzini int n; 116853018216SPaolo Bonzini 116953018216SPaolo Bonzini for (n = 0; n < 4; n++) { 11707df7f67aSAndreas Färber sysbus_init_irq(sbd, &s->irq[n]); 117153018216SPaolo Bonzini } 117253018216SPaolo Bonzini 117315c4fff5Sxiaoqiang.zhao memory_region_init_io(&s->iomem, obj, &stellaris_adc_ops, s, 117453018216SPaolo Bonzini "adc", 0x1000); 11757df7f67aSAndreas Färber sysbus_init_mmio(sbd, &s->iomem); 117653018216SPaolo Bonzini stellaris_adc_reset(s); 11777df7f67aSAndreas Färber qdev_init_gpio_in(dev, stellaris_adc_trigger, 1); 117853018216SPaolo Bonzini } 117953018216SPaolo Bonzini 1180d69ffb5bSMichael Davidsaver static 1181d69ffb5bSMichael Davidsaver void do_sys_reset(void *opaque, int n, int level) 1182d69ffb5bSMichael Davidsaver { 1183d69ffb5bSMichael Davidsaver if (level) { 1184d69ffb5bSMichael Davidsaver qemu_system_reset_request(); 1185d69ffb5bSMichael Davidsaver } 1186d69ffb5bSMichael Davidsaver } 1187d69ffb5bSMichael Davidsaver 118853018216SPaolo Bonzini /* Board init. */ 118953018216SPaolo Bonzini static stellaris_board_info stellaris_boards[] = { 119053018216SPaolo Bonzini { "LM3S811EVB", 119153018216SPaolo Bonzini 0, 119253018216SPaolo Bonzini 0x0032000e, 119353018216SPaolo Bonzini 0x001f001f, /* dc0 */ 119453018216SPaolo Bonzini 0x001132bf, 119553018216SPaolo Bonzini 0x01071013, 119653018216SPaolo Bonzini 0x3f0f01ff, 119753018216SPaolo Bonzini 0x0000001f, 119853018216SPaolo Bonzini BP_OLED_I2C 119953018216SPaolo Bonzini }, 120053018216SPaolo Bonzini { "LM3S6965EVB", 120153018216SPaolo Bonzini 0x10010002, 120253018216SPaolo Bonzini 0x1073402e, 120353018216SPaolo Bonzini 0x00ff007f, /* dc0 */ 120453018216SPaolo Bonzini 0x001133ff, 120553018216SPaolo Bonzini 0x030f5317, 120653018216SPaolo Bonzini 0x0f0f87ff, 120753018216SPaolo Bonzini 0x5000007f, 120853018216SPaolo Bonzini BP_OLED_SSI | BP_GAMEPAD 120953018216SPaolo Bonzini } 121053018216SPaolo Bonzini }; 121153018216SPaolo Bonzini 121253018216SPaolo Bonzini static void stellaris_init(const char *kernel_filename, const char *cpu_model, 121353018216SPaolo Bonzini stellaris_board_info *board) 121453018216SPaolo Bonzini { 121553018216SPaolo Bonzini static const int uart_irq[] = {5, 6, 33, 34}; 121653018216SPaolo Bonzini static const int timer_irq[] = {19, 21, 23, 35}; 121753018216SPaolo Bonzini static const uint32_t gpio_addr[7] = 121853018216SPaolo Bonzini { 0x40004000, 0x40005000, 0x40006000, 0x40007000, 121953018216SPaolo Bonzini 0x40024000, 0x40025000, 0x40026000}; 122053018216SPaolo Bonzini static const int gpio_irq[7] = {0, 1, 2, 3, 4, 30, 31}; 122153018216SPaolo Bonzini 122220c59c38SMichael Davidsaver DeviceState *gpio_dev[7], *nvic; 122353018216SPaolo Bonzini qemu_irq gpio_in[7][8]; 122453018216SPaolo Bonzini qemu_irq gpio_out[7][8]; 122553018216SPaolo Bonzini qemu_irq adc; 122653018216SPaolo Bonzini int sram_size; 122753018216SPaolo Bonzini int flash_size; 1228a5c82852SAndreas Färber I2CBus *i2c; 122953018216SPaolo Bonzini DeviceState *dev; 123053018216SPaolo Bonzini int i; 123153018216SPaolo Bonzini int j; 123253018216SPaolo Bonzini 1233fe6ac447SAlistair Francis MemoryRegion *sram = g_new(MemoryRegion, 1); 1234fe6ac447SAlistair Francis MemoryRegion *flash = g_new(MemoryRegion, 1); 1235fe6ac447SAlistair Francis MemoryRegion *system_memory = get_system_memory(); 1236fe6ac447SAlistair Francis 1237fe6ac447SAlistair Francis flash_size = (((board->dc0 & 0xffff) + 1) << 1) * 1024; 1238fe6ac447SAlistair Francis sram_size = ((board->dc0 >> 18) + 1) * 1024; 1239fe6ac447SAlistair Francis 1240fe6ac447SAlistair Francis /* Flash programming is done via the SCU, so pretend it is ROM. */ 1241fe6ac447SAlistair Francis memory_region_init_ram(flash, NULL, "stellaris.flash", flash_size, 1242f8ed85acSMarkus Armbruster &error_fatal); 1243fe6ac447SAlistair Francis vmstate_register_ram_global(flash); 1244fe6ac447SAlistair Francis memory_region_set_readonly(flash, true); 1245fe6ac447SAlistair Francis memory_region_add_subregion(system_memory, 0, flash); 1246fe6ac447SAlistair Francis 1247fe6ac447SAlistair Francis memory_region_init_ram(sram, NULL, "stellaris.sram", sram_size, 1248f8ed85acSMarkus Armbruster &error_fatal); 1249fe6ac447SAlistair Francis vmstate_register_ram_global(sram); 1250fe6ac447SAlistair Francis memory_region_add_subregion(system_memory, 0x20000000, sram); 1251fe6ac447SAlistair Francis 125220c59c38SMichael Davidsaver nvic = armv7m_init(system_memory, flash_size, NUM_IRQ_LINES, 12538b47b7daSAlistair Francis kernel_filename, cpu_model); 125453018216SPaolo Bonzini 1255d69ffb5bSMichael Davidsaver qdev_connect_gpio_out_named(nvic, "SYSRESETREQ", 0, 1256d69ffb5bSMichael Davidsaver qemu_allocate_irq(&do_sys_reset, NULL, 0)); 1257d69ffb5bSMichael Davidsaver 125853018216SPaolo Bonzini if (board->dc1 & (1 << 16)) { 12597df7f67aSAndreas Färber dev = sysbus_create_varargs(TYPE_STELLARIS_ADC, 0x40038000, 126020c59c38SMichael Davidsaver qdev_get_gpio_in(nvic, 14), 126120c59c38SMichael Davidsaver qdev_get_gpio_in(nvic, 15), 126220c59c38SMichael Davidsaver qdev_get_gpio_in(nvic, 16), 126320c59c38SMichael Davidsaver qdev_get_gpio_in(nvic, 17), 126420c59c38SMichael Davidsaver NULL); 126553018216SPaolo Bonzini adc = qdev_get_gpio_in(dev, 0); 126653018216SPaolo Bonzini } else { 126753018216SPaolo Bonzini adc = NULL; 126853018216SPaolo Bonzini } 126953018216SPaolo Bonzini for (i = 0; i < 4; i++) { 127053018216SPaolo Bonzini if (board->dc2 & (0x10000 << i)) { 12718ef1d394SAndreas Färber dev = sysbus_create_simple(TYPE_STELLARIS_GPTM, 127253018216SPaolo Bonzini 0x40030000 + i * 0x1000, 127320c59c38SMichael Davidsaver qdev_get_gpio_in(nvic, timer_irq[i])); 127453018216SPaolo Bonzini /* TODO: This is incorrect, but we get away with it because 127553018216SPaolo Bonzini the ADC output is only ever pulsed. */ 127653018216SPaolo Bonzini qdev_connect_gpio_out(dev, 0, adc); 127753018216SPaolo Bonzini } 127853018216SPaolo Bonzini } 127953018216SPaolo Bonzini 128020c59c38SMichael Davidsaver stellaris_sys_init(0x400fe000, qdev_get_gpio_in(nvic, 28), 128120c59c38SMichael Davidsaver board, nd_table[0].macaddr.a); 128253018216SPaolo Bonzini 128353018216SPaolo Bonzini for (i = 0; i < 7; i++) { 128453018216SPaolo Bonzini if (board->dc4 & (1 << i)) { 128553018216SPaolo Bonzini gpio_dev[i] = sysbus_create_simple("pl061_luminary", gpio_addr[i], 128620c59c38SMichael Davidsaver qdev_get_gpio_in(nvic, 128720c59c38SMichael Davidsaver gpio_irq[i])); 128853018216SPaolo Bonzini for (j = 0; j < 8; j++) { 128953018216SPaolo Bonzini gpio_in[i][j] = qdev_get_gpio_in(gpio_dev[i], j); 129053018216SPaolo Bonzini gpio_out[i][j] = NULL; 129153018216SPaolo Bonzini } 129253018216SPaolo Bonzini } 129353018216SPaolo Bonzini } 129453018216SPaolo Bonzini 129553018216SPaolo Bonzini if (board->dc2 & (1 << 12)) { 129620c59c38SMichael Davidsaver dev = sysbus_create_simple(TYPE_STELLARIS_I2C, 0x40020000, 129720c59c38SMichael Davidsaver qdev_get_gpio_in(nvic, 8)); 1298a5c82852SAndreas Färber i2c = (I2CBus *)qdev_get_child_bus(dev, "i2c"); 129953018216SPaolo Bonzini if (board->peripherals & BP_OLED_I2C) { 130053018216SPaolo Bonzini i2c_create_slave(i2c, "ssd0303", 0x3d); 130153018216SPaolo Bonzini } 130253018216SPaolo Bonzini } 130353018216SPaolo Bonzini 130453018216SPaolo Bonzini for (i = 0; i < 4; i++) { 130553018216SPaolo Bonzini if (board->dc2 & (1 << i)) { 130653018216SPaolo Bonzini sysbus_create_simple("pl011_luminary", 0x4000c000 + i * 0x1000, 130720c59c38SMichael Davidsaver qdev_get_gpio_in(nvic, uart_irq[i])); 130853018216SPaolo Bonzini } 130953018216SPaolo Bonzini } 131053018216SPaolo Bonzini if (board->dc2 & (1 << 4)) { 131120c59c38SMichael Davidsaver dev = sysbus_create_simple("pl022", 0x40008000, 131220c59c38SMichael Davidsaver qdev_get_gpio_in(nvic, 7)); 131353018216SPaolo Bonzini if (board->peripherals & BP_OLED_SSI) { 131453018216SPaolo Bonzini void *bus; 131553018216SPaolo Bonzini DeviceState *sddev; 131653018216SPaolo Bonzini DeviceState *ssddev; 131753018216SPaolo Bonzini 131853018216SPaolo Bonzini /* Some boards have both an OLED controller and SD card connected to 131953018216SPaolo Bonzini * the same SSI port, with the SD card chip select connected to a 132053018216SPaolo Bonzini * GPIO pin. Technically the OLED chip select is connected to the 132153018216SPaolo Bonzini * SSI Fss pin. We do not bother emulating that as both devices 132253018216SPaolo Bonzini * should never be selected simultaneously, and our OLED controller 132353018216SPaolo Bonzini * ignores stray 0xff commands that occur when deselecting the SD 132453018216SPaolo Bonzini * card. 132553018216SPaolo Bonzini */ 132653018216SPaolo Bonzini bus = qdev_get_child_bus(dev, "ssi"); 132753018216SPaolo Bonzini 132853018216SPaolo Bonzini sddev = ssi_create_slave(bus, "ssi-sd"); 132953018216SPaolo Bonzini ssddev = ssi_create_slave(bus, "ssd0323"); 1330de77914eSPeter Crosthwaite gpio_out[GPIO_D][0] = qemu_irq_split( 1331de77914eSPeter Crosthwaite qdev_get_gpio_in_named(sddev, SSI_GPIO_CS, 0), 1332de77914eSPeter Crosthwaite qdev_get_gpio_in_named(ssddev, SSI_GPIO_CS, 0)); 1333de77914eSPeter Crosthwaite gpio_out[GPIO_C][7] = qdev_get_gpio_in(ssddev, 0); 133453018216SPaolo Bonzini 133553018216SPaolo Bonzini /* Make sure the select pin is high. */ 133653018216SPaolo Bonzini qemu_irq_raise(gpio_out[GPIO_D][0]); 133753018216SPaolo Bonzini } 133853018216SPaolo Bonzini } 133953018216SPaolo Bonzini if (board->dc4 & (1 << 28)) { 134053018216SPaolo Bonzini DeviceState *enet; 134153018216SPaolo Bonzini 134253018216SPaolo Bonzini qemu_check_nic_model(&nd_table[0], "stellaris"); 134353018216SPaolo Bonzini 134453018216SPaolo Bonzini enet = qdev_create(NULL, "stellaris_enet"); 134553018216SPaolo Bonzini qdev_set_nic_properties(enet, &nd_table[0]); 134653018216SPaolo Bonzini qdev_init_nofail(enet); 134753018216SPaolo Bonzini sysbus_mmio_map(SYS_BUS_DEVICE(enet), 0, 0x40048000); 134820c59c38SMichael Davidsaver sysbus_connect_irq(SYS_BUS_DEVICE(enet), 0, qdev_get_gpio_in(nvic, 42)); 134953018216SPaolo Bonzini } 135053018216SPaolo Bonzini if (board->peripherals & BP_GAMEPAD) { 135153018216SPaolo Bonzini qemu_irq gpad_irq[5]; 135253018216SPaolo Bonzini static const int gpad_keycode[5] = { 0xc8, 0xd0, 0xcb, 0xcd, 0x1d }; 135353018216SPaolo Bonzini 135453018216SPaolo Bonzini gpad_irq[0] = qemu_irq_invert(gpio_in[GPIO_E][0]); /* up */ 135553018216SPaolo Bonzini gpad_irq[1] = qemu_irq_invert(gpio_in[GPIO_E][1]); /* down */ 135653018216SPaolo Bonzini gpad_irq[2] = qemu_irq_invert(gpio_in[GPIO_E][2]); /* left */ 135753018216SPaolo Bonzini gpad_irq[3] = qemu_irq_invert(gpio_in[GPIO_E][3]); /* right */ 135853018216SPaolo Bonzini gpad_irq[4] = qemu_irq_invert(gpio_in[GPIO_F][1]); /* select */ 135953018216SPaolo Bonzini 136053018216SPaolo Bonzini stellaris_gamepad_init(5, gpad_irq, gpad_keycode); 136153018216SPaolo Bonzini } 136253018216SPaolo Bonzini for (i = 0; i < 7; i++) { 136353018216SPaolo Bonzini if (board->dc4 & (1 << i)) { 136453018216SPaolo Bonzini for (j = 0; j < 8; j++) { 136553018216SPaolo Bonzini if (gpio_out[i][j]) { 136653018216SPaolo Bonzini qdev_connect_gpio_out(gpio_dev[i], j, gpio_out[i][j]); 136753018216SPaolo Bonzini } 136853018216SPaolo Bonzini } 136953018216SPaolo Bonzini } 137053018216SPaolo Bonzini } 137153018216SPaolo Bonzini } 137253018216SPaolo Bonzini 137353018216SPaolo Bonzini /* FIXME: Figure out how to generate these from stellaris_boards. */ 13743ef96221SMarcel Apfelbaum static void lm3s811evb_init(MachineState *machine) 137553018216SPaolo Bonzini { 13763ef96221SMarcel Apfelbaum const char *cpu_model = machine->cpu_model; 13773ef96221SMarcel Apfelbaum const char *kernel_filename = machine->kernel_filename; 137853018216SPaolo Bonzini stellaris_init(kernel_filename, cpu_model, &stellaris_boards[0]); 137953018216SPaolo Bonzini } 138053018216SPaolo Bonzini 13813ef96221SMarcel Apfelbaum static void lm3s6965evb_init(MachineState *machine) 138253018216SPaolo Bonzini { 13833ef96221SMarcel Apfelbaum const char *cpu_model = machine->cpu_model; 13843ef96221SMarcel Apfelbaum const char *kernel_filename = machine->kernel_filename; 138553018216SPaolo Bonzini stellaris_init(kernel_filename, cpu_model, &stellaris_boards[1]); 138653018216SPaolo Bonzini } 138753018216SPaolo Bonzini 13888a661aeaSAndreas Färber static void lm3s811evb_class_init(ObjectClass *oc, void *data) 138953018216SPaolo Bonzini { 13908a661aeaSAndreas Färber MachineClass *mc = MACHINE_CLASS(oc); 13918a661aeaSAndreas Färber 1392e264d29dSEduardo Habkost mc->desc = "Stellaris LM3S811EVB"; 1393e264d29dSEduardo Habkost mc->init = lm3s811evb_init; 139453018216SPaolo Bonzini } 139553018216SPaolo Bonzini 13968a661aeaSAndreas Färber static const TypeInfo lm3s811evb_type = { 13978a661aeaSAndreas Färber .name = MACHINE_TYPE_NAME("lm3s811evb"), 13988a661aeaSAndreas Färber .parent = TYPE_MACHINE, 13998a661aeaSAndreas Färber .class_init = lm3s811evb_class_init, 14008a661aeaSAndreas Färber }; 1401e264d29dSEduardo Habkost 14028a661aeaSAndreas Färber static void lm3s6965evb_class_init(ObjectClass *oc, void *data) 1403e264d29dSEduardo Habkost { 14048a661aeaSAndreas Färber MachineClass *mc = MACHINE_CLASS(oc); 14058a661aeaSAndreas Färber 1406e264d29dSEduardo Habkost mc->desc = "Stellaris LM3S6965EVB"; 1407e264d29dSEduardo Habkost mc->init = lm3s6965evb_init; 1408e264d29dSEduardo Habkost } 1409e264d29dSEduardo Habkost 14108a661aeaSAndreas Färber static const TypeInfo lm3s6965evb_type = { 14118a661aeaSAndreas Färber .name = MACHINE_TYPE_NAME("lm3s6965evb"), 14128a661aeaSAndreas Färber .parent = TYPE_MACHINE, 14138a661aeaSAndreas Färber .class_init = lm3s6965evb_class_init, 14148a661aeaSAndreas Färber }; 14158a661aeaSAndreas Färber 14168a661aeaSAndreas Färber static void stellaris_machine_init(void) 14178a661aeaSAndreas Färber { 14188a661aeaSAndreas Färber type_register_static(&lm3s811evb_type); 14198a661aeaSAndreas Färber type_register_static(&lm3s6965evb_type); 14208a661aeaSAndreas Färber } 14218a661aeaSAndreas Färber 14220e6aac87SEduardo Habkost type_init(stellaris_machine_init) 142353018216SPaolo Bonzini 142453018216SPaolo Bonzini static void stellaris_i2c_class_init(ObjectClass *klass, void *data) 142553018216SPaolo Bonzini { 142615c4fff5Sxiaoqiang.zhao DeviceClass *dc = DEVICE_CLASS(klass); 142753018216SPaolo Bonzini 142815c4fff5Sxiaoqiang.zhao dc->vmsd = &vmstate_stellaris_i2c; 142953018216SPaolo Bonzini } 143053018216SPaolo Bonzini 143153018216SPaolo Bonzini static const TypeInfo stellaris_i2c_info = { 1432d94a4015SAndreas Färber .name = TYPE_STELLARIS_I2C, 143353018216SPaolo Bonzini .parent = TYPE_SYS_BUS_DEVICE, 143453018216SPaolo Bonzini .instance_size = sizeof(stellaris_i2c_state), 143515c4fff5Sxiaoqiang.zhao .instance_init = stellaris_i2c_init, 143653018216SPaolo Bonzini .class_init = stellaris_i2c_class_init, 143753018216SPaolo Bonzini }; 143853018216SPaolo Bonzini 143953018216SPaolo Bonzini static void stellaris_gptm_class_init(ObjectClass *klass, void *data) 144053018216SPaolo Bonzini { 144115c4fff5Sxiaoqiang.zhao DeviceClass *dc = DEVICE_CLASS(klass); 144253018216SPaolo Bonzini 144315c4fff5Sxiaoqiang.zhao dc->vmsd = &vmstate_stellaris_gptm; 144453018216SPaolo Bonzini } 144553018216SPaolo Bonzini 144653018216SPaolo Bonzini static const TypeInfo stellaris_gptm_info = { 14478ef1d394SAndreas Färber .name = TYPE_STELLARIS_GPTM, 144853018216SPaolo Bonzini .parent = TYPE_SYS_BUS_DEVICE, 144953018216SPaolo Bonzini .instance_size = sizeof(gptm_state), 145015c4fff5Sxiaoqiang.zhao .instance_init = stellaris_gptm_init, 145153018216SPaolo Bonzini .class_init = stellaris_gptm_class_init, 145253018216SPaolo Bonzini }; 145353018216SPaolo Bonzini 145453018216SPaolo Bonzini static void stellaris_adc_class_init(ObjectClass *klass, void *data) 145553018216SPaolo Bonzini { 145615c4fff5Sxiaoqiang.zhao DeviceClass *dc = DEVICE_CLASS(klass); 145753018216SPaolo Bonzini 145815c4fff5Sxiaoqiang.zhao dc->vmsd = &vmstate_stellaris_adc; 145953018216SPaolo Bonzini } 146053018216SPaolo Bonzini 146153018216SPaolo Bonzini static const TypeInfo stellaris_adc_info = { 14627df7f67aSAndreas Färber .name = TYPE_STELLARIS_ADC, 146353018216SPaolo Bonzini .parent = TYPE_SYS_BUS_DEVICE, 146453018216SPaolo Bonzini .instance_size = sizeof(stellaris_adc_state), 146515c4fff5Sxiaoqiang.zhao .instance_init = stellaris_adc_init, 146653018216SPaolo Bonzini .class_init = stellaris_adc_class_init, 146753018216SPaolo Bonzini }; 146853018216SPaolo Bonzini 146953018216SPaolo Bonzini static void stellaris_register_types(void) 147053018216SPaolo Bonzini { 147153018216SPaolo Bonzini type_register_static(&stellaris_i2c_info); 147253018216SPaolo Bonzini type_register_static(&stellaris_gptm_info); 147353018216SPaolo Bonzini type_register_static(&stellaris_adc_info); 147453018216SPaolo Bonzini } 147553018216SPaolo Bonzini 147653018216SPaolo Bonzini type_init(stellaris_register_types) 1477