153018216SPaolo Bonzini /* 253018216SPaolo Bonzini * Luminary Micro Stellaris peripherals 353018216SPaolo Bonzini * 453018216SPaolo Bonzini * Copyright (c) 2006 CodeSourcery. 553018216SPaolo Bonzini * Written by Paul Brook 653018216SPaolo Bonzini * 753018216SPaolo Bonzini * This code is licensed under the GPL. 853018216SPaolo Bonzini */ 953018216SPaolo Bonzini 1012b16722SPeter Maydell #include "qemu/osdep.h" 11da34e65cSMarkus Armbruster #include "qapi/error.h" 1253018216SPaolo Bonzini #include "hw/sysbus.h" 138fd06719SAlistair Francis #include "hw/ssi/ssi.h" 1412ec8bd5SPeter Maydell #include "hw/arm/boot.h" 1553018216SPaolo Bonzini #include "qemu/timer.h" 160d09e41aSPaolo Bonzini #include "hw/i2c/i2c.h" 1753018216SPaolo Bonzini #include "net/net.h" 1853018216SPaolo Bonzini #include "hw/boards.h" 1903dd024fSPaolo Bonzini #include "qemu/log.h" 2053018216SPaolo Bonzini #include "exec/address-spaces.h" 2154d31236SMarkus Armbruster #include "sysemu/runstate.h" 22d69ffb5bSMichael Davidsaver #include "sysemu/sysemu.h" 23f04d4465SPeter Maydell #include "hw/arm/armv7m.h" 24f0d1d2c1Sxiaoqiang zhao #include "hw/char/pl011.h" 2598fa3327SPhilippe Mathieu-Daudé #include "hw/input/gamepad.h" 2664552b6bSMarkus Armbruster #include "hw/irq.h" 27566528f8SMichel Heily #include "hw/watchdog/cmsdk-apb-watchdog.h" 28d6454270SMarkus Armbruster #include "migration/vmstate.h" 29aecfbbc9SPeter Maydell #include "hw/misc/unimp.h" 30ba1ba5ccSIgor Mammedov #include "cpu.h" 3153018216SPaolo Bonzini 3253018216SPaolo Bonzini #define GPIO_A 0 3353018216SPaolo Bonzini #define GPIO_B 1 3453018216SPaolo Bonzini #define GPIO_C 2 3553018216SPaolo Bonzini #define GPIO_D 3 3653018216SPaolo Bonzini #define GPIO_E 4 3753018216SPaolo Bonzini #define GPIO_F 5 3853018216SPaolo Bonzini #define GPIO_G 6 3953018216SPaolo Bonzini 4053018216SPaolo Bonzini #define BP_OLED_I2C 0x01 4153018216SPaolo Bonzini #define BP_OLED_SSI 0x02 4253018216SPaolo Bonzini #define BP_GAMEPAD 0x04 4353018216SPaolo Bonzini 448b47b7daSAlistair Francis #define NUM_IRQ_LINES 64 458b47b7daSAlistair Francis 4653018216SPaolo Bonzini typedef const struct { 4753018216SPaolo Bonzini const char *name; 4853018216SPaolo Bonzini uint32_t did0; 4953018216SPaolo Bonzini uint32_t did1; 5053018216SPaolo Bonzini uint32_t dc0; 5153018216SPaolo Bonzini uint32_t dc1; 5253018216SPaolo Bonzini uint32_t dc2; 5353018216SPaolo Bonzini uint32_t dc3; 5453018216SPaolo Bonzini uint32_t dc4; 5553018216SPaolo Bonzini uint32_t peripherals; 5653018216SPaolo Bonzini } stellaris_board_info; 5753018216SPaolo Bonzini 5853018216SPaolo Bonzini /* General purpose timer module. */ 5953018216SPaolo Bonzini 608ef1d394SAndreas Färber #define TYPE_STELLARIS_GPTM "stellaris-gptm" 618ef1d394SAndreas Färber #define STELLARIS_GPTM(obj) \ 628ef1d394SAndreas Färber OBJECT_CHECK(gptm_state, (obj), TYPE_STELLARIS_GPTM) 638ef1d394SAndreas Färber 6453018216SPaolo Bonzini typedef struct gptm_state { 658ef1d394SAndreas Färber SysBusDevice parent_obj; 668ef1d394SAndreas Färber 6753018216SPaolo Bonzini MemoryRegion iomem; 6853018216SPaolo Bonzini uint32_t config; 6953018216SPaolo Bonzini uint32_t mode[2]; 7053018216SPaolo Bonzini uint32_t control; 7153018216SPaolo Bonzini uint32_t state; 7253018216SPaolo Bonzini uint32_t mask; 7353018216SPaolo Bonzini uint32_t load[2]; 7453018216SPaolo Bonzini uint32_t match[2]; 7553018216SPaolo Bonzini uint32_t prescale[2]; 7653018216SPaolo Bonzini uint32_t match_prescale[2]; 7753018216SPaolo Bonzini uint32_t rtc; 7853018216SPaolo Bonzini int64_t tick[2]; 7953018216SPaolo Bonzini struct gptm_state *opaque[2]; 8053018216SPaolo Bonzini QEMUTimer *timer[2]; 8153018216SPaolo Bonzini /* The timers have an alternate output used to trigger the ADC. */ 8253018216SPaolo Bonzini qemu_irq trigger; 8353018216SPaolo Bonzini qemu_irq irq; 8453018216SPaolo Bonzini } gptm_state; 8553018216SPaolo Bonzini 8653018216SPaolo Bonzini static void gptm_update_irq(gptm_state *s) 8753018216SPaolo Bonzini { 8853018216SPaolo Bonzini int level; 8953018216SPaolo Bonzini level = (s->state & s->mask) != 0; 9053018216SPaolo Bonzini qemu_set_irq(s->irq, level); 9153018216SPaolo Bonzini } 9253018216SPaolo Bonzini 9353018216SPaolo Bonzini static void gptm_stop(gptm_state *s, int n) 9453018216SPaolo Bonzini { 95bc72ad67SAlex Bligh timer_del(s->timer[n]); 9653018216SPaolo Bonzini } 9753018216SPaolo Bonzini 9853018216SPaolo Bonzini static void gptm_reload(gptm_state *s, int n, int reset) 9953018216SPaolo Bonzini { 10053018216SPaolo Bonzini int64_t tick; 10153018216SPaolo Bonzini if (reset) 102bc72ad67SAlex Bligh tick = qemu_clock_get_ns(QEMU_CLOCK_VIRTUAL); 10353018216SPaolo Bonzini else 10453018216SPaolo Bonzini tick = s->tick[n]; 10553018216SPaolo Bonzini 10653018216SPaolo Bonzini if (s->config == 0) { 10753018216SPaolo Bonzini /* 32-bit CountDown. */ 10853018216SPaolo Bonzini uint32_t count; 10953018216SPaolo Bonzini count = s->load[0] | (s->load[1] << 16); 11053018216SPaolo Bonzini tick += (int64_t)count * system_clock_scale; 11153018216SPaolo Bonzini } else if (s->config == 1) { 11253018216SPaolo Bonzini /* 32-bit RTC. 1Hz tick. */ 11373bcb24dSRutuja Shah tick += NANOSECONDS_PER_SECOND; 11453018216SPaolo Bonzini } else if (s->mode[n] == 0xa) { 11553018216SPaolo Bonzini /* PWM mode. Not implemented. */ 11653018216SPaolo Bonzini } else { 117df3692e0SPeter Maydell qemu_log_mask(LOG_UNIMP, 118df3692e0SPeter Maydell "GPTM: 16-bit timer mode unimplemented: 0x%x\n", 119df3692e0SPeter Maydell s->mode[n]); 120df3692e0SPeter Maydell return; 12153018216SPaolo Bonzini } 12253018216SPaolo Bonzini s->tick[n] = tick; 123bc72ad67SAlex Bligh timer_mod(s->timer[n], tick); 12453018216SPaolo Bonzini } 12553018216SPaolo Bonzini 12653018216SPaolo Bonzini static void gptm_tick(void *opaque) 12753018216SPaolo Bonzini { 12853018216SPaolo Bonzini gptm_state **p = (gptm_state **)opaque; 12953018216SPaolo Bonzini gptm_state *s; 13053018216SPaolo Bonzini int n; 13153018216SPaolo Bonzini 13253018216SPaolo Bonzini s = *p; 13353018216SPaolo Bonzini n = p - s->opaque; 13453018216SPaolo Bonzini if (s->config == 0) { 13553018216SPaolo Bonzini s->state |= 1; 13653018216SPaolo Bonzini if ((s->control & 0x20)) { 13753018216SPaolo Bonzini /* Output trigger. */ 13853018216SPaolo Bonzini qemu_irq_pulse(s->trigger); 13953018216SPaolo Bonzini } 14053018216SPaolo Bonzini if (s->mode[0] & 1) { 14153018216SPaolo Bonzini /* One-shot. */ 14253018216SPaolo Bonzini s->control &= ~1; 14353018216SPaolo Bonzini } else { 14453018216SPaolo Bonzini /* Periodic. */ 14553018216SPaolo Bonzini gptm_reload(s, 0, 0); 14653018216SPaolo Bonzini } 14753018216SPaolo Bonzini } else if (s->config == 1) { 14853018216SPaolo Bonzini /* RTC. */ 14953018216SPaolo Bonzini uint32_t match; 15053018216SPaolo Bonzini s->rtc++; 15153018216SPaolo Bonzini match = s->match[0] | (s->match[1] << 16); 15253018216SPaolo Bonzini if (s->rtc > match) 15353018216SPaolo Bonzini s->rtc = 0; 15453018216SPaolo Bonzini if (s->rtc == 0) { 15553018216SPaolo Bonzini s->state |= 8; 15653018216SPaolo Bonzini } 15753018216SPaolo Bonzini gptm_reload(s, 0, 0); 15853018216SPaolo Bonzini } else if (s->mode[n] == 0xa) { 15953018216SPaolo Bonzini /* PWM mode. Not implemented. */ 16053018216SPaolo Bonzini } else { 161df3692e0SPeter Maydell qemu_log_mask(LOG_UNIMP, 162df3692e0SPeter Maydell "GPTM: 16-bit timer mode unimplemented: 0x%x\n", 163df3692e0SPeter Maydell s->mode[n]); 16453018216SPaolo Bonzini } 16553018216SPaolo Bonzini gptm_update_irq(s); 16653018216SPaolo Bonzini } 16753018216SPaolo Bonzini 16853018216SPaolo Bonzini static uint64_t gptm_read(void *opaque, hwaddr offset, 16953018216SPaolo Bonzini unsigned size) 17053018216SPaolo Bonzini { 17153018216SPaolo Bonzini gptm_state *s = (gptm_state *)opaque; 17253018216SPaolo Bonzini 17353018216SPaolo Bonzini switch (offset) { 17453018216SPaolo Bonzini case 0x00: /* CFG */ 17553018216SPaolo Bonzini return s->config; 17653018216SPaolo Bonzini case 0x04: /* TAMR */ 17753018216SPaolo Bonzini return s->mode[0]; 17853018216SPaolo Bonzini case 0x08: /* TBMR */ 17953018216SPaolo Bonzini return s->mode[1]; 18053018216SPaolo Bonzini case 0x0c: /* CTL */ 18153018216SPaolo Bonzini return s->control; 18253018216SPaolo Bonzini case 0x18: /* IMR */ 18353018216SPaolo Bonzini return s->mask; 18453018216SPaolo Bonzini case 0x1c: /* RIS */ 18553018216SPaolo Bonzini return s->state; 18653018216SPaolo Bonzini case 0x20: /* MIS */ 18753018216SPaolo Bonzini return s->state & s->mask; 18853018216SPaolo Bonzini case 0x24: /* CR */ 18953018216SPaolo Bonzini return 0; 19053018216SPaolo Bonzini case 0x28: /* TAILR */ 19153018216SPaolo Bonzini return s->load[0] | ((s->config < 4) ? (s->load[1] << 16) : 0); 19253018216SPaolo Bonzini case 0x2c: /* TBILR */ 19353018216SPaolo Bonzini return s->load[1]; 19453018216SPaolo Bonzini case 0x30: /* TAMARCHR */ 19553018216SPaolo Bonzini return s->match[0] | ((s->config < 4) ? (s->match[1] << 16) : 0); 19653018216SPaolo Bonzini case 0x34: /* TBMATCHR */ 19753018216SPaolo Bonzini return s->match[1]; 19853018216SPaolo Bonzini case 0x38: /* TAPR */ 19953018216SPaolo Bonzini return s->prescale[0]; 20053018216SPaolo Bonzini case 0x3c: /* TBPR */ 20153018216SPaolo Bonzini return s->prescale[1]; 20253018216SPaolo Bonzini case 0x40: /* TAPMR */ 20353018216SPaolo Bonzini return s->match_prescale[0]; 20453018216SPaolo Bonzini case 0x44: /* TBPMR */ 20553018216SPaolo Bonzini return s->match_prescale[1]; 20653018216SPaolo Bonzini case 0x48: /* TAR */ 2071a791721SPeter Maydell if (s->config == 1) { 20853018216SPaolo Bonzini return s->rtc; 2091a791721SPeter Maydell } 2101a791721SPeter Maydell qemu_log_mask(LOG_UNIMP, 2119492e4b2SPhilippe Mathieu-Daudé "GPTM: read of TAR but timer read not supported\n"); 2121a791721SPeter Maydell return 0; 21353018216SPaolo Bonzini case 0x4c: /* TBR */ 2141a791721SPeter Maydell qemu_log_mask(LOG_UNIMP, 2159492e4b2SPhilippe Mathieu-Daudé "GPTM: read of TBR but timer read not supported\n"); 2161a791721SPeter Maydell return 0; 21753018216SPaolo Bonzini default: 2181a791721SPeter Maydell qemu_log_mask(LOG_GUEST_ERROR, 219d29183d3SPhilippe Mathieu-Daudé "GPTM: read at bad offset 0x02%" HWADDR_PRIx "\n", 220d29183d3SPhilippe Mathieu-Daudé offset); 22153018216SPaolo Bonzini return 0; 22253018216SPaolo Bonzini } 22353018216SPaolo Bonzini } 22453018216SPaolo Bonzini 22553018216SPaolo Bonzini static void gptm_write(void *opaque, hwaddr offset, 22653018216SPaolo Bonzini uint64_t value, unsigned size) 22753018216SPaolo Bonzini { 22853018216SPaolo Bonzini gptm_state *s = (gptm_state *)opaque; 22953018216SPaolo Bonzini uint32_t oldval; 23053018216SPaolo Bonzini 23153018216SPaolo Bonzini /* The timers should be disabled before changing the configuration. 23253018216SPaolo Bonzini We take advantage of this and defer everything until the timer 23353018216SPaolo Bonzini is enabled. */ 23453018216SPaolo Bonzini switch (offset) { 23553018216SPaolo Bonzini case 0x00: /* CFG */ 23653018216SPaolo Bonzini s->config = value; 23753018216SPaolo Bonzini break; 23853018216SPaolo Bonzini case 0x04: /* TAMR */ 23953018216SPaolo Bonzini s->mode[0] = value; 24053018216SPaolo Bonzini break; 24153018216SPaolo Bonzini case 0x08: /* TBMR */ 24253018216SPaolo Bonzini s->mode[1] = value; 24353018216SPaolo Bonzini break; 24453018216SPaolo Bonzini case 0x0c: /* CTL */ 24553018216SPaolo Bonzini oldval = s->control; 24653018216SPaolo Bonzini s->control = value; 24753018216SPaolo Bonzini /* TODO: Implement pause. */ 24853018216SPaolo Bonzini if ((oldval ^ value) & 1) { 24953018216SPaolo Bonzini if (value & 1) { 25053018216SPaolo Bonzini gptm_reload(s, 0, 1); 25153018216SPaolo Bonzini } else { 25253018216SPaolo Bonzini gptm_stop(s, 0); 25353018216SPaolo Bonzini } 25453018216SPaolo Bonzini } 25553018216SPaolo Bonzini if (((oldval ^ value) & 0x100) && s->config >= 4) { 25653018216SPaolo Bonzini if (value & 0x100) { 25753018216SPaolo Bonzini gptm_reload(s, 1, 1); 25853018216SPaolo Bonzini } else { 25953018216SPaolo Bonzini gptm_stop(s, 1); 26053018216SPaolo Bonzini } 26153018216SPaolo Bonzini } 26253018216SPaolo Bonzini break; 26353018216SPaolo Bonzini case 0x18: /* IMR */ 26453018216SPaolo Bonzini s->mask = value & 0x77; 26553018216SPaolo Bonzini gptm_update_irq(s); 26653018216SPaolo Bonzini break; 26753018216SPaolo Bonzini case 0x24: /* CR */ 26853018216SPaolo Bonzini s->state &= ~value; 26953018216SPaolo Bonzini break; 27053018216SPaolo Bonzini case 0x28: /* TAILR */ 27153018216SPaolo Bonzini s->load[0] = value & 0xffff; 27253018216SPaolo Bonzini if (s->config < 4) { 27353018216SPaolo Bonzini s->load[1] = value >> 16; 27453018216SPaolo Bonzini } 27553018216SPaolo Bonzini break; 27653018216SPaolo Bonzini case 0x2c: /* TBILR */ 27753018216SPaolo Bonzini s->load[1] = value & 0xffff; 27853018216SPaolo Bonzini break; 27953018216SPaolo Bonzini case 0x30: /* TAMARCHR */ 28053018216SPaolo Bonzini s->match[0] = value & 0xffff; 28153018216SPaolo Bonzini if (s->config < 4) { 28253018216SPaolo Bonzini s->match[1] = value >> 16; 28353018216SPaolo Bonzini } 28453018216SPaolo Bonzini break; 28553018216SPaolo Bonzini case 0x34: /* TBMATCHR */ 28653018216SPaolo Bonzini s->match[1] = value >> 16; 28753018216SPaolo Bonzini break; 28853018216SPaolo Bonzini case 0x38: /* TAPR */ 28953018216SPaolo Bonzini s->prescale[0] = value; 29053018216SPaolo Bonzini break; 29153018216SPaolo Bonzini case 0x3c: /* TBPR */ 29253018216SPaolo Bonzini s->prescale[1] = value; 29353018216SPaolo Bonzini break; 29453018216SPaolo Bonzini case 0x40: /* TAPMR */ 29553018216SPaolo Bonzini s->match_prescale[0] = value; 29653018216SPaolo Bonzini break; 29753018216SPaolo Bonzini case 0x44: /* TBPMR */ 29853018216SPaolo Bonzini s->match_prescale[0] = value; 29953018216SPaolo Bonzini break; 30053018216SPaolo Bonzini default: 301df3692e0SPeter Maydell qemu_log_mask(LOG_GUEST_ERROR, 302d29183d3SPhilippe Mathieu-Daudé "GPTM: write at bad offset 0x02%" HWADDR_PRIx "\n", 303d29183d3SPhilippe Mathieu-Daudé offset); 30453018216SPaolo Bonzini } 30553018216SPaolo Bonzini gptm_update_irq(s); 30653018216SPaolo Bonzini } 30753018216SPaolo Bonzini 30853018216SPaolo Bonzini static const MemoryRegionOps gptm_ops = { 30953018216SPaolo Bonzini .read = gptm_read, 31053018216SPaolo Bonzini .write = gptm_write, 31153018216SPaolo Bonzini .endianness = DEVICE_NATIVE_ENDIAN, 31253018216SPaolo Bonzini }; 31353018216SPaolo Bonzini 31453018216SPaolo Bonzini static const VMStateDescription vmstate_stellaris_gptm = { 31553018216SPaolo Bonzini .name = "stellaris_gptm", 31653018216SPaolo Bonzini .version_id = 1, 31753018216SPaolo Bonzini .minimum_version_id = 1, 31853018216SPaolo Bonzini .fields = (VMStateField[]) { 31953018216SPaolo Bonzini VMSTATE_UINT32(config, gptm_state), 32053018216SPaolo Bonzini VMSTATE_UINT32_ARRAY(mode, gptm_state, 2), 32153018216SPaolo Bonzini VMSTATE_UINT32(control, gptm_state), 32253018216SPaolo Bonzini VMSTATE_UINT32(state, gptm_state), 32353018216SPaolo Bonzini VMSTATE_UINT32(mask, gptm_state), 32453018216SPaolo Bonzini VMSTATE_UNUSED(8), 32553018216SPaolo Bonzini VMSTATE_UINT32_ARRAY(load, gptm_state, 2), 32653018216SPaolo Bonzini VMSTATE_UINT32_ARRAY(match, gptm_state, 2), 32753018216SPaolo Bonzini VMSTATE_UINT32_ARRAY(prescale, gptm_state, 2), 32853018216SPaolo Bonzini VMSTATE_UINT32_ARRAY(match_prescale, gptm_state, 2), 32953018216SPaolo Bonzini VMSTATE_UINT32(rtc, gptm_state), 33053018216SPaolo Bonzini VMSTATE_INT64_ARRAY(tick, gptm_state, 2), 331e720677eSPaolo Bonzini VMSTATE_TIMER_PTR_ARRAY(timer, gptm_state, 2), 33253018216SPaolo Bonzini VMSTATE_END_OF_LIST() 33353018216SPaolo Bonzini } 33453018216SPaolo Bonzini }; 33553018216SPaolo Bonzini 33615c4fff5Sxiaoqiang.zhao static void stellaris_gptm_init(Object *obj) 33753018216SPaolo Bonzini { 33815c4fff5Sxiaoqiang.zhao DeviceState *dev = DEVICE(obj); 33915c4fff5Sxiaoqiang.zhao gptm_state *s = STELLARIS_GPTM(obj); 34015c4fff5Sxiaoqiang.zhao SysBusDevice *sbd = SYS_BUS_DEVICE(obj); 34153018216SPaolo Bonzini 3428ef1d394SAndreas Färber sysbus_init_irq(sbd, &s->irq); 3438ef1d394SAndreas Färber qdev_init_gpio_out(dev, &s->trigger, 1); 34453018216SPaolo Bonzini 34515c4fff5Sxiaoqiang.zhao memory_region_init_io(&s->iomem, obj, &gptm_ops, s, 34653018216SPaolo Bonzini "gptm", 0x1000); 3478ef1d394SAndreas Färber sysbus_init_mmio(sbd, &s->iomem); 34853018216SPaolo Bonzini 34953018216SPaolo Bonzini s->opaque[0] = s->opaque[1] = s; 350af6c91b4SPan Nengyuan } 351af6c91b4SPan Nengyuan 352af6c91b4SPan Nengyuan static void stellaris_gptm_realize(DeviceState *dev, Error **errp) 353af6c91b4SPan Nengyuan { 354af6c91b4SPan Nengyuan gptm_state *s = STELLARIS_GPTM(dev); 355bc72ad67SAlex Bligh s->timer[0] = timer_new_ns(QEMU_CLOCK_VIRTUAL, gptm_tick, &s->opaque[0]); 356bc72ad67SAlex Bligh s->timer[1] = timer_new_ns(QEMU_CLOCK_VIRTUAL, gptm_tick, &s->opaque[1]); 35753018216SPaolo Bonzini } 35853018216SPaolo Bonzini 35953018216SPaolo Bonzini /* System controller. */ 36053018216SPaolo Bonzini 36153018216SPaolo Bonzini typedef struct { 36253018216SPaolo Bonzini MemoryRegion iomem; 36353018216SPaolo Bonzini uint32_t pborctl; 36453018216SPaolo Bonzini uint32_t ldopctl; 36553018216SPaolo Bonzini uint32_t int_status; 36653018216SPaolo Bonzini uint32_t int_mask; 36753018216SPaolo Bonzini uint32_t resc; 36853018216SPaolo Bonzini uint32_t rcc; 36953018216SPaolo Bonzini uint32_t rcc2; 37053018216SPaolo Bonzini uint32_t rcgc[3]; 37153018216SPaolo Bonzini uint32_t scgc[3]; 37253018216SPaolo Bonzini uint32_t dcgc[3]; 37353018216SPaolo Bonzini uint32_t clkvclr; 37453018216SPaolo Bonzini uint32_t ldoarst; 37553018216SPaolo Bonzini uint32_t user0; 37653018216SPaolo Bonzini uint32_t user1; 37753018216SPaolo Bonzini qemu_irq irq; 37853018216SPaolo Bonzini stellaris_board_info *board; 37953018216SPaolo Bonzini } ssys_state; 38053018216SPaolo Bonzini 38153018216SPaolo Bonzini static void ssys_update(ssys_state *s) 38253018216SPaolo Bonzini { 38353018216SPaolo Bonzini qemu_set_irq(s->irq, (s->int_status & s->int_mask) != 0); 38453018216SPaolo Bonzini } 38553018216SPaolo Bonzini 38653018216SPaolo Bonzini static uint32_t pllcfg_sandstorm[16] = { 38753018216SPaolo Bonzini 0x31c0, /* 1 Mhz */ 38853018216SPaolo Bonzini 0x1ae0, /* 1.8432 Mhz */ 38953018216SPaolo Bonzini 0x18c0, /* 2 Mhz */ 39053018216SPaolo Bonzini 0xd573, /* 2.4576 Mhz */ 39153018216SPaolo Bonzini 0x37a6, /* 3.57954 Mhz */ 39253018216SPaolo Bonzini 0x1ae2, /* 3.6864 Mhz */ 39353018216SPaolo Bonzini 0x0c40, /* 4 Mhz */ 39453018216SPaolo Bonzini 0x98bc, /* 4.906 Mhz */ 39553018216SPaolo Bonzini 0x935b, /* 4.9152 Mhz */ 39653018216SPaolo Bonzini 0x09c0, /* 5 Mhz */ 39753018216SPaolo Bonzini 0x4dee, /* 5.12 Mhz */ 39853018216SPaolo Bonzini 0x0c41, /* 6 Mhz */ 39953018216SPaolo Bonzini 0x75db, /* 6.144 Mhz */ 40053018216SPaolo Bonzini 0x1ae6, /* 7.3728 Mhz */ 40153018216SPaolo Bonzini 0x0600, /* 8 Mhz */ 40253018216SPaolo Bonzini 0x585b /* 8.192 Mhz */ 40353018216SPaolo Bonzini }; 40453018216SPaolo Bonzini 40553018216SPaolo Bonzini static uint32_t pllcfg_fury[16] = { 40653018216SPaolo Bonzini 0x3200, /* 1 Mhz */ 40753018216SPaolo Bonzini 0x1b20, /* 1.8432 Mhz */ 40853018216SPaolo Bonzini 0x1900, /* 2 Mhz */ 40953018216SPaolo Bonzini 0xf42b, /* 2.4576 Mhz */ 41053018216SPaolo Bonzini 0x37e3, /* 3.57954 Mhz */ 41153018216SPaolo Bonzini 0x1b21, /* 3.6864 Mhz */ 41253018216SPaolo Bonzini 0x0c80, /* 4 Mhz */ 41353018216SPaolo Bonzini 0x98ee, /* 4.906 Mhz */ 41453018216SPaolo Bonzini 0xd5b4, /* 4.9152 Mhz */ 41553018216SPaolo Bonzini 0x0a00, /* 5 Mhz */ 41653018216SPaolo Bonzini 0x4e27, /* 5.12 Mhz */ 41753018216SPaolo Bonzini 0x1902, /* 6 Mhz */ 41853018216SPaolo Bonzini 0xec1c, /* 6.144 Mhz */ 41953018216SPaolo Bonzini 0x1b23, /* 7.3728 Mhz */ 42053018216SPaolo Bonzini 0x0640, /* 8 Mhz */ 42153018216SPaolo Bonzini 0xb11c /* 8.192 Mhz */ 42253018216SPaolo Bonzini }; 42353018216SPaolo Bonzini 42453018216SPaolo Bonzini #define DID0_VER_MASK 0x70000000 42553018216SPaolo Bonzini #define DID0_VER_0 0x00000000 42653018216SPaolo Bonzini #define DID0_VER_1 0x10000000 42753018216SPaolo Bonzini 42853018216SPaolo Bonzini #define DID0_CLASS_MASK 0x00FF0000 42953018216SPaolo Bonzini #define DID0_CLASS_SANDSTORM 0x00000000 43053018216SPaolo Bonzini #define DID0_CLASS_FURY 0x00010000 43153018216SPaolo Bonzini 43253018216SPaolo Bonzini static int ssys_board_class(const ssys_state *s) 43353018216SPaolo Bonzini { 43453018216SPaolo Bonzini uint32_t did0 = s->board->did0; 43553018216SPaolo Bonzini switch (did0 & DID0_VER_MASK) { 43653018216SPaolo Bonzini case DID0_VER_0: 43753018216SPaolo Bonzini return DID0_CLASS_SANDSTORM; 43853018216SPaolo Bonzini case DID0_VER_1: 43953018216SPaolo Bonzini switch (did0 & DID0_CLASS_MASK) { 44053018216SPaolo Bonzini case DID0_CLASS_SANDSTORM: 44153018216SPaolo Bonzini case DID0_CLASS_FURY: 44253018216SPaolo Bonzini return did0 & DID0_CLASS_MASK; 44353018216SPaolo Bonzini } 44453018216SPaolo Bonzini /* for unknown classes, fall through */ 44553018216SPaolo Bonzini default: 446df3692e0SPeter Maydell /* This can only happen if the hardwired constant did0 value 447df3692e0SPeter Maydell * in this board's stellaris_board_info struct is wrong. 448df3692e0SPeter Maydell */ 449df3692e0SPeter Maydell g_assert_not_reached(); 45053018216SPaolo Bonzini } 45153018216SPaolo Bonzini } 45253018216SPaolo Bonzini 45353018216SPaolo Bonzini static uint64_t ssys_read(void *opaque, hwaddr offset, 45453018216SPaolo Bonzini unsigned size) 45553018216SPaolo Bonzini { 45653018216SPaolo Bonzini ssys_state *s = (ssys_state *)opaque; 45753018216SPaolo Bonzini 45853018216SPaolo Bonzini switch (offset) { 45953018216SPaolo Bonzini case 0x000: /* DID0 */ 46053018216SPaolo Bonzini return s->board->did0; 46153018216SPaolo Bonzini case 0x004: /* DID1 */ 46253018216SPaolo Bonzini return s->board->did1; 46353018216SPaolo Bonzini case 0x008: /* DC0 */ 46453018216SPaolo Bonzini return s->board->dc0; 46553018216SPaolo Bonzini case 0x010: /* DC1 */ 46653018216SPaolo Bonzini return s->board->dc1; 46753018216SPaolo Bonzini case 0x014: /* DC2 */ 46853018216SPaolo Bonzini return s->board->dc2; 46953018216SPaolo Bonzini case 0x018: /* DC3 */ 47053018216SPaolo Bonzini return s->board->dc3; 47153018216SPaolo Bonzini case 0x01c: /* DC4 */ 47253018216SPaolo Bonzini return s->board->dc4; 47353018216SPaolo Bonzini case 0x030: /* PBORCTL */ 47453018216SPaolo Bonzini return s->pborctl; 47553018216SPaolo Bonzini case 0x034: /* LDOPCTL */ 47653018216SPaolo Bonzini return s->ldopctl; 47753018216SPaolo Bonzini case 0x040: /* SRCR0 */ 47853018216SPaolo Bonzini return 0; 47953018216SPaolo Bonzini case 0x044: /* SRCR1 */ 48053018216SPaolo Bonzini return 0; 48153018216SPaolo Bonzini case 0x048: /* SRCR2 */ 48253018216SPaolo Bonzini return 0; 48353018216SPaolo Bonzini case 0x050: /* RIS */ 48453018216SPaolo Bonzini return s->int_status; 48553018216SPaolo Bonzini case 0x054: /* IMC */ 48653018216SPaolo Bonzini return s->int_mask; 48753018216SPaolo Bonzini case 0x058: /* MISC */ 48853018216SPaolo Bonzini return s->int_status & s->int_mask; 48953018216SPaolo Bonzini case 0x05c: /* RESC */ 49053018216SPaolo Bonzini return s->resc; 49153018216SPaolo Bonzini case 0x060: /* RCC */ 49253018216SPaolo Bonzini return s->rcc; 49353018216SPaolo Bonzini case 0x064: /* PLLCFG */ 49453018216SPaolo Bonzini { 49553018216SPaolo Bonzini int xtal; 49653018216SPaolo Bonzini xtal = (s->rcc >> 6) & 0xf; 49753018216SPaolo Bonzini switch (ssys_board_class(s)) { 49853018216SPaolo Bonzini case DID0_CLASS_FURY: 49953018216SPaolo Bonzini return pllcfg_fury[xtal]; 50053018216SPaolo Bonzini case DID0_CLASS_SANDSTORM: 50153018216SPaolo Bonzini return pllcfg_sandstorm[xtal]; 50253018216SPaolo Bonzini default: 503df3692e0SPeter Maydell g_assert_not_reached(); 50453018216SPaolo Bonzini } 50553018216SPaolo Bonzini } 50653018216SPaolo Bonzini case 0x070: /* RCC2 */ 50753018216SPaolo Bonzini return s->rcc2; 50853018216SPaolo Bonzini case 0x100: /* RCGC0 */ 50953018216SPaolo Bonzini return s->rcgc[0]; 51053018216SPaolo Bonzini case 0x104: /* RCGC1 */ 51153018216SPaolo Bonzini return s->rcgc[1]; 51253018216SPaolo Bonzini case 0x108: /* RCGC2 */ 51353018216SPaolo Bonzini return s->rcgc[2]; 51453018216SPaolo Bonzini case 0x110: /* SCGC0 */ 51553018216SPaolo Bonzini return s->scgc[0]; 51653018216SPaolo Bonzini case 0x114: /* SCGC1 */ 51753018216SPaolo Bonzini return s->scgc[1]; 51853018216SPaolo Bonzini case 0x118: /* SCGC2 */ 51953018216SPaolo Bonzini return s->scgc[2]; 52053018216SPaolo Bonzini case 0x120: /* DCGC0 */ 52153018216SPaolo Bonzini return s->dcgc[0]; 52253018216SPaolo Bonzini case 0x124: /* DCGC1 */ 52353018216SPaolo Bonzini return s->dcgc[1]; 52453018216SPaolo Bonzini case 0x128: /* DCGC2 */ 52553018216SPaolo Bonzini return s->dcgc[2]; 52653018216SPaolo Bonzini case 0x150: /* CLKVCLR */ 52753018216SPaolo Bonzini return s->clkvclr; 52853018216SPaolo Bonzini case 0x160: /* LDOARST */ 52953018216SPaolo Bonzini return s->ldoarst; 53053018216SPaolo Bonzini case 0x1e0: /* USER0 */ 53153018216SPaolo Bonzini return s->user0; 53253018216SPaolo Bonzini case 0x1e4: /* USER1 */ 53353018216SPaolo Bonzini return s->user1; 53453018216SPaolo Bonzini default: 535df3692e0SPeter Maydell qemu_log_mask(LOG_GUEST_ERROR, 536df3692e0SPeter Maydell "SSYS: read at bad offset 0x%x\n", (int)offset); 53753018216SPaolo Bonzini return 0; 53853018216SPaolo Bonzini } 53953018216SPaolo Bonzini } 54053018216SPaolo Bonzini 54153018216SPaolo Bonzini static bool ssys_use_rcc2(ssys_state *s) 54253018216SPaolo Bonzini { 54353018216SPaolo Bonzini return (s->rcc2 >> 31) & 0x1; 54453018216SPaolo Bonzini } 54553018216SPaolo Bonzini 54653018216SPaolo Bonzini /* 54753018216SPaolo Bonzini * Caculate the sys. clock period in ms. 54853018216SPaolo Bonzini */ 54953018216SPaolo Bonzini static void ssys_calculate_system_clock(ssys_state *s) 55053018216SPaolo Bonzini { 55153018216SPaolo Bonzini if (ssys_use_rcc2(s)) { 55253018216SPaolo Bonzini system_clock_scale = 5 * (((s->rcc2 >> 23) & 0x3f) + 1); 55353018216SPaolo Bonzini } else { 55453018216SPaolo Bonzini system_clock_scale = 5 * (((s->rcc >> 23) & 0xf) + 1); 55553018216SPaolo Bonzini } 55653018216SPaolo Bonzini } 55753018216SPaolo Bonzini 55853018216SPaolo Bonzini static void ssys_write(void *opaque, hwaddr offset, 55953018216SPaolo Bonzini uint64_t value, unsigned size) 56053018216SPaolo Bonzini { 56153018216SPaolo Bonzini ssys_state *s = (ssys_state *)opaque; 56253018216SPaolo Bonzini 56353018216SPaolo Bonzini switch (offset) { 56453018216SPaolo Bonzini case 0x030: /* PBORCTL */ 56553018216SPaolo Bonzini s->pborctl = value & 0xffff; 56653018216SPaolo Bonzini break; 56753018216SPaolo Bonzini case 0x034: /* LDOPCTL */ 56853018216SPaolo Bonzini s->ldopctl = value & 0x1f; 56953018216SPaolo Bonzini break; 57053018216SPaolo Bonzini case 0x040: /* SRCR0 */ 57153018216SPaolo Bonzini case 0x044: /* SRCR1 */ 57253018216SPaolo Bonzini case 0x048: /* SRCR2 */ 5739194524bSPhilippe Mathieu-Daudé qemu_log_mask(LOG_UNIMP, "Peripheral reset not implemented\n"); 57453018216SPaolo Bonzini break; 57553018216SPaolo Bonzini case 0x054: /* IMC */ 57653018216SPaolo Bonzini s->int_mask = value & 0x7f; 57753018216SPaolo Bonzini break; 57853018216SPaolo Bonzini case 0x058: /* MISC */ 57953018216SPaolo Bonzini s->int_status &= ~value; 58053018216SPaolo Bonzini break; 58153018216SPaolo Bonzini case 0x05c: /* RESC */ 58253018216SPaolo Bonzini s->resc = value & 0x3f; 58353018216SPaolo Bonzini break; 58453018216SPaolo Bonzini case 0x060: /* RCC */ 58553018216SPaolo Bonzini if ((s->rcc & (1 << 13)) != 0 && (value & (1 << 13)) == 0) { 58653018216SPaolo Bonzini /* PLL enable. */ 58753018216SPaolo Bonzini s->int_status |= (1 << 6); 58853018216SPaolo Bonzini } 58953018216SPaolo Bonzini s->rcc = value; 59053018216SPaolo Bonzini ssys_calculate_system_clock(s); 59153018216SPaolo Bonzini break; 59253018216SPaolo Bonzini case 0x070: /* RCC2 */ 59353018216SPaolo Bonzini if (ssys_board_class(s) == DID0_CLASS_SANDSTORM) { 59453018216SPaolo Bonzini break; 59553018216SPaolo Bonzini } 59653018216SPaolo Bonzini 59753018216SPaolo Bonzini if ((s->rcc2 & (1 << 13)) != 0 && (value & (1 << 13)) == 0) { 59853018216SPaolo Bonzini /* PLL enable. */ 59953018216SPaolo Bonzini s->int_status |= (1 << 6); 60053018216SPaolo Bonzini } 60153018216SPaolo Bonzini s->rcc2 = value; 60253018216SPaolo Bonzini ssys_calculate_system_clock(s); 60353018216SPaolo Bonzini break; 60453018216SPaolo Bonzini case 0x100: /* RCGC0 */ 60553018216SPaolo Bonzini s->rcgc[0] = value; 60653018216SPaolo Bonzini break; 60753018216SPaolo Bonzini case 0x104: /* RCGC1 */ 60853018216SPaolo Bonzini s->rcgc[1] = value; 60953018216SPaolo Bonzini break; 61053018216SPaolo Bonzini case 0x108: /* RCGC2 */ 61153018216SPaolo Bonzini s->rcgc[2] = value; 61253018216SPaolo Bonzini break; 61353018216SPaolo Bonzini case 0x110: /* SCGC0 */ 61453018216SPaolo Bonzini s->scgc[0] = value; 61553018216SPaolo Bonzini break; 61653018216SPaolo Bonzini case 0x114: /* SCGC1 */ 61753018216SPaolo Bonzini s->scgc[1] = value; 61853018216SPaolo Bonzini break; 61953018216SPaolo Bonzini case 0x118: /* SCGC2 */ 62053018216SPaolo Bonzini s->scgc[2] = value; 62153018216SPaolo Bonzini break; 62253018216SPaolo Bonzini case 0x120: /* DCGC0 */ 62353018216SPaolo Bonzini s->dcgc[0] = value; 62453018216SPaolo Bonzini break; 62553018216SPaolo Bonzini case 0x124: /* DCGC1 */ 62653018216SPaolo Bonzini s->dcgc[1] = value; 62753018216SPaolo Bonzini break; 62853018216SPaolo Bonzini case 0x128: /* DCGC2 */ 62953018216SPaolo Bonzini s->dcgc[2] = value; 63053018216SPaolo Bonzini break; 63153018216SPaolo Bonzini case 0x150: /* CLKVCLR */ 63253018216SPaolo Bonzini s->clkvclr = value; 63353018216SPaolo Bonzini break; 63453018216SPaolo Bonzini case 0x160: /* LDOARST */ 63553018216SPaolo Bonzini s->ldoarst = value; 63653018216SPaolo Bonzini break; 63753018216SPaolo Bonzini default: 638df3692e0SPeter Maydell qemu_log_mask(LOG_GUEST_ERROR, 639df3692e0SPeter Maydell "SSYS: write at bad offset 0x%x\n", (int)offset); 64053018216SPaolo Bonzini } 64153018216SPaolo Bonzini ssys_update(s); 64253018216SPaolo Bonzini } 64353018216SPaolo Bonzini 64453018216SPaolo Bonzini static const MemoryRegionOps ssys_ops = { 64553018216SPaolo Bonzini .read = ssys_read, 64653018216SPaolo Bonzini .write = ssys_write, 64753018216SPaolo Bonzini .endianness = DEVICE_NATIVE_ENDIAN, 64853018216SPaolo Bonzini }; 64953018216SPaolo Bonzini 65053018216SPaolo Bonzini static void ssys_reset(void *opaque) 65153018216SPaolo Bonzini { 65253018216SPaolo Bonzini ssys_state *s = (ssys_state *)opaque; 65353018216SPaolo Bonzini 65453018216SPaolo Bonzini s->pborctl = 0x7ffd; 65553018216SPaolo Bonzini s->rcc = 0x078e3ac0; 65653018216SPaolo Bonzini 65753018216SPaolo Bonzini if (ssys_board_class(s) == DID0_CLASS_SANDSTORM) { 65853018216SPaolo Bonzini s->rcc2 = 0; 65953018216SPaolo Bonzini } else { 66053018216SPaolo Bonzini s->rcc2 = 0x07802810; 66153018216SPaolo Bonzini } 66253018216SPaolo Bonzini s->rcgc[0] = 1; 66353018216SPaolo Bonzini s->scgc[0] = 1; 66453018216SPaolo Bonzini s->dcgc[0] = 1; 66553018216SPaolo Bonzini ssys_calculate_system_clock(s); 66653018216SPaolo Bonzini } 66753018216SPaolo Bonzini 66853018216SPaolo Bonzini static int stellaris_sys_post_load(void *opaque, int version_id) 66953018216SPaolo Bonzini { 67053018216SPaolo Bonzini ssys_state *s = opaque; 67153018216SPaolo Bonzini 67253018216SPaolo Bonzini ssys_calculate_system_clock(s); 67353018216SPaolo Bonzini 67453018216SPaolo Bonzini return 0; 67553018216SPaolo Bonzini } 67653018216SPaolo Bonzini 67753018216SPaolo Bonzini static const VMStateDescription vmstate_stellaris_sys = { 67853018216SPaolo Bonzini .name = "stellaris_sys", 67953018216SPaolo Bonzini .version_id = 2, 68053018216SPaolo Bonzini .minimum_version_id = 1, 68153018216SPaolo Bonzini .post_load = stellaris_sys_post_load, 68253018216SPaolo Bonzini .fields = (VMStateField[]) { 68353018216SPaolo Bonzini VMSTATE_UINT32(pborctl, ssys_state), 68453018216SPaolo Bonzini VMSTATE_UINT32(ldopctl, ssys_state), 68553018216SPaolo Bonzini VMSTATE_UINT32(int_mask, ssys_state), 68653018216SPaolo Bonzini VMSTATE_UINT32(int_status, ssys_state), 68753018216SPaolo Bonzini VMSTATE_UINT32(resc, ssys_state), 68853018216SPaolo Bonzini VMSTATE_UINT32(rcc, ssys_state), 68953018216SPaolo Bonzini VMSTATE_UINT32_V(rcc2, ssys_state, 2), 69053018216SPaolo Bonzini VMSTATE_UINT32_ARRAY(rcgc, ssys_state, 3), 69153018216SPaolo Bonzini VMSTATE_UINT32_ARRAY(scgc, ssys_state, 3), 69253018216SPaolo Bonzini VMSTATE_UINT32_ARRAY(dcgc, ssys_state, 3), 69353018216SPaolo Bonzini VMSTATE_UINT32(clkvclr, ssys_state), 69453018216SPaolo Bonzini VMSTATE_UINT32(ldoarst, ssys_state), 69553018216SPaolo Bonzini VMSTATE_END_OF_LIST() 69653018216SPaolo Bonzini } 69753018216SPaolo Bonzini }; 69853018216SPaolo Bonzini 69953018216SPaolo Bonzini static int stellaris_sys_init(uint32_t base, qemu_irq irq, 70053018216SPaolo Bonzini stellaris_board_info * board, 70153018216SPaolo Bonzini uint8_t *macaddr) 70253018216SPaolo Bonzini { 70353018216SPaolo Bonzini ssys_state *s; 70453018216SPaolo Bonzini 705b45c03f5SMarkus Armbruster s = g_new0(ssys_state, 1); 70653018216SPaolo Bonzini s->irq = irq; 70753018216SPaolo Bonzini s->board = board; 70853018216SPaolo Bonzini /* Most devices come preprogrammed with a MAC address in the user data. */ 70953018216SPaolo Bonzini s->user0 = macaddr[0] | (macaddr[1] << 8) | (macaddr[2] << 16); 71053018216SPaolo Bonzini s->user1 = macaddr[3] | (macaddr[4] << 8) | (macaddr[5] << 16); 71153018216SPaolo Bonzini 7122c9b15caSPaolo Bonzini memory_region_init_io(&s->iomem, NULL, &ssys_ops, s, "ssys", 0x00001000); 71353018216SPaolo Bonzini memory_region_add_subregion(get_system_memory(), base, &s->iomem); 71453018216SPaolo Bonzini ssys_reset(s); 7151df2c9a2SPeter Xu vmstate_register(NULL, VMSTATE_INSTANCE_ID_ANY, &vmstate_stellaris_sys, s); 71653018216SPaolo Bonzini return 0; 71753018216SPaolo Bonzini } 71853018216SPaolo Bonzini 71953018216SPaolo Bonzini 72053018216SPaolo Bonzini /* I2C controller. */ 72153018216SPaolo Bonzini 722d94a4015SAndreas Färber #define TYPE_STELLARIS_I2C "stellaris-i2c" 723d94a4015SAndreas Färber #define STELLARIS_I2C(obj) \ 724d94a4015SAndreas Färber OBJECT_CHECK(stellaris_i2c_state, (obj), TYPE_STELLARIS_I2C) 725d94a4015SAndreas Färber 72653018216SPaolo Bonzini typedef struct { 727d94a4015SAndreas Färber SysBusDevice parent_obj; 728d94a4015SAndreas Färber 729a5c82852SAndreas Färber I2CBus *bus; 73053018216SPaolo Bonzini qemu_irq irq; 73153018216SPaolo Bonzini MemoryRegion iomem; 73253018216SPaolo Bonzini uint32_t msa; 73353018216SPaolo Bonzini uint32_t mcs; 73453018216SPaolo Bonzini uint32_t mdr; 73553018216SPaolo Bonzini uint32_t mtpr; 73653018216SPaolo Bonzini uint32_t mimr; 73753018216SPaolo Bonzini uint32_t mris; 73853018216SPaolo Bonzini uint32_t mcr; 73953018216SPaolo Bonzini } stellaris_i2c_state; 74053018216SPaolo Bonzini 74153018216SPaolo Bonzini #define STELLARIS_I2C_MCS_BUSY 0x01 74253018216SPaolo Bonzini #define STELLARIS_I2C_MCS_ERROR 0x02 74353018216SPaolo Bonzini #define STELLARIS_I2C_MCS_ADRACK 0x04 74453018216SPaolo Bonzini #define STELLARIS_I2C_MCS_DATACK 0x08 74553018216SPaolo Bonzini #define STELLARIS_I2C_MCS_ARBLST 0x10 74653018216SPaolo Bonzini #define STELLARIS_I2C_MCS_IDLE 0x20 74753018216SPaolo Bonzini #define STELLARIS_I2C_MCS_BUSBSY 0x40 74853018216SPaolo Bonzini 74953018216SPaolo Bonzini static uint64_t stellaris_i2c_read(void *opaque, hwaddr offset, 75053018216SPaolo Bonzini unsigned size) 75153018216SPaolo Bonzini { 75253018216SPaolo Bonzini stellaris_i2c_state *s = (stellaris_i2c_state *)opaque; 75353018216SPaolo Bonzini 75453018216SPaolo Bonzini switch (offset) { 75553018216SPaolo Bonzini case 0x00: /* MSA */ 75653018216SPaolo Bonzini return s->msa; 75753018216SPaolo Bonzini case 0x04: /* MCS */ 75853018216SPaolo Bonzini /* We don't emulate timing, so the controller is never busy. */ 75953018216SPaolo Bonzini return s->mcs | STELLARIS_I2C_MCS_IDLE; 76053018216SPaolo Bonzini case 0x08: /* MDR */ 76153018216SPaolo Bonzini return s->mdr; 76253018216SPaolo Bonzini case 0x0c: /* MTPR */ 76353018216SPaolo Bonzini return s->mtpr; 76453018216SPaolo Bonzini case 0x10: /* MIMR */ 76553018216SPaolo Bonzini return s->mimr; 76653018216SPaolo Bonzini case 0x14: /* MRIS */ 76753018216SPaolo Bonzini return s->mris; 76853018216SPaolo Bonzini case 0x18: /* MMIS */ 76953018216SPaolo Bonzini return s->mris & s->mimr; 77053018216SPaolo Bonzini case 0x20: /* MCR */ 77153018216SPaolo Bonzini return s->mcr; 77253018216SPaolo Bonzini default: 773df3692e0SPeter Maydell qemu_log_mask(LOG_GUEST_ERROR, 774df3692e0SPeter Maydell "stellaris_i2c: read at bad offset 0x%x\n", (int)offset); 77553018216SPaolo Bonzini return 0; 77653018216SPaolo Bonzini } 77753018216SPaolo Bonzini } 77853018216SPaolo Bonzini 77953018216SPaolo Bonzini static void stellaris_i2c_update(stellaris_i2c_state *s) 78053018216SPaolo Bonzini { 78153018216SPaolo Bonzini int level; 78253018216SPaolo Bonzini 78353018216SPaolo Bonzini level = (s->mris & s->mimr) != 0; 78453018216SPaolo Bonzini qemu_set_irq(s->irq, level); 78553018216SPaolo Bonzini } 78653018216SPaolo Bonzini 78753018216SPaolo Bonzini static void stellaris_i2c_write(void *opaque, hwaddr offset, 78853018216SPaolo Bonzini uint64_t value, unsigned size) 78953018216SPaolo Bonzini { 79053018216SPaolo Bonzini stellaris_i2c_state *s = (stellaris_i2c_state *)opaque; 79153018216SPaolo Bonzini 79253018216SPaolo Bonzini switch (offset) { 79353018216SPaolo Bonzini case 0x00: /* MSA */ 79453018216SPaolo Bonzini s->msa = value & 0xff; 79553018216SPaolo Bonzini break; 79653018216SPaolo Bonzini case 0x04: /* MCS */ 79753018216SPaolo Bonzini if ((s->mcr & 0x10) == 0) { 79853018216SPaolo Bonzini /* Disabled. Do nothing. */ 79953018216SPaolo Bonzini break; 80053018216SPaolo Bonzini } 80153018216SPaolo Bonzini /* Grab the bus if this is starting a transfer. */ 80253018216SPaolo Bonzini if ((value & 2) && (s->mcs & STELLARIS_I2C_MCS_BUSBSY) == 0) { 80353018216SPaolo Bonzini if (i2c_start_transfer(s->bus, s->msa >> 1, s->msa & 1)) { 80453018216SPaolo Bonzini s->mcs |= STELLARIS_I2C_MCS_ARBLST; 80553018216SPaolo Bonzini } else { 80653018216SPaolo Bonzini s->mcs &= ~STELLARIS_I2C_MCS_ARBLST; 80753018216SPaolo Bonzini s->mcs |= STELLARIS_I2C_MCS_BUSBSY; 80853018216SPaolo Bonzini } 80953018216SPaolo Bonzini } 81053018216SPaolo Bonzini /* If we don't have the bus then indicate an error. */ 81153018216SPaolo Bonzini if (!i2c_bus_busy(s->bus) 81253018216SPaolo Bonzini || (s->mcs & STELLARIS_I2C_MCS_BUSBSY) == 0) { 81353018216SPaolo Bonzini s->mcs |= STELLARIS_I2C_MCS_ERROR; 81453018216SPaolo Bonzini break; 81553018216SPaolo Bonzini } 81653018216SPaolo Bonzini s->mcs &= ~STELLARIS_I2C_MCS_ERROR; 81753018216SPaolo Bonzini if (value & 1) { 81853018216SPaolo Bonzini /* Transfer a byte. */ 81953018216SPaolo Bonzini /* TODO: Handle errors. */ 82053018216SPaolo Bonzini if (s->msa & 1) { 82153018216SPaolo Bonzini /* Recv */ 82205f9f17eSCorey Minyard s->mdr = i2c_recv(s->bus); 82353018216SPaolo Bonzini } else { 82453018216SPaolo Bonzini /* Send */ 82553018216SPaolo Bonzini i2c_send(s->bus, s->mdr); 82653018216SPaolo Bonzini } 82753018216SPaolo Bonzini /* Raise an interrupt. */ 82853018216SPaolo Bonzini s->mris |= 1; 82953018216SPaolo Bonzini } 83053018216SPaolo Bonzini if (value & 4) { 83153018216SPaolo Bonzini /* Finish transfer. */ 83253018216SPaolo Bonzini i2c_end_transfer(s->bus); 83353018216SPaolo Bonzini s->mcs &= ~STELLARIS_I2C_MCS_BUSBSY; 83453018216SPaolo Bonzini } 83553018216SPaolo Bonzini break; 83653018216SPaolo Bonzini case 0x08: /* MDR */ 83753018216SPaolo Bonzini s->mdr = value & 0xff; 83853018216SPaolo Bonzini break; 83953018216SPaolo Bonzini case 0x0c: /* MTPR */ 84053018216SPaolo Bonzini s->mtpr = value & 0xff; 84153018216SPaolo Bonzini break; 84253018216SPaolo Bonzini case 0x10: /* MIMR */ 84353018216SPaolo Bonzini s->mimr = 1; 84453018216SPaolo Bonzini break; 84553018216SPaolo Bonzini case 0x1c: /* MICR */ 84653018216SPaolo Bonzini s->mris &= ~value; 84753018216SPaolo Bonzini break; 84853018216SPaolo Bonzini case 0x20: /* MCR */ 849df3692e0SPeter Maydell if (value & 1) { 8509492e4b2SPhilippe Mathieu-Daudé qemu_log_mask(LOG_UNIMP, 8519492e4b2SPhilippe Mathieu-Daudé "stellaris_i2c: Loopback not implemented\n"); 852df3692e0SPeter Maydell } 853df3692e0SPeter Maydell if (value & 0x20) { 854df3692e0SPeter Maydell qemu_log_mask(LOG_UNIMP, 8559492e4b2SPhilippe Mathieu-Daudé "stellaris_i2c: Slave mode not implemented\n"); 856df3692e0SPeter Maydell } 85753018216SPaolo Bonzini s->mcr = value & 0x31; 85853018216SPaolo Bonzini break; 85953018216SPaolo Bonzini default: 860df3692e0SPeter Maydell qemu_log_mask(LOG_GUEST_ERROR, 861df3692e0SPeter Maydell "stellaris_i2c: write at bad offset 0x%x\n", (int)offset); 86253018216SPaolo Bonzini } 86353018216SPaolo Bonzini stellaris_i2c_update(s); 86453018216SPaolo Bonzini } 86553018216SPaolo Bonzini 86653018216SPaolo Bonzini static void stellaris_i2c_reset(stellaris_i2c_state *s) 86753018216SPaolo Bonzini { 86853018216SPaolo Bonzini if (s->mcs & STELLARIS_I2C_MCS_BUSBSY) 86953018216SPaolo Bonzini i2c_end_transfer(s->bus); 87053018216SPaolo Bonzini 87153018216SPaolo Bonzini s->msa = 0; 87253018216SPaolo Bonzini s->mcs = 0; 87353018216SPaolo Bonzini s->mdr = 0; 87453018216SPaolo Bonzini s->mtpr = 1; 87553018216SPaolo Bonzini s->mimr = 0; 87653018216SPaolo Bonzini s->mris = 0; 87753018216SPaolo Bonzini s->mcr = 0; 87853018216SPaolo Bonzini stellaris_i2c_update(s); 87953018216SPaolo Bonzini } 88053018216SPaolo Bonzini 88153018216SPaolo Bonzini static const MemoryRegionOps stellaris_i2c_ops = { 88253018216SPaolo Bonzini .read = stellaris_i2c_read, 88353018216SPaolo Bonzini .write = stellaris_i2c_write, 88453018216SPaolo Bonzini .endianness = DEVICE_NATIVE_ENDIAN, 88553018216SPaolo Bonzini }; 88653018216SPaolo Bonzini 88753018216SPaolo Bonzini static const VMStateDescription vmstate_stellaris_i2c = { 88853018216SPaolo Bonzini .name = "stellaris_i2c", 88953018216SPaolo Bonzini .version_id = 1, 89053018216SPaolo Bonzini .minimum_version_id = 1, 89153018216SPaolo Bonzini .fields = (VMStateField[]) { 89253018216SPaolo Bonzini VMSTATE_UINT32(msa, stellaris_i2c_state), 89353018216SPaolo Bonzini VMSTATE_UINT32(mcs, stellaris_i2c_state), 89453018216SPaolo Bonzini VMSTATE_UINT32(mdr, stellaris_i2c_state), 89553018216SPaolo Bonzini VMSTATE_UINT32(mtpr, stellaris_i2c_state), 89653018216SPaolo Bonzini VMSTATE_UINT32(mimr, stellaris_i2c_state), 89753018216SPaolo Bonzini VMSTATE_UINT32(mris, stellaris_i2c_state), 89853018216SPaolo Bonzini VMSTATE_UINT32(mcr, stellaris_i2c_state), 89953018216SPaolo Bonzini VMSTATE_END_OF_LIST() 90053018216SPaolo Bonzini } 90153018216SPaolo Bonzini }; 90253018216SPaolo Bonzini 90315c4fff5Sxiaoqiang.zhao static void stellaris_i2c_init(Object *obj) 90453018216SPaolo Bonzini { 90515c4fff5Sxiaoqiang.zhao DeviceState *dev = DEVICE(obj); 90615c4fff5Sxiaoqiang.zhao stellaris_i2c_state *s = STELLARIS_I2C(obj); 90715c4fff5Sxiaoqiang.zhao SysBusDevice *sbd = SYS_BUS_DEVICE(obj); 908a5c82852SAndreas Färber I2CBus *bus; 90953018216SPaolo Bonzini 910d94a4015SAndreas Färber sysbus_init_irq(sbd, &s->irq); 911d94a4015SAndreas Färber bus = i2c_init_bus(dev, "i2c"); 91253018216SPaolo Bonzini s->bus = bus; 91353018216SPaolo Bonzini 91415c4fff5Sxiaoqiang.zhao memory_region_init_io(&s->iomem, obj, &stellaris_i2c_ops, s, 91553018216SPaolo Bonzini "i2c", 0x1000); 916d94a4015SAndreas Färber sysbus_init_mmio(sbd, &s->iomem); 91753018216SPaolo Bonzini /* ??? For now we only implement the master interface. */ 91853018216SPaolo Bonzini stellaris_i2c_reset(s); 91953018216SPaolo Bonzini } 92053018216SPaolo Bonzini 92153018216SPaolo Bonzini /* Analogue to Digital Converter. This is only partially implemented, 92253018216SPaolo Bonzini enough for applications that use a combined ADC and timer tick. */ 92353018216SPaolo Bonzini 92453018216SPaolo Bonzini #define STELLARIS_ADC_EM_CONTROLLER 0 92553018216SPaolo Bonzini #define STELLARIS_ADC_EM_COMP 1 92653018216SPaolo Bonzini #define STELLARIS_ADC_EM_EXTERNAL 4 92753018216SPaolo Bonzini #define STELLARIS_ADC_EM_TIMER 5 92853018216SPaolo Bonzini #define STELLARIS_ADC_EM_PWM0 6 92953018216SPaolo Bonzini #define STELLARIS_ADC_EM_PWM1 7 93053018216SPaolo Bonzini #define STELLARIS_ADC_EM_PWM2 8 93153018216SPaolo Bonzini 93253018216SPaolo Bonzini #define STELLARIS_ADC_FIFO_EMPTY 0x0100 93353018216SPaolo Bonzini #define STELLARIS_ADC_FIFO_FULL 0x1000 93453018216SPaolo Bonzini 9357df7f67aSAndreas Färber #define TYPE_STELLARIS_ADC "stellaris-adc" 9367df7f67aSAndreas Färber #define STELLARIS_ADC(obj) \ 9377df7f67aSAndreas Färber OBJECT_CHECK(stellaris_adc_state, (obj), TYPE_STELLARIS_ADC) 9387df7f67aSAndreas Färber 9397df7f67aSAndreas Färber typedef struct StellarisADCState { 9407df7f67aSAndreas Färber SysBusDevice parent_obj; 9417df7f67aSAndreas Färber 94253018216SPaolo Bonzini MemoryRegion iomem; 94353018216SPaolo Bonzini uint32_t actss; 94453018216SPaolo Bonzini uint32_t ris; 94553018216SPaolo Bonzini uint32_t im; 94653018216SPaolo Bonzini uint32_t emux; 94753018216SPaolo Bonzini uint32_t ostat; 94853018216SPaolo Bonzini uint32_t ustat; 94953018216SPaolo Bonzini uint32_t sspri; 95053018216SPaolo Bonzini uint32_t sac; 95153018216SPaolo Bonzini struct { 95253018216SPaolo Bonzini uint32_t state; 95353018216SPaolo Bonzini uint32_t data[16]; 95453018216SPaolo Bonzini } fifo[4]; 95553018216SPaolo Bonzini uint32_t ssmux[4]; 95653018216SPaolo Bonzini uint32_t ssctl[4]; 95753018216SPaolo Bonzini uint32_t noise; 95853018216SPaolo Bonzini qemu_irq irq[4]; 95953018216SPaolo Bonzini } stellaris_adc_state; 96053018216SPaolo Bonzini 96153018216SPaolo Bonzini static uint32_t stellaris_adc_fifo_read(stellaris_adc_state *s, int n) 96253018216SPaolo Bonzini { 96353018216SPaolo Bonzini int tail; 96453018216SPaolo Bonzini 96553018216SPaolo Bonzini tail = s->fifo[n].state & 0xf; 96653018216SPaolo Bonzini if (s->fifo[n].state & STELLARIS_ADC_FIFO_EMPTY) { 96753018216SPaolo Bonzini s->ustat |= 1 << n; 96853018216SPaolo Bonzini } else { 96953018216SPaolo Bonzini s->fifo[n].state = (s->fifo[n].state & ~0xf) | ((tail + 1) & 0xf); 97053018216SPaolo Bonzini s->fifo[n].state &= ~STELLARIS_ADC_FIFO_FULL; 97153018216SPaolo Bonzini if (tail + 1 == ((s->fifo[n].state >> 4) & 0xf)) 97253018216SPaolo Bonzini s->fifo[n].state |= STELLARIS_ADC_FIFO_EMPTY; 97353018216SPaolo Bonzini } 97453018216SPaolo Bonzini return s->fifo[n].data[tail]; 97553018216SPaolo Bonzini } 97653018216SPaolo Bonzini 97753018216SPaolo Bonzini static void stellaris_adc_fifo_write(stellaris_adc_state *s, int n, 97853018216SPaolo Bonzini uint32_t value) 97953018216SPaolo Bonzini { 98053018216SPaolo Bonzini int head; 98153018216SPaolo Bonzini 98253018216SPaolo Bonzini /* TODO: Real hardware has limited size FIFOs. We have a full 16 entry 98353018216SPaolo Bonzini FIFO fir each sequencer. */ 98453018216SPaolo Bonzini head = (s->fifo[n].state >> 4) & 0xf; 98553018216SPaolo Bonzini if (s->fifo[n].state & STELLARIS_ADC_FIFO_FULL) { 98653018216SPaolo Bonzini s->ostat |= 1 << n; 98753018216SPaolo Bonzini return; 98853018216SPaolo Bonzini } 98953018216SPaolo Bonzini s->fifo[n].data[head] = value; 99053018216SPaolo Bonzini head = (head + 1) & 0xf; 99153018216SPaolo Bonzini s->fifo[n].state &= ~STELLARIS_ADC_FIFO_EMPTY; 99253018216SPaolo Bonzini s->fifo[n].state = (s->fifo[n].state & ~0xf0) | (head << 4); 99353018216SPaolo Bonzini if ((s->fifo[n].state & 0xf) == head) 99453018216SPaolo Bonzini s->fifo[n].state |= STELLARIS_ADC_FIFO_FULL; 99553018216SPaolo Bonzini } 99653018216SPaolo Bonzini 99753018216SPaolo Bonzini static void stellaris_adc_update(stellaris_adc_state *s) 99853018216SPaolo Bonzini { 99953018216SPaolo Bonzini int level; 100053018216SPaolo Bonzini int n; 100153018216SPaolo Bonzini 100253018216SPaolo Bonzini for (n = 0; n < 4; n++) { 100353018216SPaolo Bonzini level = (s->ris & s->im & (1 << n)) != 0; 100453018216SPaolo Bonzini qemu_set_irq(s->irq[n], level); 100553018216SPaolo Bonzini } 100653018216SPaolo Bonzini } 100753018216SPaolo Bonzini 100853018216SPaolo Bonzini static void stellaris_adc_trigger(void *opaque, int irq, int level) 100953018216SPaolo Bonzini { 101053018216SPaolo Bonzini stellaris_adc_state *s = (stellaris_adc_state *)opaque; 101153018216SPaolo Bonzini int n; 101253018216SPaolo Bonzini 101353018216SPaolo Bonzini for (n = 0; n < 4; n++) { 101453018216SPaolo Bonzini if ((s->actss & (1 << n)) == 0) { 101553018216SPaolo Bonzini continue; 101653018216SPaolo Bonzini } 101753018216SPaolo Bonzini 101853018216SPaolo Bonzini if (((s->emux >> (n * 4)) & 0xff) != 5) { 101953018216SPaolo Bonzini continue; 102053018216SPaolo Bonzini } 102153018216SPaolo Bonzini 102253018216SPaolo Bonzini /* Some applications use the ADC as a random number source, so introduce 102353018216SPaolo Bonzini some variation into the signal. */ 102453018216SPaolo Bonzini s->noise = s->noise * 314159 + 1; 102553018216SPaolo Bonzini /* ??? actual inputs not implemented. Return an arbitrary value. */ 102653018216SPaolo Bonzini stellaris_adc_fifo_write(s, n, 0x200 + ((s->noise >> 16) & 7)); 102753018216SPaolo Bonzini s->ris |= (1 << n); 102853018216SPaolo Bonzini stellaris_adc_update(s); 102953018216SPaolo Bonzini } 103053018216SPaolo Bonzini } 103153018216SPaolo Bonzini 103253018216SPaolo Bonzini static void stellaris_adc_reset(stellaris_adc_state *s) 103353018216SPaolo Bonzini { 103453018216SPaolo Bonzini int n; 103553018216SPaolo Bonzini 103653018216SPaolo Bonzini for (n = 0; n < 4; n++) { 103753018216SPaolo Bonzini s->ssmux[n] = 0; 103853018216SPaolo Bonzini s->ssctl[n] = 0; 103953018216SPaolo Bonzini s->fifo[n].state = STELLARIS_ADC_FIFO_EMPTY; 104053018216SPaolo Bonzini } 104153018216SPaolo Bonzini } 104253018216SPaolo Bonzini 104353018216SPaolo Bonzini static uint64_t stellaris_adc_read(void *opaque, hwaddr offset, 104453018216SPaolo Bonzini unsigned size) 104553018216SPaolo Bonzini { 104653018216SPaolo Bonzini stellaris_adc_state *s = (stellaris_adc_state *)opaque; 104753018216SPaolo Bonzini 104853018216SPaolo Bonzini /* TODO: Implement this. */ 104953018216SPaolo Bonzini if (offset >= 0x40 && offset < 0xc0) { 105053018216SPaolo Bonzini int n; 105153018216SPaolo Bonzini n = (offset - 0x40) >> 5; 105253018216SPaolo Bonzini switch (offset & 0x1f) { 105353018216SPaolo Bonzini case 0x00: /* SSMUX */ 105453018216SPaolo Bonzini return s->ssmux[n]; 105553018216SPaolo Bonzini case 0x04: /* SSCTL */ 105653018216SPaolo Bonzini return s->ssctl[n]; 105753018216SPaolo Bonzini case 0x08: /* SSFIFO */ 105853018216SPaolo Bonzini return stellaris_adc_fifo_read(s, n); 105953018216SPaolo Bonzini case 0x0c: /* SSFSTAT */ 106053018216SPaolo Bonzini return s->fifo[n].state; 106153018216SPaolo Bonzini default: 106253018216SPaolo Bonzini break; 106353018216SPaolo Bonzini } 106453018216SPaolo Bonzini } 106553018216SPaolo Bonzini switch (offset) { 106653018216SPaolo Bonzini case 0x00: /* ACTSS */ 106753018216SPaolo Bonzini return s->actss; 106853018216SPaolo Bonzini case 0x04: /* RIS */ 106953018216SPaolo Bonzini return s->ris; 107053018216SPaolo Bonzini case 0x08: /* IM */ 107153018216SPaolo Bonzini return s->im; 107253018216SPaolo Bonzini case 0x0c: /* ISC */ 107353018216SPaolo Bonzini return s->ris & s->im; 107453018216SPaolo Bonzini case 0x10: /* OSTAT */ 107553018216SPaolo Bonzini return s->ostat; 107653018216SPaolo Bonzini case 0x14: /* EMUX */ 107753018216SPaolo Bonzini return s->emux; 107853018216SPaolo Bonzini case 0x18: /* USTAT */ 107953018216SPaolo Bonzini return s->ustat; 108053018216SPaolo Bonzini case 0x20: /* SSPRI */ 108153018216SPaolo Bonzini return s->sspri; 108253018216SPaolo Bonzini case 0x30: /* SAC */ 108353018216SPaolo Bonzini return s->sac; 108453018216SPaolo Bonzini default: 1085df3692e0SPeter Maydell qemu_log_mask(LOG_GUEST_ERROR, 1086df3692e0SPeter Maydell "stellaris_adc: read at bad offset 0x%x\n", (int)offset); 108753018216SPaolo Bonzini return 0; 108853018216SPaolo Bonzini } 108953018216SPaolo Bonzini } 109053018216SPaolo Bonzini 109153018216SPaolo Bonzini static void stellaris_adc_write(void *opaque, hwaddr offset, 109253018216SPaolo Bonzini uint64_t value, unsigned size) 109353018216SPaolo Bonzini { 109453018216SPaolo Bonzini stellaris_adc_state *s = (stellaris_adc_state *)opaque; 109553018216SPaolo Bonzini 109653018216SPaolo Bonzini /* TODO: Implement this. */ 109753018216SPaolo Bonzini if (offset >= 0x40 && offset < 0xc0) { 109853018216SPaolo Bonzini int n; 109953018216SPaolo Bonzini n = (offset - 0x40) >> 5; 110053018216SPaolo Bonzini switch (offset & 0x1f) { 110153018216SPaolo Bonzini case 0x00: /* SSMUX */ 110253018216SPaolo Bonzini s->ssmux[n] = value & 0x33333333; 110353018216SPaolo Bonzini return; 110453018216SPaolo Bonzini case 0x04: /* SSCTL */ 110553018216SPaolo Bonzini if (value != 6) { 1106df3692e0SPeter Maydell qemu_log_mask(LOG_UNIMP, 1107df3692e0SPeter Maydell "ADC: Unimplemented sequence %" PRIx64 "\n", 110853018216SPaolo Bonzini value); 110953018216SPaolo Bonzini } 111053018216SPaolo Bonzini s->ssctl[n] = value; 111153018216SPaolo Bonzini return; 111253018216SPaolo Bonzini default: 111353018216SPaolo Bonzini break; 111453018216SPaolo Bonzini } 111553018216SPaolo Bonzini } 111653018216SPaolo Bonzini switch (offset) { 111753018216SPaolo Bonzini case 0x00: /* ACTSS */ 111853018216SPaolo Bonzini s->actss = value & 0xf; 111953018216SPaolo Bonzini break; 112053018216SPaolo Bonzini case 0x08: /* IM */ 112153018216SPaolo Bonzini s->im = value; 112253018216SPaolo Bonzini break; 112353018216SPaolo Bonzini case 0x0c: /* ISC */ 112453018216SPaolo Bonzini s->ris &= ~value; 112553018216SPaolo Bonzini break; 112653018216SPaolo Bonzini case 0x10: /* OSTAT */ 112753018216SPaolo Bonzini s->ostat &= ~value; 112853018216SPaolo Bonzini break; 112953018216SPaolo Bonzini case 0x14: /* EMUX */ 113053018216SPaolo Bonzini s->emux = value; 113153018216SPaolo Bonzini break; 113253018216SPaolo Bonzini case 0x18: /* USTAT */ 113353018216SPaolo Bonzini s->ustat &= ~value; 113453018216SPaolo Bonzini break; 113553018216SPaolo Bonzini case 0x20: /* SSPRI */ 113653018216SPaolo Bonzini s->sspri = value; 113753018216SPaolo Bonzini break; 113853018216SPaolo Bonzini case 0x28: /* PSSI */ 11399492e4b2SPhilippe Mathieu-Daudé qemu_log_mask(LOG_UNIMP, "ADC: sample initiate unimplemented\n"); 114053018216SPaolo Bonzini break; 114153018216SPaolo Bonzini case 0x30: /* SAC */ 114253018216SPaolo Bonzini s->sac = value; 114353018216SPaolo Bonzini break; 114453018216SPaolo Bonzini default: 1145df3692e0SPeter Maydell qemu_log_mask(LOG_GUEST_ERROR, 1146df3692e0SPeter Maydell "stellaris_adc: write at bad offset 0x%x\n", (int)offset); 114753018216SPaolo Bonzini } 114853018216SPaolo Bonzini stellaris_adc_update(s); 114953018216SPaolo Bonzini } 115053018216SPaolo Bonzini 115153018216SPaolo Bonzini static const MemoryRegionOps stellaris_adc_ops = { 115253018216SPaolo Bonzini .read = stellaris_adc_read, 115353018216SPaolo Bonzini .write = stellaris_adc_write, 115453018216SPaolo Bonzini .endianness = DEVICE_NATIVE_ENDIAN, 115553018216SPaolo Bonzini }; 115653018216SPaolo Bonzini 115753018216SPaolo Bonzini static const VMStateDescription vmstate_stellaris_adc = { 115853018216SPaolo Bonzini .name = "stellaris_adc", 115953018216SPaolo Bonzini .version_id = 1, 116053018216SPaolo Bonzini .minimum_version_id = 1, 116153018216SPaolo Bonzini .fields = (VMStateField[]) { 116253018216SPaolo Bonzini VMSTATE_UINT32(actss, stellaris_adc_state), 116353018216SPaolo Bonzini VMSTATE_UINT32(ris, stellaris_adc_state), 116453018216SPaolo Bonzini VMSTATE_UINT32(im, stellaris_adc_state), 116553018216SPaolo Bonzini VMSTATE_UINT32(emux, stellaris_adc_state), 116653018216SPaolo Bonzini VMSTATE_UINT32(ostat, stellaris_adc_state), 116753018216SPaolo Bonzini VMSTATE_UINT32(ustat, stellaris_adc_state), 116853018216SPaolo Bonzini VMSTATE_UINT32(sspri, stellaris_adc_state), 116953018216SPaolo Bonzini VMSTATE_UINT32(sac, stellaris_adc_state), 117053018216SPaolo Bonzini VMSTATE_UINT32(fifo[0].state, stellaris_adc_state), 117153018216SPaolo Bonzini VMSTATE_UINT32_ARRAY(fifo[0].data, stellaris_adc_state, 16), 117253018216SPaolo Bonzini VMSTATE_UINT32(ssmux[0], stellaris_adc_state), 117353018216SPaolo Bonzini VMSTATE_UINT32(ssctl[0], stellaris_adc_state), 117453018216SPaolo Bonzini VMSTATE_UINT32(fifo[1].state, stellaris_adc_state), 117553018216SPaolo Bonzini VMSTATE_UINT32_ARRAY(fifo[1].data, stellaris_adc_state, 16), 117653018216SPaolo Bonzini VMSTATE_UINT32(ssmux[1], stellaris_adc_state), 117753018216SPaolo Bonzini VMSTATE_UINT32(ssctl[1], stellaris_adc_state), 117853018216SPaolo Bonzini VMSTATE_UINT32(fifo[2].state, stellaris_adc_state), 117953018216SPaolo Bonzini VMSTATE_UINT32_ARRAY(fifo[2].data, stellaris_adc_state, 16), 118053018216SPaolo Bonzini VMSTATE_UINT32(ssmux[2], stellaris_adc_state), 118153018216SPaolo Bonzini VMSTATE_UINT32(ssctl[2], stellaris_adc_state), 118253018216SPaolo Bonzini VMSTATE_UINT32(fifo[3].state, stellaris_adc_state), 118353018216SPaolo Bonzini VMSTATE_UINT32_ARRAY(fifo[3].data, stellaris_adc_state, 16), 118453018216SPaolo Bonzini VMSTATE_UINT32(ssmux[3], stellaris_adc_state), 118553018216SPaolo Bonzini VMSTATE_UINT32(ssctl[3], stellaris_adc_state), 118653018216SPaolo Bonzini VMSTATE_UINT32(noise, stellaris_adc_state), 118753018216SPaolo Bonzini VMSTATE_END_OF_LIST() 118853018216SPaolo Bonzini } 118953018216SPaolo Bonzini }; 119053018216SPaolo Bonzini 119115c4fff5Sxiaoqiang.zhao static void stellaris_adc_init(Object *obj) 119253018216SPaolo Bonzini { 119315c4fff5Sxiaoqiang.zhao DeviceState *dev = DEVICE(obj); 119415c4fff5Sxiaoqiang.zhao stellaris_adc_state *s = STELLARIS_ADC(obj); 119515c4fff5Sxiaoqiang.zhao SysBusDevice *sbd = SYS_BUS_DEVICE(obj); 119653018216SPaolo Bonzini int n; 119753018216SPaolo Bonzini 119853018216SPaolo Bonzini for (n = 0; n < 4; n++) { 11997df7f67aSAndreas Färber sysbus_init_irq(sbd, &s->irq[n]); 120053018216SPaolo Bonzini } 120153018216SPaolo Bonzini 120215c4fff5Sxiaoqiang.zhao memory_region_init_io(&s->iomem, obj, &stellaris_adc_ops, s, 120353018216SPaolo Bonzini "adc", 0x1000); 12047df7f67aSAndreas Färber sysbus_init_mmio(sbd, &s->iomem); 120553018216SPaolo Bonzini stellaris_adc_reset(s); 12067df7f67aSAndreas Färber qdev_init_gpio_in(dev, stellaris_adc_trigger, 1); 120753018216SPaolo Bonzini } 120853018216SPaolo Bonzini 1209d69ffb5bSMichael Davidsaver static 1210d69ffb5bSMichael Davidsaver void do_sys_reset(void *opaque, int n, int level) 1211d69ffb5bSMichael Davidsaver { 1212d69ffb5bSMichael Davidsaver if (level) { 1213cf83f140SEric Blake qemu_system_reset_request(SHUTDOWN_CAUSE_GUEST_RESET); 1214d69ffb5bSMichael Davidsaver } 1215d69ffb5bSMichael Davidsaver } 1216d69ffb5bSMichael Davidsaver 121753018216SPaolo Bonzini /* Board init. */ 121853018216SPaolo Bonzini static stellaris_board_info stellaris_boards[] = { 121953018216SPaolo Bonzini { "LM3S811EVB", 122053018216SPaolo Bonzini 0, 122153018216SPaolo Bonzini 0x0032000e, 122253018216SPaolo Bonzini 0x001f001f, /* dc0 */ 122353018216SPaolo Bonzini 0x001132bf, 122453018216SPaolo Bonzini 0x01071013, 122553018216SPaolo Bonzini 0x3f0f01ff, 122653018216SPaolo Bonzini 0x0000001f, 122753018216SPaolo Bonzini BP_OLED_I2C 122853018216SPaolo Bonzini }, 122953018216SPaolo Bonzini { "LM3S6965EVB", 123053018216SPaolo Bonzini 0x10010002, 123153018216SPaolo Bonzini 0x1073402e, 123253018216SPaolo Bonzini 0x00ff007f, /* dc0 */ 123353018216SPaolo Bonzini 0x001133ff, 123453018216SPaolo Bonzini 0x030f5317, 123553018216SPaolo Bonzini 0x0f0f87ff, 123653018216SPaolo Bonzini 0x5000007f, 123753018216SPaolo Bonzini BP_OLED_SSI | BP_GAMEPAD 123853018216SPaolo Bonzini } 123953018216SPaolo Bonzini }; 124053018216SPaolo Bonzini 1241ba1ba5ccSIgor Mammedov static void stellaris_init(MachineState *ms, stellaris_board_info *board) 124253018216SPaolo Bonzini { 124353018216SPaolo Bonzini static const int uart_irq[] = {5, 6, 33, 34}; 124453018216SPaolo Bonzini static const int timer_irq[] = {19, 21, 23, 35}; 124553018216SPaolo Bonzini static const uint32_t gpio_addr[7] = 124653018216SPaolo Bonzini { 0x40004000, 0x40005000, 0x40006000, 0x40007000, 124753018216SPaolo Bonzini 0x40024000, 0x40025000, 0x40026000}; 124853018216SPaolo Bonzini static const int gpio_irq[7] = {0, 1, 2, 3, 4, 30, 31}; 124953018216SPaolo Bonzini 1250394c8bbfSPeter Maydell /* Memory map of SoC devices, from 1251394c8bbfSPeter Maydell * Stellaris LM3S6965 Microcontroller Data Sheet (rev I) 1252394c8bbfSPeter Maydell * http://www.ti.com/lit/ds/symlink/lm3s6965.pdf 1253394c8bbfSPeter Maydell * 1254566528f8SMichel Heily * 40000000 wdtimer 1255394c8bbfSPeter Maydell * 40002000 i2c (unimplemented) 1256394c8bbfSPeter Maydell * 40004000 GPIO 1257394c8bbfSPeter Maydell * 40005000 GPIO 1258394c8bbfSPeter Maydell * 40006000 GPIO 1259394c8bbfSPeter Maydell * 40007000 GPIO 1260394c8bbfSPeter Maydell * 40008000 SSI 1261394c8bbfSPeter Maydell * 4000c000 UART 1262394c8bbfSPeter Maydell * 4000d000 UART 1263394c8bbfSPeter Maydell * 4000e000 UART 1264394c8bbfSPeter Maydell * 40020000 i2c 1265394c8bbfSPeter Maydell * 40021000 i2c (unimplemented) 1266394c8bbfSPeter Maydell * 40024000 GPIO 1267394c8bbfSPeter Maydell * 40025000 GPIO 1268394c8bbfSPeter Maydell * 40026000 GPIO 1269394c8bbfSPeter Maydell * 40028000 PWM (unimplemented) 1270394c8bbfSPeter Maydell * 4002c000 QEI (unimplemented) 1271394c8bbfSPeter Maydell * 4002d000 QEI (unimplemented) 1272394c8bbfSPeter Maydell * 40030000 gptimer 1273394c8bbfSPeter Maydell * 40031000 gptimer 1274394c8bbfSPeter Maydell * 40032000 gptimer 1275394c8bbfSPeter Maydell * 40033000 gptimer 1276394c8bbfSPeter Maydell * 40038000 ADC 1277394c8bbfSPeter Maydell * 4003c000 analogue comparator (unimplemented) 1278394c8bbfSPeter Maydell * 40048000 ethernet 1279394c8bbfSPeter Maydell * 400fc000 hibernation module (unimplemented) 1280394c8bbfSPeter Maydell * 400fd000 flash memory control (unimplemented) 1281394c8bbfSPeter Maydell * 400fe000 system control 1282394c8bbfSPeter Maydell */ 1283394c8bbfSPeter Maydell 128420c59c38SMichael Davidsaver DeviceState *gpio_dev[7], *nvic; 128553018216SPaolo Bonzini qemu_irq gpio_in[7][8]; 128653018216SPaolo Bonzini qemu_irq gpio_out[7][8]; 128753018216SPaolo Bonzini qemu_irq adc; 128853018216SPaolo Bonzini int sram_size; 128953018216SPaolo Bonzini int flash_size; 1290a5c82852SAndreas Färber I2CBus *i2c; 129153018216SPaolo Bonzini DeviceState *dev; 129253018216SPaolo Bonzini int i; 129353018216SPaolo Bonzini int j; 129453018216SPaolo Bonzini 1295fe6ac447SAlistair Francis MemoryRegion *sram = g_new(MemoryRegion, 1); 1296fe6ac447SAlistair Francis MemoryRegion *flash = g_new(MemoryRegion, 1); 1297fe6ac447SAlistair Francis MemoryRegion *system_memory = get_system_memory(); 1298fe6ac447SAlistair Francis 1299fe6ac447SAlistair Francis flash_size = (((board->dc0 & 0xffff) + 1) << 1) * 1024; 1300fe6ac447SAlistair Francis sram_size = ((board->dc0 >> 18) + 1) * 1024; 1301fe6ac447SAlistair Francis 1302fe6ac447SAlistair Francis /* Flash programming is done via the SCU, so pretend it is ROM. */ 1303*16260006SPhilippe Mathieu-Daudé memory_region_init_rom(flash, NULL, "stellaris.flash", flash_size, 1304f8ed85acSMarkus Armbruster &error_fatal); 1305fe6ac447SAlistair Francis memory_region_add_subregion(system_memory, 0, flash); 1306fe6ac447SAlistair Francis 130798a99ce0SPeter Maydell memory_region_init_ram(sram, NULL, "stellaris.sram", sram_size, 1308f8ed85acSMarkus Armbruster &error_fatal); 1309fe6ac447SAlistair Francis memory_region_add_subregion(system_memory, 0x20000000, sram); 1310fe6ac447SAlistair Francis 1311f04d4465SPeter Maydell nvic = qdev_create(NULL, TYPE_ARMV7M); 1312f04d4465SPeter Maydell qdev_prop_set_uint32(nvic, "num-irq", NUM_IRQ_LINES); 1313f04d4465SPeter Maydell qdev_prop_set_string(nvic, "cpu-type", ms->cpu_type); 1314a1c5a062SStefan Hajnoczi qdev_prop_set_bit(nvic, "enable-bitband", true); 1315f04d4465SPeter Maydell object_property_set_link(OBJECT(nvic), OBJECT(get_system_memory()), 1316f04d4465SPeter Maydell "memory", &error_abort); 1317f04d4465SPeter Maydell /* This will exit with an error if the user passed us a bad cpu_type */ 1318f04d4465SPeter Maydell qdev_init_nofail(nvic); 131953018216SPaolo Bonzini 1320d69ffb5bSMichael Davidsaver qdev_connect_gpio_out_named(nvic, "SYSRESETREQ", 0, 1321d69ffb5bSMichael Davidsaver qemu_allocate_irq(&do_sys_reset, NULL, 0)); 1322d69ffb5bSMichael Davidsaver 132353018216SPaolo Bonzini if (board->dc1 & (1 << 16)) { 13247df7f67aSAndreas Färber dev = sysbus_create_varargs(TYPE_STELLARIS_ADC, 0x40038000, 132520c59c38SMichael Davidsaver qdev_get_gpio_in(nvic, 14), 132620c59c38SMichael Davidsaver qdev_get_gpio_in(nvic, 15), 132720c59c38SMichael Davidsaver qdev_get_gpio_in(nvic, 16), 132820c59c38SMichael Davidsaver qdev_get_gpio_in(nvic, 17), 132920c59c38SMichael Davidsaver NULL); 133053018216SPaolo Bonzini adc = qdev_get_gpio_in(dev, 0); 133153018216SPaolo Bonzini } else { 133253018216SPaolo Bonzini adc = NULL; 133353018216SPaolo Bonzini } 133453018216SPaolo Bonzini for (i = 0; i < 4; i++) { 133553018216SPaolo Bonzini if (board->dc2 & (0x10000 << i)) { 13368ef1d394SAndreas Färber dev = sysbus_create_simple(TYPE_STELLARIS_GPTM, 133753018216SPaolo Bonzini 0x40030000 + i * 0x1000, 133820c59c38SMichael Davidsaver qdev_get_gpio_in(nvic, timer_irq[i])); 133953018216SPaolo Bonzini /* TODO: This is incorrect, but we get away with it because 134053018216SPaolo Bonzini the ADC output is only ever pulsed. */ 134153018216SPaolo Bonzini qdev_connect_gpio_out(dev, 0, adc); 134253018216SPaolo Bonzini } 134353018216SPaolo Bonzini } 134453018216SPaolo Bonzini 134520c59c38SMichael Davidsaver stellaris_sys_init(0x400fe000, qdev_get_gpio_in(nvic, 28), 134620c59c38SMichael Davidsaver board, nd_table[0].macaddr.a); 134753018216SPaolo Bonzini 1348566528f8SMichel Heily 1349566528f8SMichel Heily if (board->dc1 & (1 << 3)) { /* watchdog present */ 1350566528f8SMichel Heily dev = qdev_create(NULL, TYPE_LUMINARY_WATCHDOG); 1351566528f8SMichel Heily 1352566528f8SMichel Heily /* system_clock_scale is valid now */ 1353566528f8SMichel Heily uint32_t mainclk = NANOSECONDS_PER_SECOND / system_clock_scale; 1354566528f8SMichel Heily qdev_prop_set_uint32(dev, "wdogclk-frq", mainclk); 1355566528f8SMichel Heily 1356566528f8SMichel Heily qdev_init_nofail(dev); 1357566528f8SMichel Heily sysbus_mmio_map(SYS_BUS_DEVICE(dev), 1358566528f8SMichel Heily 0, 1359566528f8SMichel Heily 0x40000000u); 1360566528f8SMichel Heily sysbus_connect_irq(SYS_BUS_DEVICE(dev), 1361566528f8SMichel Heily 0, 1362566528f8SMichel Heily qdev_get_gpio_in(nvic, 18)); 1363566528f8SMichel Heily } 1364566528f8SMichel Heily 1365566528f8SMichel Heily 136653018216SPaolo Bonzini for (i = 0; i < 7; i++) { 136753018216SPaolo Bonzini if (board->dc4 & (1 << i)) { 136853018216SPaolo Bonzini gpio_dev[i] = sysbus_create_simple("pl061_luminary", gpio_addr[i], 136920c59c38SMichael Davidsaver qdev_get_gpio_in(nvic, 137020c59c38SMichael Davidsaver gpio_irq[i])); 137153018216SPaolo Bonzini for (j = 0; j < 8; j++) { 137253018216SPaolo Bonzini gpio_in[i][j] = qdev_get_gpio_in(gpio_dev[i], j); 137353018216SPaolo Bonzini gpio_out[i][j] = NULL; 137453018216SPaolo Bonzini } 137553018216SPaolo Bonzini } 137653018216SPaolo Bonzini } 137753018216SPaolo Bonzini 137853018216SPaolo Bonzini if (board->dc2 & (1 << 12)) { 137920c59c38SMichael Davidsaver dev = sysbus_create_simple(TYPE_STELLARIS_I2C, 0x40020000, 138020c59c38SMichael Davidsaver qdev_get_gpio_in(nvic, 8)); 1381a5c82852SAndreas Färber i2c = (I2CBus *)qdev_get_child_bus(dev, "i2c"); 138253018216SPaolo Bonzini if (board->peripherals & BP_OLED_I2C) { 138353018216SPaolo Bonzini i2c_create_slave(i2c, "ssd0303", 0x3d); 138453018216SPaolo Bonzini } 138553018216SPaolo Bonzini } 138653018216SPaolo Bonzini 138753018216SPaolo Bonzini for (i = 0; i < 4; i++) { 138853018216SPaolo Bonzini if (board->dc2 & (1 << i)) { 1389f0d1d2c1Sxiaoqiang zhao pl011_luminary_create(0x4000c000 + i * 0x1000, 1390f0d1d2c1Sxiaoqiang zhao qdev_get_gpio_in(nvic, uart_irq[i]), 13919bca0edbSPeter Maydell serial_hd(i)); 139253018216SPaolo Bonzini } 139353018216SPaolo Bonzini } 139453018216SPaolo Bonzini if (board->dc2 & (1 << 4)) { 139520c59c38SMichael Davidsaver dev = sysbus_create_simple("pl022", 0x40008000, 139620c59c38SMichael Davidsaver qdev_get_gpio_in(nvic, 7)); 139753018216SPaolo Bonzini if (board->peripherals & BP_OLED_SSI) { 139853018216SPaolo Bonzini void *bus; 139953018216SPaolo Bonzini DeviceState *sddev; 140053018216SPaolo Bonzini DeviceState *ssddev; 140153018216SPaolo Bonzini 140253018216SPaolo Bonzini /* Some boards have both an OLED controller and SD card connected to 140353018216SPaolo Bonzini * the same SSI port, with the SD card chip select connected to a 140453018216SPaolo Bonzini * GPIO pin. Technically the OLED chip select is connected to the 140553018216SPaolo Bonzini * SSI Fss pin. We do not bother emulating that as both devices 140653018216SPaolo Bonzini * should never be selected simultaneously, and our OLED controller 140753018216SPaolo Bonzini * ignores stray 0xff commands that occur when deselecting the SD 140853018216SPaolo Bonzini * card. 140953018216SPaolo Bonzini */ 141053018216SPaolo Bonzini bus = qdev_get_child_bus(dev, "ssi"); 141153018216SPaolo Bonzini 141253018216SPaolo Bonzini sddev = ssi_create_slave(bus, "ssi-sd"); 141353018216SPaolo Bonzini ssddev = ssi_create_slave(bus, "ssd0323"); 1414de77914eSPeter Crosthwaite gpio_out[GPIO_D][0] = qemu_irq_split( 1415de77914eSPeter Crosthwaite qdev_get_gpio_in_named(sddev, SSI_GPIO_CS, 0), 1416de77914eSPeter Crosthwaite qdev_get_gpio_in_named(ssddev, SSI_GPIO_CS, 0)); 1417de77914eSPeter Crosthwaite gpio_out[GPIO_C][7] = qdev_get_gpio_in(ssddev, 0); 141853018216SPaolo Bonzini 141953018216SPaolo Bonzini /* Make sure the select pin is high. */ 142053018216SPaolo Bonzini qemu_irq_raise(gpio_out[GPIO_D][0]); 142153018216SPaolo Bonzini } 142253018216SPaolo Bonzini } 142353018216SPaolo Bonzini if (board->dc4 & (1 << 28)) { 142453018216SPaolo Bonzini DeviceState *enet; 142553018216SPaolo Bonzini 142653018216SPaolo Bonzini qemu_check_nic_model(&nd_table[0], "stellaris"); 142753018216SPaolo Bonzini 142853018216SPaolo Bonzini enet = qdev_create(NULL, "stellaris_enet"); 142953018216SPaolo Bonzini qdev_set_nic_properties(enet, &nd_table[0]); 143053018216SPaolo Bonzini qdev_init_nofail(enet); 143153018216SPaolo Bonzini sysbus_mmio_map(SYS_BUS_DEVICE(enet), 0, 0x40048000); 143220c59c38SMichael Davidsaver sysbus_connect_irq(SYS_BUS_DEVICE(enet), 0, qdev_get_gpio_in(nvic, 42)); 143353018216SPaolo Bonzini } 143453018216SPaolo Bonzini if (board->peripherals & BP_GAMEPAD) { 143553018216SPaolo Bonzini qemu_irq gpad_irq[5]; 143653018216SPaolo Bonzini static const int gpad_keycode[5] = { 0xc8, 0xd0, 0xcb, 0xcd, 0x1d }; 143753018216SPaolo Bonzini 143853018216SPaolo Bonzini gpad_irq[0] = qemu_irq_invert(gpio_in[GPIO_E][0]); /* up */ 143953018216SPaolo Bonzini gpad_irq[1] = qemu_irq_invert(gpio_in[GPIO_E][1]); /* down */ 144053018216SPaolo Bonzini gpad_irq[2] = qemu_irq_invert(gpio_in[GPIO_E][2]); /* left */ 144153018216SPaolo Bonzini gpad_irq[3] = qemu_irq_invert(gpio_in[GPIO_E][3]); /* right */ 144253018216SPaolo Bonzini gpad_irq[4] = qemu_irq_invert(gpio_in[GPIO_F][1]); /* select */ 144353018216SPaolo Bonzini 144453018216SPaolo Bonzini stellaris_gamepad_init(5, gpad_irq, gpad_keycode); 144553018216SPaolo Bonzini } 144653018216SPaolo Bonzini for (i = 0; i < 7; i++) { 144753018216SPaolo Bonzini if (board->dc4 & (1 << i)) { 144853018216SPaolo Bonzini for (j = 0; j < 8; j++) { 144953018216SPaolo Bonzini if (gpio_out[i][j]) { 145053018216SPaolo Bonzini qdev_connect_gpio_out(gpio_dev[i], j, gpio_out[i][j]); 145153018216SPaolo Bonzini } 145253018216SPaolo Bonzini } 145353018216SPaolo Bonzini } 145453018216SPaolo Bonzini } 1455aecfbbc9SPeter Maydell 1456aecfbbc9SPeter Maydell /* Add dummy regions for the devices we don't implement yet, 1457aecfbbc9SPeter Maydell * so guest accesses don't cause unlogged crashes. 1458aecfbbc9SPeter Maydell */ 1459aecfbbc9SPeter Maydell create_unimplemented_device("i2c-0", 0x40002000, 0x1000); 1460aecfbbc9SPeter Maydell create_unimplemented_device("i2c-2", 0x40021000, 0x1000); 1461aecfbbc9SPeter Maydell create_unimplemented_device("PWM", 0x40028000, 0x1000); 1462aecfbbc9SPeter Maydell create_unimplemented_device("QEI-0", 0x4002c000, 0x1000); 1463aecfbbc9SPeter Maydell create_unimplemented_device("QEI-1", 0x4002d000, 0x1000); 1464aecfbbc9SPeter Maydell create_unimplemented_device("analogue-comparator", 0x4003c000, 0x1000); 1465aecfbbc9SPeter Maydell create_unimplemented_device("hibernation", 0x400fc000, 0x1000); 1466aecfbbc9SPeter Maydell create_unimplemented_device("flash-control", 0x400fd000, 0x1000); 1467f04d4465SPeter Maydell 1468f04d4465SPeter Maydell armv7m_load_kernel(ARM_CPU(first_cpu), ms->kernel_filename, flash_size); 146953018216SPaolo Bonzini } 147053018216SPaolo Bonzini 147153018216SPaolo Bonzini /* FIXME: Figure out how to generate these from stellaris_boards. */ 14723ef96221SMarcel Apfelbaum static void lm3s811evb_init(MachineState *machine) 147353018216SPaolo Bonzini { 1474ba1ba5ccSIgor Mammedov stellaris_init(machine, &stellaris_boards[0]); 147553018216SPaolo Bonzini } 147653018216SPaolo Bonzini 14773ef96221SMarcel Apfelbaum static void lm3s6965evb_init(MachineState *machine) 147853018216SPaolo Bonzini { 1479ba1ba5ccSIgor Mammedov stellaris_init(machine, &stellaris_boards[1]); 148053018216SPaolo Bonzini } 148153018216SPaolo Bonzini 14828a661aeaSAndreas Färber static void lm3s811evb_class_init(ObjectClass *oc, void *data) 148353018216SPaolo Bonzini { 14848a661aeaSAndreas Färber MachineClass *mc = MACHINE_CLASS(oc); 14858a661aeaSAndreas Färber 1486e264d29dSEduardo Habkost mc->desc = "Stellaris LM3S811EVB"; 1487e264d29dSEduardo Habkost mc->init = lm3s811evb_init; 14884672cbd7SPeter Maydell mc->ignore_memory_transaction_failures = true; 1489ba1ba5ccSIgor Mammedov mc->default_cpu_type = ARM_CPU_TYPE_NAME("cortex-m3"); 149053018216SPaolo Bonzini } 149153018216SPaolo Bonzini 14928a661aeaSAndreas Färber static const TypeInfo lm3s811evb_type = { 14938a661aeaSAndreas Färber .name = MACHINE_TYPE_NAME("lm3s811evb"), 14948a661aeaSAndreas Färber .parent = TYPE_MACHINE, 14958a661aeaSAndreas Färber .class_init = lm3s811evb_class_init, 14968a661aeaSAndreas Färber }; 1497e264d29dSEduardo Habkost 14988a661aeaSAndreas Färber static void lm3s6965evb_class_init(ObjectClass *oc, void *data) 1499e264d29dSEduardo Habkost { 15008a661aeaSAndreas Färber MachineClass *mc = MACHINE_CLASS(oc); 15018a661aeaSAndreas Färber 1502e264d29dSEduardo Habkost mc->desc = "Stellaris LM3S6965EVB"; 1503e264d29dSEduardo Habkost mc->init = lm3s6965evb_init; 15044672cbd7SPeter Maydell mc->ignore_memory_transaction_failures = true; 1505ba1ba5ccSIgor Mammedov mc->default_cpu_type = ARM_CPU_TYPE_NAME("cortex-m3"); 1506e264d29dSEduardo Habkost } 1507e264d29dSEduardo Habkost 15088a661aeaSAndreas Färber static const TypeInfo lm3s6965evb_type = { 15098a661aeaSAndreas Färber .name = MACHINE_TYPE_NAME("lm3s6965evb"), 15108a661aeaSAndreas Färber .parent = TYPE_MACHINE, 15118a661aeaSAndreas Färber .class_init = lm3s6965evb_class_init, 15128a661aeaSAndreas Färber }; 15138a661aeaSAndreas Färber 15148a661aeaSAndreas Färber static void stellaris_machine_init(void) 15158a661aeaSAndreas Färber { 15168a661aeaSAndreas Färber type_register_static(&lm3s811evb_type); 15178a661aeaSAndreas Färber type_register_static(&lm3s6965evb_type); 15188a661aeaSAndreas Färber } 15198a661aeaSAndreas Färber 15200e6aac87SEduardo Habkost type_init(stellaris_machine_init) 152153018216SPaolo Bonzini 152253018216SPaolo Bonzini static void stellaris_i2c_class_init(ObjectClass *klass, void *data) 152353018216SPaolo Bonzini { 152415c4fff5Sxiaoqiang.zhao DeviceClass *dc = DEVICE_CLASS(klass); 152553018216SPaolo Bonzini 152615c4fff5Sxiaoqiang.zhao dc->vmsd = &vmstate_stellaris_i2c; 152753018216SPaolo Bonzini } 152853018216SPaolo Bonzini 152953018216SPaolo Bonzini static const TypeInfo stellaris_i2c_info = { 1530d94a4015SAndreas Färber .name = TYPE_STELLARIS_I2C, 153153018216SPaolo Bonzini .parent = TYPE_SYS_BUS_DEVICE, 153253018216SPaolo Bonzini .instance_size = sizeof(stellaris_i2c_state), 153315c4fff5Sxiaoqiang.zhao .instance_init = stellaris_i2c_init, 153453018216SPaolo Bonzini .class_init = stellaris_i2c_class_init, 153553018216SPaolo Bonzini }; 153653018216SPaolo Bonzini 153753018216SPaolo Bonzini static void stellaris_gptm_class_init(ObjectClass *klass, void *data) 153853018216SPaolo Bonzini { 153915c4fff5Sxiaoqiang.zhao DeviceClass *dc = DEVICE_CLASS(klass); 154053018216SPaolo Bonzini 154115c4fff5Sxiaoqiang.zhao dc->vmsd = &vmstate_stellaris_gptm; 1542af6c91b4SPan Nengyuan dc->realize = stellaris_gptm_realize; 154353018216SPaolo Bonzini } 154453018216SPaolo Bonzini 154553018216SPaolo Bonzini static const TypeInfo stellaris_gptm_info = { 15468ef1d394SAndreas Färber .name = TYPE_STELLARIS_GPTM, 154753018216SPaolo Bonzini .parent = TYPE_SYS_BUS_DEVICE, 154853018216SPaolo Bonzini .instance_size = sizeof(gptm_state), 154915c4fff5Sxiaoqiang.zhao .instance_init = stellaris_gptm_init, 155053018216SPaolo Bonzini .class_init = stellaris_gptm_class_init, 155153018216SPaolo Bonzini }; 155253018216SPaolo Bonzini 155353018216SPaolo Bonzini static void stellaris_adc_class_init(ObjectClass *klass, void *data) 155453018216SPaolo Bonzini { 155515c4fff5Sxiaoqiang.zhao DeviceClass *dc = DEVICE_CLASS(klass); 155653018216SPaolo Bonzini 155715c4fff5Sxiaoqiang.zhao dc->vmsd = &vmstate_stellaris_adc; 155853018216SPaolo Bonzini } 155953018216SPaolo Bonzini 156053018216SPaolo Bonzini static const TypeInfo stellaris_adc_info = { 15617df7f67aSAndreas Färber .name = TYPE_STELLARIS_ADC, 156253018216SPaolo Bonzini .parent = TYPE_SYS_BUS_DEVICE, 156353018216SPaolo Bonzini .instance_size = sizeof(stellaris_adc_state), 156415c4fff5Sxiaoqiang.zhao .instance_init = stellaris_adc_init, 156553018216SPaolo Bonzini .class_init = stellaris_adc_class_init, 156653018216SPaolo Bonzini }; 156753018216SPaolo Bonzini 156853018216SPaolo Bonzini static void stellaris_register_types(void) 156953018216SPaolo Bonzini { 157053018216SPaolo Bonzini type_register_static(&stellaris_i2c_info); 157153018216SPaolo Bonzini type_register_static(&stellaris_gptm_info); 157253018216SPaolo Bonzini type_register_static(&stellaris_adc_info); 157353018216SPaolo Bonzini } 157453018216SPaolo Bonzini 157553018216SPaolo Bonzini type_init(stellaris_register_types) 1576