153018216SPaolo Bonzini /* 253018216SPaolo Bonzini * Luminary Micro Stellaris peripherals 353018216SPaolo Bonzini * 453018216SPaolo Bonzini * Copyright (c) 2006 CodeSourcery. 553018216SPaolo Bonzini * Written by Paul Brook 653018216SPaolo Bonzini * 753018216SPaolo Bonzini * This code is licensed under the GPL. 853018216SPaolo Bonzini */ 953018216SPaolo Bonzini 1012b16722SPeter Maydell #include "qemu/osdep.h" 11da34e65cSMarkus Armbruster #include "qapi/error.h" 1253018216SPaolo Bonzini #include "hw/sysbus.h" 138fd06719SAlistair Francis #include "hw/ssi/ssi.h" 14bd2be150SPeter Maydell #include "hw/arm/arm.h" 15bd2be150SPeter Maydell #include "hw/devices.h" 1653018216SPaolo Bonzini #include "qemu/timer.h" 170d09e41aSPaolo Bonzini #include "hw/i2c/i2c.h" 1853018216SPaolo Bonzini #include "net/net.h" 1953018216SPaolo Bonzini #include "hw/boards.h" 2003dd024fSPaolo Bonzini #include "qemu/log.h" 2153018216SPaolo Bonzini #include "exec/address-spaces.h" 22d69ffb5bSMichael Davidsaver #include "sysemu/sysemu.h" 23f0d1d2c1Sxiaoqiang zhao #include "hw/char/pl011.h" 24aecfbbc9SPeter Maydell #include "hw/misc/unimp.h" 2553018216SPaolo Bonzini 2653018216SPaolo Bonzini #define GPIO_A 0 2753018216SPaolo Bonzini #define GPIO_B 1 2853018216SPaolo Bonzini #define GPIO_C 2 2953018216SPaolo Bonzini #define GPIO_D 3 3053018216SPaolo Bonzini #define GPIO_E 4 3153018216SPaolo Bonzini #define GPIO_F 5 3253018216SPaolo Bonzini #define GPIO_G 6 3353018216SPaolo Bonzini 3453018216SPaolo Bonzini #define BP_OLED_I2C 0x01 3553018216SPaolo Bonzini #define BP_OLED_SSI 0x02 3653018216SPaolo Bonzini #define BP_GAMEPAD 0x04 3753018216SPaolo Bonzini 388b47b7daSAlistair Francis #define NUM_IRQ_LINES 64 398b47b7daSAlistair Francis 4053018216SPaolo Bonzini typedef const struct { 4153018216SPaolo Bonzini const char *name; 4253018216SPaolo Bonzini uint32_t did0; 4353018216SPaolo Bonzini uint32_t did1; 4453018216SPaolo Bonzini uint32_t dc0; 4553018216SPaolo Bonzini uint32_t dc1; 4653018216SPaolo Bonzini uint32_t dc2; 4753018216SPaolo Bonzini uint32_t dc3; 4853018216SPaolo Bonzini uint32_t dc4; 4953018216SPaolo Bonzini uint32_t peripherals; 5053018216SPaolo Bonzini } stellaris_board_info; 5153018216SPaolo Bonzini 5253018216SPaolo Bonzini /* General purpose timer module. */ 5353018216SPaolo Bonzini 548ef1d394SAndreas Färber #define TYPE_STELLARIS_GPTM "stellaris-gptm" 558ef1d394SAndreas Färber #define STELLARIS_GPTM(obj) \ 568ef1d394SAndreas Färber OBJECT_CHECK(gptm_state, (obj), TYPE_STELLARIS_GPTM) 578ef1d394SAndreas Färber 5853018216SPaolo Bonzini typedef struct gptm_state { 598ef1d394SAndreas Färber SysBusDevice parent_obj; 608ef1d394SAndreas Färber 6153018216SPaolo Bonzini MemoryRegion iomem; 6253018216SPaolo Bonzini uint32_t config; 6353018216SPaolo Bonzini uint32_t mode[2]; 6453018216SPaolo Bonzini uint32_t control; 6553018216SPaolo Bonzini uint32_t state; 6653018216SPaolo Bonzini uint32_t mask; 6753018216SPaolo Bonzini uint32_t load[2]; 6853018216SPaolo Bonzini uint32_t match[2]; 6953018216SPaolo Bonzini uint32_t prescale[2]; 7053018216SPaolo Bonzini uint32_t match_prescale[2]; 7153018216SPaolo Bonzini uint32_t rtc; 7253018216SPaolo Bonzini int64_t tick[2]; 7353018216SPaolo Bonzini struct gptm_state *opaque[2]; 7453018216SPaolo Bonzini QEMUTimer *timer[2]; 7553018216SPaolo Bonzini /* The timers have an alternate output used to trigger the ADC. */ 7653018216SPaolo Bonzini qemu_irq trigger; 7753018216SPaolo Bonzini qemu_irq irq; 7853018216SPaolo Bonzini } gptm_state; 7953018216SPaolo Bonzini 8053018216SPaolo Bonzini static void gptm_update_irq(gptm_state *s) 8153018216SPaolo Bonzini { 8253018216SPaolo Bonzini int level; 8353018216SPaolo Bonzini level = (s->state & s->mask) != 0; 8453018216SPaolo Bonzini qemu_set_irq(s->irq, level); 8553018216SPaolo Bonzini } 8653018216SPaolo Bonzini 8753018216SPaolo Bonzini static void gptm_stop(gptm_state *s, int n) 8853018216SPaolo Bonzini { 89bc72ad67SAlex Bligh timer_del(s->timer[n]); 9053018216SPaolo Bonzini } 9153018216SPaolo Bonzini 9253018216SPaolo Bonzini static void gptm_reload(gptm_state *s, int n, int reset) 9353018216SPaolo Bonzini { 9453018216SPaolo Bonzini int64_t tick; 9553018216SPaolo Bonzini if (reset) 96bc72ad67SAlex Bligh tick = qemu_clock_get_ns(QEMU_CLOCK_VIRTUAL); 9753018216SPaolo Bonzini else 9853018216SPaolo Bonzini tick = s->tick[n]; 9953018216SPaolo Bonzini 10053018216SPaolo Bonzini if (s->config == 0) { 10153018216SPaolo Bonzini /* 32-bit CountDown. */ 10253018216SPaolo Bonzini uint32_t count; 10353018216SPaolo Bonzini count = s->load[0] | (s->load[1] << 16); 10453018216SPaolo Bonzini tick += (int64_t)count * system_clock_scale; 10553018216SPaolo Bonzini } else if (s->config == 1) { 10653018216SPaolo Bonzini /* 32-bit RTC. 1Hz tick. */ 10773bcb24dSRutuja Shah tick += NANOSECONDS_PER_SECOND; 10853018216SPaolo Bonzini } else if (s->mode[n] == 0xa) { 10953018216SPaolo Bonzini /* PWM mode. Not implemented. */ 11053018216SPaolo Bonzini } else { 111df3692e0SPeter Maydell qemu_log_mask(LOG_UNIMP, 112df3692e0SPeter Maydell "GPTM: 16-bit timer mode unimplemented: 0x%x\n", 113df3692e0SPeter Maydell s->mode[n]); 114df3692e0SPeter Maydell return; 11553018216SPaolo Bonzini } 11653018216SPaolo Bonzini s->tick[n] = tick; 117bc72ad67SAlex Bligh timer_mod(s->timer[n], tick); 11853018216SPaolo Bonzini } 11953018216SPaolo Bonzini 12053018216SPaolo Bonzini static void gptm_tick(void *opaque) 12153018216SPaolo Bonzini { 12253018216SPaolo Bonzini gptm_state **p = (gptm_state **)opaque; 12353018216SPaolo Bonzini gptm_state *s; 12453018216SPaolo Bonzini int n; 12553018216SPaolo Bonzini 12653018216SPaolo Bonzini s = *p; 12753018216SPaolo Bonzini n = p - s->opaque; 12853018216SPaolo Bonzini if (s->config == 0) { 12953018216SPaolo Bonzini s->state |= 1; 13053018216SPaolo Bonzini if ((s->control & 0x20)) { 13153018216SPaolo Bonzini /* Output trigger. */ 13253018216SPaolo Bonzini qemu_irq_pulse(s->trigger); 13353018216SPaolo Bonzini } 13453018216SPaolo Bonzini if (s->mode[0] & 1) { 13553018216SPaolo Bonzini /* One-shot. */ 13653018216SPaolo Bonzini s->control &= ~1; 13753018216SPaolo Bonzini } else { 13853018216SPaolo Bonzini /* Periodic. */ 13953018216SPaolo Bonzini gptm_reload(s, 0, 0); 14053018216SPaolo Bonzini } 14153018216SPaolo Bonzini } else if (s->config == 1) { 14253018216SPaolo Bonzini /* RTC. */ 14353018216SPaolo Bonzini uint32_t match; 14453018216SPaolo Bonzini s->rtc++; 14553018216SPaolo Bonzini match = s->match[0] | (s->match[1] << 16); 14653018216SPaolo Bonzini if (s->rtc > match) 14753018216SPaolo Bonzini s->rtc = 0; 14853018216SPaolo Bonzini if (s->rtc == 0) { 14953018216SPaolo Bonzini s->state |= 8; 15053018216SPaolo Bonzini } 15153018216SPaolo Bonzini gptm_reload(s, 0, 0); 15253018216SPaolo Bonzini } else if (s->mode[n] == 0xa) { 15353018216SPaolo Bonzini /* PWM mode. Not implemented. */ 15453018216SPaolo Bonzini } else { 155df3692e0SPeter Maydell qemu_log_mask(LOG_UNIMP, 156df3692e0SPeter Maydell "GPTM: 16-bit timer mode unimplemented: 0x%x\n", 157df3692e0SPeter Maydell s->mode[n]); 15853018216SPaolo Bonzini } 15953018216SPaolo Bonzini gptm_update_irq(s); 16053018216SPaolo Bonzini } 16153018216SPaolo Bonzini 16253018216SPaolo Bonzini static uint64_t gptm_read(void *opaque, hwaddr offset, 16353018216SPaolo Bonzini unsigned size) 16453018216SPaolo Bonzini { 16553018216SPaolo Bonzini gptm_state *s = (gptm_state *)opaque; 16653018216SPaolo Bonzini 16753018216SPaolo Bonzini switch (offset) { 16853018216SPaolo Bonzini case 0x00: /* CFG */ 16953018216SPaolo Bonzini return s->config; 17053018216SPaolo Bonzini case 0x04: /* TAMR */ 17153018216SPaolo Bonzini return s->mode[0]; 17253018216SPaolo Bonzini case 0x08: /* TBMR */ 17353018216SPaolo Bonzini return s->mode[1]; 17453018216SPaolo Bonzini case 0x0c: /* CTL */ 17553018216SPaolo Bonzini return s->control; 17653018216SPaolo Bonzini case 0x18: /* IMR */ 17753018216SPaolo Bonzini return s->mask; 17853018216SPaolo Bonzini case 0x1c: /* RIS */ 17953018216SPaolo Bonzini return s->state; 18053018216SPaolo Bonzini case 0x20: /* MIS */ 18153018216SPaolo Bonzini return s->state & s->mask; 18253018216SPaolo Bonzini case 0x24: /* CR */ 18353018216SPaolo Bonzini return 0; 18453018216SPaolo Bonzini case 0x28: /* TAILR */ 18553018216SPaolo Bonzini return s->load[0] | ((s->config < 4) ? (s->load[1] << 16) : 0); 18653018216SPaolo Bonzini case 0x2c: /* TBILR */ 18753018216SPaolo Bonzini return s->load[1]; 18853018216SPaolo Bonzini case 0x30: /* TAMARCHR */ 18953018216SPaolo Bonzini return s->match[0] | ((s->config < 4) ? (s->match[1] << 16) : 0); 19053018216SPaolo Bonzini case 0x34: /* TBMATCHR */ 19153018216SPaolo Bonzini return s->match[1]; 19253018216SPaolo Bonzini case 0x38: /* TAPR */ 19353018216SPaolo Bonzini return s->prescale[0]; 19453018216SPaolo Bonzini case 0x3c: /* TBPR */ 19553018216SPaolo Bonzini return s->prescale[1]; 19653018216SPaolo Bonzini case 0x40: /* TAPMR */ 19753018216SPaolo Bonzini return s->match_prescale[0]; 19853018216SPaolo Bonzini case 0x44: /* TBPMR */ 19953018216SPaolo Bonzini return s->match_prescale[1]; 20053018216SPaolo Bonzini case 0x48: /* TAR */ 2011a791721SPeter Maydell if (s->config == 1) { 20253018216SPaolo Bonzini return s->rtc; 2031a791721SPeter Maydell } 2041a791721SPeter Maydell qemu_log_mask(LOG_UNIMP, 2051a791721SPeter Maydell "GPTM: read of TAR but timer read not supported"); 2061a791721SPeter Maydell return 0; 20753018216SPaolo Bonzini case 0x4c: /* TBR */ 2081a791721SPeter Maydell qemu_log_mask(LOG_UNIMP, 2091a791721SPeter Maydell "GPTM: read of TBR but timer read not supported"); 2101a791721SPeter Maydell return 0; 21153018216SPaolo Bonzini default: 2121a791721SPeter Maydell qemu_log_mask(LOG_GUEST_ERROR, 2131a791721SPeter Maydell "GPTM: read at bad offset 0x%x\n", (int)offset); 21453018216SPaolo Bonzini return 0; 21553018216SPaolo Bonzini } 21653018216SPaolo Bonzini } 21753018216SPaolo Bonzini 21853018216SPaolo Bonzini static void gptm_write(void *opaque, hwaddr offset, 21953018216SPaolo Bonzini uint64_t value, unsigned size) 22053018216SPaolo Bonzini { 22153018216SPaolo Bonzini gptm_state *s = (gptm_state *)opaque; 22253018216SPaolo Bonzini uint32_t oldval; 22353018216SPaolo Bonzini 22453018216SPaolo Bonzini /* The timers should be disabled before changing the configuration. 22553018216SPaolo Bonzini We take advantage of this and defer everything until the timer 22653018216SPaolo Bonzini is enabled. */ 22753018216SPaolo Bonzini switch (offset) { 22853018216SPaolo Bonzini case 0x00: /* CFG */ 22953018216SPaolo Bonzini s->config = value; 23053018216SPaolo Bonzini break; 23153018216SPaolo Bonzini case 0x04: /* TAMR */ 23253018216SPaolo Bonzini s->mode[0] = value; 23353018216SPaolo Bonzini break; 23453018216SPaolo Bonzini case 0x08: /* TBMR */ 23553018216SPaolo Bonzini s->mode[1] = value; 23653018216SPaolo Bonzini break; 23753018216SPaolo Bonzini case 0x0c: /* CTL */ 23853018216SPaolo Bonzini oldval = s->control; 23953018216SPaolo Bonzini s->control = value; 24053018216SPaolo Bonzini /* TODO: Implement pause. */ 24153018216SPaolo Bonzini if ((oldval ^ value) & 1) { 24253018216SPaolo Bonzini if (value & 1) { 24353018216SPaolo Bonzini gptm_reload(s, 0, 1); 24453018216SPaolo Bonzini } else { 24553018216SPaolo Bonzini gptm_stop(s, 0); 24653018216SPaolo Bonzini } 24753018216SPaolo Bonzini } 24853018216SPaolo Bonzini if (((oldval ^ value) & 0x100) && s->config >= 4) { 24953018216SPaolo Bonzini if (value & 0x100) { 25053018216SPaolo Bonzini gptm_reload(s, 1, 1); 25153018216SPaolo Bonzini } else { 25253018216SPaolo Bonzini gptm_stop(s, 1); 25353018216SPaolo Bonzini } 25453018216SPaolo Bonzini } 25553018216SPaolo Bonzini break; 25653018216SPaolo Bonzini case 0x18: /* IMR */ 25753018216SPaolo Bonzini s->mask = value & 0x77; 25853018216SPaolo Bonzini gptm_update_irq(s); 25953018216SPaolo Bonzini break; 26053018216SPaolo Bonzini case 0x24: /* CR */ 26153018216SPaolo Bonzini s->state &= ~value; 26253018216SPaolo Bonzini break; 26353018216SPaolo Bonzini case 0x28: /* TAILR */ 26453018216SPaolo Bonzini s->load[0] = value & 0xffff; 26553018216SPaolo Bonzini if (s->config < 4) { 26653018216SPaolo Bonzini s->load[1] = value >> 16; 26753018216SPaolo Bonzini } 26853018216SPaolo Bonzini break; 26953018216SPaolo Bonzini case 0x2c: /* TBILR */ 27053018216SPaolo Bonzini s->load[1] = value & 0xffff; 27153018216SPaolo Bonzini break; 27253018216SPaolo Bonzini case 0x30: /* TAMARCHR */ 27353018216SPaolo Bonzini s->match[0] = value & 0xffff; 27453018216SPaolo Bonzini if (s->config < 4) { 27553018216SPaolo Bonzini s->match[1] = value >> 16; 27653018216SPaolo Bonzini } 27753018216SPaolo Bonzini break; 27853018216SPaolo Bonzini case 0x34: /* TBMATCHR */ 27953018216SPaolo Bonzini s->match[1] = value >> 16; 28053018216SPaolo Bonzini break; 28153018216SPaolo Bonzini case 0x38: /* TAPR */ 28253018216SPaolo Bonzini s->prescale[0] = value; 28353018216SPaolo Bonzini break; 28453018216SPaolo Bonzini case 0x3c: /* TBPR */ 28553018216SPaolo Bonzini s->prescale[1] = value; 28653018216SPaolo Bonzini break; 28753018216SPaolo Bonzini case 0x40: /* TAPMR */ 28853018216SPaolo Bonzini s->match_prescale[0] = value; 28953018216SPaolo Bonzini break; 29053018216SPaolo Bonzini case 0x44: /* TBPMR */ 29153018216SPaolo Bonzini s->match_prescale[0] = value; 29253018216SPaolo Bonzini break; 29353018216SPaolo Bonzini default: 294df3692e0SPeter Maydell qemu_log_mask(LOG_GUEST_ERROR, 295df3692e0SPeter Maydell "GPTM: read at bad offset 0x%x\n", (int)offset); 29653018216SPaolo Bonzini } 29753018216SPaolo Bonzini gptm_update_irq(s); 29853018216SPaolo Bonzini } 29953018216SPaolo Bonzini 30053018216SPaolo Bonzini static const MemoryRegionOps gptm_ops = { 30153018216SPaolo Bonzini .read = gptm_read, 30253018216SPaolo Bonzini .write = gptm_write, 30353018216SPaolo Bonzini .endianness = DEVICE_NATIVE_ENDIAN, 30453018216SPaolo Bonzini }; 30553018216SPaolo Bonzini 30653018216SPaolo Bonzini static const VMStateDescription vmstate_stellaris_gptm = { 30753018216SPaolo Bonzini .name = "stellaris_gptm", 30853018216SPaolo Bonzini .version_id = 1, 30953018216SPaolo Bonzini .minimum_version_id = 1, 31053018216SPaolo Bonzini .fields = (VMStateField[]) { 31153018216SPaolo Bonzini VMSTATE_UINT32(config, gptm_state), 31253018216SPaolo Bonzini VMSTATE_UINT32_ARRAY(mode, gptm_state, 2), 31353018216SPaolo Bonzini VMSTATE_UINT32(control, gptm_state), 31453018216SPaolo Bonzini VMSTATE_UINT32(state, gptm_state), 31553018216SPaolo Bonzini VMSTATE_UINT32(mask, gptm_state), 31653018216SPaolo Bonzini VMSTATE_UNUSED(8), 31753018216SPaolo Bonzini VMSTATE_UINT32_ARRAY(load, gptm_state, 2), 31853018216SPaolo Bonzini VMSTATE_UINT32_ARRAY(match, gptm_state, 2), 31953018216SPaolo Bonzini VMSTATE_UINT32_ARRAY(prescale, gptm_state, 2), 32053018216SPaolo Bonzini VMSTATE_UINT32_ARRAY(match_prescale, gptm_state, 2), 32153018216SPaolo Bonzini VMSTATE_UINT32(rtc, gptm_state), 32253018216SPaolo Bonzini VMSTATE_INT64_ARRAY(tick, gptm_state, 2), 323e720677eSPaolo Bonzini VMSTATE_TIMER_PTR_ARRAY(timer, gptm_state, 2), 32453018216SPaolo Bonzini VMSTATE_END_OF_LIST() 32553018216SPaolo Bonzini } 32653018216SPaolo Bonzini }; 32753018216SPaolo Bonzini 32815c4fff5Sxiaoqiang.zhao static void stellaris_gptm_init(Object *obj) 32953018216SPaolo Bonzini { 33015c4fff5Sxiaoqiang.zhao DeviceState *dev = DEVICE(obj); 33115c4fff5Sxiaoqiang.zhao gptm_state *s = STELLARIS_GPTM(obj); 33215c4fff5Sxiaoqiang.zhao SysBusDevice *sbd = SYS_BUS_DEVICE(obj); 33353018216SPaolo Bonzini 3348ef1d394SAndreas Färber sysbus_init_irq(sbd, &s->irq); 3358ef1d394SAndreas Färber qdev_init_gpio_out(dev, &s->trigger, 1); 33653018216SPaolo Bonzini 33715c4fff5Sxiaoqiang.zhao memory_region_init_io(&s->iomem, obj, &gptm_ops, s, 33853018216SPaolo Bonzini "gptm", 0x1000); 3398ef1d394SAndreas Färber sysbus_init_mmio(sbd, &s->iomem); 34053018216SPaolo Bonzini 34153018216SPaolo Bonzini s->opaque[0] = s->opaque[1] = s; 342bc72ad67SAlex Bligh s->timer[0] = timer_new_ns(QEMU_CLOCK_VIRTUAL, gptm_tick, &s->opaque[0]); 343bc72ad67SAlex Bligh s->timer[1] = timer_new_ns(QEMU_CLOCK_VIRTUAL, gptm_tick, &s->opaque[1]); 34453018216SPaolo Bonzini } 34553018216SPaolo Bonzini 34653018216SPaolo Bonzini 34753018216SPaolo Bonzini /* System controller. */ 34853018216SPaolo Bonzini 34953018216SPaolo Bonzini typedef struct { 35053018216SPaolo Bonzini MemoryRegion iomem; 35153018216SPaolo Bonzini uint32_t pborctl; 35253018216SPaolo Bonzini uint32_t ldopctl; 35353018216SPaolo Bonzini uint32_t int_status; 35453018216SPaolo Bonzini uint32_t int_mask; 35553018216SPaolo Bonzini uint32_t resc; 35653018216SPaolo Bonzini uint32_t rcc; 35753018216SPaolo Bonzini uint32_t rcc2; 35853018216SPaolo Bonzini uint32_t rcgc[3]; 35953018216SPaolo Bonzini uint32_t scgc[3]; 36053018216SPaolo Bonzini uint32_t dcgc[3]; 36153018216SPaolo Bonzini uint32_t clkvclr; 36253018216SPaolo Bonzini uint32_t ldoarst; 36353018216SPaolo Bonzini uint32_t user0; 36453018216SPaolo Bonzini uint32_t user1; 36553018216SPaolo Bonzini qemu_irq irq; 36653018216SPaolo Bonzini stellaris_board_info *board; 36753018216SPaolo Bonzini } ssys_state; 36853018216SPaolo Bonzini 36953018216SPaolo Bonzini static void ssys_update(ssys_state *s) 37053018216SPaolo Bonzini { 37153018216SPaolo Bonzini qemu_set_irq(s->irq, (s->int_status & s->int_mask) != 0); 37253018216SPaolo Bonzini } 37353018216SPaolo Bonzini 37453018216SPaolo Bonzini static uint32_t pllcfg_sandstorm[16] = { 37553018216SPaolo Bonzini 0x31c0, /* 1 Mhz */ 37653018216SPaolo Bonzini 0x1ae0, /* 1.8432 Mhz */ 37753018216SPaolo Bonzini 0x18c0, /* 2 Mhz */ 37853018216SPaolo Bonzini 0xd573, /* 2.4576 Mhz */ 37953018216SPaolo Bonzini 0x37a6, /* 3.57954 Mhz */ 38053018216SPaolo Bonzini 0x1ae2, /* 3.6864 Mhz */ 38153018216SPaolo Bonzini 0x0c40, /* 4 Mhz */ 38253018216SPaolo Bonzini 0x98bc, /* 4.906 Mhz */ 38353018216SPaolo Bonzini 0x935b, /* 4.9152 Mhz */ 38453018216SPaolo Bonzini 0x09c0, /* 5 Mhz */ 38553018216SPaolo Bonzini 0x4dee, /* 5.12 Mhz */ 38653018216SPaolo Bonzini 0x0c41, /* 6 Mhz */ 38753018216SPaolo Bonzini 0x75db, /* 6.144 Mhz */ 38853018216SPaolo Bonzini 0x1ae6, /* 7.3728 Mhz */ 38953018216SPaolo Bonzini 0x0600, /* 8 Mhz */ 39053018216SPaolo Bonzini 0x585b /* 8.192 Mhz */ 39153018216SPaolo Bonzini }; 39253018216SPaolo Bonzini 39353018216SPaolo Bonzini static uint32_t pllcfg_fury[16] = { 39453018216SPaolo Bonzini 0x3200, /* 1 Mhz */ 39553018216SPaolo Bonzini 0x1b20, /* 1.8432 Mhz */ 39653018216SPaolo Bonzini 0x1900, /* 2 Mhz */ 39753018216SPaolo Bonzini 0xf42b, /* 2.4576 Mhz */ 39853018216SPaolo Bonzini 0x37e3, /* 3.57954 Mhz */ 39953018216SPaolo Bonzini 0x1b21, /* 3.6864 Mhz */ 40053018216SPaolo Bonzini 0x0c80, /* 4 Mhz */ 40153018216SPaolo Bonzini 0x98ee, /* 4.906 Mhz */ 40253018216SPaolo Bonzini 0xd5b4, /* 4.9152 Mhz */ 40353018216SPaolo Bonzini 0x0a00, /* 5 Mhz */ 40453018216SPaolo Bonzini 0x4e27, /* 5.12 Mhz */ 40553018216SPaolo Bonzini 0x1902, /* 6 Mhz */ 40653018216SPaolo Bonzini 0xec1c, /* 6.144 Mhz */ 40753018216SPaolo Bonzini 0x1b23, /* 7.3728 Mhz */ 40853018216SPaolo Bonzini 0x0640, /* 8 Mhz */ 40953018216SPaolo Bonzini 0xb11c /* 8.192 Mhz */ 41053018216SPaolo Bonzini }; 41153018216SPaolo Bonzini 41253018216SPaolo Bonzini #define DID0_VER_MASK 0x70000000 41353018216SPaolo Bonzini #define DID0_VER_0 0x00000000 41453018216SPaolo Bonzini #define DID0_VER_1 0x10000000 41553018216SPaolo Bonzini 41653018216SPaolo Bonzini #define DID0_CLASS_MASK 0x00FF0000 41753018216SPaolo Bonzini #define DID0_CLASS_SANDSTORM 0x00000000 41853018216SPaolo Bonzini #define DID0_CLASS_FURY 0x00010000 41953018216SPaolo Bonzini 42053018216SPaolo Bonzini static int ssys_board_class(const ssys_state *s) 42153018216SPaolo Bonzini { 42253018216SPaolo Bonzini uint32_t did0 = s->board->did0; 42353018216SPaolo Bonzini switch (did0 & DID0_VER_MASK) { 42453018216SPaolo Bonzini case DID0_VER_0: 42553018216SPaolo Bonzini return DID0_CLASS_SANDSTORM; 42653018216SPaolo Bonzini case DID0_VER_1: 42753018216SPaolo Bonzini switch (did0 & DID0_CLASS_MASK) { 42853018216SPaolo Bonzini case DID0_CLASS_SANDSTORM: 42953018216SPaolo Bonzini case DID0_CLASS_FURY: 43053018216SPaolo Bonzini return did0 & DID0_CLASS_MASK; 43153018216SPaolo Bonzini } 43253018216SPaolo Bonzini /* for unknown classes, fall through */ 43353018216SPaolo Bonzini default: 434df3692e0SPeter Maydell /* This can only happen if the hardwired constant did0 value 435df3692e0SPeter Maydell * in this board's stellaris_board_info struct is wrong. 436df3692e0SPeter Maydell */ 437df3692e0SPeter Maydell g_assert_not_reached(); 43853018216SPaolo Bonzini } 43953018216SPaolo Bonzini } 44053018216SPaolo Bonzini 44153018216SPaolo Bonzini static uint64_t ssys_read(void *opaque, hwaddr offset, 44253018216SPaolo Bonzini unsigned size) 44353018216SPaolo Bonzini { 44453018216SPaolo Bonzini ssys_state *s = (ssys_state *)opaque; 44553018216SPaolo Bonzini 44653018216SPaolo Bonzini switch (offset) { 44753018216SPaolo Bonzini case 0x000: /* DID0 */ 44853018216SPaolo Bonzini return s->board->did0; 44953018216SPaolo Bonzini case 0x004: /* DID1 */ 45053018216SPaolo Bonzini return s->board->did1; 45153018216SPaolo Bonzini case 0x008: /* DC0 */ 45253018216SPaolo Bonzini return s->board->dc0; 45353018216SPaolo Bonzini case 0x010: /* DC1 */ 45453018216SPaolo Bonzini return s->board->dc1; 45553018216SPaolo Bonzini case 0x014: /* DC2 */ 45653018216SPaolo Bonzini return s->board->dc2; 45753018216SPaolo Bonzini case 0x018: /* DC3 */ 45853018216SPaolo Bonzini return s->board->dc3; 45953018216SPaolo Bonzini case 0x01c: /* DC4 */ 46053018216SPaolo Bonzini return s->board->dc4; 46153018216SPaolo Bonzini case 0x030: /* PBORCTL */ 46253018216SPaolo Bonzini return s->pborctl; 46353018216SPaolo Bonzini case 0x034: /* LDOPCTL */ 46453018216SPaolo Bonzini return s->ldopctl; 46553018216SPaolo Bonzini case 0x040: /* SRCR0 */ 46653018216SPaolo Bonzini return 0; 46753018216SPaolo Bonzini case 0x044: /* SRCR1 */ 46853018216SPaolo Bonzini return 0; 46953018216SPaolo Bonzini case 0x048: /* SRCR2 */ 47053018216SPaolo Bonzini return 0; 47153018216SPaolo Bonzini case 0x050: /* RIS */ 47253018216SPaolo Bonzini return s->int_status; 47353018216SPaolo Bonzini case 0x054: /* IMC */ 47453018216SPaolo Bonzini return s->int_mask; 47553018216SPaolo Bonzini case 0x058: /* MISC */ 47653018216SPaolo Bonzini return s->int_status & s->int_mask; 47753018216SPaolo Bonzini case 0x05c: /* RESC */ 47853018216SPaolo Bonzini return s->resc; 47953018216SPaolo Bonzini case 0x060: /* RCC */ 48053018216SPaolo Bonzini return s->rcc; 48153018216SPaolo Bonzini case 0x064: /* PLLCFG */ 48253018216SPaolo Bonzini { 48353018216SPaolo Bonzini int xtal; 48453018216SPaolo Bonzini xtal = (s->rcc >> 6) & 0xf; 48553018216SPaolo Bonzini switch (ssys_board_class(s)) { 48653018216SPaolo Bonzini case DID0_CLASS_FURY: 48753018216SPaolo Bonzini return pllcfg_fury[xtal]; 48853018216SPaolo Bonzini case DID0_CLASS_SANDSTORM: 48953018216SPaolo Bonzini return pllcfg_sandstorm[xtal]; 49053018216SPaolo Bonzini default: 491df3692e0SPeter Maydell g_assert_not_reached(); 49253018216SPaolo Bonzini } 49353018216SPaolo Bonzini } 49453018216SPaolo Bonzini case 0x070: /* RCC2 */ 49553018216SPaolo Bonzini return s->rcc2; 49653018216SPaolo Bonzini case 0x100: /* RCGC0 */ 49753018216SPaolo Bonzini return s->rcgc[0]; 49853018216SPaolo Bonzini case 0x104: /* RCGC1 */ 49953018216SPaolo Bonzini return s->rcgc[1]; 50053018216SPaolo Bonzini case 0x108: /* RCGC2 */ 50153018216SPaolo Bonzini return s->rcgc[2]; 50253018216SPaolo Bonzini case 0x110: /* SCGC0 */ 50353018216SPaolo Bonzini return s->scgc[0]; 50453018216SPaolo Bonzini case 0x114: /* SCGC1 */ 50553018216SPaolo Bonzini return s->scgc[1]; 50653018216SPaolo Bonzini case 0x118: /* SCGC2 */ 50753018216SPaolo Bonzini return s->scgc[2]; 50853018216SPaolo Bonzini case 0x120: /* DCGC0 */ 50953018216SPaolo Bonzini return s->dcgc[0]; 51053018216SPaolo Bonzini case 0x124: /* DCGC1 */ 51153018216SPaolo Bonzini return s->dcgc[1]; 51253018216SPaolo Bonzini case 0x128: /* DCGC2 */ 51353018216SPaolo Bonzini return s->dcgc[2]; 51453018216SPaolo Bonzini case 0x150: /* CLKVCLR */ 51553018216SPaolo Bonzini return s->clkvclr; 51653018216SPaolo Bonzini case 0x160: /* LDOARST */ 51753018216SPaolo Bonzini return s->ldoarst; 51853018216SPaolo Bonzini case 0x1e0: /* USER0 */ 51953018216SPaolo Bonzini return s->user0; 52053018216SPaolo Bonzini case 0x1e4: /* USER1 */ 52153018216SPaolo Bonzini return s->user1; 52253018216SPaolo Bonzini default: 523df3692e0SPeter Maydell qemu_log_mask(LOG_GUEST_ERROR, 524df3692e0SPeter Maydell "SSYS: read at bad offset 0x%x\n", (int)offset); 52553018216SPaolo Bonzini return 0; 52653018216SPaolo Bonzini } 52753018216SPaolo Bonzini } 52853018216SPaolo Bonzini 52953018216SPaolo Bonzini static bool ssys_use_rcc2(ssys_state *s) 53053018216SPaolo Bonzini { 53153018216SPaolo Bonzini return (s->rcc2 >> 31) & 0x1; 53253018216SPaolo Bonzini } 53353018216SPaolo Bonzini 53453018216SPaolo Bonzini /* 53553018216SPaolo Bonzini * Caculate the sys. clock period in ms. 53653018216SPaolo Bonzini */ 53753018216SPaolo Bonzini static void ssys_calculate_system_clock(ssys_state *s) 53853018216SPaolo Bonzini { 53953018216SPaolo Bonzini if (ssys_use_rcc2(s)) { 54053018216SPaolo Bonzini system_clock_scale = 5 * (((s->rcc2 >> 23) & 0x3f) + 1); 54153018216SPaolo Bonzini } else { 54253018216SPaolo Bonzini system_clock_scale = 5 * (((s->rcc >> 23) & 0xf) + 1); 54353018216SPaolo Bonzini } 54453018216SPaolo Bonzini } 54553018216SPaolo Bonzini 54653018216SPaolo Bonzini static void ssys_write(void *opaque, hwaddr offset, 54753018216SPaolo Bonzini uint64_t value, unsigned size) 54853018216SPaolo Bonzini { 54953018216SPaolo Bonzini ssys_state *s = (ssys_state *)opaque; 55053018216SPaolo Bonzini 55153018216SPaolo Bonzini switch (offset) { 55253018216SPaolo Bonzini case 0x030: /* PBORCTL */ 55353018216SPaolo Bonzini s->pborctl = value & 0xffff; 55453018216SPaolo Bonzini break; 55553018216SPaolo Bonzini case 0x034: /* LDOPCTL */ 55653018216SPaolo Bonzini s->ldopctl = value & 0x1f; 55753018216SPaolo Bonzini break; 55853018216SPaolo Bonzini case 0x040: /* SRCR0 */ 55953018216SPaolo Bonzini case 0x044: /* SRCR1 */ 56053018216SPaolo Bonzini case 0x048: /* SRCR2 */ 56153018216SPaolo Bonzini fprintf(stderr, "Peripheral reset not implemented\n"); 56253018216SPaolo Bonzini break; 56353018216SPaolo Bonzini case 0x054: /* IMC */ 56453018216SPaolo Bonzini s->int_mask = value & 0x7f; 56553018216SPaolo Bonzini break; 56653018216SPaolo Bonzini case 0x058: /* MISC */ 56753018216SPaolo Bonzini s->int_status &= ~value; 56853018216SPaolo Bonzini break; 56953018216SPaolo Bonzini case 0x05c: /* RESC */ 57053018216SPaolo Bonzini s->resc = value & 0x3f; 57153018216SPaolo Bonzini break; 57253018216SPaolo Bonzini case 0x060: /* RCC */ 57353018216SPaolo Bonzini if ((s->rcc & (1 << 13)) != 0 && (value & (1 << 13)) == 0) { 57453018216SPaolo Bonzini /* PLL enable. */ 57553018216SPaolo Bonzini s->int_status |= (1 << 6); 57653018216SPaolo Bonzini } 57753018216SPaolo Bonzini s->rcc = value; 57853018216SPaolo Bonzini ssys_calculate_system_clock(s); 57953018216SPaolo Bonzini break; 58053018216SPaolo Bonzini case 0x070: /* RCC2 */ 58153018216SPaolo Bonzini if (ssys_board_class(s) == DID0_CLASS_SANDSTORM) { 58253018216SPaolo Bonzini break; 58353018216SPaolo Bonzini } 58453018216SPaolo Bonzini 58553018216SPaolo Bonzini if ((s->rcc2 & (1 << 13)) != 0 && (value & (1 << 13)) == 0) { 58653018216SPaolo Bonzini /* PLL enable. */ 58753018216SPaolo Bonzini s->int_status |= (1 << 6); 58853018216SPaolo Bonzini } 58953018216SPaolo Bonzini s->rcc2 = value; 59053018216SPaolo Bonzini ssys_calculate_system_clock(s); 59153018216SPaolo Bonzini break; 59253018216SPaolo Bonzini case 0x100: /* RCGC0 */ 59353018216SPaolo Bonzini s->rcgc[0] = value; 59453018216SPaolo Bonzini break; 59553018216SPaolo Bonzini case 0x104: /* RCGC1 */ 59653018216SPaolo Bonzini s->rcgc[1] = value; 59753018216SPaolo Bonzini break; 59853018216SPaolo Bonzini case 0x108: /* RCGC2 */ 59953018216SPaolo Bonzini s->rcgc[2] = value; 60053018216SPaolo Bonzini break; 60153018216SPaolo Bonzini case 0x110: /* SCGC0 */ 60253018216SPaolo Bonzini s->scgc[0] = value; 60353018216SPaolo Bonzini break; 60453018216SPaolo Bonzini case 0x114: /* SCGC1 */ 60553018216SPaolo Bonzini s->scgc[1] = value; 60653018216SPaolo Bonzini break; 60753018216SPaolo Bonzini case 0x118: /* SCGC2 */ 60853018216SPaolo Bonzini s->scgc[2] = value; 60953018216SPaolo Bonzini break; 61053018216SPaolo Bonzini case 0x120: /* DCGC0 */ 61153018216SPaolo Bonzini s->dcgc[0] = value; 61253018216SPaolo Bonzini break; 61353018216SPaolo Bonzini case 0x124: /* DCGC1 */ 61453018216SPaolo Bonzini s->dcgc[1] = value; 61553018216SPaolo Bonzini break; 61653018216SPaolo Bonzini case 0x128: /* DCGC2 */ 61753018216SPaolo Bonzini s->dcgc[2] = value; 61853018216SPaolo Bonzini break; 61953018216SPaolo Bonzini case 0x150: /* CLKVCLR */ 62053018216SPaolo Bonzini s->clkvclr = value; 62153018216SPaolo Bonzini break; 62253018216SPaolo Bonzini case 0x160: /* LDOARST */ 62353018216SPaolo Bonzini s->ldoarst = value; 62453018216SPaolo Bonzini break; 62553018216SPaolo Bonzini default: 626df3692e0SPeter Maydell qemu_log_mask(LOG_GUEST_ERROR, 627df3692e0SPeter Maydell "SSYS: write at bad offset 0x%x\n", (int)offset); 62853018216SPaolo Bonzini } 62953018216SPaolo Bonzini ssys_update(s); 63053018216SPaolo Bonzini } 63153018216SPaolo Bonzini 63253018216SPaolo Bonzini static const MemoryRegionOps ssys_ops = { 63353018216SPaolo Bonzini .read = ssys_read, 63453018216SPaolo Bonzini .write = ssys_write, 63553018216SPaolo Bonzini .endianness = DEVICE_NATIVE_ENDIAN, 63653018216SPaolo Bonzini }; 63753018216SPaolo Bonzini 63853018216SPaolo Bonzini static void ssys_reset(void *opaque) 63953018216SPaolo Bonzini { 64053018216SPaolo Bonzini ssys_state *s = (ssys_state *)opaque; 64153018216SPaolo Bonzini 64253018216SPaolo Bonzini s->pborctl = 0x7ffd; 64353018216SPaolo Bonzini s->rcc = 0x078e3ac0; 64453018216SPaolo Bonzini 64553018216SPaolo Bonzini if (ssys_board_class(s) == DID0_CLASS_SANDSTORM) { 64653018216SPaolo Bonzini s->rcc2 = 0; 64753018216SPaolo Bonzini } else { 64853018216SPaolo Bonzini s->rcc2 = 0x07802810; 64953018216SPaolo Bonzini } 65053018216SPaolo Bonzini s->rcgc[0] = 1; 65153018216SPaolo Bonzini s->scgc[0] = 1; 65253018216SPaolo Bonzini s->dcgc[0] = 1; 65353018216SPaolo Bonzini ssys_calculate_system_clock(s); 65453018216SPaolo Bonzini } 65553018216SPaolo Bonzini 65653018216SPaolo Bonzini static int stellaris_sys_post_load(void *opaque, int version_id) 65753018216SPaolo Bonzini { 65853018216SPaolo Bonzini ssys_state *s = opaque; 65953018216SPaolo Bonzini 66053018216SPaolo Bonzini ssys_calculate_system_clock(s); 66153018216SPaolo Bonzini 66253018216SPaolo Bonzini return 0; 66353018216SPaolo Bonzini } 66453018216SPaolo Bonzini 66553018216SPaolo Bonzini static const VMStateDescription vmstate_stellaris_sys = { 66653018216SPaolo Bonzini .name = "stellaris_sys", 66753018216SPaolo Bonzini .version_id = 2, 66853018216SPaolo Bonzini .minimum_version_id = 1, 66953018216SPaolo Bonzini .post_load = stellaris_sys_post_load, 67053018216SPaolo Bonzini .fields = (VMStateField[]) { 67153018216SPaolo Bonzini VMSTATE_UINT32(pborctl, ssys_state), 67253018216SPaolo Bonzini VMSTATE_UINT32(ldopctl, ssys_state), 67353018216SPaolo Bonzini VMSTATE_UINT32(int_mask, ssys_state), 67453018216SPaolo Bonzini VMSTATE_UINT32(int_status, ssys_state), 67553018216SPaolo Bonzini VMSTATE_UINT32(resc, ssys_state), 67653018216SPaolo Bonzini VMSTATE_UINT32(rcc, ssys_state), 67753018216SPaolo Bonzini VMSTATE_UINT32_V(rcc2, ssys_state, 2), 67853018216SPaolo Bonzini VMSTATE_UINT32_ARRAY(rcgc, ssys_state, 3), 67953018216SPaolo Bonzini VMSTATE_UINT32_ARRAY(scgc, ssys_state, 3), 68053018216SPaolo Bonzini VMSTATE_UINT32_ARRAY(dcgc, ssys_state, 3), 68153018216SPaolo Bonzini VMSTATE_UINT32(clkvclr, ssys_state), 68253018216SPaolo Bonzini VMSTATE_UINT32(ldoarst, ssys_state), 68353018216SPaolo Bonzini VMSTATE_END_OF_LIST() 68453018216SPaolo Bonzini } 68553018216SPaolo Bonzini }; 68653018216SPaolo Bonzini 68753018216SPaolo Bonzini static int stellaris_sys_init(uint32_t base, qemu_irq irq, 68853018216SPaolo Bonzini stellaris_board_info * board, 68953018216SPaolo Bonzini uint8_t *macaddr) 69053018216SPaolo Bonzini { 69153018216SPaolo Bonzini ssys_state *s; 69253018216SPaolo Bonzini 693b45c03f5SMarkus Armbruster s = g_new0(ssys_state, 1); 69453018216SPaolo Bonzini s->irq = irq; 69553018216SPaolo Bonzini s->board = board; 69653018216SPaolo Bonzini /* Most devices come preprogrammed with a MAC address in the user data. */ 69753018216SPaolo Bonzini s->user0 = macaddr[0] | (macaddr[1] << 8) | (macaddr[2] << 16); 69853018216SPaolo Bonzini s->user1 = macaddr[3] | (macaddr[4] << 8) | (macaddr[5] << 16); 69953018216SPaolo Bonzini 7002c9b15caSPaolo Bonzini memory_region_init_io(&s->iomem, NULL, &ssys_ops, s, "ssys", 0x00001000); 70153018216SPaolo Bonzini memory_region_add_subregion(get_system_memory(), base, &s->iomem); 70253018216SPaolo Bonzini ssys_reset(s); 70353018216SPaolo Bonzini vmstate_register(NULL, -1, &vmstate_stellaris_sys, s); 70453018216SPaolo Bonzini return 0; 70553018216SPaolo Bonzini } 70653018216SPaolo Bonzini 70753018216SPaolo Bonzini 70853018216SPaolo Bonzini /* I2C controller. */ 70953018216SPaolo Bonzini 710d94a4015SAndreas Färber #define TYPE_STELLARIS_I2C "stellaris-i2c" 711d94a4015SAndreas Färber #define STELLARIS_I2C(obj) \ 712d94a4015SAndreas Färber OBJECT_CHECK(stellaris_i2c_state, (obj), TYPE_STELLARIS_I2C) 713d94a4015SAndreas Färber 71453018216SPaolo Bonzini typedef struct { 715d94a4015SAndreas Färber SysBusDevice parent_obj; 716d94a4015SAndreas Färber 717a5c82852SAndreas Färber I2CBus *bus; 71853018216SPaolo Bonzini qemu_irq irq; 71953018216SPaolo Bonzini MemoryRegion iomem; 72053018216SPaolo Bonzini uint32_t msa; 72153018216SPaolo Bonzini uint32_t mcs; 72253018216SPaolo Bonzini uint32_t mdr; 72353018216SPaolo Bonzini uint32_t mtpr; 72453018216SPaolo Bonzini uint32_t mimr; 72553018216SPaolo Bonzini uint32_t mris; 72653018216SPaolo Bonzini uint32_t mcr; 72753018216SPaolo Bonzini } stellaris_i2c_state; 72853018216SPaolo Bonzini 72953018216SPaolo Bonzini #define STELLARIS_I2C_MCS_BUSY 0x01 73053018216SPaolo Bonzini #define STELLARIS_I2C_MCS_ERROR 0x02 73153018216SPaolo Bonzini #define STELLARIS_I2C_MCS_ADRACK 0x04 73253018216SPaolo Bonzini #define STELLARIS_I2C_MCS_DATACK 0x08 73353018216SPaolo Bonzini #define STELLARIS_I2C_MCS_ARBLST 0x10 73453018216SPaolo Bonzini #define STELLARIS_I2C_MCS_IDLE 0x20 73553018216SPaolo Bonzini #define STELLARIS_I2C_MCS_BUSBSY 0x40 73653018216SPaolo Bonzini 73753018216SPaolo Bonzini static uint64_t stellaris_i2c_read(void *opaque, hwaddr offset, 73853018216SPaolo Bonzini unsigned size) 73953018216SPaolo Bonzini { 74053018216SPaolo Bonzini stellaris_i2c_state *s = (stellaris_i2c_state *)opaque; 74153018216SPaolo Bonzini 74253018216SPaolo Bonzini switch (offset) { 74353018216SPaolo Bonzini case 0x00: /* MSA */ 74453018216SPaolo Bonzini return s->msa; 74553018216SPaolo Bonzini case 0x04: /* MCS */ 74653018216SPaolo Bonzini /* We don't emulate timing, so the controller is never busy. */ 74753018216SPaolo Bonzini return s->mcs | STELLARIS_I2C_MCS_IDLE; 74853018216SPaolo Bonzini case 0x08: /* MDR */ 74953018216SPaolo Bonzini return s->mdr; 75053018216SPaolo Bonzini case 0x0c: /* MTPR */ 75153018216SPaolo Bonzini return s->mtpr; 75253018216SPaolo Bonzini case 0x10: /* MIMR */ 75353018216SPaolo Bonzini return s->mimr; 75453018216SPaolo Bonzini case 0x14: /* MRIS */ 75553018216SPaolo Bonzini return s->mris; 75653018216SPaolo Bonzini case 0x18: /* MMIS */ 75753018216SPaolo Bonzini return s->mris & s->mimr; 75853018216SPaolo Bonzini case 0x20: /* MCR */ 75953018216SPaolo Bonzini return s->mcr; 76053018216SPaolo Bonzini default: 761df3692e0SPeter Maydell qemu_log_mask(LOG_GUEST_ERROR, 762df3692e0SPeter Maydell "stellaris_i2c: read at bad offset 0x%x\n", (int)offset); 76353018216SPaolo Bonzini return 0; 76453018216SPaolo Bonzini } 76553018216SPaolo Bonzini } 76653018216SPaolo Bonzini 76753018216SPaolo Bonzini static void stellaris_i2c_update(stellaris_i2c_state *s) 76853018216SPaolo Bonzini { 76953018216SPaolo Bonzini int level; 77053018216SPaolo Bonzini 77153018216SPaolo Bonzini level = (s->mris & s->mimr) != 0; 77253018216SPaolo Bonzini qemu_set_irq(s->irq, level); 77353018216SPaolo Bonzini } 77453018216SPaolo Bonzini 77553018216SPaolo Bonzini static void stellaris_i2c_write(void *opaque, hwaddr offset, 77653018216SPaolo Bonzini uint64_t value, unsigned size) 77753018216SPaolo Bonzini { 77853018216SPaolo Bonzini stellaris_i2c_state *s = (stellaris_i2c_state *)opaque; 77953018216SPaolo Bonzini 78053018216SPaolo Bonzini switch (offset) { 78153018216SPaolo Bonzini case 0x00: /* MSA */ 78253018216SPaolo Bonzini s->msa = value & 0xff; 78353018216SPaolo Bonzini break; 78453018216SPaolo Bonzini case 0x04: /* MCS */ 78553018216SPaolo Bonzini if ((s->mcr & 0x10) == 0) { 78653018216SPaolo Bonzini /* Disabled. Do nothing. */ 78753018216SPaolo Bonzini break; 78853018216SPaolo Bonzini } 78953018216SPaolo Bonzini /* Grab the bus if this is starting a transfer. */ 79053018216SPaolo Bonzini if ((value & 2) && (s->mcs & STELLARIS_I2C_MCS_BUSBSY) == 0) { 79153018216SPaolo Bonzini if (i2c_start_transfer(s->bus, s->msa >> 1, s->msa & 1)) { 79253018216SPaolo Bonzini s->mcs |= STELLARIS_I2C_MCS_ARBLST; 79353018216SPaolo Bonzini } else { 79453018216SPaolo Bonzini s->mcs &= ~STELLARIS_I2C_MCS_ARBLST; 79553018216SPaolo Bonzini s->mcs |= STELLARIS_I2C_MCS_BUSBSY; 79653018216SPaolo Bonzini } 79753018216SPaolo Bonzini } 79853018216SPaolo Bonzini /* If we don't have the bus then indicate an error. */ 79953018216SPaolo Bonzini if (!i2c_bus_busy(s->bus) 80053018216SPaolo Bonzini || (s->mcs & STELLARIS_I2C_MCS_BUSBSY) == 0) { 80153018216SPaolo Bonzini s->mcs |= STELLARIS_I2C_MCS_ERROR; 80253018216SPaolo Bonzini break; 80353018216SPaolo Bonzini } 80453018216SPaolo Bonzini s->mcs &= ~STELLARIS_I2C_MCS_ERROR; 80553018216SPaolo Bonzini if (value & 1) { 80653018216SPaolo Bonzini /* Transfer a byte. */ 80753018216SPaolo Bonzini /* TODO: Handle errors. */ 80853018216SPaolo Bonzini if (s->msa & 1) { 80953018216SPaolo Bonzini /* Recv */ 81053018216SPaolo Bonzini s->mdr = i2c_recv(s->bus) & 0xff; 81153018216SPaolo Bonzini } else { 81253018216SPaolo Bonzini /* Send */ 81353018216SPaolo Bonzini i2c_send(s->bus, s->mdr); 81453018216SPaolo Bonzini } 81553018216SPaolo Bonzini /* Raise an interrupt. */ 81653018216SPaolo Bonzini s->mris |= 1; 81753018216SPaolo Bonzini } 81853018216SPaolo Bonzini if (value & 4) { 81953018216SPaolo Bonzini /* Finish transfer. */ 82053018216SPaolo Bonzini i2c_end_transfer(s->bus); 82153018216SPaolo Bonzini s->mcs &= ~STELLARIS_I2C_MCS_BUSBSY; 82253018216SPaolo Bonzini } 82353018216SPaolo Bonzini break; 82453018216SPaolo Bonzini case 0x08: /* MDR */ 82553018216SPaolo Bonzini s->mdr = value & 0xff; 82653018216SPaolo Bonzini break; 82753018216SPaolo Bonzini case 0x0c: /* MTPR */ 82853018216SPaolo Bonzini s->mtpr = value & 0xff; 82953018216SPaolo Bonzini break; 83053018216SPaolo Bonzini case 0x10: /* MIMR */ 83153018216SPaolo Bonzini s->mimr = 1; 83253018216SPaolo Bonzini break; 83353018216SPaolo Bonzini case 0x1c: /* MICR */ 83453018216SPaolo Bonzini s->mris &= ~value; 83553018216SPaolo Bonzini break; 83653018216SPaolo Bonzini case 0x20: /* MCR */ 837df3692e0SPeter Maydell if (value & 1) { 838df3692e0SPeter Maydell qemu_log_mask(LOG_UNIMP, "stellaris_i2c: Loopback not implemented"); 839df3692e0SPeter Maydell } 840df3692e0SPeter Maydell if (value & 0x20) { 841df3692e0SPeter Maydell qemu_log_mask(LOG_UNIMP, 842df3692e0SPeter Maydell "stellaris_i2c: Slave mode not implemented"); 843df3692e0SPeter Maydell } 84453018216SPaolo Bonzini s->mcr = value & 0x31; 84553018216SPaolo Bonzini break; 84653018216SPaolo Bonzini default: 847df3692e0SPeter Maydell qemu_log_mask(LOG_GUEST_ERROR, 848df3692e0SPeter Maydell "stellaris_i2c: write at bad offset 0x%x\n", (int)offset); 84953018216SPaolo Bonzini } 85053018216SPaolo Bonzini stellaris_i2c_update(s); 85153018216SPaolo Bonzini } 85253018216SPaolo Bonzini 85353018216SPaolo Bonzini static void stellaris_i2c_reset(stellaris_i2c_state *s) 85453018216SPaolo Bonzini { 85553018216SPaolo Bonzini if (s->mcs & STELLARIS_I2C_MCS_BUSBSY) 85653018216SPaolo Bonzini i2c_end_transfer(s->bus); 85753018216SPaolo Bonzini 85853018216SPaolo Bonzini s->msa = 0; 85953018216SPaolo Bonzini s->mcs = 0; 86053018216SPaolo Bonzini s->mdr = 0; 86153018216SPaolo Bonzini s->mtpr = 1; 86253018216SPaolo Bonzini s->mimr = 0; 86353018216SPaolo Bonzini s->mris = 0; 86453018216SPaolo Bonzini s->mcr = 0; 86553018216SPaolo Bonzini stellaris_i2c_update(s); 86653018216SPaolo Bonzini } 86753018216SPaolo Bonzini 86853018216SPaolo Bonzini static const MemoryRegionOps stellaris_i2c_ops = { 86953018216SPaolo Bonzini .read = stellaris_i2c_read, 87053018216SPaolo Bonzini .write = stellaris_i2c_write, 87153018216SPaolo Bonzini .endianness = DEVICE_NATIVE_ENDIAN, 87253018216SPaolo Bonzini }; 87353018216SPaolo Bonzini 87453018216SPaolo Bonzini static const VMStateDescription vmstate_stellaris_i2c = { 87553018216SPaolo Bonzini .name = "stellaris_i2c", 87653018216SPaolo Bonzini .version_id = 1, 87753018216SPaolo Bonzini .minimum_version_id = 1, 87853018216SPaolo Bonzini .fields = (VMStateField[]) { 87953018216SPaolo Bonzini VMSTATE_UINT32(msa, stellaris_i2c_state), 88053018216SPaolo Bonzini VMSTATE_UINT32(mcs, stellaris_i2c_state), 88153018216SPaolo Bonzini VMSTATE_UINT32(mdr, stellaris_i2c_state), 88253018216SPaolo Bonzini VMSTATE_UINT32(mtpr, stellaris_i2c_state), 88353018216SPaolo Bonzini VMSTATE_UINT32(mimr, stellaris_i2c_state), 88453018216SPaolo Bonzini VMSTATE_UINT32(mris, stellaris_i2c_state), 88553018216SPaolo Bonzini VMSTATE_UINT32(mcr, stellaris_i2c_state), 88653018216SPaolo Bonzini VMSTATE_END_OF_LIST() 88753018216SPaolo Bonzini } 88853018216SPaolo Bonzini }; 88953018216SPaolo Bonzini 89015c4fff5Sxiaoqiang.zhao static void stellaris_i2c_init(Object *obj) 89153018216SPaolo Bonzini { 89215c4fff5Sxiaoqiang.zhao DeviceState *dev = DEVICE(obj); 89315c4fff5Sxiaoqiang.zhao stellaris_i2c_state *s = STELLARIS_I2C(obj); 89415c4fff5Sxiaoqiang.zhao SysBusDevice *sbd = SYS_BUS_DEVICE(obj); 895a5c82852SAndreas Färber I2CBus *bus; 89653018216SPaolo Bonzini 897d94a4015SAndreas Färber sysbus_init_irq(sbd, &s->irq); 898d94a4015SAndreas Färber bus = i2c_init_bus(dev, "i2c"); 89953018216SPaolo Bonzini s->bus = bus; 90053018216SPaolo Bonzini 90115c4fff5Sxiaoqiang.zhao memory_region_init_io(&s->iomem, obj, &stellaris_i2c_ops, s, 90253018216SPaolo Bonzini "i2c", 0x1000); 903d94a4015SAndreas Färber sysbus_init_mmio(sbd, &s->iomem); 90453018216SPaolo Bonzini /* ??? For now we only implement the master interface. */ 90553018216SPaolo Bonzini stellaris_i2c_reset(s); 90653018216SPaolo Bonzini } 90753018216SPaolo Bonzini 90853018216SPaolo Bonzini /* Analogue to Digital Converter. This is only partially implemented, 90953018216SPaolo Bonzini enough for applications that use a combined ADC and timer tick. */ 91053018216SPaolo Bonzini 91153018216SPaolo Bonzini #define STELLARIS_ADC_EM_CONTROLLER 0 91253018216SPaolo Bonzini #define STELLARIS_ADC_EM_COMP 1 91353018216SPaolo Bonzini #define STELLARIS_ADC_EM_EXTERNAL 4 91453018216SPaolo Bonzini #define STELLARIS_ADC_EM_TIMER 5 91553018216SPaolo Bonzini #define STELLARIS_ADC_EM_PWM0 6 91653018216SPaolo Bonzini #define STELLARIS_ADC_EM_PWM1 7 91753018216SPaolo Bonzini #define STELLARIS_ADC_EM_PWM2 8 91853018216SPaolo Bonzini 91953018216SPaolo Bonzini #define STELLARIS_ADC_FIFO_EMPTY 0x0100 92053018216SPaolo Bonzini #define STELLARIS_ADC_FIFO_FULL 0x1000 92153018216SPaolo Bonzini 9227df7f67aSAndreas Färber #define TYPE_STELLARIS_ADC "stellaris-adc" 9237df7f67aSAndreas Färber #define STELLARIS_ADC(obj) \ 9247df7f67aSAndreas Färber OBJECT_CHECK(stellaris_adc_state, (obj), TYPE_STELLARIS_ADC) 9257df7f67aSAndreas Färber 9267df7f67aSAndreas Färber typedef struct StellarisADCState { 9277df7f67aSAndreas Färber SysBusDevice parent_obj; 9287df7f67aSAndreas Färber 92953018216SPaolo Bonzini MemoryRegion iomem; 93053018216SPaolo Bonzini uint32_t actss; 93153018216SPaolo Bonzini uint32_t ris; 93253018216SPaolo Bonzini uint32_t im; 93353018216SPaolo Bonzini uint32_t emux; 93453018216SPaolo Bonzini uint32_t ostat; 93553018216SPaolo Bonzini uint32_t ustat; 93653018216SPaolo Bonzini uint32_t sspri; 93753018216SPaolo Bonzini uint32_t sac; 93853018216SPaolo Bonzini struct { 93953018216SPaolo Bonzini uint32_t state; 94053018216SPaolo Bonzini uint32_t data[16]; 94153018216SPaolo Bonzini } fifo[4]; 94253018216SPaolo Bonzini uint32_t ssmux[4]; 94353018216SPaolo Bonzini uint32_t ssctl[4]; 94453018216SPaolo Bonzini uint32_t noise; 94553018216SPaolo Bonzini qemu_irq irq[4]; 94653018216SPaolo Bonzini } stellaris_adc_state; 94753018216SPaolo Bonzini 94853018216SPaolo Bonzini static uint32_t stellaris_adc_fifo_read(stellaris_adc_state *s, int n) 94953018216SPaolo Bonzini { 95053018216SPaolo Bonzini int tail; 95153018216SPaolo Bonzini 95253018216SPaolo Bonzini tail = s->fifo[n].state & 0xf; 95353018216SPaolo Bonzini if (s->fifo[n].state & STELLARIS_ADC_FIFO_EMPTY) { 95453018216SPaolo Bonzini s->ustat |= 1 << n; 95553018216SPaolo Bonzini } else { 95653018216SPaolo Bonzini s->fifo[n].state = (s->fifo[n].state & ~0xf) | ((tail + 1) & 0xf); 95753018216SPaolo Bonzini s->fifo[n].state &= ~STELLARIS_ADC_FIFO_FULL; 95853018216SPaolo Bonzini if (tail + 1 == ((s->fifo[n].state >> 4) & 0xf)) 95953018216SPaolo Bonzini s->fifo[n].state |= STELLARIS_ADC_FIFO_EMPTY; 96053018216SPaolo Bonzini } 96153018216SPaolo Bonzini return s->fifo[n].data[tail]; 96253018216SPaolo Bonzini } 96353018216SPaolo Bonzini 96453018216SPaolo Bonzini static void stellaris_adc_fifo_write(stellaris_adc_state *s, int n, 96553018216SPaolo Bonzini uint32_t value) 96653018216SPaolo Bonzini { 96753018216SPaolo Bonzini int head; 96853018216SPaolo Bonzini 96953018216SPaolo Bonzini /* TODO: Real hardware has limited size FIFOs. We have a full 16 entry 97053018216SPaolo Bonzini FIFO fir each sequencer. */ 97153018216SPaolo Bonzini head = (s->fifo[n].state >> 4) & 0xf; 97253018216SPaolo Bonzini if (s->fifo[n].state & STELLARIS_ADC_FIFO_FULL) { 97353018216SPaolo Bonzini s->ostat |= 1 << n; 97453018216SPaolo Bonzini return; 97553018216SPaolo Bonzini } 97653018216SPaolo Bonzini s->fifo[n].data[head] = value; 97753018216SPaolo Bonzini head = (head + 1) & 0xf; 97853018216SPaolo Bonzini s->fifo[n].state &= ~STELLARIS_ADC_FIFO_EMPTY; 97953018216SPaolo Bonzini s->fifo[n].state = (s->fifo[n].state & ~0xf0) | (head << 4); 98053018216SPaolo Bonzini if ((s->fifo[n].state & 0xf) == head) 98153018216SPaolo Bonzini s->fifo[n].state |= STELLARIS_ADC_FIFO_FULL; 98253018216SPaolo Bonzini } 98353018216SPaolo Bonzini 98453018216SPaolo Bonzini static void stellaris_adc_update(stellaris_adc_state *s) 98553018216SPaolo Bonzini { 98653018216SPaolo Bonzini int level; 98753018216SPaolo Bonzini int n; 98853018216SPaolo Bonzini 98953018216SPaolo Bonzini for (n = 0; n < 4; n++) { 99053018216SPaolo Bonzini level = (s->ris & s->im & (1 << n)) != 0; 99153018216SPaolo Bonzini qemu_set_irq(s->irq[n], level); 99253018216SPaolo Bonzini } 99353018216SPaolo Bonzini } 99453018216SPaolo Bonzini 99553018216SPaolo Bonzini static void stellaris_adc_trigger(void *opaque, int irq, int level) 99653018216SPaolo Bonzini { 99753018216SPaolo Bonzini stellaris_adc_state *s = (stellaris_adc_state *)opaque; 99853018216SPaolo Bonzini int n; 99953018216SPaolo Bonzini 100053018216SPaolo Bonzini for (n = 0; n < 4; n++) { 100153018216SPaolo Bonzini if ((s->actss & (1 << n)) == 0) { 100253018216SPaolo Bonzini continue; 100353018216SPaolo Bonzini } 100453018216SPaolo Bonzini 100553018216SPaolo Bonzini if (((s->emux >> (n * 4)) & 0xff) != 5) { 100653018216SPaolo Bonzini continue; 100753018216SPaolo Bonzini } 100853018216SPaolo Bonzini 100953018216SPaolo Bonzini /* Some applications use the ADC as a random number source, so introduce 101053018216SPaolo Bonzini some variation into the signal. */ 101153018216SPaolo Bonzini s->noise = s->noise * 314159 + 1; 101253018216SPaolo Bonzini /* ??? actual inputs not implemented. Return an arbitrary value. */ 101353018216SPaolo Bonzini stellaris_adc_fifo_write(s, n, 0x200 + ((s->noise >> 16) & 7)); 101453018216SPaolo Bonzini s->ris |= (1 << n); 101553018216SPaolo Bonzini stellaris_adc_update(s); 101653018216SPaolo Bonzini } 101753018216SPaolo Bonzini } 101853018216SPaolo Bonzini 101953018216SPaolo Bonzini static void stellaris_adc_reset(stellaris_adc_state *s) 102053018216SPaolo Bonzini { 102153018216SPaolo Bonzini int n; 102253018216SPaolo Bonzini 102353018216SPaolo Bonzini for (n = 0; n < 4; n++) { 102453018216SPaolo Bonzini s->ssmux[n] = 0; 102553018216SPaolo Bonzini s->ssctl[n] = 0; 102653018216SPaolo Bonzini s->fifo[n].state = STELLARIS_ADC_FIFO_EMPTY; 102753018216SPaolo Bonzini } 102853018216SPaolo Bonzini } 102953018216SPaolo Bonzini 103053018216SPaolo Bonzini static uint64_t stellaris_adc_read(void *opaque, hwaddr offset, 103153018216SPaolo Bonzini unsigned size) 103253018216SPaolo Bonzini { 103353018216SPaolo Bonzini stellaris_adc_state *s = (stellaris_adc_state *)opaque; 103453018216SPaolo Bonzini 103553018216SPaolo Bonzini /* TODO: Implement this. */ 103653018216SPaolo Bonzini if (offset >= 0x40 && offset < 0xc0) { 103753018216SPaolo Bonzini int n; 103853018216SPaolo Bonzini n = (offset - 0x40) >> 5; 103953018216SPaolo Bonzini switch (offset & 0x1f) { 104053018216SPaolo Bonzini case 0x00: /* SSMUX */ 104153018216SPaolo Bonzini return s->ssmux[n]; 104253018216SPaolo Bonzini case 0x04: /* SSCTL */ 104353018216SPaolo Bonzini return s->ssctl[n]; 104453018216SPaolo Bonzini case 0x08: /* SSFIFO */ 104553018216SPaolo Bonzini return stellaris_adc_fifo_read(s, n); 104653018216SPaolo Bonzini case 0x0c: /* SSFSTAT */ 104753018216SPaolo Bonzini return s->fifo[n].state; 104853018216SPaolo Bonzini default: 104953018216SPaolo Bonzini break; 105053018216SPaolo Bonzini } 105153018216SPaolo Bonzini } 105253018216SPaolo Bonzini switch (offset) { 105353018216SPaolo Bonzini case 0x00: /* ACTSS */ 105453018216SPaolo Bonzini return s->actss; 105553018216SPaolo Bonzini case 0x04: /* RIS */ 105653018216SPaolo Bonzini return s->ris; 105753018216SPaolo Bonzini case 0x08: /* IM */ 105853018216SPaolo Bonzini return s->im; 105953018216SPaolo Bonzini case 0x0c: /* ISC */ 106053018216SPaolo Bonzini return s->ris & s->im; 106153018216SPaolo Bonzini case 0x10: /* OSTAT */ 106253018216SPaolo Bonzini return s->ostat; 106353018216SPaolo Bonzini case 0x14: /* EMUX */ 106453018216SPaolo Bonzini return s->emux; 106553018216SPaolo Bonzini case 0x18: /* USTAT */ 106653018216SPaolo Bonzini return s->ustat; 106753018216SPaolo Bonzini case 0x20: /* SSPRI */ 106853018216SPaolo Bonzini return s->sspri; 106953018216SPaolo Bonzini case 0x30: /* SAC */ 107053018216SPaolo Bonzini return s->sac; 107153018216SPaolo Bonzini default: 1072df3692e0SPeter Maydell qemu_log_mask(LOG_GUEST_ERROR, 1073df3692e0SPeter Maydell "stellaris_adc: read at bad offset 0x%x\n", (int)offset); 107453018216SPaolo Bonzini return 0; 107553018216SPaolo Bonzini } 107653018216SPaolo Bonzini } 107753018216SPaolo Bonzini 107853018216SPaolo Bonzini static void stellaris_adc_write(void *opaque, hwaddr offset, 107953018216SPaolo Bonzini uint64_t value, unsigned size) 108053018216SPaolo Bonzini { 108153018216SPaolo Bonzini stellaris_adc_state *s = (stellaris_adc_state *)opaque; 108253018216SPaolo Bonzini 108353018216SPaolo Bonzini /* TODO: Implement this. */ 108453018216SPaolo Bonzini if (offset >= 0x40 && offset < 0xc0) { 108553018216SPaolo Bonzini int n; 108653018216SPaolo Bonzini n = (offset - 0x40) >> 5; 108753018216SPaolo Bonzini switch (offset & 0x1f) { 108853018216SPaolo Bonzini case 0x00: /* SSMUX */ 108953018216SPaolo Bonzini s->ssmux[n] = value & 0x33333333; 109053018216SPaolo Bonzini return; 109153018216SPaolo Bonzini case 0x04: /* SSCTL */ 109253018216SPaolo Bonzini if (value != 6) { 1093df3692e0SPeter Maydell qemu_log_mask(LOG_UNIMP, 1094df3692e0SPeter Maydell "ADC: Unimplemented sequence %" PRIx64 "\n", 109553018216SPaolo Bonzini value); 109653018216SPaolo Bonzini } 109753018216SPaolo Bonzini s->ssctl[n] = value; 109853018216SPaolo Bonzini return; 109953018216SPaolo Bonzini default: 110053018216SPaolo Bonzini break; 110153018216SPaolo Bonzini } 110253018216SPaolo Bonzini } 110353018216SPaolo Bonzini switch (offset) { 110453018216SPaolo Bonzini case 0x00: /* ACTSS */ 110553018216SPaolo Bonzini s->actss = value & 0xf; 110653018216SPaolo Bonzini break; 110753018216SPaolo Bonzini case 0x08: /* IM */ 110853018216SPaolo Bonzini s->im = value; 110953018216SPaolo Bonzini break; 111053018216SPaolo Bonzini case 0x0c: /* ISC */ 111153018216SPaolo Bonzini s->ris &= ~value; 111253018216SPaolo Bonzini break; 111353018216SPaolo Bonzini case 0x10: /* OSTAT */ 111453018216SPaolo Bonzini s->ostat &= ~value; 111553018216SPaolo Bonzini break; 111653018216SPaolo Bonzini case 0x14: /* EMUX */ 111753018216SPaolo Bonzini s->emux = value; 111853018216SPaolo Bonzini break; 111953018216SPaolo Bonzini case 0x18: /* USTAT */ 112053018216SPaolo Bonzini s->ustat &= ~value; 112153018216SPaolo Bonzini break; 112253018216SPaolo Bonzini case 0x20: /* SSPRI */ 112353018216SPaolo Bonzini s->sspri = value; 112453018216SPaolo Bonzini break; 112553018216SPaolo Bonzini case 0x28: /* PSSI */ 1126df3692e0SPeter Maydell qemu_log_mask(LOG_UNIMP, "ADC: sample initiate unimplemented"); 112753018216SPaolo Bonzini break; 112853018216SPaolo Bonzini case 0x30: /* SAC */ 112953018216SPaolo Bonzini s->sac = value; 113053018216SPaolo Bonzini break; 113153018216SPaolo Bonzini default: 1132df3692e0SPeter Maydell qemu_log_mask(LOG_GUEST_ERROR, 1133df3692e0SPeter Maydell "stellaris_adc: write at bad offset 0x%x\n", (int)offset); 113453018216SPaolo Bonzini } 113553018216SPaolo Bonzini stellaris_adc_update(s); 113653018216SPaolo Bonzini } 113753018216SPaolo Bonzini 113853018216SPaolo Bonzini static const MemoryRegionOps stellaris_adc_ops = { 113953018216SPaolo Bonzini .read = stellaris_adc_read, 114053018216SPaolo Bonzini .write = stellaris_adc_write, 114153018216SPaolo Bonzini .endianness = DEVICE_NATIVE_ENDIAN, 114253018216SPaolo Bonzini }; 114353018216SPaolo Bonzini 114453018216SPaolo Bonzini static const VMStateDescription vmstate_stellaris_adc = { 114553018216SPaolo Bonzini .name = "stellaris_adc", 114653018216SPaolo Bonzini .version_id = 1, 114753018216SPaolo Bonzini .minimum_version_id = 1, 114853018216SPaolo Bonzini .fields = (VMStateField[]) { 114953018216SPaolo Bonzini VMSTATE_UINT32(actss, stellaris_adc_state), 115053018216SPaolo Bonzini VMSTATE_UINT32(ris, stellaris_adc_state), 115153018216SPaolo Bonzini VMSTATE_UINT32(im, stellaris_adc_state), 115253018216SPaolo Bonzini VMSTATE_UINT32(emux, stellaris_adc_state), 115353018216SPaolo Bonzini VMSTATE_UINT32(ostat, stellaris_adc_state), 115453018216SPaolo Bonzini VMSTATE_UINT32(ustat, stellaris_adc_state), 115553018216SPaolo Bonzini VMSTATE_UINT32(sspri, stellaris_adc_state), 115653018216SPaolo Bonzini VMSTATE_UINT32(sac, stellaris_adc_state), 115753018216SPaolo Bonzini VMSTATE_UINT32(fifo[0].state, stellaris_adc_state), 115853018216SPaolo Bonzini VMSTATE_UINT32_ARRAY(fifo[0].data, stellaris_adc_state, 16), 115953018216SPaolo Bonzini VMSTATE_UINT32(ssmux[0], stellaris_adc_state), 116053018216SPaolo Bonzini VMSTATE_UINT32(ssctl[0], stellaris_adc_state), 116153018216SPaolo Bonzini VMSTATE_UINT32(fifo[1].state, stellaris_adc_state), 116253018216SPaolo Bonzini VMSTATE_UINT32_ARRAY(fifo[1].data, stellaris_adc_state, 16), 116353018216SPaolo Bonzini VMSTATE_UINT32(ssmux[1], stellaris_adc_state), 116453018216SPaolo Bonzini VMSTATE_UINT32(ssctl[1], stellaris_adc_state), 116553018216SPaolo Bonzini VMSTATE_UINT32(fifo[2].state, stellaris_adc_state), 116653018216SPaolo Bonzini VMSTATE_UINT32_ARRAY(fifo[2].data, stellaris_adc_state, 16), 116753018216SPaolo Bonzini VMSTATE_UINT32(ssmux[2], stellaris_adc_state), 116853018216SPaolo Bonzini VMSTATE_UINT32(ssctl[2], stellaris_adc_state), 116953018216SPaolo Bonzini VMSTATE_UINT32(fifo[3].state, stellaris_adc_state), 117053018216SPaolo Bonzini VMSTATE_UINT32_ARRAY(fifo[3].data, stellaris_adc_state, 16), 117153018216SPaolo Bonzini VMSTATE_UINT32(ssmux[3], stellaris_adc_state), 117253018216SPaolo Bonzini VMSTATE_UINT32(ssctl[3], stellaris_adc_state), 117353018216SPaolo Bonzini VMSTATE_UINT32(noise, stellaris_adc_state), 117453018216SPaolo Bonzini VMSTATE_END_OF_LIST() 117553018216SPaolo Bonzini } 117653018216SPaolo Bonzini }; 117753018216SPaolo Bonzini 117815c4fff5Sxiaoqiang.zhao static void stellaris_adc_init(Object *obj) 117953018216SPaolo Bonzini { 118015c4fff5Sxiaoqiang.zhao DeviceState *dev = DEVICE(obj); 118115c4fff5Sxiaoqiang.zhao stellaris_adc_state *s = STELLARIS_ADC(obj); 118215c4fff5Sxiaoqiang.zhao SysBusDevice *sbd = SYS_BUS_DEVICE(obj); 118353018216SPaolo Bonzini int n; 118453018216SPaolo Bonzini 118553018216SPaolo Bonzini for (n = 0; n < 4; n++) { 11867df7f67aSAndreas Färber sysbus_init_irq(sbd, &s->irq[n]); 118753018216SPaolo Bonzini } 118853018216SPaolo Bonzini 118915c4fff5Sxiaoqiang.zhao memory_region_init_io(&s->iomem, obj, &stellaris_adc_ops, s, 119053018216SPaolo Bonzini "adc", 0x1000); 11917df7f67aSAndreas Färber sysbus_init_mmio(sbd, &s->iomem); 119253018216SPaolo Bonzini stellaris_adc_reset(s); 11937df7f67aSAndreas Färber qdev_init_gpio_in(dev, stellaris_adc_trigger, 1); 119453018216SPaolo Bonzini } 119553018216SPaolo Bonzini 1196d69ffb5bSMichael Davidsaver static 1197d69ffb5bSMichael Davidsaver void do_sys_reset(void *opaque, int n, int level) 1198d69ffb5bSMichael Davidsaver { 1199d69ffb5bSMichael Davidsaver if (level) { 1200cf83f140SEric Blake qemu_system_reset_request(SHUTDOWN_CAUSE_GUEST_RESET); 1201d69ffb5bSMichael Davidsaver } 1202d69ffb5bSMichael Davidsaver } 1203d69ffb5bSMichael Davidsaver 120453018216SPaolo Bonzini /* Board init. */ 120553018216SPaolo Bonzini static stellaris_board_info stellaris_boards[] = { 120653018216SPaolo Bonzini { "LM3S811EVB", 120753018216SPaolo Bonzini 0, 120853018216SPaolo Bonzini 0x0032000e, 120953018216SPaolo Bonzini 0x001f001f, /* dc0 */ 121053018216SPaolo Bonzini 0x001132bf, 121153018216SPaolo Bonzini 0x01071013, 121253018216SPaolo Bonzini 0x3f0f01ff, 121353018216SPaolo Bonzini 0x0000001f, 121453018216SPaolo Bonzini BP_OLED_I2C 121553018216SPaolo Bonzini }, 121653018216SPaolo Bonzini { "LM3S6965EVB", 121753018216SPaolo Bonzini 0x10010002, 121853018216SPaolo Bonzini 0x1073402e, 121953018216SPaolo Bonzini 0x00ff007f, /* dc0 */ 122053018216SPaolo Bonzini 0x001133ff, 122153018216SPaolo Bonzini 0x030f5317, 122253018216SPaolo Bonzini 0x0f0f87ff, 122353018216SPaolo Bonzini 0x5000007f, 122453018216SPaolo Bonzini BP_OLED_SSI | BP_GAMEPAD 122553018216SPaolo Bonzini } 122653018216SPaolo Bonzini }; 122753018216SPaolo Bonzini 122853018216SPaolo Bonzini static void stellaris_init(const char *kernel_filename, const char *cpu_model, 122953018216SPaolo Bonzini stellaris_board_info *board) 123053018216SPaolo Bonzini { 123153018216SPaolo Bonzini static const int uart_irq[] = {5, 6, 33, 34}; 123253018216SPaolo Bonzini static const int timer_irq[] = {19, 21, 23, 35}; 123353018216SPaolo Bonzini static const uint32_t gpio_addr[7] = 123453018216SPaolo Bonzini { 0x40004000, 0x40005000, 0x40006000, 0x40007000, 123553018216SPaolo Bonzini 0x40024000, 0x40025000, 0x40026000}; 123653018216SPaolo Bonzini static const int gpio_irq[7] = {0, 1, 2, 3, 4, 30, 31}; 123753018216SPaolo Bonzini 1238394c8bbfSPeter Maydell /* Memory map of SoC devices, from 1239394c8bbfSPeter Maydell * Stellaris LM3S6965 Microcontroller Data Sheet (rev I) 1240394c8bbfSPeter Maydell * http://www.ti.com/lit/ds/symlink/lm3s6965.pdf 1241394c8bbfSPeter Maydell * 1242394c8bbfSPeter Maydell * 40000000 wdtimer (unimplemented) 1243394c8bbfSPeter Maydell * 40002000 i2c (unimplemented) 1244394c8bbfSPeter Maydell * 40004000 GPIO 1245394c8bbfSPeter Maydell * 40005000 GPIO 1246394c8bbfSPeter Maydell * 40006000 GPIO 1247394c8bbfSPeter Maydell * 40007000 GPIO 1248394c8bbfSPeter Maydell * 40008000 SSI 1249394c8bbfSPeter Maydell * 4000c000 UART 1250394c8bbfSPeter Maydell * 4000d000 UART 1251394c8bbfSPeter Maydell * 4000e000 UART 1252394c8bbfSPeter Maydell * 40020000 i2c 1253394c8bbfSPeter Maydell * 40021000 i2c (unimplemented) 1254394c8bbfSPeter Maydell * 40024000 GPIO 1255394c8bbfSPeter Maydell * 40025000 GPIO 1256394c8bbfSPeter Maydell * 40026000 GPIO 1257394c8bbfSPeter Maydell * 40028000 PWM (unimplemented) 1258394c8bbfSPeter Maydell * 4002c000 QEI (unimplemented) 1259394c8bbfSPeter Maydell * 4002d000 QEI (unimplemented) 1260394c8bbfSPeter Maydell * 40030000 gptimer 1261394c8bbfSPeter Maydell * 40031000 gptimer 1262394c8bbfSPeter Maydell * 40032000 gptimer 1263394c8bbfSPeter Maydell * 40033000 gptimer 1264394c8bbfSPeter Maydell * 40038000 ADC 1265394c8bbfSPeter Maydell * 4003c000 analogue comparator (unimplemented) 1266394c8bbfSPeter Maydell * 40048000 ethernet 1267394c8bbfSPeter Maydell * 400fc000 hibernation module (unimplemented) 1268394c8bbfSPeter Maydell * 400fd000 flash memory control (unimplemented) 1269394c8bbfSPeter Maydell * 400fe000 system control 1270394c8bbfSPeter Maydell */ 1271394c8bbfSPeter Maydell 127220c59c38SMichael Davidsaver DeviceState *gpio_dev[7], *nvic; 127353018216SPaolo Bonzini qemu_irq gpio_in[7][8]; 127453018216SPaolo Bonzini qemu_irq gpio_out[7][8]; 127553018216SPaolo Bonzini qemu_irq adc; 127653018216SPaolo Bonzini int sram_size; 127753018216SPaolo Bonzini int flash_size; 1278a5c82852SAndreas Färber I2CBus *i2c; 127953018216SPaolo Bonzini DeviceState *dev; 128053018216SPaolo Bonzini int i; 128153018216SPaolo Bonzini int j; 128253018216SPaolo Bonzini 1283fe6ac447SAlistair Francis MemoryRegion *sram = g_new(MemoryRegion, 1); 1284fe6ac447SAlistair Francis MemoryRegion *flash = g_new(MemoryRegion, 1); 1285fe6ac447SAlistair Francis MemoryRegion *system_memory = get_system_memory(); 1286fe6ac447SAlistair Francis 1287fe6ac447SAlistair Francis flash_size = (((board->dc0 & 0xffff) + 1) << 1) * 1024; 1288fe6ac447SAlistair Francis sram_size = ((board->dc0 >> 18) + 1) * 1024; 1289fe6ac447SAlistair Francis 1290fe6ac447SAlistair Francis /* Flash programming is done via the SCU, so pretend it is ROM. */ 129198a99ce0SPeter Maydell memory_region_init_ram(flash, NULL, "stellaris.flash", flash_size, 1292f8ed85acSMarkus Armbruster &error_fatal); 1293fe6ac447SAlistair Francis memory_region_set_readonly(flash, true); 1294fe6ac447SAlistair Francis memory_region_add_subregion(system_memory, 0, flash); 1295fe6ac447SAlistair Francis 129698a99ce0SPeter Maydell memory_region_init_ram(sram, NULL, "stellaris.sram", sram_size, 1297f8ed85acSMarkus Armbruster &error_fatal); 1298fe6ac447SAlistair Francis memory_region_add_subregion(system_memory, 0x20000000, sram); 1299fe6ac447SAlistair Francis 130020c59c38SMichael Davidsaver nvic = armv7m_init(system_memory, flash_size, NUM_IRQ_LINES, 13018b47b7daSAlistair Francis kernel_filename, cpu_model); 130253018216SPaolo Bonzini 1303d69ffb5bSMichael Davidsaver qdev_connect_gpio_out_named(nvic, "SYSRESETREQ", 0, 1304d69ffb5bSMichael Davidsaver qemu_allocate_irq(&do_sys_reset, NULL, 0)); 1305d69ffb5bSMichael Davidsaver 130653018216SPaolo Bonzini if (board->dc1 & (1 << 16)) { 13077df7f67aSAndreas Färber dev = sysbus_create_varargs(TYPE_STELLARIS_ADC, 0x40038000, 130820c59c38SMichael Davidsaver qdev_get_gpio_in(nvic, 14), 130920c59c38SMichael Davidsaver qdev_get_gpio_in(nvic, 15), 131020c59c38SMichael Davidsaver qdev_get_gpio_in(nvic, 16), 131120c59c38SMichael Davidsaver qdev_get_gpio_in(nvic, 17), 131220c59c38SMichael Davidsaver NULL); 131353018216SPaolo Bonzini adc = qdev_get_gpio_in(dev, 0); 131453018216SPaolo Bonzini } else { 131553018216SPaolo Bonzini adc = NULL; 131653018216SPaolo Bonzini } 131753018216SPaolo Bonzini for (i = 0; i < 4; i++) { 131853018216SPaolo Bonzini if (board->dc2 & (0x10000 << i)) { 13198ef1d394SAndreas Färber dev = sysbus_create_simple(TYPE_STELLARIS_GPTM, 132053018216SPaolo Bonzini 0x40030000 + i * 0x1000, 132120c59c38SMichael Davidsaver qdev_get_gpio_in(nvic, timer_irq[i])); 132253018216SPaolo Bonzini /* TODO: This is incorrect, but we get away with it because 132353018216SPaolo Bonzini the ADC output is only ever pulsed. */ 132453018216SPaolo Bonzini qdev_connect_gpio_out(dev, 0, adc); 132553018216SPaolo Bonzini } 132653018216SPaolo Bonzini } 132753018216SPaolo Bonzini 132820c59c38SMichael Davidsaver stellaris_sys_init(0x400fe000, qdev_get_gpio_in(nvic, 28), 132920c59c38SMichael Davidsaver board, nd_table[0].macaddr.a); 133053018216SPaolo Bonzini 133153018216SPaolo Bonzini for (i = 0; i < 7; i++) { 133253018216SPaolo Bonzini if (board->dc4 & (1 << i)) { 133353018216SPaolo Bonzini gpio_dev[i] = sysbus_create_simple("pl061_luminary", gpio_addr[i], 133420c59c38SMichael Davidsaver qdev_get_gpio_in(nvic, 133520c59c38SMichael Davidsaver gpio_irq[i])); 133653018216SPaolo Bonzini for (j = 0; j < 8; j++) { 133753018216SPaolo Bonzini gpio_in[i][j] = qdev_get_gpio_in(gpio_dev[i], j); 133853018216SPaolo Bonzini gpio_out[i][j] = NULL; 133953018216SPaolo Bonzini } 134053018216SPaolo Bonzini } 134153018216SPaolo Bonzini } 134253018216SPaolo Bonzini 134353018216SPaolo Bonzini if (board->dc2 & (1 << 12)) { 134420c59c38SMichael Davidsaver dev = sysbus_create_simple(TYPE_STELLARIS_I2C, 0x40020000, 134520c59c38SMichael Davidsaver qdev_get_gpio_in(nvic, 8)); 1346a5c82852SAndreas Färber i2c = (I2CBus *)qdev_get_child_bus(dev, "i2c"); 134753018216SPaolo Bonzini if (board->peripherals & BP_OLED_I2C) { 134853018216SPaolo Bonzini i2c_create_slave(i2c, "ssd0303", 0x3d); 134953018216SPaolo Bonzini } 135053018216SPaolo Bonzini } 135153018216SPaolo Bonzini 135253018216SPaolo Bonzini for (i = 0; i < 4; i++) { 135353018216SPaolo Bonzini if (board->dc2 & (1 << i)) { 1354f0d1d2c1Sxiaoqiang zhao pl011_luminary_create(0x4000c000 + i * 0x1000, 1355f0d1d2c1Sxiaoqiang zhao qdev_get_gpio_in(nvic, uart_irq[i]), 1356f0d1d2c1Sxiaoqiang zhao serial_hds[i]); 135753018216SPaolo Bonzini } 135853018216SPaolo Bonzini } 135953018216SPaolo Bonzini if (board->dc2 & (1 << 4)) { 136020c59c38SMichael Davidsaver dev = sysbus_create_simple("pl022", 0x40008000, 136120c59c38SMichael Davidsaver qdev_get_gpio_in(nvic, 7)); 136253018216SPaolo Bonzini if (board->peripherals & BP_OLED_SSI) { 136353018216SPaolo Bonzini void *bus; 136453018216SPaolo Bonzini DeviceState *sddev; 136553018216SPaolo Bonzini DeviceState *ssddev; 136653018216SPaolo Bonzini 136753018216SPaolo Bonzini /* Some boards have both an OLED controller and SD card connected to 136853018216SPaolo Bonzini * the same SSI port, with the SD card chip select connected to a 136953018216SPaolo Bonzini * GPIO pin. Technically the OLED chip select is connected to the 137053018216SPaolo Bonzini * SSI Fss pin. We do not bother emulating that as both devices 137153018216SPaolo Bonzini * should never be selected simultaneously, and our OLED controller 137253018216SPaolo Bonzini * ignores stray 0xff commands that occur when deselecting the SD 137353018216SPaolo Bonzini * card. 137453018216SPaolo Bonzini */ 137553018216SPaolo Bonzini bus = qdev_get_child_bus(dev, "ssi"); 137653018216SPaolo Bonzini 137753018216SPaolo Bonzini sddev = ssi_create_slave(bus, "ssi-sd"); 137853018216SPaolo Bonzini ssddev = ssi_create_slave(bus, "ssd0323"); 1379de77914eSPeter Crosthwaite gpio_out[GPIO_D][0] = qemu_irq_split( 1380de77914eSPeter Crosthwaite qdev_get_gpio_in_named(sddev, SSI_GPIO_CS, 0), 1381de77914eSPeter Crosthwaite qdev_get_gpio_in_named(ssddev, SSI_GPIO_CS, 0)); 1382de77914eSPeter Crosthwaite gpio_out[GPIO_C][7] = qdev_get_gpio_in(ssddev, 0); 138353018216SPaolo Bonzini 138453018216SPaolo Bonzini /* Make sure the select pin is high. */ 138553018216SPaolo Bonzini qemu_irq_raise(gpio_out[GPIO_D][0]); 138653018216SPaolo Bonzini } 138753018216SPaolo Bonzini } 138853018216SPaolo Bonzini if (board->dc4 & (1 << 28)) { 138953018216SPaolo Bonzini DeviceState *enet; 139053018216SPaolo Bonzini 139153018216SPaolo Bonzini qemu_check_nic_model(&nd_table[0], "stellaris"); 139253018216SPaolo Bonzini 139353018216SPaolo Bonzini enet = qdev_create(NULL, "stellaris_enet"); 139453018216SPaolo Bonzini qdev_set_nic_properties(enet, &nd_table[0]); 139553018216SPaolo Bonzini qdev_init_nofail(enet); 139653018216SPaolo Bonzini sysbus_mmio_map(SYS_BUS_DEVICE(enet), 0, 0x40048000); 139720c59c38SMichael Davidsaver sysbus_connect_irq(SYS_BUS_DEVICE(enet), 0, qdev_get_gpio_in(nvic, 42)); 139853018216SPaolo Bonzini } 139953018216SPaolo Bonzini if (board->peripherals & BP_GAMEPAD) { 140053018216SPaolo Bonzini qemu_irq gpad_irq[5]; 140153018216SPaolo Bonzini static const int gpad_keycode[5] = { 0xc8, 0xd0, 0xcb, 0xcd, 0x1d }; 140253018216SPaolo Bonzini 140353018216SPaolo Bonzini gpad_irq[0] = qemu_irq_invert(gpio_in[GPIO_E][0]); /* up */ 140453018216SPaolo Bonzini gpad_irq[1] = qemu_irq_invert(gpio_in[GPIO_E][1]); /* down */ 140553018216SPaolo Bonzini gpad_irq[2] = qemu_irq_invert(gpio_in[GPIO_E][2]); /* left */ 140653018216SPaolo Bonzini gpad_irq[3] = qemu_irq_invert(gpio_in[GPIO_E][3]); /* right */ 140753018216SPaolo Bonzini gpad_irq[4] = qemu_irq_invert(gpio_in[GPIO_F][1]); /* select */ 140853018216SPaolo Bonzini 140953018216SPaolo Bonzini stellaris_gamepad_init(5, gpad_irq, gpad_keycode); 141053018216SPaolo Bonzini } 141153018216SPaolo Bonzini for (i = 0; i < 7; i++) { 141253018216SPaolo Bonzini if (board->dc4 & (1 << i)) { 141353018216SPaolo Bonzini for (j = 0; j < 8; j++) { 141453018216SPaolo Bonzini if (gpio_out[i][j]) { 141553018216SPaolo Bonzini qdev_connect_gpio_out(gpio_dev[i], j, gpio_out[i][j]); 141653018216SPaolo Bonzini } 141753018216SPaolo Bonzini } 141853018216SPaolo Bonzini } 141953018216SPaolo Bonzini } 1420aecfbbc9SPeter Maydell 1421aecfbbc9SPeter Maydell /* Add dummy regions for the devices we don't implement yet, 1422aecfbbc9SPeter Maydell * so guest accesses don't cause unlogged crashes. 1423aecfbbc9SPeter Maydell */ 1424aecfbbc9SPeter Maydell create_unimplemented_device("wdtimer", 0x40000000, 0x1000); 1425aecfbbc9SPeter Maydell create_unimplemented_device("i2c-0", 0x40002000, 0x1000); 1426aecfbbc9SPeter Maydell create_unimplemented_device("i2c-2", 0x40021000, 0x1000); 1427aecfbbc9SPeter Maydell create_unimplemented_device("PWM", 0x40028000, 0x1000); 1428aecfbbc9SPeter Maydell create_unimplemented_device("QEI-0", 0x4002c000, 0x1000); 1429aecfbbc9SPeter Maydell create_unimplemented_device("QEI-1", 0x4002d000, 0x1000); 1430aecfbbc9SPeter Maydell create_unimplemented_device("analogue-comparator", 0x4003c000, 0x1000); 1431aecfbbc9SPeter Maydell create_unimplemented_device("hibernation", 0x400fc000, 0x1000); 1432aecfbbc9SPeter Maydell create_unimplemented_device("flash-control", 0x400fd000, 0x1000); 143353018216SPaolo Bonzini } 143453018216SPaolo Bonzini 143553018216SPaolo Bonzini /* FIXME: Figure out how to generate these from stellaris_boards. */ 14363ef96221SMarcel Apfelbaum static void lm3s811evb_init(MachineState *machine) 143753018216SPaolo Bonzini { 14383ef96221SMarcel Apfelbaum const char *cpu_model = machine->cpu_model; 14393ef96221SMarcel Apfelbaum const char *kernel_filename = machine->kernel_filename; 144053018216SPaolo Bonzini stellaris_init(kernel_filename, cpu_model, &stellaris_boards[0]); 144153018216SPaolo Bonzini } 144253018216SPaolo Bonzini 14433ef96221SMarcel Apfelbaum static void lm3s6965evb_init(MachineState *machine) 144453018216SPaolo Bonzini { 14453ef96221SMarcel Apfelbaum const char *cpu_model = machine->cpu_model; 14463ef96221SMarcel Apfelbaum const char *kernel_filename = machine->kernel_filename; 144753018216SPaolo Bonzini stellaris_init(kernel_filename, cpu_model, &stellaris_boards[1]); 144853018216SPaolo Bonzini } 144953018216SPaolo Bonzini 14508a661aeaSAndreas Färber static void lm3s811evb_class_init(ObjectClass *oc, void *data) 145153018216SPaolo Bonzini { 14528a661aeaSAndreas Färber MachineClass *mc = MACHINE_CLASS(oc); 14538a661aeaSAndreas Färber 1454e264d29dSEduardo Habkost mc->desc = "Stellaris LM3S811EVB"; 1455e264d29dSEduardo Habkost mc->init = lm3s811evb_init; 1456*4672cbd7SPeter Maydell mc->ignore_memory_transaction_failures = true; 145753018216SPaolo Bonzini } 145853018216SPaolo Bonzini 14598a661aeaSAndreas Färber static const TypeInfo lm3s811evb_type = { 14608a661aeaSAndreas Färber .name = MACHINE_TYPE_NAME("lm3s811evb"), 14618a661aeaSAndreas Färber .parent = TYPE_MACHINE, 14628a661aeaSAndreas Färber .class_init = lm3s811evb_class_init, 14638a661aeaSAndreas Färber }; 1464e264d29dSEduardo Habkost 14658a661aeaSAndreas Färber static void lm3s6965evb_class_init(ObjectClass *oc, void *data) 1466e264d29dSEduardo Habkost { 14678a661aeaSAndreas Färber MachineClass *mc = MACHINE_CLASS(oc); 14688a661aeaSAndreas Färber 1469e264d29dSEduardo Habkost mc->desc = "Stellaris LM3S6965EVB"; 1470e264d29dSEduardo Habkost mc->init = lm3s6965evb_init; 1471*4672cbd7SPeter Maydell mc->ignore_memory_transaction_failures = true; 1472e264d29dSEduardo Habkost } 1473e264d29dSEduardo Habkost 14748a661aeaSAndreas Färber static const TypeInfo lm3s6965evb_type = { 14758a661aeaSAndreas Färber .name = MACHINE_TYPE_NAME("lm3s6965evb"), 14768a661aeaSAndreas Färber .parent = TYPE_MACHINE, 14778a661aeaSAndreas Färber .class_init = lm3s6965evb_class_init, 14788a661aeaSAndreas Färber }; 14798a661aeaSAndreas Färber 14808a661aeaSAndreas Färber static void stellaris_machine_init(void) 14818a661aeaSAndreas Färber { 14828a661aeaSAndreas Färber type_register_static(&lm3s811evb_type); 14838a661aeaSAndreas Färber type_register_static(&lm3s6965evb_type); 14848a661aeaSAndreas Färber } 14858a661aeaSAndreas Färber 14860e6aac87SEduardo Habkost type_init(stellaris_machine_init) 148753018216SPaolo Bonzini 148853018216SPaolo Bonzini static void stellaris_i2c_class_init(ObjectClass *klass, void *data) 148953018216SPaolo Bonzini { 149015c4fff5Sxiaoqiang.zhao DeviceClass *dc = DEVICE_CLASS(klass); 149153018216SPaolo Bonzini 149215c4fff5Sxiaoqiang.zhao dc->vmsd = &vmstate_stellaris_i2c; 149353018216SPaolo Bonzini } 149453018216SPaolo Bonzini 149553018216SPaolo Bonzini static const TypeInfo stellaris_i2c_info = { 1496d94a4015SAndreas Färber .name = TYPE_STELLARIS_I2C, 149753018216SPaolo Bonzini .parent = TYPE_SYS_BUS_DEVICE, 149853018216SPaolo Bonzini .instance_size = sizeof(stellaris_i2c_state), 149915c4fff5Sxiaoqiang.zhao .instance_init = stellaris_i2c_init, 150053018216SPaolo Bonzini .class_init = stellaris_i2c_class_init, 150153018216SPaolo Bonzini }; 150253018216SPaolo Bonzini 150353018216SPaolo Bonzini static void stellaris_gptm_class_init(ObjectClass *klass, void *data) 150453018216SPaolo Bonzini { 150515c4fff5Sxiaoqiang.zhao DeviceClass *dc = DEVICE_CLASS(klass); 150653018216SPaolo Bonzini 150715c4fff5Sxiaoqiang.zhao dc->vmsd = &vmstate_stellaris_gptm; 150853018216SPaolo Bonzini } 150953018216SPaolo Bonzini 151053018216SPaolo Bonzini static const TypeInfo stellaris_gptm_info = { 15118ef1d394SAndreas Färber .name = TYPE_STELLARIS_GPTM, 151253018216SPaolo Bonzini .parent = TYPE_SYS_BUS_DEVICE, 151353018216SPaolo Bonzini .instance_size = sizeof(gptm_state), 151415c4fff5Sxiaoqiang.zhao .instance_init = stellaris_gptm_init, 151553018216SPaolo Bonzini .class_init = stellaris_gptm_class_init, 151653018216SPaolo Bonzini }; 151753018216SPaolo Bonzini 151853018216SPaolo Bonzini static void stellaris_adc_class_init(ObjectClass *klass, void *data) 151953018216SPaolo Bonzini { 152015c4fff5Sxiaoqiang.zhao DeviceClass *dc = DEVICE_CLASS(klass); 152153018216SPaolo Bonzini 152215c4fff5Sxiaoqiang.zhao dc->vmsd = &vmstate_stellaris_adc; 152353018216SPaolo Bonzini } 152453018216SPaolo Bonzini 152553018216SPaolo Bonzini static const TypeInfo stellaris_adc_info = { 15267df7f67aSAndreas Färber .name = TYPE_STELLARIS_ADC, 152753018216SPaolo Bonzini .parent = TYPE_SYS_BUS_DEVICE, 152853018216SPaolo Bonzini .instance_size = sizeof(stellaris_adc_state), 152915c4fff5Sxiaoqiang.zhao .instance_init = stellaris_adc_init, 153053018216SPaolo Bonzini .class_init = stellaris_adc_class_init, 153153018216SPaolo Bonzini }; 153253018216SPaolo Bonzini 153353018216SPaolo Bonzini static void stellaris_register_types(void) 153453018216SPaolo Bonzini { 153553018216SPaolo Bonzini type_register_static(&stellaris_i2c_info); 153653018216SPaolo Bonzini type_register_static(&stellaris_gptm_info); 153753018216SPaolo Bonzini type_register_static(&stellaris_adc_info); 153853018216SPaolo Bonzini } 153953018216SPaolo Bonzini 154053018216SPaolo Bonzini type_init(stellaris_register_types) 1541