153018216SPaolo Bonzini /* 253018216SPaolo Bonzini * Luminary Micro Stellaris peripherals 353018216SPaolo Bonzini * 453018216SPaolo Bonzini * Copyright (c) 2006 CodeSourcery. 553018216SPaolo Bonzini * Written by Paul Brook 653018216SPaolo Bonzini * 753018216SPaolo Bonzini * This code is licensed under the GPL. 853018216SPaolo Bonzini */ 953018216SPaolo Bonzini 1012b16722SPeter Maydell #include "qemu/osdep.h" 11da34e65cSMarkus Armbruster #include "qapi/error.h" 12d0a030d8SZongyuan Li #include "hw/core/split-irq.h" 1353018216SPaolo Bonzini #include "hw/sysbus.h" 1436aa285fSMarkus Armbruster #include "hw/sd/sd.h" 158fd06719SAlistair Francis #include "hw/ssi/ssi.h" 1612ec8bd5SPeter Maydell #include "hw/arm/boot.h" 1753018216SPaolo Bonzini #include "qemu/timer.h" 180d09e41aSPaolo Bonzini #include "hw/i2c/i2c.h" 1953018216SPaolo Bonzini #include "net/net.h" 2053018216SPaolo Bonzini #include "hw/boards.h" 2103dd024fSPaolo Bonzini #include "qemu/log.h" 2253018216SPaolo Bonzini #include "exec/address-spaces.h" 23d69ffb5bSMichael Davidsaver #include "sysemu/sysemu.h" 24f04d4465SPeter Maydell #include "hw/arm/armv7m.h" 25f0d1d2c1Sxiaoqiang zhao #include "hw/char/pl011.h" 2698fa3327SPhilippe Mathieu-Daudé #include "hw/input/gamepad.h" 2764552b6bSMarkus Armbruster #include "hw/irq.h" 28566528f8SMichel Heily #include "hw/watchdog/cmsdk-apb-watchdog.h" 29d6454270SMarkus Armbruster #include "migration/vmstate.h" 30aecfbbc9SPeter Maydell #include "hw/misc/unimp.h" 31f3eb7557SPeter Maydell #include "hw/timer/stellaris-gptm.h" 321e31d8eeSPeter Maydell #include "hw/qdev-clock.h" 33db1015e9SEduardo Habkost #include "qom/object.h" 3453018216SPaolo Bonzini 3553018216SPaolo Bonzini #define GPIO_A 0 3653018216SPaolo Bonzini #define GPIO_B 1 3753018216SPaolo Bonzini #define GPIO_C 2 3853018216SPaolo Bonzini #define GPIO_D 3 3953018216SPaolo Bonzini #define GPIO_E 4 4053018216SPaolo Bonzini #define GPIO_F 5 4153018216SPaolo Bonzini #define GPIO_G 6 4253018216SPaolo Bonzini 4353018216SPaolo Bonzini #define BP_OLED_I2C 0x01 4453018216SPaolo Bonzini #define BP_OLED_SSI 0x02 4553018216SPaolo Bonzini #define BP_GAMEPAD 0x04 4653018216SPaolo Bonzini 478b47b7daSAlistair Francis #define NUM_IRQ_LINES 64 488b47b7daSAlistair Francis 4953018216SPaolo Bonzini typedef const struct { 5053018216SPaolo Bonzini const char *name; 5153018216SPaolo Bonzini uint32_t did0; 5253018216SPaolo Bonzini uint32_t did1; 5353018216SPaolo Bonzini uint32_t dc0; 5453018216SPaolo Bonzini uint32_t dc1; 5553018216SPaolo Bonzini uint32_t dc2; 5653018216SPaolo Bonzini uint32_t dc3; 5753018216SPaolo Bonzini uint32_t dc4; 5853018216SPaolo Bonzini uint32_t peripherals; 5953018216SPaolo Bonzini } stellaris_board_info; 6053018216SPaolo Bonzini 6153018216SPaolo Bonzini /* System controller. */ 6253018216SPaolo Bonzini 634bebb9adSPeter Maydell #define TYPE_STELLARIS_SYS "stellaris-sys" 644bebb9adSPeter Maydell OBJECT_DECLARE_SIMPLE_TYPE(ssys_state, STELLARIS_SYS) 654bebb9adSPeter Maydell 664bebb9adSPeter Maydell struct ssys_state { 674bebb9adSPeter Maydell SysBusDevice parent_obj; 684bebb9adSPeter Maydell 6953018216SPaolo Bonzini MemoryRegion iomem; 7053018216SPaolo Bonzini uint32_t pborctl; 7153018216SPaolo Bonzini uint32_t ldopctl; 7253018216SPaolo Bonzini uint32_t int_status; 7353018216SPaolo Bonzini uint32_t int_mask; 7453018216SPaolo Bonzini uint32_t resc; 7553018216SPaolo Bonzini uint32_t rcc; 7653018216SPaolo Bonzini uint32_t rcc2; 7753018216SPaolo Bonzini uint32_t rcgc[3]; 7853018216SPaolo Bonzini uint32_t scgc[3]; 7953018216SPaolo Bonzini uint32_t dcgc[3]; 8053018216SPaolo Bonzini uint32_t clkvclr; 8153018216SPaolo Bonzini uint32_t ldoarst; 824bebb9adSPeter Maydell qemu_irq irq; 831e31d8eeSPeter Maydell Clock *sysclk; 844bebb9adSPeter Maydell /* Properties (all read-only registers) */ 8553018216SPaolo Bonzini uint32_t user0; 8653018216SPaolo Bonzini uint32_t user1; 874bebb9adSPeter Maydell uint32_t did0; 884bebb9adSPeter Maydell uint32_t did1; 894bebb9adSPeter Maydell uint32_t dc0; 904bebb9adSPeter Maydell uint32_t dc1; 914bebb9adSPeter Maydell uint32_t dc2; 924bebb9adSPeter Maydell uint32_t dc3; 934bebb9adSPeter Maydell uint32_t dc4; 944bebb9adSPeter Maydell }; 9553018216SPaolo Bonzini 9653018216SPaolo Bonzini static void ssys_update(ssys_state *s) 9753018216SPaolo Bonzini { 9853018216SPaolo Bonzini qemu_set_irq(s->irq, (s->int_status & s->int_mask) != 0); 9953018216SPaolo Bonzini } 10053018216SPaolo Bonzini 10153018216SPaolo Bonzini static uint32_t pllcfg_sandstorm[16] = { 10253018216SPaolo Bonzini 0x31c0, /* 1 Mhz */ 10353018216SPaolo Bonzini 0x1ae0, /* 1.8432 Mhz */ 10453018216SPaolo Bonzini 0x18c0, /* 2 Mhz */ 10553018216SPaolo Bonzini 0xd573, /* 2.4576 Mhz */ 10653018216SPaolo Bonzini 0x37a6, /* 3.57954 Mhz */ 10753018216SPaolo Bonzini 0x1ae2, /* 3.6864 Mhz */ 10853018216SPaolo Bonzini 0x0c40, /* 4 Mhz */ 10953018216SPaolo Bonzini 0x98bc, /* 4.906 Mhz */ 11053018216SPaolo Bonzini 0x935b, /* 4.9152 Mhz */ 11153018216SPaolo Bonzini 0x09c0, /* 5 Mhz */ 11253018216SPaolo Bonzini 0x4dee, /* 5.12 Mhz */ 11353018216SPaolo Bonzini 0x0c41, /* 6 Mhz */ 11453018216SPaolo Bonzini 0x75db, /* 6.144 Mhz */ 11553018216SPaolo Bonzini 0x1ae6, /* 7.3728 Mhz */ 11653018216SPaolo Bonzini 0x0600, /* 8 Mhz */ 11753018216SPaolo Bonzini 0x585b /* 8.192 Mhz */ 11853018216SPaolo Bonzini }; 11953018216SPaolo Bonzini 12053018216SPaolo Bonzini static uint32_t pllcfg_fury[16] = { 12153018216SPaolo Bonzini 0x3200, /* 1 Mhz */ 12253018216SPaolo Bonzini 0x1b20, /* 1.8432 Mhz */ 12353018216SPaolo Bonzini 0x1900, /* 2 Mhz */ 12453018216SPaolo Bonzini 0xf42b, /* 2.4576 Mhz */ 12553018216SPaolo Bonzini 0x37e3, /* 3.57954 Mhz */ 12653018216SPaolo Bonzini 0x1b21, /* 3.6864 Mhz */ 12753018216SPaolo Bonzini 0x0c80, /* 4 Mhz */ 12853018216SPaolo Bonzini 0x98ee, /* 4.906 Mhz */ 12953018216SPaolo Bonzini 0xd5b4, /* 4.9152 Mhz */ 13053018216SPaolo Bonzini 0x0a00, /* 5 Mhz */ 13153018216SPaolo Bonzini 0x4e27, /* 5.12 Mhz */ 13253018216SPaolo Bonzini 0x1902, /* 6 Mhz */ 13353018216SPaolo Bonzini 0xec1c, /* 6.144 Mhz */ 13453018216SPaolo Bonzini 0x1b23, /* 7.3728 Mhz */ 13553018216SPaolo Bonzini 0x0640, /* 8 Mhz */ 13653018216SPaolo Bonzini 0xb11c /* 8.192 Mhz */ 13753018216SPaolo Bonzini }; 13853018216SPaolo Bonzini 13953018216SPaolo Bonzini #define DID0_VER_MASK 0x70000000 14053018216SPaolo Bonzini #define DID0_VER_0 0x00000000 14153018216SPaolo Bonzini #define DID0_VER_1 0x10000000 14253018216SPaolo Bonzini 14353018216SPaolo Bonzini #define DID0_CLASS_MASK 0x00FF0000 14453018216SPaolo Bonzini #define DID0_CLASS_SANDSTORM 0x00000000 14553018216SPaolo Bonzini #define DID0_CLASS_FURY 0x00010000 14653018216SPaolo Bonzini 14753018216SPaolo Bonzini static int ssys_board_class(const ssys_state *s) 14853018216SPaolo Bonzini { 1494bebb9adSPeter Maydell uint32_t did0 = s->did0; 15053018216SPaolo Bonzini switch (did0 & DID0_VER_MASK) { 15153018216SPaolo Bonzini case DID0_VER_0: 15253018216SPaolo Bonzini return DID0_CLASS_SANDSTORM; 15353018216SPaolo Bonzini case DID0_VER_1: 15453018216SPaolo Bonzini switch (did0 & DID0_CLASS_MASK) { 15553018216SPaolo Bonzini case DID0_CLASS_SANDSTORM: 15653018216SPaolo Bonzini case DID0_CLASS_FURY: 15753018216SPaolo Bonzini return did0 & DID0_CLASS_MASK; 15853018216SPaolo Bonzini } 15953018216SPaolo Bonzini /* for unknown classes, fall through */ 16053018216SPaolo Bonzini default: 161df3692e0SPeter Maydell /* This can only happen if the hardwired constant did0 value 162df3692e0SPeter Maydell * in this board's stellaris_board_info struct is wrong. 163df3692e0SPeter Maydell */ 164df3692e0SPeter Maydell g_assert_not_reached(); 16553018216SPaolo Bonzini } 16653018216SPaolo Bonzini } 16753018216SPaolo Bonzini 16853018216SPaolo Bonzini static uint64_t ssys_read(void *opaque, hwaddr offset, 16953018216SPaolo Bonzini unsigned size) 17053018216SPaolo Bonzini { 17153018216SPaolo Bonzini ssys_state *s = (ssys_state *)opaque; 17253018216SPaolo Bonzini 17353018216SPaolo Bonzini switch (offset) { 17453018216SPaolo Bonzini case 0x000: /* DID0 */ 1754bebb9adSPeter Maydell return s->did0; 17653018216SPaolo Bonzini case 0x004: /* DID1 */ 1774bebb9adSPeter Maydell return s->did1; 17853018216SPaolo Bonzini case 0x008: /* DC0 */ 1794bebb9adSPeter Maydell return s->dc0; 18053018216SPaolo Bonzini case 0x010: /* DC1 */ 1814bebb9adSPeter Maydell return s->dc1; 18253018216SPaolo Bonzini case 0x014: /* DC2 */ 1834bebb9adSPeter Maydell return s->dc2; 18453018216SPaolo Bonzini case 0x018: /* DC3 */ 1854bebb9adSPeter Maydell return s->dc3; 18653018216SPaolo Bonzini case 0x01c: /* DC4 */ 1874bebb9adSPeter Maydell return s->dc4; 18853018216SPaolo Bonzini case 0x030: /* PBORCTL */ 18953018216SPaolo Bonzini return s->pborctl; 19053018216SPaolo Bonzini case 0x034: /* LDOPCTL */ 19153018216SPaolo Bonzini return s->ldopctl; 19253018216SPaolo Bonzini case 0x040: /* SRCR0 */ 19353018216SPaolo Bonzini return 0; 19453018216SPaolo Bonzini case 0x044: /* SRCR1 */ 19553018216SPaolo Bonzini return 0; 19653018216SPaolo Bonzini case 0x048: /* SRCR2 */ 19753018216SPaolo Bonzini return 0; 19853018216SPaolo Bonzini case 0x050: /* RIS */ 19953018216SPaolo Bonzini return s->int_status; 20053018216SPaolo Bonzini case 0x054: /* IMC */ 20153018216SPaolo Bonzini return s->int_mask; 20253018216SPaolo Bonzini case 0x058: /* MISC */ 20353018216SPaolo Bonzini return s->int_status & s->int_mask; 20453018216SPaolo Bonzini case 0x05c: /* RESC */ 20553018216SPaolo Bonzini return s->resc; 20653018216SPaolo Bonzini case 0x060: /* RCC */ 20753018216SPaolo Bonzini return s->rcc; 20853018216SPaolo Bonzini case 0x064: /* PLLCFG */ 20953018216SPaolo Bonzini { 21053018216SPaolo Bonzini int xtal; 21153018216SPaolo Bonzini xtal = (s->rcc >> 6) & 0xf; 21253018216SPaolo Bonzini switch (ssys_board_class(s)) { 21353018216SPaolo Bonzini case DID0_CLASS_FURY: 21453018216SPaolo Bonzini return pllcfg_fury[xtal]; 21553018216SPaolo Bonzini case DID0_CLASS_SANDSTORM: 21653018216SPaolo Bonzini return pllcfg_sandstorm[xtal]; 21753018216SPaolo Bonzini default: 218df3692e0SPeter Maydell g_assert_not_reached(); 21953018216SPaolo Bonzini } 22053018216SPaolo Bonzini } 22153018216SPaolo Bonzini case 0x070: /* RCC2 */ 22253018216SPaolo Bonzini return s->rcc2; 22353018216SPaolo Bonzini case 0x100: /* RCGC0 */ 22453018216SPaolo Bonzini return s->rcgc[0]; 22553018216SPaolo Bonzini case 0x104: /* RCGC1 */ 22653018216SPaolo Bonzini return s->rcgc[1]; 22753018216SPaolo Bonzini case 0x108: /* RCGC2 */ 22853018216SPaolo Bonzini return s->rcgc[2]; 22953018216SPaolo Bonzini case 0x110: /* SCGC0 */ 23053018216SPaolo Bonzini return s->scgc[0]; 23153018216SPaolo Bonzini case 0x114: /* SCGC1 */ 23253018216SPaolo Bonzini return s->scgc[1]; 23353018216SPaolo Bonzini case 0x118: /* SCGC2 */ 23453018216SPaolo Bonzini return s->scgc[2]; 23553018216SPaolo Bonzini case 0x120: /* DCGC0 */ 23653018216SPaolo Bonzini return s->dcgc[0]; 23753018216SPaolo Bonzini case 0x124: /* DCGC1 */ 23853018216SPaolo Bonzini return s->dcgc[1]; 23953018216SPaolo Bonzini case 0x128: /* DCGC2 */ 24053018216SPaolo Bonzini return s->dcgc[2]; 24153018216SPaolo Bonzini case 0x150: /* CLKVCLR */ 24253018216SPaolo Bonzini return s->clkvclr; 24353018216SPaolo Bonzini case 0x160: /* LDOARST */ 24453018216SPaolo Bonzini return s->ldoarst; 24553018216SPaolo Bonzini case 0x1e0: /* USER0 */ 24653018216SPaolo Bonzini return s->user0; 24753018216SPaolo Bonzini case 0x1e4: /* USER1 */ 24853018216SPaolo Bonzini return s->user1; 24953018216SPaolo Bonzini default: 250df3692e0SPeter Maydell qemu_log_mask(LOG_GUEST_ERROR, 251df3692e0SPeter Maydell "SSYS: read at bad offset 0x%x\n", (int)offset); 25253018216SPaolo Bonzini return 0; 25353018216SPaolo Bonzini } 25453018216SPaolo Bonzini } 25553018216SPaolo Bonzini 25653018216SPaolo Bonzini static bool ssys_use_rcc2(ssys_state *s) 25753018216SPaolo Bonzini { 25853018216SPaolo Bonzini return (s->rcc2 >> 31) & 0x1; 25953018216SPaolo Bonzini } 26053018216SPaolo Bonzini 26153018216SPaolo Bonzini /* 2621e31d8eeSPeter Maydell * Calculate the system clock period. We only want to propagate 2631e31d8eeSPeter Maydell * this change to the rest of the system if we're not being called 2641e31d8eeSPeter Maydell * from migration post-load. 26553018216SPaolo Bonzini */ 2661e31d8eeSPeter Maydell static void ssys_calculate_system_clock(ssys_state *s, bool propagate_clock) 26753018216SPaolo Bonzini { 268683754c7SPeter Maydell int period_ns; 2691e31d8eeSPeter Maydell /* 2701e31d8eeSPeter Maydell * SYSDIV field specifies divisor: 0 == /1, 1 == /2, etc. Input 2711e31d8eeSPeter Maydell * clock is 200MHz, which is a period of 5 ns. Dividing the clock 2721e31d8eeSPeter Maydell * frequency by X is the same as multiplying the period by X. 2731e31d8eeSPeter Maydell */ 27453018216SPaolo Bonzini if (ssys_use_rcc2(s)) { 275683754c7SPeter Maydell period_ns = 5 * (((s->rcc2 >> 23) & 0x3f) + 1); 27653018216SPaolo Bonzini } else { 277683754c7SPeter Maydell period_ns = 5 * (((s->rcc >> 23) & 0xf) + 1); 27853018216SPaolo Bonzini } 279683754c7SPeter Maydell clock_set_ns(s->sysclk, period_ns); 2801e31d8eeSPeter Maydell if (propagate_clock) { 2811e31d8eeSPeter Maydell clock_propagate(s->sysclk); 2821e31d8eeSPeter Maydell } 28353018216SPaolo Bonzini } 28453018216SPaolo Bonzini 28553018216SPaolo Bonzini static void ssys_write(void *opaque, hwaddr offset, 28653018216SPaolo Bonzini uint64_t value, unsigned size) 28753018216SPaolo Bonzini { 28853018216SPaolo Bonzini ssys_state *s = (ssys_state *)opaque; 28953018216SPaolo Bonzini 29053018216SPaolo Bonzini switch (offset) { 29153018216SPaolo Bonzini case 0x030: /* PBORCTL */ 29253018216SPaolo Bonzini s->pborctl = value & 0xffff; 29353018216SPaolo Bonzini break; 29453018216SPaolo Bonzini case 0x034: /* LDOPCTL */ 29553018216SPaolo Bonzini s->ldopctl = value & 0x1f; 29653018216SPaolo Bonzini break; 29753018216SPaolo Bonzini case 0x040: /* SRCR0 */ 29853018216SPaolo Bonzini case 0x044: /* SRCR1 */ 29953018216SPaolo Bonzini case 0x048: /* SRCR2 */ 3009194524bSPhilippe Mathieu-Daudé qemu_log_mask(LOG_UNIMP, "Peripheral reset not implemented\n"); 30153018216SPaolo Bonzini break; 30253018216SPaolo Bonzini case 0x054: /* IMC */ 30353018216SPaolo Bonzini s->int_mask = value & 0x7f; 30453018216SPaolo Bonzini break; 30553018216SPaolo Bonzini case 0x058: /* MISC */ 30653018216SPaolo Bonzini s->int_status &= ~value; 30753018216SPaolo Bonzini break; 30853018216SPaolo Bonzini case 0x05c: /* RESC */ 30953018216SPaolo Bonzini s->resc = value & 0x3f; 31053018216SPaolo Bonzini break; 31153018216SPaolo Bonzini case 0x060: /* RCC */ 31253018216SPaolo Bonzini if ((s->rcc & (1 << 13)) != 0 && (value & (1 << 13)) == 0) { 31353018216SPaolo Bonzini /* PLL enable. */ 31453018216SPaolo Bonzini s->int_status |= (1 << 6); 31553018216SPaolo Bonzini } 31653018216SPaolo Bonzini s->rcc = value; 3171e31d8eeSPeter Maydell ssys_calculate_system_clock(s, true); 31853018216SPaolo Bonzini break; 31953018216SPaolo Bonzini case 0x070: /* RCC2 */ 32053018216SPaolo Bonzini if (ssys_board_class(s) == DID0_CLASS_SANDSTORM) { 32153018216SPaolo Bonzini break; 32253018216SPaolo Bonzini } 32353018216SPaolo Bonzini 32453018216SPaolo Bonzini if ((s->rcc2 & (1 << 13)) != 0 && (value & (1 << 13)) == 0) { 32553018216SPaolo Bonzini /* PLL enable. */ 32653018216SPaolo Bonzini s->int_status |= (1 << 6); 32753018216SPaolo Bonzini } 32853018216SPaolo Bonzini s->rcc2 = value; 3291e31d8eeSPeter Maydell ssys_calculate_system_clock(s, true); 33053018216SPaolo Bonzini break; 33153018216SPaolo Bonzini case 0x100: /* RCGC0 */ 33253018216SPaolo Bonzini s->rcgc[0] = value; 33353018216SPaolo Bonzini break; 33453018216SPaolo Bonzini case 0x104: /* RCGC1 */ 33553018216SPaolo Bonzini s->rcgc[1] = value; 33653018216SPaolo Bonzini break; 33753018216SPaolo Bonzini case 0x108: /* RCGC2 */ 33853018216SPaolo Bonzini s->rcgc[2] = value; 33953018216SPaolo Bonzini break; 34053018216SPaolo Bonzini case 0x110: /* SCGC0 */ 34153018216SPaolo Bonzini s->scgc[0] = value; 34253018216SPaolo Bonzini break; 34353018216SPaolo Bonzini case 0x114: /* SCGC1 */ 34453018216SPaolo Bonzini s->scgc[1] = value; 34553018216SPaolo Bonzini break; 34653018216SPaolo Bonzini case 0x118: /* SCGC2 */ 34753018216SPaolo Bonzini s->scgc[2] = value; 34853018216SPaolo Bonzini break; 34953018216SPaolo Bonzini case 0x120: /* DCGC0 */ 35053018216SPaolo Bonzini s->dcgc[0] = value; 35153018216SPaolo Bonzini break; 35253018216SPaolo Bonzini case 0x124: /* DCGC1 */ 35353018216SPaolo Bonzini s->dcgc[1] = value; 35453018216SPaolo Bonzini break; 35553018216SPaolo Bonzini case 0x128: /* DCGC2 */ 35653018216SPaolo Bonzini s->dcgc[2] = value; 35753018216SPaolo Bonzini break; 35853018216SPaolo Bonzini case 0x150: /* CLKVCLR */ 35953018216SPaolo Bonzini s->clkvclr = value; 36053018216SPaolo Bonzini break; 36153018216SPaolo Bonzini case 0x160: /* LDOARST */ 36253018216SPaolo Bonzini s->ldoarst = value; 36353018216SPaolo Bonzini break; 36453018216SPaolo Bonzini default: 365df3692e0SPeter Maydell qemu_log_mask(LOG_GUEST_ERROR, 366df3692e0SPeter Maydell "SSYS: write at bad offset 0x%x\n", (int)offset); 36753018216SPaolo Bonzini } 36853018216SPaolo Bonzini ssys_update(s); 36953018216SPaolo Bonzini } 37053018216SPaolo Bonzini 37153018216SPaolo Bonzini static const MemoryRegionOps ssys_ops = { 37253018216SPaolo Bonzini .read = ssys_read, 37353018216SPaolo Bonzini .write = ssys_write, 37453018216SPaolo Bonzini .endianness = DEVICE_NATIVE_ENDIAN, 37553018216SPaolo Bonzini }; 37653018216SPaolo Bonzini 3774bebb9adSPeter Maydell static void stellaris_sys_reset_enter(Object *obj, ResetType type) 37853018216SPaolo Bonzini { 3794bebb9adSPeter Maydell ssys_state *s = STELLARIS_SYS(obj); 38053018216SPaolo Bonzini 38153018216SPaolo Bonzini s->pborctl = 0x7ffd; 38253018216SPaolo Bonzini s->rcc = 0x078e3ac0; 38353018216SPaolo Bonzini 38453018216SPaolo Bonzini if (ssys_board_class(s) == DID0_CLASS_SANDSTORM) { 38553018216SPaolo Bonzini s->rcc2 = 0; 38653018216SPaolo Bonzini } else { 38753018216SPaolo Bonzini s->rcc2 = 0x07802810; 38853018216SPaolo Bonzini } 38953018216SPaolo Bonzini s->rcgc[0] = 1; 39053018216SPaolo Bonzini s->scgc[0] = 1; 39153018216SPaolo Bonzini s->dcgc[0] = 1; 3924bebb9adSPeter Maydell } 3934bebb9adSPeter Maydell 3944bebb9adSPeter Maydell static void stellaris_sys_reset_hold(Object *obj) 3954bebb9adSPeter Maydell { 3964bebb9adSPeter Maydell ssys_state *s = STELLARIS_SYS(obj); 3974bebb9adSPeter Maydell 3981e31d8eeSPeter Maydell /* OK to propagate clocks from the hold phase */ 3991e31d8eeSPeter Maydell ssys_calculate_system_clock(s, true); 40053018216SPaolo Bonzini } 40153018216SPaolo Bonzini 4024bebb9adSPeter Maydell static void stellaris_sys_reset_exit(Object *obj) 4034bebb9adSPeter Maydell { 4044bebb9adSPeter Maydell } 4054bebb9adSPeter Maydell 40653018216SPaolo Bonzini static int stellaris_sys_post_load(void *opaque, int version_id) 40753018216SPaolo Bonzini { 40853018216SPaolo Bonzini ssys_state *s = opaque; 40953018216SPaolo Bonzini 4101e31d8eeSPeter Maydell ssys_calculate_system_clock(s, false); 41153018216SPaolo Bonzini 41253018216SPaolo Bonzini return 0; 41353018216SPaolo Bonzini } 41453018216SPaolo Bonzini 41553018216SPaolo Bonzini static const VMStateDescription vmstate_stellaris_sys = { 41653018216SPaolo Bonzini .name = "stellaris_sys", 41753018216SPaolo Bonzini .version_id = 2, 41853018216SPaolo Bonzini .minimum_version_id = 1, 41953018216SPaolo Bonzini .post_load = stellaris_sys_post_load, 42053018216SPaolo Bonzini .fields = (VMStateField[]) { 42153018216SPaolo Bonzini VMSTATE_UINT32(pborctl, ssys_state), 42253018216SPaolo Bonzini VMSTATE_UINT32(ldopctl, ssys_state), 42353018216SPaolo Bonzini VMSTATE_UINT32(int_mask, ssys_state), 42453018216SPaolo Bonzini VMSTATE_UINT32(int_status, ssys_state), 42553018216SPaolo Bonzini VMSTATE_UINT32(resc, ssys_state), 42653018216SPaolo Bonzini VMSTATE_UINT32(rcc, ssys_state), 42753018216SPaolo Bonzini VMSTATE_UINT32_V(rcc2, ssys_state, 2), 42853018216SPaolo Bonzini VMSTATE_UINT32_ARRAY(rcgc, ssys_state, 3), 42953018216SPaolo Bonzini VMSTATE_UINT32_ARRAY(scgc, ssys_state, 3), 43053018216SPaolo Bonzini VMSTATE_UINT32_ARRAY(dcgc, ssys_state, 3), 43153018216SPaolo Bonzini VMSTATE_UINT32(clkvclr, ssys_state), 43253018216SPaolo Bonzini VMSTATE_UINT32(ldoarst, ssys_state), 4331e31d8eeSPeter Maydell /* No field for sysclk -- handled in post-load instead */ 43453018216SPaolo Bonzini VMSTATE_END_OF_LIST() 43553018216SPaolo Bonzini } 43653018216SPaolo Bonzini }; 43753018216SPaolo Bonzini 4384bebb9adSPeter Maydell static Property stellaris_sys_properties[] = { 4394bebb9adSPeter Maydell DEFINE_PROP_UINT32("user0", ssys_state, user0, 0), 4404bebb9adSPeter Maydell DEFINE_PROP_UINT32("user1", ssys_state, user1, 0), 4414bebb9adSPeter Maydell DEFINE_PROP_UINT32("did0", ssys_state, did0, 0), 4424bebb9adSPeter Maydell DEFINE_PROP_UINT32("did1", ssys_state, did1, 0), 4434bebb9adSPeter Maydell DEFINE_PROP_UINT32("dc0", ssys_state, dc0, 0), 4444bebb9adSPeter Maydell DEFINE_PROP_UINT32("dc1", ssys_state, dc1, 0), 4454bebb9adSPeter Maydell DEFINE_PROP_UINT32("dc2", ssys_state, dc2, 0), 4464bebb9adSPeter Maydell DEFINE_PROP_UINT32("dc3", ssys_state, dc3, 0), 4474bebb9adSPeter Maydell DEFINE_PROP_UINT32("dc4", ssys_state, dc4, 0), 4484bebb9adSPeter Maydell DEFINE_PROP_END_OF_LIST() 4494bebb9adSPeter Maydell }; 4504bebb9adSPeter Maydell 4514bebb9adSPeter Maydell static void stellaris_sys_instance_init(Object *obj) 4524bebb9adSPeter Maydell { 4534bebb9adSPeter Maydell ssys_state *s = STELLARIS_SYS(obj); 4544bebb9adSPeter Maydell SysBusDevice *sbd = SYS_BUS_DEVICE(s); 4554bebb9adSPeter Maydell 4564bebb9adSPeter Maydell memory_region_init_io(&s->iomem, obj, &ssys_ops, s, "ssys", 0x00001000); 4574bebb9adSPeter Maydell sysbus_init_mmio(sbd, &s->iomem); 4584bebb9adSPeter Maydell sysbus_init_irq(sbd, &s->irq); 4591e31d8eeSPeter Maydell s->sysclk = qdev_init_clock_out(DEVICE(s), "SYSCLK"); 4604bebb9adSPeter Maydell } 4614bebb9adSPeter Maydell 46253018216SPaolo Bonzini /* I2C controller. */ 46353018216SPaolo Bonzini 464d94a4015SAndreas Färber #define TYPE_STELLARIS_I2C "stellaris-i2c" 4658063396bSEduardo Habkost OBJECT_DECLARE_SIMPLE_TYPE(stellaris_i2c_state, STELLARIS_I2C) 466d94a4015SAndreas Färber 467db1015e9SEduardo Habkost struct stellaris_i2c_state { 468d94a4015SAndreas Färber SysBusDevice parent_obj; 469d94a4015SAndreas Färber 470a5c82852SAndreas Färber I2CBus *bus; 47153018216SPaolo Bonzini qemu_irq irq; 47253018216SPaolo Bonzini MemoryRegion iomem; 47353018216SPaolo Bonzini uint32_t msa; 47453018216SPaolo Bonzini uint32_t mcs; 47553018216SPaolo Bonzini uint32_t mdr; 47653018216SPaolo Bonzini uint32_t mtpr; 47753018216SPaolo Bonzini uint32_t mimr; 47853018216SPaolo Bonzini uint32_t mris; 47953018216SPaolo Bonzini uint32_t mcr; 480db1015e9SEduardo Habkost }; 48153018216SPaolo Bonzini 48253018216SPaolo Bonzini #define STELLARIS_I2C_MCS_BUSY 0x01 48353018216SPaolo Bonzini #define STELLARIS_I2C_MCS_ERROR 0x02 48453018216SPaolo Bonzini #define STELLARIS_I2C_MCS_ADRACK 0x04 48553018216SPaolo Bonzini #define STELLARIS_I2C_MCS_DATACK 0x08 48653018216SPaolo Bonzini #define STELLARIS_I2C_MCS_ARBLST 0x10 48753018216SPaolo Bonzini #define STELLARIS_I2C_MCS_IDLE 0x20 48853018216SPaolo Bonzini #define STELLARIS_I2C_MCS_BUSBSY 0x40 48953018216SPaolo Bonzini 49053018216SPaolo Bonzini static uint64_t stellaris_i2c_read(void *opaque, hwaddr offset, 49153018216SPaolo Bonzini unsigned size) 49253018216SPaolo Bonzini { 49353018216SPaolo Bonzini stellaris_i2c_state *s = (stellaris_i2c_state *)opaque; 49453018216SPaolo Bonzini 49553018216SPaolo Bonzini switch (offset) { 49653018216SPaolo Bonzini case 0x00: /* MSA */ 49753018216SPaolo Bonzini return s->msa; 49853018216SPaolo Bonzini case 0x04: /* MCS */ 49953018216SPaolo Bonzini /* We don't emulate timing, so the controller is never busy. */ 50053018216SPaolo Bonzini return s->mcs | STELLARIS_I2C_MCS_IDLE; 50153018216SPaolo Bonzini case 0x08: /* MDR */ 50253018216SPaolo Bonzini return s->mdr; 50353018216SPaolo Bonzini case 0x0c: /* MTPR */ 50453018216SPaolo Bonzini return s->mtpr; 50553018216SPaolo Bonzini case 0x10: /* MIMR */ 50653018216SPaolo Bonzini return s->mimr; 50753018216SPaolo Bonzini case 0x14: /* MRIS */ 50853018216SPaolo Bonzini return s->mris; 50953018216SPaolo Bonzini case 0x18: /* MMIS */ 51053018216SPaolo Bonzini return s->mris & s->mimr; 51153018216SPaolo Bonzini case 0x20: /* MCR */ 51253018216SPaolo Bonzini return s->mcr; 51353018216SPaolo Bonzini default: 514df3692e0SPeter Maydell qemu_log_mask(LOG_GUEST_ERROR, 515df3692e0SPeter Maydell "stellaris_i2c: read at bad offset 0x%x\n", (int)offset); 51653018216SPaolo Bonzini return 0; 51753018216SPaolo Bonzini } 51853018216SPaolo Bonzini } 51953018216SPaolo Bonzini 52053018216SPaolo Bonzini static void stellaris_i2c_update(stellaris_i2c_state *s) 52153018216SPaolo Bonzini { 52253018216SPaolo Bonzini int level; 52353018216SPaolo Bonzini 52453018216SPaolo Bonzini level = (s->mris & s->mimr) != 0; 52553018216SPaolo Bonzini qemu_set_irq(s->irq, level); 52653018216SPaolo Bonzini } 52753018216SPaolo Bonzini 52853018216SPaolo Bonzini static void stellaris_i2c_write(void *opaque, hwaddr offset, 52953018216SPaolo Bonzini uint64_t value, unsigned size) 53053018216SPaolo Bonzini { 53153018216SPaolo Bonzini stellaris_i2c_state *s = (stellaris_i2c_state *)opaque; 53253018216SPaolo Bonzini 53353018216SPaolo Bonzini switch (offset) { 53453018216SPaolo Bonzini case 0x00: /* MSA */ 53553018216SPaolo Bonzini s->msa = value & 0xff; 53653018216SPaolo Bonzini break; 53753018216SPaolo Bonzini case 0x04: /* MCS */ 53853018216SPaolo Bonzini if ((s->mcr & 0x10) == 0) { 53953018216SPaolo Bonzini /* Disabled. Do nothing. */ 54053018216SPaolo Bonzini break; 54153018216SPaolo Bonzini } 54253018216SPaolo Bonzini /* Grab the bus if this is starting a transfer. */ 54353018216SPaolo Bonzini if ((value & 2) && (s->mcs & STELLARIS_I2C_MCS_BUSBSY) == 0) { 54453018216SPaolo Bonzini if (i2c_start_transfer(s->bus, s->msa >> 1, s->msa & 1)) { 54553018216SPaolo Bonzini s->mcs |= STELLARIS_I2C_MCS_ARBLST; 54653018216SPaolo Bonzini } else { 54753018216SPaolo Bonzini s->mcs &= ~STELLARIS_I2C_MCS_ARBLST; 54853018216SPaolo Bonzini s->mcs |= STELLARIS_I2C_MCS_BUSBSY; 54953018216SPaolo Bonzini } 55053018216SPaolo Bonzini } 55153018216SPaolo Bonzini /* If we don't have the bus then indicate an error. */ 55253018216SPaolo Bonzini if (!i2c_bus_busy(s->bus) 55353018216SPaolo Bonzini || (s->mcs & STELLARIS_I2C_MCS_BUSBSY) == 0) { 55453018216SPaolo Bonzini s->mcs |= STELLARIS_I2C_MCS_ERROR; 55553018216SPaolo Bonzini break; 55653018216SPaolo Bonzini } 55753018216SPaolo Bonzini s->mcs &= ~STELLARIS_I2C_MCS_ERROR; 55853018216SPaolo Bonzini if (value & 1) { 55953018216SPaolo Bonzini /* Transfer a byte. */ 56053018216SPaolo Bonzini /* TODO: Handle errors. */ 56153018216SPaolo Bonzini if (s->msa & 1) { 56253018216SPaolo Bonzini /* Recv */ 56305f9f17eSCorey Minyard s->mdr = i2c_recv(s->bus); 56453018216SPaolo Bonzini } else { 56553018216SPaolo Bonzini /* Send */ 56653018216SPaolo Bonzini i2c_send(s->bus, s->mdr); 56753018216SPaolo Bonzini } 56853018216SPaolo Bonzini /* Raise an interrupt. */ 56953018216SPaolo Bonzini s->mris |= 1; 57053018216SPaolo Bonzini } 57153018216SPaolo Bonzini if (value & 4) { 57253018216SPaolo Bonzini /* Finish transfer. */ 57353018216SPaolo Bonzini i2c_end_transfer(s->bus); 57453018216SPaolo Bonzini s->mcs &= ~STELLARIS_I2C_MCS_BUSBSY; 57553018216SPaolo Bonzini } 57653018216SPaolo Bonzini break; 57753018216SPaolo Bonzini case 0x08: /* MDR */ 57853018216SPaolo Bonzini s->mdr = value & 0xff; 57953018216SPaolo Bonzini break; 58053018216SPaolo Bonzini case 0x0c: /* MTPR */ 58153018216SPaolo Bonzini s->mtpr = value & 0xff; 58253018216SPaolo Bonzini break; 58353018216SPaolo Bonzini case 0x10: /* MIMR */ 58453018216SPaolo Bonzini s->mimr = 1; 58553018216SPaolo Bonzini break; 58653018216SPaolo Bonzini case 0x1c: /* MICR */ 58753018216SPaolo Bonzini s->mris &= ~value; 58853018216SPaolo Bonzini break; 58953018216SPaolo Bonzini case 0x20: /* MCR */ 590df3692e0SPeter Maydell if (value & 1) { 5919492e4b2SPhilippe Mathieu-Daudé qemu_log_mask(LOG_UNIMP, 5929492e4b2SPhilippe Mathieu-Daudé "stellaris_i2c: Loopback not implemented\n"); 593df3692e0SPeter Maydell } 594df3692e0SPeter Maydell if (value & 0x20) { 595df3692e0SPeter Maydell qemu_log_mask(LOG_UNIMP, 5969492e4b2SPhilippe Mathieu-Daudé "stellaris_i2c: Slave mode not implemented\n"); 597df3692e0SPeter Maydell } 59853018216SPaolo Bonzini s->mcr = value & 0x31; 59953018216SPaolo Bonzini break; 60053018216SPaolo Bonzini default: 601df3692e0SPeter Maydell qemu_log_mask(LOG_GUEST_ERROR, 602df3692e0SPeter Maydell "stellaris_i2c: write at bad offset 0x%x\n", (int)offset); 60353018216SPaolo Bonzini } 60453018216SPaolo Bonzini stellaris_i2c_update(s); 60553018216SPaolo Bonzini } 60653018216SPaolo Bonzini 60753018216SPaolo Bonzini static void stellaris_i2c_reset(stellaris_i2c_state *s) 60853018216SPaolo Bonzini { 60953018216SPaolo Bonzini if (s->mcs & STELLARIS_I2C_MCS_BUSBSY) 61053018216SPaolo Bonzini i2c_end_transfer(s->bus); 61153018216SPaolo Bonzini 61253018216SPaolo Bonzini s->msa = 0; 61353018216SPaolo Bonzini s->mcs = 0; 61453018216SPaolo Bonzini s->mdr = 0; 61553018216SPaolo Bonzini s->mtpr = 1; 61653018216SPaolo Bonzini s->mimr = 0; 61753018216SPaolo Bonzini s->mris = 0; 61853018216SPaolo Bonzini s->mcr = 0; 61953018216SPaolo Bonzini stellaris_i2c_update(s); 62053018216SPaolo Bonzini } 62153018216SPaolo Bonzini 62253018216SPaolo Bonzini static const MemoryRegionOps stellaris_i2c_ops = { 62353018216SPaolo Bonzini .read = stellaris_i2c_read, 62453018216SPaolo Bonzini .write = stellaris_i2c_write, 62553018216SPaolo Bonzini .endianness = DEVICE_NATIVE_ENDIAN, 62653018216SPaolo Bonzini }; 62753018216SPaolo Bonzini 62853018216SPaolo Bonzini static const VMStateDescription vmstate_stellaris_i2c = { 62953018216SPaolo Bonzini .name = "stellaris_i2c", 63053018216SPaolo Bonzini .version_id = 1, 63153018216SPaolo Bonzini .minimum_version_id = 1, 63253018216SPaolo Bonzini .fields = (VMStateField[]) { 63353018216SPaolo Bonzini VMSTATE_UINT32(msa, stellaris_i2c_state), 63453018216SPaolo Bonzini VMSTATE_UINT32(mcs, stellaris_i2c_state), 63553018216SPaolo Bonzini VMSTATE_UINT32(mdr, stellaris_i2c_state), 63653018216SPaolo Bonzini VMSTATE_UINT32(mtpr, stellaris_i2c_state), 63753018216SPaolo Bonzini VMSTATE_UINT32(mimr, stellaris_i2c_state), 63853018216SPaolo Bonzini VMSTATE_UINT32(mris, stellaris_i2c_state), 63953018216SPaolo Bonzini VMSTATE_UINT32(mcr, stellaris_i2c_state), 64053018216SPaolo Bonzini VMSTATE_END_OF_LIST() 64153018216SPaolo Bonzini } 64253018216SPaolo Bonzini }; 64353018216SPaolo Bonzini 64415c4fff5Sxiaoqiang.zhao static void stellaris_i2c_init(Object *obj) 64553018216SPaolo Bonzini { 64615c4fff5Sxiaoqiang.zhao DeviceState *dev = DEVICE(obj); 64715c4fff5Sxiaoqiang.zhao stellaris_i2c_state *s = STELLARIS_I2C(obj); 64815c4fff5Sxiaoqiang.zhao SysBusDevice *sbd = SYS_BUS_DEVICE(obj); 649a5c82852SAndreas Färber I2CBus *bus; 65053018216SPaolo Bonzini 651d94a4015SAndreas Färber sysbus_init_irq(sbd, &s->irq); 652d94a4015SAndreas Färber bus = i2c_init_bus(dev, "i2c"); 65353018216SPaolo Bonzini s->bus = bus; 65453018216SPaolo Bonzini 65515c4fff5Sxiaoqiang.zhao memory_region_init_io(&s->iomem, obj, &stellaris_i2c_ops, s, 65653018216SPaolo Bonzini "i2c", 0x1000); 657d94a4015SAndreas Färber sysbus_init_mmio(sbd, &s->iomem); 65853018216SPaolo Bonzini /* ??? For now we only implement the master interface. */ 65953018216SPaolo Bonzini stellaris_i2c_reset(s); 66053018216SPaolo Bonzini } 66153018216SPaolo Bonzini 66253018216SPaolo Bonzini /* Analogue to Digital Converter. This is only partially implemented, 66353018216SPaolo Bonzini enough for applications that use a combined ADC and timer tick. */ 66453018216SPaolo Bonzini 66553018216SPaolo Bonzini #define STELLARIS_ADC_EM_CONTROLLER 0 66653018216SPaolo Bonzini #define STELLARIS_ADC_EM_COMP 1 66753018216SPaolo Bonzini #define STELLARIS_ADC_EM_EXTERNAL 4 66853018216SPaolo Bonzini #define STELLARIS_ADC_EM_TIMER 5 66953018216SPaolo Bonzini #define STELLARIS_ADC_EM_PWM0 6 67053018216SPaolo Bonzini #define STELLARIS_ADC_EM_PWM1 7 67153018216SPaolo Bonzini #define STELLARIS_ADC_EM_PWM2 8 67253018216SPaolo Bonzini 67353018216SPaolo Bonzini #define STELLARIS_ADC_FIFO_EMPTY 0x0100 67453018216SPaolo Bonzini #define STELLARIS_ADC_FIFO_FULL 0x1000 67553018216SPaolo Bonzini 6767df7f67aSAndreas Färber #define TYPE_STELLARIS_ADC "stellaris-adc" 677d6b109daSPhilippe Mathieu-Daudé typedef struct StellarisADCState StellarisADCState; 678d6b109daSPhilippe Mathieu-Daudé DECLARE_INSTANCE_CHECKER(StellarisADCState, STELLARIS_ADC, TYPE_STELLARIS_ADC) 6797df7f67aSAndreas Färber 680db1015e9SEduardo Habkost struct StellarisADCState { 6817df7f67aSAndreas Färber SysBusDevice parent_obj; 6827df7f67aSAndreas Färber 68353018216SPaolo Bonzini MemoryRegion iomem; 68453018216SPaolo Bonzini uint32_t actss; 68553018216SPaolo Bonzini uint32_t ris; 68653018216SPaolo Bonzini uint32_t im; 68753018216SPaolo Bonzini uint32_t emux; 68853018216SPaolo Bonzini uint32_t ostat; 68953018216SPaolo Bonzini uint32_t ustat; 69053018216SPaolo Bonzini uint32_t sspri; 69153018216SPaolo Bonzini uint32_t sac; 69253018216SPaolo Bonzini struct { 69353018216SPaolo Bonzini uint32_t state; 69453018216SPaolo Bonzini uint32_t data[16]; 69553018216SPaolo Bonzini } fifo[4]; 69653018216SPaolo Bonzini uint32_t ssmux[4]; 69753018216SPaolo Bonzini uint32_t ssctl[4]; 69853018216SPaolo Bonzini uint32_t noise; 69953018216SPaolo Bonzini qemu_irq irq[4]; 700db1015e9SEduardo Habkost }; 70153018216SPaolo Bonzini 702d6b109daSPhilippe Mathieu-Daudé static uint32_t stellaris_adc_fifo_read(StellarisADCState *s, int n) 70353018216SPaolo Bonzini { 70453018216SPaolo Bonzini int tail; 70553018216SPaolo Bonzini 70653018216SPaolo Bonzini tail = s->fifo[n].state & 0xf; 70753018216SPaolo Bonzini if (s->fifo[n].state & STELLARIS_ADC_FIFO_EMPTY) { 70853018216SPaolo Bonzini s->ustat |= 1 << n; 70953018216SPaolo Bonzini } else { 71053018216SPaolo Bonzini s->fifo[n].state = (s->fifo[n].state & ~0xf) | ((tail + 1) & 0xf); 71153018216SPaolo Bonzini s->fifo[n].state &= ~STELLARIS_ADC_FIFO_FULL; 71253018216SPaolo Bonzini if (tail + 1 == ((s->fifo[n].state >> 4) & 0xf)) 71353018216SPaolo Bonzini s->fifo[n].state |= STELLARIS_ADC_FIFO_EMPTY; 71453018216SPaolo Bonzini } 71553018216SPaolo Bonzini return s->fifo[n].data[tail]; 71653018216SPaolo Bonzini } 71753018216SPaolo Bonzini 718d6b109daSPhilippe Mathieu-Daudé static void stellaris_adc_fifo_write(StellarisADCState *s, int n, 71953018216SPaolo Bonzini uint32_t value) 72053018216SPaolo Bonzini { 72153018216SPaolo Bonzini int head; 72253018216SPaolo Bonzini 72353018216SPaolo Bonzini /* TODO: Real hardware has limited size FIFOs. We have a full 16 entry 72453018216SPaolo Bonzini FIFO fir each sequencer. */ 72553018216SPaolo Bonzini head = (s->fifo[n].state >> 4) & 0xf; 72653018216SPaolo Bonzini if (s->fifo[n].state & STELLARIS_ADC_FIFO_FULL) { 72753018216SPaolo Bonzini s->ostat |= 1 << n; 72853018216SPaolo Bonzini return; 72953018216SPaolo Bonzini } 73053018216SPaolo Bonzini s->fifo[n].data[head] = value; 73153018216SPaolo Bonzini head = (head + 1) & 0xf; 73253018216SPaolo Bonzini s->fifo[n].state &= ~STELLARIS_ADC_FIFO_EMPTY; 73353018216SPaolo Bonzini s->fifo[n].state = (s->fifo[n].state & ~0xf0) | (head << 4); 73453018216SPaolo Bonzini if ((s->fifo[n].state & 0xf) == head) 73553018216SPaolo Bonzini s->fifo[n].state |= STELLARIS_ADC_FIFO_FULL; 73653018216SPaolo Bonzini } 73753018216SPaolo Bonzini 738d6b109daSPhilippe Mathieu-Daudé static void stellaris_adc_update(StellarisADCState *s) 73953018216SPaolo Bonzini { 74053018216SPaolo Bonzini int level; 74153018216SPaolo Bonzini int n; 74253018216SPaolo Bonzini 74353018216SPaolo Bonzini for (n = 0; n < 4; n++) { 74453018216SPaolo Bonzini level = (s->ris & s->im & (1 << n)) != 0; 74553018216SPaolo Bonzini qemu_set_irq(s->irq[n], level); 74653018216SPaolo Bonzini } 74753018216SPaolo Bonzini } 74853018216SPaolo Bonzini 74953018216SPaolo Bonzini static void stellaris_adc_trigger(void *opaque, int irq, int level) 75053018216SPaolo Bonzini { 751d6b109daSPhilippe Mathieu-Daudé StellarisADCState *s = opaque; 75253018216SPaolo Bonzini int n; 75353018216SPaolo Bonzini 75453018216SPaolo Bonzini for (n = 0; n < 4; n++) { 75553018216SPaolo Bonzini if ((s->actss & (1 << n)) == 0) { 75653018216SPaolo Bonzini continue; 75753018216SPaolo Bonzini } 75853018216SPaolo Bonzini 75953018216SPaolo Bonzini if (((s->emux >> (n * 4)) & 0xff) != 5) { 76053018216SPaolo Bonzini continue; 76153018216SPaolo Bonzini } 76253018216SPaolo Bonzini 76353018216SPaolo Bonzini /* Some applications use the ADC as a random number source, so introduce 76453018216SPaolo Bonzini some variation into the signal. */ 76553018216SPaolo Bonzini s->noise = s->noise * 314159 + 1; 76653018216SPaolo Bonzini /* ??? actual inputs not implemented. Return an arbitrary value. */ 76753018216SPaolo Bonzini stellaris_adc_fifo_write(s, n, 0x200 + ((s->noise >> 16) & 7)); 76853018216SPaolo Bonzini s->ris |= (1 << n); 76953018216SPaolo Bonzini stellaris_adc_update(s); 77053018216SPaolo Bonzini } 77153018216SPaolo Bonzini } 77253018216SPaolo Bonzini 773d6b109daSPhilippe Mathieu-Daudé static void stellaris_adc_reset(StellarisADCState *s) 77453018216SPaolo Bonzini { 77553018216SPaolo Bonzini int n; 77653018216SPaolo Bonzini 77753018216SPaolo Bonzini for (n = 0; n < 4; n++) { 77853018216SPaolo Bonzini s->ssmux[n] = 0; 77953018216SPaolo Bonzini s->ssctl[n] = 0; 78053018216SPaolo Bonzini s->fifo[n].state = STELLARIS_ADC_FIFO_EMPTY; 78153018216SPaolo Bonzini } 78253018216SPaolo Bonzini } 78353018216SPaolo Bonzini 78453018216SPaolo Bonzini static uint64_t stellaris_adc_read(void *opaque, hwaddr offset, 78553018216SPaolo Bonzini unsigned size) 78653018216SPaolo Bonzini { 787d6b109daSPhilippe Mathieu-Daudé StellarisADCState *s = opaque; 78853018216SPaolo Bonzini 78953018216SPaolo Bonzini /* TODO: Implement this. */ 79053018216SPaolo Bonzini if (offset >= 0x40 && offset < 0xc0) { 79153018216SPaolo Bonzini int n; 79253018216SPaolo Bonzini n = (offset - 0x40) >> 5; 79353018216SPaolo Bonzini switch (offset & 0x1f) { 79453018216SPaolo Bonzini case 0x00: /* SSMUX */ 79553018216SPaolo Bonzini return s->ssmux[n]; 79653018216SPaolo Bonzini case 0x04: /* SSCTL */ 79753018216SPaolo Bonzini return s->ssctl[n]; 79853018216SPaolo Bonzini case 0x08: /* SSFIFO */ 79953018216SPaolo Bonzini return stellaris_adc_fifo_read(s, n); 80053018216SPaolo Bonzini case 0x0c: /* SSFSTAT */ 80153018216SPaolo Bonzini return s->fifo[n].state; 80253018216SPaolo Bonzini default: 80353018216SPaolo Bonzini break; 80453018216SPaolo Bonzini } 80553018216SPaolo Bonzini } 80653018216SPaolo Bonzini switch (offset) { 80753018216SPaolo Bonzini case 0x00: /* ACTSS */ 80853018216SPaolo Bonzini return s->actss; 80953018216SPaolo Bonzini case 0x04: /* RIS */ 81053018216SPaolo Bonzini return s->ris; 81153018216SPaolo Bonzini case 0x08: /* IM */ 81253018216SPaolo Bonzini return s->im; 81353018216SPaolo Bonzini case 0x0c: /* ISC */ 81453018216SPaolo Bonzini return s->ris & s->im; 81553018216SPaolo Bonzini case 0x10: /* OSTAT */ 81653018216SPaolo Bonzini return s->ostat; 81753018216SPaolo Bonzini case 0x14: /* EMUX */ 81853018216SPaolo Bonzini return s->emux; 81953018216SPaolo Bonzini case 0x18: /* USTAT */ 82053018216SPaolo Bonzini return s->ustat; 82153018216SPaolo Bonzini case 0x20: /* SSPRI */ 82253018216SPaolo Bonzini return s->sspri; 82353018216SPaolo Bonzini case 0x30: /* SAC */ 82453018216SPaolo Bonzini return s->sac; 82553018216SPaolo Bonzini default: 826df3692e0SPeter Maydell qemu_log_mask(LOG_GUEST_ERROR, 827df3692e0SPeter Maydell "stellaris_adc: read at bad offset 0x%x\n", (int)offset); 82853018216SPaolo Bonzini return 0; 82953018216SPaolo Bonzini } 83053018216SPaolo Bonzini } 83153018216SPaolo Bonzini 83253018216SPaolo Bonzini static void stellaris_adc_write(void *opaque, hwaddr offset, 83353018216SPaolo Bonzini uint64_t value, unsigned size) 83453018216SPaolo Bonzini { 835d6b109daSPhilippe Mathieu-Daudé StellarisADCState *s = opaque; 83653018216SPaolo Bonzini 83753018216SPaolo Bonzini /* TODO: Implement this. */ 83853018216SPaolo Bonzini if (offset >= 0x40 && offset < 0xc0) { 83953018216SPaolo Bonzini int n; 84053018216SPaolo Bonzini n = (offset - 0x40) >> 5; 84153018216SPaolo Bonzini switch (offset & 0x1f) { 84253018216SPaolo Bonzini case 0x00: /* SSMUX */ 84353018216SPaolo Bonzini s->ssmux[n] = value & 0x33333333; 84453018216SPaolo Bonzini return; 84553018216SPaolo Bonzini case 0x04: /* SSCTL */ 84653018216SPaolo Bonzini if (value != 6) { 847df3692e0SPeter Maydell qemu_log_mask(LOG_UNIMP, 848df3692e0SPeter Maydell "ADC: Unimplemented sequence %" PRIx64 "\n", 84953018216SPaolo Bonzini value); 85053018216SPaolo Bonzini } 85153018216SPaolo Bonzini s->ssctl[n] = value; 85253018216SPaolo Bonzini return; 85353018216SPaolo Bonzini default: 85453018216SPaolo Bonzini break; 85553018216SPaolo Bonzini } 85653018216SPaolo Bonzini } 85753018216SPaolo Bonzini switch (offset) { 85853018216SPaolo Bonzini case 0x00: /* ACTSS */ 85953018216SPaolo Bonzini s->actss = value & 0xf; 86053018216SPaolo Bonzini break; 86153018216SPaolo Bonzini case 0x08: /* IM */ 86253018216SPaolo Bonzini s->im = value; 86353018216SPaolo Bonzini break; 86453018216SPaolo Bonzini case 0x0c: /* ISC */ 86553018216SPaolo Bonzini s->ris &= ~value; 86653018216SPaolo Bonzini break; 86753018216SPaolo Bonzini case 0x10: /* OSTAT */ 86853018216SPaolo Bonzini s->ostat &= ~value; 86953018216SPaolo Bonzini break; 87053018216SPaolo Bonzini case 0x14: /* EMUX */ 87153018216SPaolo Bonzini s->emux = value; 87253018216SPaolo Bonzini break; 87353018216SPaolo Bonzini case 0x18: /* USTAT */ 87453018216SPaolo Bonzini s->ustat &= ~value; 87553018216SPaolo Bonzini break; 87653018216SPaolo Bonzini case 0x20: /* SSPRI */ 87753018216SPaolo Bonzini s->sspri = value; 87853018216SPaolo Bonzini break; 87953018216SPaolo Bonzini case 0x28: /* PSSI */ 8809492e4b2SPhilippe Mathieu-Daudé qemu_log_mask(LOG_UNIMP, "ADC: sample initiate unimplemented\n"); 88153018216SPaolo Bonzini break; 88253018216SPaolo Bonzini case 0x30: /* SAC */ 88353018216SPaolo Bonzini s->sac = value; 88453018216SPaolo Bonzini break; 88553018216SPaolo Bonzini default: 886df3692e0SPeter Maydell qemu_log_mask(LOG_GUEST_ERROR, 887df3692e0SPeter Maydell "stellaris_adc: write at bad offset 0x%x\n", (int)offset); 88853018216SPaolo Bonzini } 88953018216SPaolo Bonzini stellaris_adc_update(s); 89053018216SPaolo Bonzini } 89153018216SPaolo Bonzini 89253018216SPaolo Bonzini static const MemoryRegionOps stellaris_adc_ops = { 89353018216SPaolo Bonzini .read = stellaris_adc_read, 89453018216SPaolo Bonzini .write = stellaris_adc_write, 89553018216SPaolo Bonzini .endianness = DEVICE_NATIVE_ENDIAN, 89653018216SPaolo Bonzini }; 89753018216SPaolo Bonzini 89853018216SPaolo Bonzini static const VMStateDescription vmstate_stellaris_adc = { 89953018216SPaolo Bonzini .name = "stellaris_adc", 90053018216SPaolo Bonzini .version_id = 1, 90153018216SPaolo Bonzini .minimum_version_id = 1, 90253018216SPaolo Bonzini .fields = (VMStateField[]) { 903d6b109daSPhilippe Mathieu-Daudé VMSTATE_UINT32(actss, StellarisADCState), 904d6b109daSPhilippe Mathieu-Daudé VMSTATE_UINT32(ris, StellarisADCState), 905d6b109daSPhilippe Mathieu-Daudé VMSTATE_UINT32(im, StellarisADCState), 906d6b109daSPhilippe Mathieu-Daudé VMSTATE_UINT32(emux, StellarisADCState), 907d6b109daSPhilippe Mathieu-Daudé VMSTATE_UINT32(ostat, StellarisADCState), 908d6b109daSPhilippe Mathieu-Daudé VMSTATE_UINT32(ustat, StellarisADCState), 909d6b109daSPhilippe Mathieu-Daudé VMSTATE_UINT32(sspri, StellarisADCState), 910d6b109daSPhilippe Mathieu-Daudé VMSTATE_UINT32(sac, StellarisADCState), 911d6b109daSPhilippe Mathieu-Daudé VMSTATE_UINT32(fifo[0].state, StellarisADCState), 912d6b109daSPhilippe Mathieu-Daudé VMSTATE_UINT32_ARRAY(fifo[0].data, StellarisADCState, 16), 913d6b109daSPhilippe Mathieu-Daudé VMSTATE_UINT32(ssmux[0], StellarisADCState), 914d6b109daSPhilippe Mathieu-Daudé VMSTATE_UINT32(ssctl[0], StellarisADCState), 915d6b109daSPhilippe Mathieu-Daudé VMSTATE_UINT32(fifo[1].state, StellarisADCState), 916d6b109daSPhilippe Mathieu-Daudé VMSTATE_UINT32_ARRAY(fifo[1].data, StellarisADCState, 16), 917d6b109daSPhilippe Mathieu-Daudé VMSTATE_UINT32(ssmux[1], StellarisADCState), 918d6b109daSPhilippe Mathieu-Daudé VMSTATE_UINT32(ssctl[1], StellarisADCState), 919d6b109daSPhilippe Mathieu-Daudé VMSTATE_UINT32(fifo[2].state, StellarisADCState), 920d6b109daSPhilippe Mathieu-Daudé VMSTATE_UINT32_ARRAY(fifo[2].data, StellarisADCState, 16), 921d6b109daSPhilippe Mathieu-Daudé VMSTATE_UINT32(ssmux[2], StellarisADCState), 922d6b109daSPhilippe Mathieu-Daudé VMSTATE_UINT32(ssctl[2], StellarisADCState), 923d6b109daSPhilippe Mathieu-Daudé VMSTATE_UINT32(fifo[3].state, StellarisADCState), 924d6b109daSPhilippe Mathieu-Daudé VMSTATE_UINT32_ARRAY(fifo[3].data, StellarisADCState, 16), 925d6b109daSPhilippe Mathieu-Daudé VMSTATE_UINT32(ssmux[3], StellarisADCState), 926d6b109daSPhilippe Mathieu-Daudé VMSTATE_UINT32(ssctl[3], StellarisADCState), 927d6b109daSPhilippe Mathieu-Daudé VMSTATE_UINT32(noise, StellarisADCState), 92853018216SPaolo Bonzini VMSTATE_END_OF_LIST() 92953018216SPaolo Bonzini } 93053018216SPaolo Bonzini }; 93153018216SPaolo Bonzini 93215c4fff5Sxiaoqiang.zhao static void stellaris_adc_init(Object *obj) 93353018216SPaolo Bonzini { 93415c4fff5Sxiaoqiang.zhao DeviceState *dev = DEVICE(obj); 935d6b109daSPhilippe Mathieu-Daudé StellarisADCState *s = STELLARIS_ADC(obj); 93615c4fff5Sxiaoqiang.zhao SysBusDevice *sbd = SYS_BUS_DEVICE(obj); 93753018216SPaolo Bonzini int n; 93853018216SPaolo Bonzini 93953018216SPaolo Bonzini for (n = 0; n < 4; n++) { 9407df7f67aSAndreas Färber sysbus_init_irq(sbd, &s->irq[n]); 94153018216SPaolo Bonzini } 94253018216SPaolo Bonzini 94315c4fff5Sxiaoqiang.zhao memory_region_init_io(&s->iomem, obj, &stellaris_adc_ops, s, 94453018216SPaolo Bonzini "adc", 0x1000); 9457df7f67aSAndreas Färber sysbus_init_mmio(sbd, &s->iomem); 94653018216SPaolo Bonzini stellaris_adc_reset(s); 9477df7f67aSAndreas Färber qdev_init_gpio_in(dev, stellaris_adc_trigger, 1); 94853018216SPaolo Bonzini } 94953018216SPaolo Bonzini 95053018216SPaolo Bonzini /* Board init. */ 95153018216SPaolo Bonzini static stellaris_board_info stellaris_boards[] = { 95253018216SPaolo Bonzini { "LM3S811EVB", 95353018216SPaolo Bonzini 0, 95453018216SPaolo Bonzini 0x0032000e, 95553018216SPaolo Bonzini 0x001f001f, /* dc0 */ 95653018216SPaolo Bonzini 0x001132bf, 95753018216SPaolo Bonzini 0x01071013, 95853018216SPaolo Bonzini 0x3f0f01ff, 95953018216SPaolo Bonzini 0x0000001f, 96053018216SPaolo Bonzini BP_OLED_I2C 96153018216SPaolo Bonzini }, 96253018216SPaolo Bonzini { "LM3S6965EVB", 96353018216SPaolo Bonzini 0x10010002, 96453018216SPaolo Bonzini 0x1073402e, 96553018216SPaolo Bonzini 0x00ff007f, /* dc0 */ 96653018216SPaolo Bonzini 0x001133ff, 96753018216SPaolo Bonzini 0x030f5317, 96853018216SPaolo Bonzini 0x0f0f87ff, 96953018216SPaolo Bonzini 0x5000007f, 97053018216SPaolo Bonzini BP_OLED_SSI | BP_GAMEPAD 97153018216SPaolo Bonzini } 97253018216SPaolo Bonzini }; 97353018216SPaolo Bonzini 974ba1ba5ccSIgor Mammedov static void stellaris_init(MachineState *ms, stellaris_board_info *board) 97553018216SPaolo Bonzini { 97653018216SPaolo Bonzini static const int uart_irq[] = {5, 6, 33, 34}; 97753018216SPaolo Bonzini static const int timer_irq[] = {19, 21, 23, 35}; 97853018216SPaolo Bonzini static const uint32_t gpio_addr[7] = 97953018216SPaolo Bonzini { 0x40004000, 0x40005000, 0x40006000, 0x40007000, 98053018216SPaolo Bonzini 0x40024000, 0x40025000, 0x40026000}; 98153018216SPaolo Bonzini static const int gpio_irq[7] = {0, 1, 2, 3, 4, 30, 31}; 98253018216SPaolo Bonzini 983394c8bbfSPeter Maydell /* Memory map of SoC devices, from 984394c8bbfSPeter Maydell * Stellaris LM3S6965 Microcontroller Data Sheet (rev I) 985394c8bbfSPeter Maydell * http://www.ti.com/lit/ds/symlink/lm3s6965.pdf 986394c8bbfSPeter Maydell * 987566528f8SMichel Heily * 40000000 wdtimer 988394c8bbfSPeter Maydell * 40002000 i2c (unimplemented) 989394c8bbfSPeter Maydell * 40004000 GPIO 990394c8bbfSPeter Maydell * 40005000 GPIO 991394c8bbfSPeter Maydell * 40006000 GPIO 992394c8bbfSPeter Maydell * 40007000 GPIO 993394c8bbfSPeter Maydell * 40008000 SSI 994394c8bbfSPeter Maydell * 4000c000 UART 995394c8bbfSPeter Maydell * 4000d000 UART 996394c8bbfSPeter Maydell * 4000e000 UART 997394c8bbfSPeter Maydell * 40020000 i2c 998394c8bbfSPeter Maydell * 40021000 i2c (unimplemented) 999394c8bbfSPeter Maydell * 40024000 GPIO 1000394c8bbfSPeter Maydell * 40025000 GPIO 1001394c8bbfSPeter Maydell * 40026000 GPIO 1002394c8bbfSPeter Maydell * 40028000 PWM (unimplemented) 1003394c8bbfSPeter Maydell * 4002c000 QEI (unimplemented) 1004394c8bbfSPeter Maydell * 4002d000 QEI (unimplemented) 1005394c8bbfSPeter Maydell * 40030000 gptimer 1006394c8bbfSPeter Maydell * 40031000 gptimer 1007394c8bbfSPeter Maydell * 40032000 gptimer 1008394c8bbfSPeter Maydell * 40033000 gptimer 1009394c8bbfSPeter Maydell * 40038000 ADC 1010394c8bbfSPeter Maydell * 4003c000 analogue comparator (unimplemented) 1011394c8bbfSPeter Maydell * 40048000 ethernet 1012394c8bbfSPeter Maydell * 400fc000 hibernation module (unimplemented) 1013394c8bbfSPeter Maydell * 400fd000 flash memory control (unimplemented) 1014394c8bbfSPeter Maydell * 400fe000 system control 1015394c8bbfSPeter Maydell */ 1016394c8bbfSPeter Maydell 101720c59c38SMichael Davidsaver DeviceState *gpio_dev[7], *nvic; 101853018216SPaolo Bonzini qemu_irq gpio_in[7][8]; 101953018216SPaolo Bonzini qemu_irq gpio_out[7][8]; 102053018216SPaolo Bonzini qemu_irq adc; 102153018216SPaolo Bonzini int sram_size; 102253018216SPaolo Bonzini int flash_size; 1023a5c82852SAndreas Färber I2CBus *i2c; 102453018216SPaolo Bonzini DeviceState *dev; 10251e31d8eeSPeter Maydell DeviceState *ssys_dev; 102653018216SPaolo Bonzini int i; 102753018216SPaolo Bonzini int j; 10288ecda75fSPeter Maydell const uint8_t *macaddr; 102953018216SPaolo Bonzini 1030fe6ac447SAlistair Francis MemoryRegion *sram = g_new(MemoryRegion, 1); 1031fe6ac447SAlistair Francis MemoryRegion *flash = g_new(MemoryRegion, 1); 1032fe6ac447SAlistair Francis MemoryRegion *system_memory = get_system_memory(); 1033fe6ac447SAlistair Francis 1034fe6ac447SAlistair Francis flash_size = (((board->dc0 & 0xffff) + 1) << 1) * 1024; 1035fe6ac447SAlistair Francis sram_size = ((board->dc0 >> 18) + 1) * 1024; 1036fe6ac447SAlistair Francis 1037fe6ac447SAlistair Francis /* Flash programming is done via the SCU, so pretend it is ROM. */ 103816260006SPhilippe Mathieu-Daudé memory_region_init_rom(flash, NULL, "stellaris.flash", flash_size, 1039f8ed85acSMarkus Armbruster &error_fatal); 1040fe6ac447SAlistair Francis memory_region_add_subregion(system_memory, 0, flash); 1041fe6ac447SAlistair Francis 104298a99ce0SPeter Maydell memory_region_init_ram(sram, NULL, "stellaris.sram", sram_size, 1043f8ed85acSMarkus Armbruster &error_fatal); 1044fe6ac447SAlistair Francis memory_region_add_subregion(system_memory, 0x20000000, sram); 1045fe6ac447SAlistair Francis 1046a861b3e9SPeter Maydell /* 1047a861b3e9SPeter Maydell * Create the system-registers object early, because we will 1048a861b3e9SPeter Maydell * need its sysclk output. 1049a861b3e9SPeter Maydell */ 1050a861b3e9SPeter Maydell ssys_dev = qdev_new(TYPE_STELLARIS_SYS); 1051a861b3e9SPeter Maydell /* Most devices come preprogrammed with a MAC address in the user data. */ 1052a861b3e9SPeter Maydell macaddr = nd_table[0].macaddr.a; 1053a861b3e9SPeter Maydell qdev_prop_set_uint32(ssys_dev, "user0", 1054a861b3e9SPeter Maydell macaddr[0] | (macaddr[1] << 8) | (macaddr[2] << 16)); 1055a861b3e9SPeter Maydell qdev_prop_set_uint32(ssys_dev, "user1", 1056a861b3e9SPeter Maydell macaddr[3] | (macaddr[4] << 8) | (macaddr[5] << 16)); 1057a861b3e9SPeter Maydell qdev_prop_set_uint32(ssys_dev, "did0", board->did0); 1058a861b3e9SPeter Maydell qdev_prop_set_uint32(ssys_dev, "did1", board->did1); 1059a861b3e9SPeter Maydell qdev_prop_set_uint32(ssys_dev, "dc0", board->dc0); 1060a861b3e9SPeter Maydell qdev_prop_set_uint32(ssys_dev, "dc1", board->dc1); 1061a861b3e9SPeter Maydell qdev_prop_set_uint32(ssys_dev, "dc2", board->dc2); 1062a861b3e9SPeter Maydell qdev_prop_set_uint32(ssys_dev, "dc3", board->dc3); 1063a861b3e9SPeter Maydell qdev_prop_set_uint32(ssys_dev, "dc4", board->dc4); 1064a861b3e9SPeter Maydell sysbus_realize_and_unref(SYS_BUS_DEVICE(ssys_dev), &error_fatal); 1065a861b3e9SPeter Maydell 10663e80f690SMarkus Armbruster nvic = qdev_new(TYPE_ARMV7M); 1067f04d4465SPeter Maydell qdev_prop_set_uint32(nvic, "num-irq", NUM_IRQ_LINES); 1068f04d4465SPeter Maydell qdev_prop_set_string(nvic, "cpu-type", ms->cpu_type); 1069a1c5a062SStefan Hajnoczi qdev_prop_set_bit(nvic, "enable-bitband", true); 10708ecda75fSPeter Maydell qdev_connect_clock_in(nvic, "cpuclk", 10718ecda75fSPeter Maydell qdev_get_clock_out(ssys_dev, "SYSCLK")); 10728ecda75fSPeter Maydell /* This SoC does not connect the systick reference clock */ 10735325cc34SMarkus Armbruster object_property_set_link(OBJECT(nvic), "memory", 10745325cc34SMarkus Armbruster OBJECT(get_system_memory()), &error_abort); 1075f04d4465SPeter Maydell /* This will exit with an error if the user passed us a bad cpu_type */ 10763c6ef471SMarkus Armbruster sysbus_realize_and_unref(SYS_BUS_DEVICE(nvic), &error_fatal); 107753018216SPaolo Bonzini 1078a861b3e9SPeter Maydell /* Now we can wire up the IRQ and MMIO of the system registers */ 1079a861b3e9SPeter Maydell sysbus_mmio_map(SYS_BUS_DEVICE(ssys_dev), 0, 0x400fe000); 1080a861b3e9SPeter Maydell sysbus_connect_irq(SYS_BUS_DEVICE(ssys_dev), 0, qdev_get_gpio_in(nvic, 28)); 1081a861b3e9SPeter Maydell 108253018216SPaolo Bonzini if (board->dc1 & (1 << 16)) { 10837df7f67aSAndreas Färber dev = sysbus_create_varargs(TYPE_STELLARIS_ADC, 0x40038000, 108420c59c38SMichael Davidsaver qdev_get_gpio_in(nvic, 14), 108520c59c38SMichael Davidsaver qdev_get_gpio_in(nvic, 15), 108620c59c38SMichael Davidsaver qdev_get_gpio_in(nvic, 16), 108720c59c38SMichael Davidsaver qdev_get_gpio_in(nvic, 17), 108820c59c38SMichael Davidsaver NULL); 108953018216SPaolo Bonzini adc = qdev_get_gpio_in(dev, 0); 109053018216SPaolo Bonzini } else { 109153018216SPaolo Bonzini adc = NULL; 109253018216SPaolo Bonzini } 109353018216SPaolo Bonzini for (i = 0; i < 4; i++) { 109453018216SPaolo Bonzini if (board->dc2 & (0x10000 << i)) { 1095d18fdd69SPeter Maydell SysBusDevice *sbd; 1096d18fdd69SPeter Maydell 1097d18fdd69SPeter Maydell dev = qdev_new(TYPE_STELLARIS_GPTM); 1098d18fdd69SPeter Maydell sbd = SYS_BUS_DEVICE(dev); 1099d18fdd69SPeter Maydell qdev_connect_clock_in(dev, "clk", 1100d18fdd69SPeter Maydell qdev_get_clock_out(ssys_dev, "SYSCLK")); 1101d18fdd69SPeter Maydell sysbus_realize_and_unref(sbd, &error_fatal); 1102d18fdd69SPeter Maydell sysbus_mmio_map(sbd, 0, 0x40030000 + i * 0x1000); 1103d18fdd69SPeter Maydell sysbus_connect_irq(sbd, 0, qdev_get_gpio_in(nvic, timer_irq[i])); 110453018216SPaolo Bonzini /* TODO: This is incorrect, but we get away with it because 110553018216SPaolo Bonzini the ADC output is only ever pulsed. */ 110653018216SPaolo Bonzini qdev_connect_gpio_out(dev, 0, adc); 110753018216SPaolo Bonzini } 110853018216SPaolo Bonzini } 110953018216SPaolo Bonzini 1110566528f8SMichel Heily if (board->dc1 & (1 << 3)) { /* watchdog present */ 11113e80f690SMarkus Armbruster dev = qdev_new(TYPE_LUMINARY_WATCHDOG); 1112566528f8SMichel Heily 11131e31d8eeSPeter Maydell qdev_connect_clock_in(dev, "WDOGCLK", 11141e31d8eeSPeter Maydell qdev_get_clock_out(ssys_dev, "SYSCLK")); 1115566528f8SMichel Heily 11163c6ef471SMarkus Armbruster sysbus_realize_and_unref(SYS_BUS_DEVICE(dev), &error_fatal); 1117566528f8SMichel Heily sysbus_mmio_map(SYS_BUS_DEVICE(dev), 1118566528f8SMichel Heily 0, 1119566528f8SMichel Heily 0x40000000u); 1120566528f8SMichel Heily sysbus_connect_irq(SYS_BUS_DEVICE(dev), 1121566528f8SMichel Heily 0, 1122566528f8SMichel Heily qdev_get_gpio_in(nvic, 18)); 1123566528f8SMichel Heily } 1124566528f8SMichel Heily 1125566528f8SMichel Heily 112653018216SPaolo Bonzini for (i = 0; i < 7; i++) { 112753018216SPaolo Bonzini if (board->dc4 & (1 << i)) { 112853018216SPaolo Bonzini gpio_dev[i] = sysbus_create_simple("pl061_luminary", gpio_addr[i], 112920c59c38SMichael Davidsaver qdev_get_gpio_in(nvic, 113020c59c38SMichael Davidsaver gpio_irq[i])); 113153018216SPaolo Bonzini for (j = 0; j < 8; j++) { 113253018216SPaolo Bonzini gpio_in[i][j] = qdev_get_gpio_in(gpio_dev[i], j); 113353018216SPaolo Bonzini gpio_out[i][j] = NULL; 113453018216SPaolo Bonzini } 113553018216SPaolo Bonzini } 113653018216SPaolo Bonzini } 113753018216SPaolo Bonzini 113853018216SPaolo Bonzini if (board->dc2 & (1 << 12)) { 113920c59c38SMichael Davidsaver dev = sysbus_create_simple(TYPE_STELLARIS_I2C, 0x40020000, 114020c59c38SMichael Davidsaver qdev_get_gpio_in(nvic, 8)); 1141a5c82852SAndreas Färber i2c = (I2CBus *)qdev_get_child_bus(dev, "i2c"); 114253018216SPaolo Bonzini if (board->peripherals & BP_OLED_I2C) { 11431373b15bSPhilippe Mathieu-Daudé i2c_slave_create_simple(i2c, "ssd0303", 0x3d); 114453018216SPaolo Bonzini } 114553018216SPaolo Bonzini } 114653018216SPaolo Bonzini 114753018216SPaolo Bonzini for (i = 0; i < 4; i++) { 114853018216SPaolo Bonzini if (board->dc2 & (1 << i)) { 1149b7f93098SPhilippe Mathieu-Daudé SysBusDevice *sbd; 1150b7f93098SPhilippe Mathieu-Daudé 1151b7f93098SPhilippe Mathieu-Daudé dev = qdev_new("pl011_luminary"); 1152b7f93098SPhilippe Mathieu-Daudé sbd = SYS_BUS_DEVICE(dev); 1153b7f93098SPhilippe Mathieu-Daudé qdev_prop_set_chr(dev, "chardev", serial_hd(i)); 1154b7f93098SPhilippe Mathieu-Daudé sysbus_realize_and_unref(sbd, &error_fatal); 1155b7f93098SPhilippe Mathieu-Daudé sysbus_mmio_map(sbd, 0, 0x4000c000 + i * 0x1000); 1156b7f93098SPhilippe Mathieu-Daudé sysbus_connect_irq(sbd, 0, qdev_get_gpio_in(nvic, uart_irq[i])); 115753018216SPaolo Bonzini } 115853018216SPaolo Bonzini } 115953018216SPaolo Bonzini if (board->dc2 & (1 << 4)) { 116020c59c38SMichael Davidsaver dev = sysbus_create_simple("pl022", 0x40008000, 116120c59c38SMichael Davidsaver qdev_get_gpio_in(nvic, 7)); 116253018216SPaolo Bonzini if (board->peripherals & BP_OLED_SSI) { 116353018216SPaolo Bonzini void *bus; 116453018216SPaolo Bonzini DeviceState *sddev; 116553018216SPaolo Bonzini DeviceState *ssddev; 116636aa285fSMarkus Armbruster DriveInfo *dinfo; 116736aa285fSMarkus Armbruster DeviceState *carddev; 1168d0a030d8SZongyuan Li DeviceState *gpio_d_splitter; 116936aa285fSMarkus Armbruster BlockBackend *blk; 117053018216SPaolo Bonzini 11715092e014SPeter Maydell /* 11725092e014SPeter Maydell * Some boards have both an OLED controller and SD card connected to 117353018216SPaolo Bonzini * the same SSI port, with the SD card chip select connected to a 117453018216SPaolo Bonzini * GPIO pin. Technically the OLED chip select is connected to the 117553018216SPaolo Bonzini * SSI Fss pin. We do not bother emulating that as both devices 117653018216SPaolo Bonzini * should never be selected simultaneously, and our OLED controller 117753018216SPaolo Bonzini * ignores stray 0xff commands that occur when deselecting the SD 117853018216SPaolo Bonzini * card. 11795092e014SPeter Maydell * 11805092e014SPeter Maydell * The h/w wiring is: 11815092e014SPeter Maydell * - GPIO pin D0 is wired to the active-low SD card chip select 11825092e014SPeter Maydell * - GPIO pin A3 is wired to the active-low OLED chip select 11835092e014SPeter Maydell * - The SoC wiring of the PL061 "auxiliary function" for A3 is 11845092e014SPeter Maydell * SSI0Fss ("frame signal"), which is an output from the SoC's 11855092e014SPeter Maydell * SSI controller. The SSI controller takes SSI0Fss low when it 11865092e014SPeter Maydell * transmits a frame, so it can work as a chip-select signal. 11875092e014SPeter Maydell * - GPIO A4 is aux-function SSI0Rx, and wired to the SD card Tx 11885092e014SPeter Maydell * (the OLED never sends data to the CPU, so no wiring needed) 11895092e014SPeter Maydell * - GPIO A5 is aux-function SSI0Tx, and wired to the SD card Rx 11905092e014SPeter Maydell * and the OLED display-data-in 11915092e014SPeter Maydell * - GPIO A2 is aux-function SSI0Clk, wired to SD card and OLED 11925092e014SPeter Maydell * serial-clock input 11935092e014SPeter Maydell * So a guest that wants to use the OLED can configure the PL061 11945092e014SPeter Maydell * to make pins A2, A3, A5 aux-function, so they are connected 11955092e014SPeter Maydell * directly to the SSI controller. When the SSI controller sends 11965092e014SPeter Maydell * data it asserts SSI0Fss which selects the OLED. 11975092e014SPeter Maydell * A guest that wants to use the SD card configures A2, A4 and A5 11985092e014SPeter Maydell * as aux-function, but leaves A3 as a software-controlled GPIO 11995092e014SPeter Maydell * line. It asserts the SD card chip-select by using the PL061 12005092e014SPeter Maydell * to control pin D0, and lets the SSI controller handle Clk, Tx 12015092e014SPeter Maydell * and Rx. (The SSI controller asserts Fss during tx cycles as 12025092e014SPeter Maydell * usual, but because A3 is not set to aux-function this is not 12035092e014SPeter Maydell * forwarded to the OLED, and so the OLED stays unselected.) 12045092e014SPeter Maydell * 12055092e014SPeter Maydell * The QEMU implementation instead is: 12065092e014SPeter Maydell * - GPIO pin D0 is wired to the active-low SD card chip select, 12075092e014SPeter Maydell * and also to the OLED chip-select which is implemented 12085092e014SPeter Maydell * as *active-high* 12095092e014SPeter Maydell * - SSI controller signals go to the devices regardless of 12105092e014SPeter Maydell * whether the guest programs A2, A4, A5 as aux-function or not 12115092e014SPeter Maydell * 12125092e014SPeter Maydell * The problem with this implementation is if the guest doesn't 12135092e014SPeter Maydell * care about the SD card and only uses the OLED. In that case it 12145092e014SPeter Maydell * may choose never to do anything with D0 (leaving it in its 12155092e014SPeter Maydell * default floating state, which reliably leaves the card disabled 12165092e014SPeter Maydell * because an SD card has a pullup on CS within the card itself), 12175092e014SPeter Maydell * and only set up A2, A3, A5. This for us would mean the OLED 12185092e014SPeter Maydell * never gets the chip-select assert it needs. We work around 12195092e014SPeter Maydell * this with a manual raise of D0 here (despite board creation 12205092e014SPeter Maydell * code being the wrong place to raise IRQ lines) to put the OLED 12215092e014SPeter Maydell * into an initially selected state. 12225092e014SPeter Maydell * 12235092e014SPeter Maydell * In theory the right way to model this would be: 12245092e014SPeter Maydell * - Implement aux-function support in the PL061, with an 12255092e014SPeter Maydell * extra set of AFIN and AFOUT GPIO lines (set up so that 12265092e014SPeter Maydell * if a GPIO line is in auxfn mode the main GPIO in and out 12275092e014SPeter Maydell * track the AFIN and AFOUT lines) 12285092e014SPeter Maydell * - Wire the AFOUT for D0 up to either a line from the 12295092e014SPeter Maydell * SSI controller that's pulled low around every transmit, 12305092e014SPeter Maydell * or at least to an always-0 line here on the board 12315092e014SPeter Maydell * - Make the ssd0323 OLED controller chipselect active-low 123253018216SPaolo Bonzini */ 123353018216SPaolo Bonzini bus = qdev_get_child_bus(dev, "ssi"); 1234ec7e429bSPhilippe Mathieu-Daudé sddev = ssi_create_peripheral(bus, "ssi-sd"); 123536aa285fSMarkus Armbruster 123636aa285fSMarkus Armbruster dinfo = drive_get(IF_SD, 0, 0); 123736aa285fSMarkus Armbruster blk = dinfo ? blk_by_legacy_dinfo(dinfo) : NULL; 123836aa285fSMarkus Armbruster carddev = qdev_new(TYPE_SD_CARD); 123936aa285fSMarkus Armbruster qdev_prop_set_drive_err(carddev, "drive", blk, &error_fatal); 124036aa285fSMarkus Armbruster qdev_prop_set_bit(carddev, "spi", true); 124136aa285fSMarkus Armbruster qdev_realize_and_unref(carddev, 124236aa285fSMarkus Armbruster qdev_get_child_bus(sddev, "sd-bus"), 124336aa285fSMarkus Armbruster &error_fatal); 124436aa285fSMarkus Armbruster 1245a617e65fSCédric Le Goater ssddev = qdev_new("ssd0323"); 1246a617e65fSCédric Le Goater qdev_prop_set_uint8(ssddev, "cs", 1); 1247a617e65fSCédric Le Goater qdev_realize_and_unref(ssddev, bus, &error_fatal); 1248d0a030d8SZongyuan Li 1249d0a030d8SZongyuan Li gpio_d_splitter = qdev_new(TYPE_SPLIT_IRQ); 1250d0a030d8SZongyuan Li qdev_prop_set_uint32(gpio_d_splitter, "num-lines", 2); 1251d0a030d8SZongyuan Li qdev_realize_and_unref(gpio_d_splitter, NULL, &error_fatal); 1252d0a030d8SZongyuan Li qdev_connect_gpio_out( 1253d0a030d8SZongyuan Li gpio_d_splitter, 0, 1254d0a030d8SZongyuan Li qdev_get_gpio_in_named(sddev, SSI_GPIO_CS, 0)); 1255d0a030d8SZongyuan Li qdev_connect_gpio_out( 1256d0a030d8SZongyuan Li gpio_d_splitter, 1, 1257de77914eSPeter Crosthwaite qdev_get_gpio_in_named(ssddev, SSI_GPIO_CS, 0)); 1258d0a030d8SZongyuan Li gpio_out[GPIO_D][0] = qdev_get_gpio_in(gpio_d_splitter, 0); 1259d0a030d8SZongyuan Li 1260de77914eSPeter Crosthwaite gpio_out[GPIO_C][7] = qdev_get_gpio_in(ssddev, 0); 126153018216SPaolo Bonzini 126253018216SPaolo Bonzini /* Make sure the select pin is high. */ 126353018216SPaolo Bonzini qemu_irq_raise(gpio_out[GPIO_D][0]); 126453018216SPaolo Bonzini } 126553018216SPaolo Bonzini } 126653018216SPaolo Bonzini if (board->dc4 & (1 << 28)) { 126753018216SPaolo Bonzini DeviceState *enet; 126853018216SPaolo Bonzini 126953018216SPaolo Bonzini qemu_check_nic_model(&nd_table[0], "stellaris"); 127053018216SPaolo Bonzini 12713e80f690SMarkus Armbruster enet = qdev_new("stellaris_enet"); 127253018216SPaolo Bonzini qdev_set_nic_properties(enet, &nd_table[0]); 12733c6ef471SMarkus Armbruster sysbus_realize_and_unref(SYS_BUS_DEVICE(enet), &error_fatal); 127453018216SPaolo Bonzini sysbus_mmio_map(SYS_BUS_DEVICE(enet), 0, 0x40048000); 127520c59c38SMichael Davidsaver sysbus_connect_irq(SYS_BUS_DEVICE(enet), 0, qdev_get_gpio_in(nvic, 42)); 127653018216SPaolo Bonzini } 127753018216SPaolo Bonzini if (board->peripherals & BP_GAMEPAD) { 127853018216SPaolo Bonzini qemu_irq gpad_irq[5]; 127953018216SPaolo Bonzini static const int gpad_keycode[5] = { 0xc8, 0xd0, 0xcb, 0xcd, 0x1d }; 128053018216SPaolo Bonzini 128153018216SPaolo Bonzini gpad_irq[0] = qemu_irq_invert(gpio_in[GPIO_E][0]); /* up */ 128253018216SPaolo Bonzini gpad_irq[1] = qemu_irq_invert(gpio_in[GPIO_E][1]); /* down */ 128353018216SPaolo Bonzini gpad_irq[2] = qemu_irq_invert(gpio_in[GPIO_E][2]); /* left */ 128453018216SPaolo Bonzini gpad_irq[3] = qemu_irq_invert(gpio_in[GPIO_E][3]); /* right */ 128553018216SPaolo Bonzini gpad_irq[4] = qemu_irq_invert(gpio_in[GPIO_F][1]); /* select */ 128653018216SPaolo Bonzini 128753018216SPaolo Bonzini stellaris_gamepad_init(5, gpad_irq, gpad_keycode); 128853018216SPaolo Bonzini } 128953018216SPaolo Bonzini for (i = 0; i < 7; i++) { 129053018216SPaolo Bonzini if (board->dc4 & (1 << i)) { 129153018216SPaolo Bonzini for (j = 0; j < 8; j++) { 129253018216SPaolo Bonzini if (gpio_out[i][j]) { 129353018216SPaolo Bonzini qdev_connect_gpio_out(gpio_dev[i], j, gpio_out[i][j]); 129453018216SPaolo Bonzini } 129553018216SPaolo Bonzini } 129653018216SPaolo Bonzini } 129753018216SPaolo Bonzini } 1298aecfbbc9SPeter Maydell 1299aecfbbc9SPeter Maydell /* Add dummy regions for the devices we don't implement yet, 1300aecfbbc9SPeter Maydell * so guest accesses don't cause unlogged crashes. 1301aecfbbc9SPeter Maydell */ 1302aecfbbc9SPeter Maydell create_unimplemented_device("i2c-0", 0x40002000, 0x1000); 1303aecfbbc9SPeter Maydell create_unimplemented_device("i2c-2", 0x40021000, 0x1000); 1304aecfbbc9SPeter Maydell create_unimplemented_device("PWM", 0x40028000, 0x1000); 1305aecfbbc9SPeter Maydell create_unimplemented_device("QEI-0", 0x4002c000, 0x1000); 1306aecfbbc9SPeter Maydell create_unimplemented_device("QEI-1", 0x4002d000, 0x1000); 1307aecfbbc9SPeter Maydell create_unimplemented_device("analogue-comparator", 0x4003c000, 0x1000); 1308aecfbbc9SPeter Maydell create_unimplemented_device("hibernation", 0x400fc000, 0x1000); 1309aecfbbc9SPeter Maydell create_unimplemented_device("flash-control", 0x400fd000, 0x1000); 1310f04d4465SPeter Maydell 1311761c532aSPeter Maydell armv7m_load_kernel(ARM_CPU(first_cpu), ms->kernel_filename, 0, flash_size); 131253018216SPaolo Bonzini } 131353018216SPaolo Bonzini 131453018216SPaolo Bonzini /* FIXME: Figure out how to generate these from stellaris_boards. */ 13153ef96221SMarcel Apfelbaum static void lm3s811evb_init(MachineState *machine) 131653018216SPaolo Bonzini { 1317ba1ba5ccSIgor Mammedov stellaris_init(machine, &stellaris_boards[0]); 131853018216SPaolo Bonzini } 131953018216SPaolo Bonzini 13203ef96221SMarcel Apfelbaum static void lm3s6965evb_init(MachineState *machine) 132153018216SPaolo Bonzini { 1322ba1ba5ccSIgor Mammedov stellaris_init(machine, &stellaris_boards[1]); 132353018216SPaolo Bonzini } 132453018216SPaolo Bonzini 13258a661aeaSAndreas Färber static void lm3s811evb_class_init(ObjectClass *oc, void *data) 132653018216SPaolo Bonzini { 13278a661aeaSAndreas Färber MachineClass *mc = MACHINE_CLASS(oc); 13288a661aeaSAndreas Färber 1329fd8f71b9SPhilippe Mathieu-Daudé mc->desc = "Stellaris LM3S811EVB (Cortex-M3)"; 1330e264d29dSEduardo Habkost mc->init = lm3s811evb_init; 13314672cbd7SPeter Maydell mc->ignore_memory_transaction_failures = true; 1332ba1ba5ccSIgor Mammedov mc->default_cpu_type = ARM_CPU_TYPE_NAME("cortex-m3"); 133353018216SPaolo Bonzini } 133453018216SPaolo Bonzini 13358a661aeaSAndreas Färber static const TypeInfo lm3s811evb_type = { 13368a661aeaSAndreas Färber .name = MACHINE_TYPE_NAME("lm3s811evb"), 13378a661aeaSAndreas Färber .parent = TYPE_MACHINE, 13388a661aeaSAndreas Färber .class_init = lm3s811evb_class_init, 13398a661aeaSAndreas Färber }; 1340e264d29dSEduardo Habkost 13418a661aeaSAndreas Färber static void lm3s6965evb_class_init(ObjectClass *oc, void *data) 1342e264d29dSEduardo Habkost { 13438a661aeaSAndreas Färber MachineClass *mc = MACHINE_CLASS(oc); 13448a661aeaSAndreas Färber 1345fd8f71b9SPhilippe Mathieu-Daudé mc->desc = "Stellaris LM3S6965EVB (Cortex-M3)"; 1346e264d29dSEduardo Habkost mc->init = lm3s6965evb_init; 13474672cbd7SPeter Maydell mc->ignore_memory_transaction_failures = true; 1348ba1ba5ccSIgor Mammedov mc->default_cpu_type = ARM_CPU_TYPE_NAME("cortex-m3"); 1349e264d29dSEduardo Habkost } 1350e264d29dSEduardo Habkost 13518a661aeaSAndreas Färber static const TypeInfo lm3s6965evb_type = { 13528a661aeaSAndreas Färber .name = MACHINE_TYPE_NAME("lm3s6965evb"), 13538a661aeaSAndreas Färber .parent = TYPE_MACHINE, 13548a661aeaSAndreas Färber .class_init = lm3s6965evb_class_init, 13558a661aeaSAndreas Färber }; 13568a661aeaSAndreas Färber 13578a661aeaSAndreas Färber static void stellaris_machine_init(void) 13588a661aeaSAndreas Färber { 13598a661aeaSAndreas Färber type_register_static(&lm3s811evb_type); 13608a661aeaSAndreas Färber type_register_static(&lm3s6965evb_type); 13618a661aeaSAndreas Färber } 13628a661aeaSAndreas Färber 13630e6aac87SEduardo Habkost type_init(stellaris_machine_init) 136453018216SPaolo Bonzini 136553018216SPaolo Bonzini static void stellaris_i2c_class_init(ObjectClass *klass, void *data) 136653018216SPaolo Bonzini { 136715c4fff5Sxiaoqiang.zhao DeviceClass *dc = DEVICE_CLASS(klass); 136853018216SPaolo Bonzini 136915c4fff5Sxiaoqiang.zhao dc->vmsd = &vmstate_stellaris_i2c; 137053018216SPaolo Bonzini } 137153018216SPaolo Bonzini 137253018216SPaolo Bonzini static const TypeInfo stellaris_i2c_info = { 1373d94a4015SAndreas Färber .name = TYPE_STELLARIS_I2C, 137453018216SPaolo Bonzini .parent = TYPE_SYS_BUS_DEVICE, 137553018216SPaolo Bonzini .instance_size = sizeof(stellaris_i2c_state), 137615c4fff5Sxiaoqiang.zhao .instance_init = stellaris_i2c_init, 137753018216SPaolo Bonzini .class_init = stellaris_i2c_class_init, 137853018216SPaolo Bonzini }; 137953018216SPaolo Bonzini 138053018216SPaolo Bonzini static void stellaris_adc_class_init(ObjectClass *klass, void *data) 138153018216SPaolo Bonzini { 138215c4fff5Sxiaoqiang.zhao DeviceClass *dc = DEVICE_CLASS(klass); 138353018216SPaolo Bonzini 138415c4fff5Sxiaoqiang.zhao dc->vmsd = &vmstate_stellaris_adc; 138553018216SPaolo Bonzini } 138653018216SPaolo Bonzini 138753018216SPaolo Bonzini static const TypeInfo stellaris_adc_info = { 13887df7f67aSAndreas Färber .name = TYPE_STELLARIS_ADC, 138953018216SPaolo Bonzini .parent = TYPE_SYS_BUS_DEVICE, 1390d6b109daSPhilippe Mathieu-Daudé .instance_size = sizeof(StellarisADCState), 139115c4fff5Sxiaoqiang.zhao .instance_init = stellaris_adc_init, 139253018216SPaolo Bonzini .class_init = stellaris_adc_class_init, 139353018216SPaolo Bonzini }; 139453018216SPaolo Bonzini 13954bebb9adSPeter Maydell static void stellaris_sys_class_init(ObjectClass *klass, void *data) 13964bebb9adSPeter Maydell { 13974bebb9adSPeter Maydell DeviceClass *dc = DEVICE_CLASS(klass); 13984bebb9adSPeter Maydell ResettableClass *rc = RESETTABLE_CLASS(klass); 13994bebb9adSPeter Maydell 14004bebb9adSPeter Maydell dc->vmsd = &vmstate_stellaris_sys; 14014bebb9adSPeter Maydell rc->phases.enter = stellaris_sys_reset_enter; 14024bebb9adSPeter Maydell rc->phases.hold = stellaris_sys_reset_hold; 14034bebb9adSPeter Maydell rc->phases.exit = stellaris_sys_reset_exit; 14044bebb9adSPeter Maydell device_class_set_props(dc, stellaris_sys_properties); 14054bebb9adSPeter Maydell } 14064bebb9adSPeter Maydell 14074bebb9adSPeter Maydell static const TypeInfo stellaris_sys_info = { 14084bebb9adSPeter Maydell .name = TYPE_STELLARIS_SYS, 14094bebb9adSPeter Maydell .parent = TYPE_SYS_BUS_DEVICE, 14104bebb9adSPeter Maydell .instance_size = sizeof(ssys_state), 14114bebb9adSPeter Maydell .instance_init = stellaris_sys_instance_init, 14124bebb9adSPeter Maydell .class_init = stellaris_sys_class_init, 14134bebb9adSPeter Maydell }; 14144bebb9adSPeter Maydell 141553018216SPaolo Bonzini static void stellaris_register_types(void) 141653018216SPaolo Bonzini { 141753018216SPaolo Bonzini type_register_static(&stellaris_i2c_info); 141853018216SPaolo Bonzini type_register_static(&stellaris_adc_info); 14194bebb9adSPeter Maydell type_register_static(&stellaris_sys_info); 142053018216SPaolo Bonzini } 142153018216SPaolo Bonzini 142253018216SPaolo Bonzini type_init(stellaris_register_types) 1423