153018216SPaolo Bonzini /* 253018216SPaolo Bonzini * Luminary Micro Stellaris peripherals 353018216SPaolo Bonzini * 453018216SPaolo Bonzini * Copyright (c) 2006 CodeSourcery. 553018216SPaolo Bonzini * Written by Paul Brook 653018216SPaolo Bonzini * 753018216SPaolo Bonzini * This code is licensed under the GPL. 853018216SPaolo Bonzini */ 953018216SPaolo Bonzini 1012b16722SPeter Maydell #include "qemu/osdep.h" 11da34e65cSMarkus Armbruster #include "qapi/error.h" 1253018216SPaolo Bonzini #include "hw/sysbus.h" 138fd06719SAlistair Francis #include "hw/ssi/ssi.h" 1412ec8bd5SPeter Maydell #include "hw/arm/boot.h" 1553018216SPaolo Bonzini #include "qemu/timer.h" 160d09e41aSPaolo Bonzini #include "hw/i2c/i2c.h" 1753018216SPaolo Bonzini #include "net/net.h" 1853018216SPaolo Bonzini #include "hw/boards.h" 1903dd024fSPaolo Bonzini #include "qemu/log.h" 2053018216SPaolo Bonzini #include "exec/address-spaces.h" 21d69ffb5bSMichael Davidsaver #include "sysemu/sysemu.h" 22f04d4465SPeter Maydell #include "hw/arm/armv7m.h" 23f0d1d2c1Sxiaoqiang zhao #include "hw/char/pl011.h" 2498fa3327SPhilippe Mathieu-Daudé #include "hw/input/gamepad.h" 2564552b6bSMarkus Armbruster #include "hw/irq.h" 26566528f8SMichel Heily #include "hw/watchdog/cmsdk-apb-watchdog.h" 27d6454270SMarkus Armbruster #include "migration/vmstate.h" 28aecfbbc9SPeter Maydell #include "hw/misc/unimp.h" 29*f3eb7557SPeter Maydell #include "hw/timer/stellaris-gptm.h" 301e31d8eeSPeter Maydell #include "hw/qdev-clock.h" 31db1015e9SEduardo Habkost #include "qom/object.h" 3253018216SPaolo Bonzini 3353018216SPaolo Bonzini #define GPIO_A 0 3453018216SPaolo Bonzini #define GPIO_B 1 3553018216SPaolo Bonzini #define GPIO_C 2 3653018216SPaolo Bonzini #define GPIO_D 3 3753018216SPaolo Bonzini #define GPIO_E 4 3853018216SPaolo Bonzini #define GPIO_F 5 3953018216SPaolo Bonzini #define GPIO_G 6 4053018216SPaolo Bonzini 4153018216SPaolo Bonzini #define BP_OLED_I2C 0x01 4253018216SPaolo Bonzini #define BP_OLED_SSI 0x02 4353018216SPaolo Bonzini #define BP_GAMEPAD 0x04 4453018216SPaolo Bonzini 458b47b7daSAlistair Francis #define NUM_IRQ_LINES 64 468b47b7daSAlistair Francis 4753018216SPaolo Bonzini typedef const struct { 4853018216SPaolo Bonzini const char *name; 4953018216SPaolo Bonzini uint32_t did0; 5053018216SPaolo Bonzini uint32_t did1; 5153018216SPaolo Bonzini uint32_t dc0; 5253018216SPaolo Bonzini uint32_t dc1; 5353018216SPaolo Bonzini uint32_t dc2; 5453018216SPaolo Bonzini uint32_t dc3; 5553018216SPaolo Bonzini uint32_t dc4; 5653018216SPaolo Bonzini uint32_t peripherals; 5753018216SPaolo Bonzini } stellaris_board_info; 5853018216SPaolo Bonzini 5953018216SPaolo Bonzini /* System controller. */ 6053018216SPaolo Bonzini 614bebb9adSPeter Maydell #define TYPE_STELLARIS_SYS "stellaris-sys" 624bebb9adSPeter Maydell OBJECT_DECLARE_SIMPLE_TYPE(ssys_state, STELLARIS_SYS) 634bebb9adSPeter Maydell 644bebb9adSPeter Maydell struct ssys_state { 654bebb9adSPeter Maydell SysBusDevice parent_obj; 664bebb9adSPeter Maydell 6753018216SPaolo Bonzini MemoryRegion iomem; 6853018216SPaolo Bonzini uint32_t pborctl; 6953018216SPaolo Bonzini uint32_t ldopctl; 7053018216SPaolo Bonzini uint32_t int_status; 7153018216SPaolo Bonzini uint32_t int_mask; 7253018216SPaolo Bonzini uint32_t resc; 7353018216SPaolo Bonzini uint32_t rcc; 7453018216SPaolo Bonzini uint32_t rcc2; 7553018216SPaolo Bonzini uint32_t rcgc[3]; 7653018216SPaolo Bonzini uint32_t scgc[3]; 7753018216SPaolo Bonzini uint32_t dcgc[3]; 7853018216SPaolo Bonzini uint32_t clkvclr; 7953018216SPaolo Bonzini uint32_t ldoarst; 804bebb9adSPeter Maydell qemu_irq irq; 811e31d8eeSPeter Maydell Clock *sysclk; 824bebb9adSPeter Maydell /* Properties (all read-only registers) */ 8353018216SPaolo Bonzini uint32_t user0; 8453018216SPaolo Bonzini uint32_t user1; 854bebb9adSPeter Maydell uint32_t did0; 864bebb9adSPeter Maydell uint32_t did1; 874bebb9adSPeter Maydell uint32_t dc0; 884bebb9adSPeter Maydell uint32_t dc1; 894bebb9adSPeter Maydell uint32_t dc2; 904bebb9adSPeter Maydell uint32_t dc3; 914bebb9adSPeter Maydell uint32_t dc4; 924bebb9adSPeter Maydell }; 9353018216SPaolo Bonzini 9453018216SPaolo Bonzini static void ssys_update(ssys_state *s) 9553018216SPaolo Bonzini { 9653018216SPaolo Bonzini qemu_set_irq(s->irq, (s->int_status & s->int_mask) != 0); 9753018216SPaolo Bonzini } 9853018216SPaolo Bonzini 9953018216SPaolo Bonzini static uint32_t pllcfg_sandstorm[16] = { 10053018216SPaolo Bonzini 0x31c0, /* 1 Mhz */ 10153018216SPaolo Bonzini 0x1ae0, /* 1.8432 Mhz */ 10253018216SPaolo Bonzini 0x18c0, /* 2 Mhz */ 10353018216SPaolo Bonzini 0xd573, /* 2.4576 Mhz */ 10453018216SPaolo Bonzini 0x37a6, /* 3.57954 Mhz */ 10553018216SPaolo Bonzini 0x1ae2, /* 3.6864 Mhz */ 10653018216SPaolo Bonzini 0x0c40, /* 4 Mhz */ 10753018216SPaolo Bonzini 0x98bc, /* 4.906 Mhz */ 10853018216SPaolo Bonzini 0x935b, /* 4.9152 Mhz */ 10953018216SPaolo Bonzini 0x09c0, /* 5 Mhz */ 11053018216SPaolo Bonzini 0x4dee, /* 5.12 Mhz */ 11153018216SPaolo Bonzini 0x0c41, /* 6 Mhz */ 11253018216SPaolo Bonzini 0x75db, /* 6.144 Mhz */ 11353018216SPaolo Bonzini 0x1ae6, /* 7.3728 Mhz */ 11453018216SPaolo Bonzini 0x0600, /* 8 Mhz */ 11553018216SPaolo Bonzini 0x585b /* 8.192 Mhz */ 11653018216SPaolo Bonzini }; 11753018216SPaolo Bonzini 11853018216SPaolo Bonzini static uint32_t pllcfg_fury[16] = { 11953018216SPaolo Bonzini 0x3200, /* 1 Mhz */ 12053018216SPaolo Bonzini 0x1b20, /* 1.8432 Mhz */ 12153018216SPaolo Bonzini 0x1900, /* 2 Mhz */ 12253018216SPaolo Bonzini 0xf42b, /* 2.4576 Mhz */ 12353018216SPaolo Bonzini 0x37e3, /* 3.57954 Mhz */ 12453018216SPaolo Bonzini 0x1b21, /* 3.6864 Mhz */ 12553018216SPaolo Bonzini 0x0c80, /* 4 Mhz */ 12653018216SPaolo Bonzini 0x98ee, /* 4.906 Mhz */ 12753018216SPaolo Bonzini 0xd5b4, /* 4.9152 Mhz */ 12853018216SPaolo Bonzini 0x0a00, /* 5 Mhz */ 12953018216SPaolo Bonzini 0x4e27, /* 5.12 Mhz */ 13053018216SPaolo Bonzini 0x1902, /* 6 Mhz */ 13153018216SPaolo Bonzini 0xec1c, /* 6.144 Mhz */ 13253018216SPaolo Bonzini 0x1b23, /* 7.3728 Mhz */ 13353018216SPaolo Bonzini 0x0640, /* 8 Mhz */ 13453018216SPaolo Bonzini 0xb11c /* 8.192 Mhz */ 13553018216SPaolo Bonzini }; 13653018216SPaolo Bonzini 13753018216SPaolo Bonzini #define DID0_VER_MASK 0x70000000 13853018216SPaolo Bonzini #define DID0_VER_0 0x00000000 13953018216SPaolo Bonzini #define DID0_VER_1 0x10000000 14053018216SPaolo Bonzini 14153018216SPaolo Bonzini #define DID0_CLASS_MASK 0x00FF0000 14253018216SPaolo Bonzini #define DID0_CLASS_SANDSTORM 0x00000000 14353018216SPaolo Bonzini #define DID0_CLASS_FURY 0x00010000 14453018216SPaolo Bonzini 14553018216SPaolo Bonzini static int ssys_board_class(const ssys_state *s) 14653018216SPaolo Bonzini { 1474bebb9adSPeter Maydell uint32_t did0 = s->did0; 14853018216SPaolo Bonzini switch (did0 & DID0_VER_MASK) { 14953018216SPaolo Bonzini case DID0_VER_0: 15053018216SPaolo Bonzini return DID0_CLASS_SANDSTORM; 15153018216SPaolo Bonzini case DID0_VER_1: 15253018216SPaolo Bonzini switch (did0 & DID0_CLASS_MASK) { 15353018216SPaolo Bonzini case DID0_CLASS_SANDSTORM: 15453018216SPaolo Bonzini case DID0_CLASS_FURY: 15553018216SPaolo Bonzini return did0 & DID0_CLASS_MASK; 15653018216SPaolo Bonzini } 15753018216SPaolo Bonzini /* for unknown classes, fall through */ 15853018216SPaolo Bonzini default: 159df3692e0SPeter Maydell /* This can only happen if the hardwired constant did0 value 160df3692e0SPeter Maydell * in this board's stellaris_board_info struct is wrong. 161df3692e0SPeter Maydell */ 162df3692e0SPeter Maydell g_assert_not_reached(); 16353018216SPaolo Bonzini } 16453018216SPaolo Bonzini } 16553018216SPaolo Bonzini 16653018216SPaolo Bonzini static uint64_t ssys_read(void *opaque, hwaddr offset, 16753018216SPaolo Bonzini unsigned size) 16853018216SPaolo Bonzini { 16953018216SPaolo Bonzini ssys_state *s = (ssys_state *)opaque; 17053018216SPaolo Bonzini 17153018216SPaolo Bonzini switch (offset) { 17253018216SPaolo Bonzini case 0x000: /* DID0 */ 1734bebb9adSPeter Maydell return s->did0; 17453018216SPaolo Bonzini case 0x004: /* DID1 */ 1754bebb9adSPeter Maydell return s->did1; 17653018216SPaolo Bonzini case 0x008: /* DC0 */ 1774bebb9adSPeter Maydell return s->dc0; 17853018216SPaolo Bonzini case 0x010: /* DC1 */ 1794bebb9adSPeter Maydell return s->dc1; 18053018216SPaolo Bonzini case 0x014: /* DC2 */ 1814bebb9adSPeter Maydell return s->dc2; 18253018216SPaolo Bonzini case 0x018: /* DC3 */ 1834bebb9adSPeter Maydell return s->dc3; 18453018216SPaolo Bonzini case 0x01c: /* DC4 */ 1854bebb9adSPeter Maydell return s->dc4; 18653018216SPaolo Bonzini case 0x030: /* PBORCTL */ 18753018216SPaolo Bonzini return s->pborctl; 18853018216SPaolo Bonzini case 0x034: /* LDOPCTL */ 18953018216SPaolo Bonzini return s->ldopctl; 19053018216SPaolo Bonzini case 0x040: /* SRCR0 */ 19153018216SPaolo Bonzini return 0; 19253018216SPaolo Bonzini case 0x044: /* SRCR1 */ 19353018216SPaolo Bonzini return 0; 19453018216SPaolo Bonzini case 0x048: /* SRCR2 */ 19553018216SPaolo Bonzini return 0; 19653018216SPaolo Bonzini case 0x050: /* RIS */ 19753018216SPaolo Bonzini return s->int_status; 19853018216SPaolo Bonzini case 0x054: /* IMC */ 19953018216SPaolo Bonzini return s->int_mask; 20053018216SPaolo Bonzini case 0x058: /* MISC */ 20153018216SPaolo Bonzini return s->int_status & s->int_mask; 20253018216SPaolo Bonzini case 0x05c: /* RESC */ 20353018216SPaolo Bonzini return s->resc; 20453018216SPaolo Bonzini case 0x060: /* RCC */ 20553018216SPaolo Bonzini return s->rcc; 20653018216SPaolo Bonzini case 0x064: /* PLLCFG */ 20753018216SPaolo Bonzini { 20853018216SPaolo Bonzini int xtal; 20953018216SPaolo Bonzini xtal = (s->rcc >> 6) & 0xf; 21053018216SPaolo Bonzini switch (ssys_board_class(s)) { 21153018216SPaolo Bonzini case DID0_CLASS_FURY: 21253018216SPaolo Bonzini return pllcfg_fury[xtal]; 21353018216SPaolo Bonzini case DID0_CLASS_SANDSTORM: 21453018216SPaolo Bonzini return pllcfg_sandstorm[xtal]; 21553018216SPaolo Bonzini default: 216df3692e0SPeter Maydell g_assert_not_reached(); 21753018216SPaolo Bonzini } 21853018216SPaolo Bonzini } 21953018216SPaolo Bonzini case 0x070: /* RCC2 */ 22053018216SPaolo Bonzini return s->rcc2; 22153018216SPaolo Bonzini case 0x100: /* RCGC0 */ 22253018216SPaolo Bonzini return s->rcgc[0]; 22353018216SPaolo Bonzini case 0x104: /* RCGC1 */ 22453018216SPaolo Bonzini return s->rcgc[1]; 22553018216SPaolo Bonzini case 0x108: /* RCGC2 */ 22653018216SPaolo Bonzini return s->rcgc[2]; 22753018216SPaolo Bonzini case 0x110: /* SCGC0 */ 22853018216SPaolo Bonzini return s->scgc[0]; 22953018216SPaolo Bonzini case 0x114: /* SCGC1 */ 23053018216SPaolo Bonzini return s->scgc[1]; 23153018216SPaolo Bonzini case 0x118: /* SCGC2 */ 23253018216SPaolo Bonzini return s->scgc[2]; 23353018216SPaolo Bonzini case 0x120: /* DCGC0 */ 23453018216SPaolo Bonzini return s->dcgc[0]; 23553018216SPaolo Bonzini case 0x124: /* DCGC1 */ 23653018216SPaolo Bonzini return s->dcgc[1]; 23753018216SPaolo Bonzini case 0x128: /* DCGC2 */ 23853018216SPaolo Bonzini return s->dcgc[2]; 23953018216SPaolo Bonzini case 0x150: /* CLKVCLR */ 24053018216SPaolo Bonzini return s->clkvclr; 24153018216SPaolo Bonzini case 0x160: /* LDOARST */ 24253018216SPaolo Bonzini return s->ldoarst; 24353018216SPaolo Bonzini case 0x1e0: /* USER0 */ 24453018216SPaolo Bonzini return s->user0; 24553018216SPaolo Bonzini case 0x1e4: /* USER1 */ 24653018216SPaolo Bonzini return s->user1; 24753018216SPaolo Bonzini default: 248df3692e0SPeter Maydell qemu_log_mask(LOG_GUEST_ERROR, 249df3692e0SPeter Maydell "SSYS: read at bad offset 0x%x\n", (int)offset); 25053018216SPaolo Bonzini return 0; 25153018216SPaolo Bonzini } 25253018216SPaolo Bonzini } 25353018216SPaolo Bonzini 25453018216SPaolo Bonzini static bool ssys_use_rcc2(ssys_state *s) 25553018216SPaolo Bonzini { 25653018216SPaolo Bonzini return (s->rcc2 >> 31) & 0x1; 25753018216SPaolo Bonzini } 25853018216SPaolo Bonzini 25953018216SPaolo Bonzini /* 2601e31d8eeSPeter Maydell * Calculate the system clock period. We only want to propagate 2611e31d8eeSPeter Maydell * this change to the rest of the system if we're not being called 2621e31d8eeSPeter Maydell * from migration post-load. 26353018216SPaolo Bonzini */ 2641e31d8eeSPeter Maydell static void ssys_calculate_system_clock(ssys_state *s, bool propagate_clock) 26553018216SPaolo Bonzini { 2661e31d8eeSPeter Maydell /* 2671e31d8eeSPeter Maydell * SYSDIV field specifies divisor: 0 == /1, 1 == /2, etc. Input 2681e31d8eeSPeter Maydell * clock is 200MHz, which is a period of 5 ns. Dividing the clock 2691e31d8eeSPeter Maydell * frequency by X is the same as multiplying the period by X. 2701e31d8eeSPeter Maydell */ 27153018216SPaolo Bonzini if (ssys_use_rcc2(s)) { 27253018216SPaolo Bonzini system_clock_scale = 5 * (((s->rcc2 >> 23) & 0x3f) + 1); 27353018216SPaolo Bonzini } else { 27453018216SPaolo Bonzini system_clock_scale = 5 * (((s->rcc >> 23) & 0xf) + 1); 27553018216SPaolo Bonzini } 2761e31d8eeSPeter Maydell clock_set_ns(s->sysclk, system_clock_scale); 2771e31d8eeSPeter Maydell if (propagate_clock) { 2781e31d8eeSPeter Maydell clock_propagate(s->sysclk); 2791e31d8eeSPeter Maydell } 28053018216SPaolo Bonzini } 28153018216SPaolo Bonzini 28253018216SPaolo Bonzini static void ssys_write(void *opaque, hwaddr offset, 28353018216SPaolo Bonzini uint64_t value, unsigned size) 28453018216SPaolo Bonzini { 28553018216SPaolo Bonzini ssys_state *s = (ssys_state *)opaque; 28653018216SPaolo Bonzini 28753018216SPaolo Bonzini switch (offset) { 28853018216SPaolo Bonzini case 0x030: /* PBORCTL */ 28953018216SPaolo Bonzini s->pborctl = value & 0xffff; 29053018216SPaolo Bonzini break; 29153018216SPaolo Bonzini case 0x034: /* LDOPCTL */ 29253018216SPaolo Bonzini s->ldopctl = value & 0x1f; 29353018216SPaolo Bonzini break; 29453018216SPaolo Bonzini case 0x040: /* SRCR0 */ 29553018216SPaolo Bonzini case 0x044: /* SRCR1 */ 29653018216SPaolo Bonzini case 0x048: /* SRCR2 */ 2979194524bSPhilippe Mathieu-Daudé qemu_log_mask(LOG_UNIMP, "Peripheral reset not implemented\n"); 29853018216SPaolo Bonzini break; 29953018216SPaolo Bonzini case 0x054: /* IMC */ 30053018216SPaolo Bonzini s->int_mask = value & 0x7f; 30153018216SPaolo Bonzini break; 30253018216SPaolo Bonzini case 0x058: /* MISC */ 30353018216SPaolo Bonzini s->int_status &= ~value; 30453018216SPaolo Bonzini break; 30553018216SPaolo Bonzini case 0x05c: /* RESC */ 30653018216SPaolo Bonzini s->resc = value & 0x3f; 30753018216SPaolo Bonzini break; 30853018216SPaolo Bonzini case 0x060: /* RCC */ 30953018216SPaolo Bonzini if ((s->rcc & (1 << 13)) != 0 && (value & (1 << 13)) == 0) { 31053018216SPaolo Bonzini /* PLL enable. */ 31153018216SPaolo Bonzini s->int_status |= (1 << 6); 31253018216SPaolo Bonzini } 31353018216SPaolo Bonzini s->rcc = value; 3141e31d8eeSPeter Maydell ssys_calculate_system_clock(s, true); 31553018216SPaolo Bonzini break; 31653018216SPaolo Bonzini case 0x070: /* RCC2 */ 31753018216SPaolo Bonzini if (ssys_board_class(s) == DID0_CLASS_SANDSTORM) { 31853018216SPaolo Bonzini break; 31953018216SPaolo Bonzini } 32053018216SPaolo Bonzini 32153018216SPaolo Bonzini if ((s->rcc2 & (1 << 13)) != 0 && (value & (1 << 13)) == 0) { 32253018216SPaolo Bonzini /* PLL enable. */ 32353018216SPaolo Bonzini s->int_status |= (1 << 6); 32453018216SPaolo Bonzini } 32553018216SPaolo Bonzini s->rcc2 = value; 3261e31d8eeSPeter Maydell ssys_calculate_system_clock(s, true); 32753018216SPaolo Bonzini break; 32853018216SPaolo Bonzini case 0x100: /* RCGC0 */ 32953018216SPaolo Bonzini s->rcgc[0] = value; 33053018216SPaolo Bonzini break; 33153018216SPaolo Bonzini case 0x104: /* RCGC1 */ 33253018216SPaolo Bonzini s->rcgc[1] = value; 33353018216SPaolo Bonzini break; 33453018216SPaolo Bonzini case 0x108: /* RCGC2 */ 33553018216SPaolo Bonzini s->rcgc[2] = value; 33653018216SPaolo Bonzini break; 33753018216SPaolo Bonzini case 0x110: /* SCGC0 */ 33853018216SPaolo Bonzini s->scgc[0] = value; 33953018216SPaolo Bonzini break; 34053018216SPaolo Bonzini case 0x114: /* SCGC1 */ 34153018216SPaolo Bonzini s->scgc[1] = value; 34253018216SPaolo Bonzini break; 34353018216SPaolo Bonzini case 0x118: /* SCGC2 */ 34453018216SPaolo Bonzini s->scgc[2] = value; 34553018216SPaolo Bonzini break; 34653018216SPaolo Bonzini case 0x120: /* DCGC0 */ 34753018216SPaolo Bonzini s->dcgc[0] = value; 34853018216SPaolo Bonzini break; 34953018216SPaolo Bonzini case 0x124: /* DCGC1 */ 35053018216SPaolo Bonzini s->dcgc[1] = value; 35153018216SPaolo Bonzini break; 35253018216SPaolo Bonzini case 0x128: /* DCGC2 */ 35353018216SPaolo Bonzini s->dcgc[2] = value; 35453018216SPaolo Bonzini break; 35553018216SPaolo Bonzini case 0x150: /* CLKVCLR */ 35653018216SPaolo Bonzini s->clkvclr = value; 35753018216SPaolo Bonzini break; 35853018216SPaolo Bonzini case 0x160: /* LDOARST */ 35953018216SPaolo Bonzini s->ldoarst = value; 36053018216SPaolo Bonzini break; 36153018216SPaolo Bonzini default: 362df3692e0SPeter Maydell qemu_log_mask(LOG_GUEST_ERROR, 363df3692e0SPeter Maydell "SSYS: write at bad offset 0x%x\n", (int)offset); 36453018216SPaolo Bonzini } 36553018216SPaolo Bonzini ssys_update(s); 36653018216SPaolo Bonzini } 36753018216SPaolo Bonzini 36853018216SPaolo Bonzini static const MemoryRegionOps ssys_ops = { 36953018216SPaolo Bonzini .read = ssys_read, 37053018216SPaolo Bonzini .write = ssys_write, 37153018216SPaolo Bonzini .endianness = DEVICE_NATIVE_ENDIAN, 37253018216SPaolo Bonzini }; 37353018216SPaolo Bonzini 3744bebb9adSPeter Maydell static void stellaris_sys_reset_enter(Object *obj, ResetType type) 37553018216SPaolo Bonzini { 3764bebb9adSPeter Maydell ssys_state *s = STELLARIS_SYS(obj); 37753018216SPaolo Bonzini 37853018216SPaolo Bonzini s->pborctl = 0x7ffd; 37953018216SPaolo Bonzini s->rcc = 0x078e3ac0; 38053018216SPaolo Bonzini 38153018216SPaolo Bonzini if (ssys_board_class(s) == DID0_CLASS_SANDSTORM) { 38253018216SPaolo Bonzini s->rcc2 = 0; 38353018216SPaolo Bonzini } else { 38453018216SPaolo Bonzini s->rcc2 = 0x07802810; 38553018216SPaolo Bonzini } 38653018216SPaolo Bonzini s->rcgc[0] = 1; 38753018216SPaolo Bonzini s->scgc[0] = 1; 38853018216SPaolo Bonzini s->dcgc[0] = 1; 3894bebb9adSPeter Maydell } 3904bebb9adSPeter Maydell 3914bebb9adSPeter Maydell static void stellaris_sys_reset_hold(Object *obj) 3924bebb9adSPeter Maydell { 3934bebb9adSPeter Maydell ssys_state *s = STELLARIS_SYS(obj); 3944bebb9adSPeter Maydell 3951e31d8eeSPeter Maydell /* OK to propagate clocks from the hold phase */ 3961e31d8eeSPeter Maydell ssys_calculate_system_clock(s, true); 39753018216SPaolo Bonzini } 39853018216SPaolo Bonzini 3994bebb9adSPeter Maydell static void stellaris_sys_reset_exit(Object *obj) 4004bebb9adSPeter Maydell { 4014bebb9adSPeter Maydell } 4024bebb9adSPeter Maydell 40353018216SPaolo Bonzini static int stellaris_sys_post_load(void *opaque, int version_id) 40453018216SPaolo Bonzini { 40553018216SPaolo Bonzini ssys_state *s = opaque; 40653018216SPaolo Bonzini 4071e31d8eeSPeter Maydell ssys_calculate_system_clock(s, false); 40853018216SPaolo Bonzini 40953018216SPaolo Bonzini return 0; 41053018216SPaolo Bonzini } 41153018216SPaolo Bonzini 41253018216SPaolo Bonzini static const VMStateDescription vmstate_stellaris_sys = { 41353018216SPaolo Bonzini .name = "stellaris_sys", 41453018216SPaolo Bonzini .version_id = 2, 41553018216SPaolo Bonzini .minimum_version_id = 1, 41653018216SPaolo Bonzini .post_load = stellaris_sys_post_load, 41753018216SPaolo Bonzini .fields = (VMStateField[]) { 41853018216SPaolo Bonzini VMSTATE_UINT32(pborctl, ssys_state), 41953018216SPaolo Bonzini VMSTATE_UINT32(ldopctl, ssys_state), 42053018216SPaolo Bonzini VMSTATE_UINT32(int_mask, ssys_state), 42153018216SPaolo Bonzini VMSTATE_UINT32(int_status, ssys_state), 42253018216SPaolo Bonzini VMSTATE_UINT32(resc, ssys_state), 42353018216SPaolo Bonzini VMSTATE_UINT32(rcc, ssys_state), 42453018216SPaolo Bonzini VMSTATE_UINT32_V(rcc2, ssys_state, 2), 42553018216SPaolo Bonzini VMSTATE_UINT32_ARRAY(rcgc, ssys_state, 3), 42653018216SPaolo Bonzini VMSTATE_UINT32_ARRAY(scgc, ssys_state, 3), 42753018216SPaolo Bonzini VMSTATE_UINT32_ARRAY(dcgc, ssys_state, 3), 42853018216SPaolo Bonzini VMSTATE_UINT32(clkvclr, ssys_state), 42953018216SPaolo Bonzini VMSTATE_UINT32(ldoarst, ssys_state), 4301e31d8eeSPeter Maydell /* No field for sysclk -- handled in post-load instead */ 43153018216SPaolo Bonzini VMSTATE_END_OF_LIST() 43253018216SPaolo Bonzini } 43353018216SPaolo Bonzini }; 43453018216SPaolo Bonzini 4354bebb9adSPeter Maydell static Property stellaris_sys_properties[] = { 4364bebb9adSPeter Maydell DEFINE_PROP_UINT32("user0", ssys_state, user0, 0), 4374bebb9adSPeter Maydell DEFINE_PROP_UINT32("user1", ssys_state, user1, 0), 4384bebb9adSPeter Maydell DEFINE_PROP_UINT32("did0", ssys_state, did0, 0), 4394bebb9adSPeter Maydell DEFINE_PROP_UINT32("did1", ssys_state, did1, 0), 4404bebb9adSPeter Maydell DEFINE_PROP_UINT32("dc0", ssys_state, dc0, 0), 4414bebb9adSPeter Maydell DEFINE_PROP_UINT32("dc1", ssys_state, dc1, 0), 4424bebb9adSPeter Maydell DEFINE_PROP_UINT32("dc2", ssys_state, dc2, 0), 4434bebb9adSPeter Maydell DEFINE_PROP_UINT32("dc3", ssys_state, dc3, 0), 4444bebb9adSPeter Maydell DEFINE_PROP_UINT32("dc4", ssys_state, dc4, 0), 4454bebb9adSPeter Maydell DEFINE_PROP_END_OF_LIST() 4464bebb9adSPeter Maydell }; 4474bebb9adSPeter Maydell 4484bebb9adSPeter Maydell static void stellaris_sys_instance_init(Object *obj) 4494bebb9adSPeter Maydell { 4504bebb9adSPeter Maydell ssys_state *s = STELLARIS_SYS(obj); 4514bebb9adSPeter Maydell SysBusDevice *sbd = SYS_BUS_DEVICE(s); 4524bebb9adSPeter Maydell 4534bebb9adSPeter Maydell memory_region_init_io(&s->iomem, obj, &ssys_ops, s, "ssys", 0x00001000); 4544bebb9adSPeter Maydell sysbus_init_mmio(sbd, &s->iomem); 4554bebb9adSPeter Maydell sysbus_init_irq(sbd, &s->irq); 4561e31d8eeSPeter Maydell s->sysclk = qdev_init_clock_out(DEVICE(s), "SYSCLK"); 4574bebb9adSPeter Maydell } 4584bebb9adSPeter Maydell 45953018216SPaolo Bonzini /* I2C controller. */ 46053018216SPaolo Bonzini 461d94a4015SAndreas Färber #define TYPE_STELLARIS_I2C "stellaris-i2c" 4628063396bSEduardo Habkost OBJECT_DECLARE_SIMPLE_TYPE(stellaris_i2c_state, STELLARIS_I2C) 463d94a4015SAndreas Färber 464db1015e9SEduardo Habkost struct stellaris_i2c_state { 465d94a4015SAndreas Färber SysBusDevice parent_obj; 466d94a4015SAndreas Färber 467a5c82852SAndreas Färber I2CBus *bus; 46853018216SPaolo Bonzini qemu_irq irq; 46953018216SPaolo Bonzini MemoryRegion iomem; 47053018216SPaolo Bonzini uint32_t msa; 47153018216SPaolo Bonzini uint32_t mcs; 47253018216SPaolo Bonzini uint32_t mdr; 47353018216SPaolo Bonzini uint32_t mtpr; 47453018216SPaolo Bonzini uint32_t mimr; 47553018216SPaolo Bonzini uint32_t mris; 47653018216SPaolo Bonzini uint32_t mcr; 477db1015e9SEduardo Habkost }; 47853018216SPaolo Bonzini 47953018216SPaolo Bonzini #define STELLARIS_I2C_MCS_BUSY 0x01 48053018216SPaolo Bonzini #define STELLARIS_I2C_MCS_ERROR 0x02 48153018216SPaolo Bonzini #define STELLARIS_I2C_MCS_ADRACK 0x04 48253018216SPaolo Bonzini #define STELLARIS_I2C_MCS_DATACK 0x08 48353018216SPaolo Bonzini #define STELLARIS_I2C_MCS_ARBLST 0x10 48453018216SPaolo Bonzini #define STELLARIS_I2C_MCS_IDLE 0x20 48553018216SPaolo Bonzini #define STELLARIS_I2C_MCS_BUSBSY 0x40 48653018216SPaolo Bonzini 48753018216SPaolo Bonzini static uint64_t stellaris_i2c_read(void *opaque, hwaddr offset, 48853018216SPaolo Bonzini unsigned size) 48953018216SPaolo Bonzini { 49053018216SPaolo Bonzini stellaris_i2c_state *s = (stellaris_i2c_state *)opaque; 49153018216SPaolo Bonzini 49253018216SPaolo Bonzini switch (offset) { 49353018216SPaolo Bonzini case 0x00: /* MSA */ 49453018216SPaolo Bonzini return s->msa; 49553018216SPaolo Bonzini case 0x04: /* MCS */ 49653018216SPaolo Bonzini /* We don't emulate timing, so the controller is never busy. */ 49753018216SPaolo Bonzini return s->mcs | STELLARIS_I2C_MCS_IDLE; 49853018216SPaolo Bonzini case 0x08: /* MDR */ 49953018216SPaolo Bonzini return s->mdr; 50053018216SPaolo Bonzini case 0x0c: /* MTPR */ 50153018216SPaolo Bonzini return s->mtpr; 50253018216SPaolo Bonzini case 0x10: /* MIMR */ 50353018216SPaolo Bonzini return s->mimr; 50453018216SPaolo Bonzini case 0x14: /* MRIS */ 50553018216SPaolo Bonzini return s->mris; 50653018216SPaolo Bonzini case 0x18: /* MMIS */ 50753018216SPaolo Bonzini return s->mris & s->mimr; 50853018216SPaolo Bonzini case 0x20: /* MCR */ 50953018216SPaolo Bonzini return s->mcr; 51053018216SPaolo Bonzini default: 511df3692e0SPeter Maydell qemu_log_mask(LOG_GUEST_ERROR, 512df3692e0SPeter Maydell "stellaris_i2c: read at bad offset 0x%x\n", (int)offset); 51353018216SPaolo Bonzini return 0; 51453018216SPaolo Bonzini } 51553018216SPaolo Bonzini } 51653018216SPaolo Bonzini 51753018216SPaolo Bonzini static void stellaris_i2c_update(stellaris_i2c_state *s) 51853018216SPaolo Bonzini { 51953018216SPaolo Bonzini int level; 52053018216SPaolo Bonzini 52153018216SPaolo Bonzini level = (s->mris & s->mimr) != 0; 52253018216SPaolo Bonzini qemu_set_irq(s->irq, level); 52353018216SPaolo Bonzini } 52453018216SPaolo Bonzini 52553018216SPaolo Bonzini static void stellaris_i2c_write(void *opaque, hwaddr offset, 52653018216SPaolo Bonzini uint64_t value, unsigned size) 52753018216SPaolo Bonzini { 52853018216SPaolo Bonzini stellaris_i2c_state *s = (stellaris_i2c_state *)opaque; 52953018216SPaolo Bonzini 53053018216SPaolo Bonzini switch (offset) { 53153018216SPaolo Bonzini case 0x00: /* MSA */ 53253018216SPaolo Bonzini s->msa = value & 0xff; 53353018216SPaolo Bonzini break; 53453018216SPaolo Bonzini case 0x04: /* MCS */ 53553018216SPaolo Bonzini if ((s->mcr & 0x10) == 0) { 53653018216SPaolo Bonzini /* Disabled. Do nothing. */ 53753018216SPaolo Bonzini break; 53853018216SPaolo Bonzini } 53953018216SPaolo Bonzini /* Grab the bus if this is starting a transfer. */ 54053018216SPaolo Bonzini if ((value & 2) && (s->mcs & STELLARIS_I2C_MCS_BUSBSY) == 0) { 54153018216SPaolo Bonzini if (i2c_start_transfer(s->bus, s->msa >> 1, s->msa & 1)) { 54253018216SPaolo Bonzini s->mcs |= STELLARIS_I2C_MCS_ARBLST; 54353018216SPaolo Bonzini } else { 54453018216SPaolo Bonzini s->mcs &= ~STELLARIS_I2C_MCS_ARBLST; 54553018216SPaolo Bonzini s->mcs |= STELLARIS_I2C_MCS_BUSBSY; 54653018216SPaolo Bonzini } 54753018216SPaolo Bonzini } 54853018216SPaolo Bonzini /* If we don't have the bus then indicate an error. */ 54953018216SPaolo Bonzini if (!i2c_bus_busy(s->bus) 55053018216SPaolo Bonzini || (s->mcs & STELLARIS_I2C_MCS_BUSBSY) == 0) { 55153018216SPaolo Bonzini s->mcs |= STELLARIS_I2C_MCS_ERROR; 55253018216SPaolo Bonzini break; 55353018216SPaolo Bonzini } 55453018216SPaolo Bonzini s->mcs &= ~STELLARIS_I2C_MCS_ERROR; 55553018216SPaolo Bonzini if (value & 1) { 55653018216SPaolo Bonzini /* Transfer a byte. */ 55753018216SPaolo Bonzini /* TODO: Handle errors. */ 55853018216SPaolo Bonzini if (s->msa & 1) { 55953018216SPaolo Bonzini /* Recv */ 56005f9f17eSCorey Minyard s->mdr = i2c_recv(s->bus); 56153018216SPaolo Bonzini } else { 56253018216SPaolo Bonzini /* Send */ 56353018216SPaolo Bonzini i2c_send(s->bus, s->mdr); 56453018216SPaolo Bonzini } 56553018216SPaolo Bonzini /* Raise an interrupt. */ 56653018216SPaolo Bonzini s->mris |= 1; 56753018216SPaolo Bonzini } 56853018216SPaolo Bonzini if (value & 4) { 56953018216SPaolo Bonzini /* Finish transfer. */ 57053018216SPaolo Bonzini i2c_end_transfer(s->bus); 57153018216SPaolo Bonzini s->mcs &= ~STELLARIS_I2C_MCS_BUSBSY; 57253018216SPaolo Bonzini } 57353018216SPaolo Bonzini break; 57453018216SPaolo Bonzini case 0x08: /* MDR */ 57553018216SPaolo Bonzini s->mdr = value & 0xff; 57653018216SPaolo Bonzini break; 57753018216SPaolo Bonzini case 0x0c: /* MTPR */ 57853018216SPaolo Bonzini s->mtpr = value & 0xff; 57953018216SPaolo Bonzini break; 58053018216SPaolo Bonzini case 0x10: /* MIMR */ 58153018216SPaolo Bonzini s->mimr = 1; 58253018216SPaolo Bonzini break; 58353018216SPaolo Bonzini case 0x1c: /* MICR */ 58453018216SPaolo Bonzini s->mris &= ~value; 58553018216SPaolo Bonzini break; 58653018216SPaolo Bonzini case 0x20: /* MCR */ 587df3692e0SPeter Maydell if (value & 1) { 5889492e4b2SPhilippe Mathieu-Daudé qemu_log_mask(LOG_UNIMP, 5899492e4b2SPhilippe Mathieu-Daudé "stellaris_i2c: Loopback not implemented\n"); 590df3692e0SPeter Maydell } 591df3692e0SPeter Maydell if (value & 0x20) { 592df3692e0SPeter Maydell qemu_log_mask(LOG_UNIMP, 5939492e4b2SPhilippe Mathieu-Daudé "stellaris_i2c: Slave mode not implemented\n"); 594df3692e0SPeter Maydell } 59553018216SPaolo Bonzini s->mcr = value & 0x31; 59653018216SPaolo Bonzini break; 59753018216SPaolo Bonzini default: 598df3692e0SPeter Maydell qemu_log_mask(LOG_GUEST_ERROR, 599df3692e0SPeter Maydell "stellaris_i2c: write at bad offset 0x%x\n", (int)offset); 60053018216SPaolo Bonzini } 60153018216SPaolo Bonzini stellaris_i2c_update(s); 60253018216SPaolo Bonzini } 60353018216SPaolo Bonzini 60453018216SPaolo Bonzini static void stellaris_i2c_reset(stellaris_i2c_state *s) 60553018216SPaolo Bonzini { 60653018216SPaolo Bonzini if (s->mcs & STELLARIS_I2C_MCS_BUSBSY) 60753018216SPaolo Bonzini i2c_end_transfer(s->bus); 60853018216SPaolo Bonzini 60953018216SPaolo Bonzini s->msa = 0; 61053018216SPaolo Bonzini s->mcs = 0; 61153018216SPaolo Bonzini s->mdr = 0; 61253018216SPaolo Bonzini s->mtpr = 1; 61353018216SPaolo Bonzini s->mimr = 0; 61453018216SPaolo Bonzini s->mris = 0; 61553018216SPaolo Bonzini s->mcr = 0; 61653018216SPaolo Bonzini stellaris_i2c_update(s); 61753018216SPaolo Bonzini } 61853018216SPaolo Bonzini 61953018216SPaolo Bonzini static const MemoryRegionOps stellaris_i2c_ops = { 62053018216SPaolo Bonzini .read = stellaris_i2c_read, 62153018216SPaolo Bonzini .write = stellaris_i2c_write, 62253018216SPaolo Bonzini .endianness = DEVICE_NATIVE_ENDIAN, 62353018216SPaolo Bonzini }; 62453018216SPaolo Bonzini 62553018216SPaolo Bonzini static const VMStateDescription vmstate_stellaris_i2c = { 62653018216SPaolo Bonzini .name = "stellaris_i2c", 62753018216SPaolo Bonzini .version_id = 1, 62853018216SPaolo Bonzini .minimum_version_id = 1, 62953018216SPaolo Bonzini .fields = (VMStateField[]) { 63053018216SPaolo Bonzini VMSTATE_UINT32(msa, stellaris_i2c_state), 63153018216SPaolo Bonzini VMSTATE_UINT32(mcs, stellaris_i2c_state), 63253018216SPaolo Bonzini VMSTATE_UINT32(mdr, stellaris_i2c_state), 63353018216SPaolo Bonzini VMSTATE_UINT32(mtpr, stellaris_i2c_state), 63453018216SPaolo Bonzini VMSTATE_UINT32(mimr, stellaris_i2c_state), 63553018216SPaolo Bonzini VMSTATE_UINT32(mris, stellaris_i2c_state), 63653018216SPaolo Bonzini VMSTATE_UINT32(mcr, stellaris_i2c_state), 63753018216SPaolo Bonzini VMSTATE_END_OF_LIST() 63853018216SPaolo Bonzini } 63953018216SPaolo Bonzini }; 64053018216SPaolo Bonzini 64115c4fff5Sxiaoqiang.zhao static void stellaris_i2c_init(Object *obj) 64253018216SPaolo Bonzini { 64315c4fff5Sxiaoqiang.zhao DeviceState *dev = DEVICE(obj); 64415c4fff5Sxiaoqiang.zhao stellaris_i2c_state *s = STELLARIS_I2C(obj); 64515c4fff5Sxiaoqiang.zhao SysBusDevice *sbd = SYS_BUS_DEVICE(obj); 646a5c82852SAndreas Färber I2CBus *bus; 64753018216SPaolo Bonzini 648d94a4015SAndreas Färber sysbus_init_irq(sbd, &s->irq); 649d94a4015SAndreas Färber bus = i2c_init_bus(dev, "i2c"); 65053018216SPaolo Bonzini s->bus = bus; 65153018216SPaolo Bonzini 65215c4fff5Sxiaoqiang.zhao memory_region_init_io(&s->iomem, obj, &stellaris_i2c_ops, s, 65353018216SPaolo Bonzini "i2c", 0x1000); 654d94a4015SAndreas Färber sysbus_init_mmio(sbd, &s->iomem); 65553018216SPaolo Bonzini /* ??? For now we only implement the master interface. */ 65653018216SPaolo Bonzini stellaris_i2c_reset(s); 65753018216SPaolo Bonzini } 65853018216SPaolo Bonzini 65953018216SPaolo Bonzini /* Analogue to Digital Converter. This is only partially implemented, 66053018216SPaolo Bonzini enough for applications that use a combined ADC and timer tick. */ 66153018216SPaolo Bonzini 66253018216SPaolo Bonzini #define STELLARIS_ADC_EM_CONTROLLER 0 66353018216SPaolo Bonzini #define STELLARIS_ADC_EM_COMP 1 66453018216SPaolo Bonzini #define STELLARIS_ADC_EM_EXTERNAL 4 66553018216SPaolo Bonzini #define STELLARIS_ADC_EM_TIMER 5 66653018216SPaolo Bonzini #define STELLARIS_ADC_EM_PWM0 6 66753018216SPaolo Bonzini #define STELLARIS_ADC_EM_PWM1 7 66853018216SPaolo Bonzini #define STELLARIS_ADC_EM_PWM2 8 66953018216SPaolo Bonzini 67053018216SPaolo Bonzini #define STELLARIS_ADC_FIFO_EMPTY 0x0100 67153018216SPaolo Bonzini #define STELLARIS_ADC_FIFO_FULL 0x1000 67253018216SPaolo Bonzini 6737df7f67aSAndreas Färber #define TYPE_STELLARIS_ADC "stellaris-adc" 674db1015e9SEduardo Habkost typedef struct StellarisADCState stellaris_adc_state; 6758110fa1dSEduardo Habkost DECLARE_INSTANCE_CHECKER(stellaris_adc_state, STELLARIS_ADC, 6768110fa1dSEduardo Habkost TYPE_STELLARIS_ADC) 6777df7f67aSAndreas Färber 678db1015e9SEduardo Habkost struct StellarisADCState { 6797df7f67aSAndreas Färber SysBusDevice parent_obj; 6807df7f67aSAndreas Färber 68153018216SPaolo Bonzini MemoryRegion iomem; 68253018216SPaolo Bonzini uint32_t actss; 68353018216SPaolo Bonzini uint32_t ris; 68453018216SPaolo Bonzini uint32_t im; 68553018216SPaolo Bonzini uint32_t emux; 68653018216SPaolo Bonzini uint32_t ostat; 68753018216SPaolo Bonzini uint32_t ustat; 68853018216SPaolo Bonzini uint32_t sspri; 68953018216SPaolo Bonzini uint32_t sac; 69053018216SPaolo Bonzini struct { 69153018216SPaolo Bonzini uint32_t state; 69253018216SPaolo Bonzini uint32_t data[16]; 69353018216SPaolo Bonzini } fifo[4]; 69453018216SPaolo Bonzini uint32_t ssmux[4]; 69553018216SPaolo Bonzini uint32_t ssctl[4]; 69653018216SPaolo Bonzini uint32_t noise; 69753018216SPaolo Bonzini qemu_irq irq[4]; 698db1015e9SEduardo Habkost }; 69953018216SPaolo Bonzini 70053018216SPaolo Bonzini static uint32_t stellaris_adc_fifo_read(stellaris_adc_state *s, int n) 70153018216SPaolo Bonzini { 70253018216SPaolo Bonzini int tail; 70353018216SPaolo Bonzini 70453018216SPaolo Bonzini tail = s->fifo[n].state & 0xf; 70553018216SPaolo Bonzini if (s->fifo[n].state & STELLARIS_ADC_FIFO_EMPTY) { 70653018216SPaolo Bonzini s->ustat |= 1 << n; 70753018216SPaolo Bonzini } else { 70853018216SPaolo Bonzini s->fifo[n].state = (s->fifo[n].state & ~0xf) | ((tail + 1) & 0xf); 70953018216SPaolo Bonzini s->fifo[n].state &= ~STELLARIS_ADC_FIFO_FULL; 71053018216SPaolo Bonzini if (tail + 1 == ((s->fifo[n].state >> 4) & 0xf)) 71153018216SPaolo Bonzini s->fifo[n].state |= STELLARIS_ADC_FIFO_EMPTY; 71253018216SPaolo Bonzini } 71353018216SPaolo Bonzini return s->fifo[n].data[tail]; 71453018216SPaolo Bonzini } 71553018216SPaolo Bonzini 71653018216SPaolo Bonzini static void stellaris_adc_fifo_write(stellaris_adc_state *s, int n, 71753018216SPaolo Bonzini uint32_t value) 71853018216SPaolo Bonzini { 71953018216SPaolo Bonzini int head; 72053018216SPaolo Bonzini 72153018216SPaolo Bonzini /* TODO: Real hardware has limited size FIFOs. We have a full 16 entry 72253018216SPaolo Bonzini FIFO fir each sequencer. */ 72353018216SPaolo Bonzini head = (s->fifo[n].state >> 4) & 0xf; 72453018216SPaolo Bonzini if (s->fifo[n].state & STELLARIS_ADC_FIFO_FULL) { 72553018216SPaolo Bonzini s->ostat |= 1 << n; 72653018216SPaolo Bonzini return; 72753018216SPaolo Bonzini } 72853018216SPaolo Bonzini s->fifo[n].data[head] = value; 72953018216SPaolo Bonzini head = (head + 1) & 0xf; 73053018216SPaolo Bonzini s->fifo[n].state &= ~STELLARIS_ADC_FIFO_EMPTY; 73153018216SPaolo Bonzini s->fifo[n].state = (s->fifo[n].state & ~0xf0) | (head << 4); 73253018216SPaolo Bonzini if ((s->fifo[n].state & 0xf) == head) 73353018216SPaolo Bonzini s->fifo[n].state |= STELLARIS_ADC_FIFO_FULL; 73453018216SPaolo Bonzini } 73553018216SPaolo Bonzini 73653018216SPaolo Bonzini static void stellaris_adc_update(stellaris_adc_state *s) 73753018216SPaolo Bonzini { 73853018216SPaolo Bonzini int level; 73953018216SPaolo Bonzini int n; 74053018216SPaolo Bonzini 74153018216SPaolo Bonzini for (n = 0; n < 4; n++) { 74253018216SPaolo Bonzini level = (s->ris & s->im & (1 << n)) != 0; 74353018216SPaolo Bonzini qemu_set_irq(s->irq[n], level); 74453018216SPaolo Bonzini } 74553018216SPaolo Bonzini } 74653018216SPaolo Bonzini 74753018216SPaolo Bonzini static void stellaris_adc_trigger(void *opaque, int irq, int level) 74853018216SPaolo Bonzini { 74953018216SPaolo Bonzini stellaris_adc_state *s = (stellaris_adc_state *)opaque; 75053018216SPaolo Bonzini int n; 75153018216SPaolo Bonzini 75253018216SPaolo Bonzini for (n = 0; n < 4; n++) { 75353018216SPaolo Bonzini if ((s->actss & (1 << n)) == 0) { 75453018216SPaolo Bonzini continue; 75553018216SPaolo Bonzini } 75653018216SPaolo Bonzini 75753018216SPaolo Bonzini if (((s->emux >> (n * 4)) & 0xff) != 5) { 75853018216SPaolo Bonzini continue; 75953018216SPaolo Bonzini } 76053018216SPaolo Bonzini 76153018216SPaolo Bonzini /* Some applications use the ADC as a random number source, so introduce 76253018216SPaolo Bonzini some variation into the signal. */ 76353018216SPaolo Bonzini s->noise = s->noise * 314159 + 1; 76453018216SPaolo Bonzini /* ??? actual inputs not implemented. Return an arbitrary value. */ 76553018216SPaolo Bonzini stellaris_adc_fifo_write(s, n, 0x200 + ((s->noise >> 16) & 7)); 76653018216SPaolo Bonzini s->ris |= (1 << n); 76753018216SPaolo Bonzini stellaris_adc_update(s); 76853018216SPaolo Bonzini } 76953018216SPaolo Bonzini } 77053018216SPaolo Bonzini 77153018216SPaolo Bonzini static void stellaris_adc_reset(stellaris_adc_state *s) 77253018216SPaolo Bonzini { 77353018216SPaolo Bonzini int n; 77453018216SPaolo Bonzini 77553018216SPaolo Bonzini for (n = 0; n < 4; n++) { 77653018216SPaolo Bonzini s->ssmux[n] = 0; 77753018216SPaolo Bonzini s->ssctl[n] = 0; 77853018216SPaolo Bonzini s->fifo[n].state = STELLARIS_ADC_FIFO_EMPTY; 77953018216SPaolo Bonzini } 78053018216SPaolo Bonzini } 78153018216SPaolo Bonzini 78253018216SPaolo Bonzini static uint64_t stellaris_adc_read(void *opaque, hwaddr offset, 78353018216SPaolo Bonzini unsigned size) 78453018216SPaolo Bonzini { 78553018216SPaolo Bonzini stellaris_adc_state *s = (stellaris_adc_state *)opaque; 78653018216SPaolo Bonzini 78753018216SPaolo Bonzini /* TODO: Implement this. */ 78853018216SPaolo Bonzini if (offset >= 0x40 && offset < 0xc0) { 78953018216SPaolo Bonzini int n; 79053018216SPaolo Bonzini n = (offset - 0x40) >> 5; 79153018216SPaolo Bonzini switch (offset & 0x1f) { 79253018216SPaolo Bonzini case 0x00: /* SSMUX */ 79353018216SPaolo Bonzini return s->ssmux[n]; 79453018216SPaolo Bonzini case 0x04: /* SSCTL */ 79553018216SPaolo Bonzini return s->ssctl[n]; 79653018216SPaolo Bonzini case 0x08: /* SSFIFO */ 79753018216SPaolo Bonzini return stellaris_adc_fifo_read(s, n); 79853018216SPaolo Bonzini case 0x0c: /* SSFSTAT */ 79953018216SPaolo Bonzini return s->fifo[n].state; 80053018216SPaolo Bonzini default: 80153018216SPaolo Bonzini break; 80253018216SPaolo Bonzini } 80353018216SPaolo Bonzini } 80453018216SPaolo Bonzini switch (offset) { 80553018216SPaolo Bonzini case 0x00: /* ACTSS */ 80653018216SPaolo Bonzini return s->actss; 80753018216SPaolo Bonzini case 0x04: /* RIS */ 80853018216SPaolo Bonzini return s->ris; 80953018216SPaolo Bonzini case 0x08: /* IM */ 81053018216SPaolo Bonzini return s->im; 81153018216SPaolo Bonzini case 0x0c: /* ISC */ 81253018216SPaolo Bonzini return s->ris & s->im; 81353018216SPaolo Bonzini case 0x10: /* OSTAT */ 81453018216SPaolo Bonzini return s->ostat; 81553018216SPaolo Bonzini case 0x14: /* EMUX */ 81653018216SPaolo Bonzini return s->emux; 81753018216SPaolo Bonzini case 0x18: /* USTAT */ 81853018216SPaolo Bonzini return s->ustat; 81953018216SPaolo Bonzini case 0x20: /* SSPRI */ 82053018216SPaolo Bonzini return s->sspri; 82153018216SPaolo Bonzini case 0x30: /* SAC */ 82253018216SPaolo Bonzini return s->sac; 82353018216SPaolo Bonzini default: 824df3692e0SPeter Maydell qemu_log_mask(LOG_GUEST_ERROR, 825df3692e0SPeter Maydell "stellaris_adc: read at bad offset 0x%x\n", (int)offset); 82653018216SPaolo Bonzini return 0; 82753018216SPaolo Bonzini } 82853018216SPaolo Bonzini } 82953018216SPaolo Bonzini 83053018216SPaolo Bonzini static void stellaris_adc_write(void *opaque, hwaddr offset, 83153018216SPaolo Bonzini uint64_t value, unsigned size) 83253018216SPaolo Bonzini { 83353018216SPaolo Bonzini stellaris_adc_state *s = (stellaris_adc_state *)opaque; 83453018216SPaolo Bonzini 83553018216SPaolo Bonzini /* TODO: Implement this. */ 83653018216SPaolo Bonzini if (offset >= 0x40 && offset < 0xc0) { 83753018216SPaolo Bonzini int n; 83853018216SPaolo Bonzini n = (offset - 0x40) >> 5; 83953018216SPaolo Bonzini switch (offset & 0x1f) { 84053018216SPaolo Bonzini case 0x00: /* SSMUX */ 84153018216SPaolo Bonzini s->ssmux[n] = value & 0x33333333; 84253018216SPaolo Bonzini return; 84353018216SPaolo Bonzini case 0x04: /* SSCTL */ 84453018216SPaolo Bonzini if (value != 6) { 845df3692e0SPeter Maydell qemu_log_mask(LOG_UNIMP, 846df3692e0SPeter Maydell "ADC: Unimplemented sequence %" PRIx64 "\n", 84753018216SPaolo Bonzini value); 84853018216SPaolo Bonzini } 84953018216SPaolo Bonzini s->ssctl[n] = value; 85053018216SPaolo Bonzini return; 85153018216SPaolo Bonzini default: 85253018216SPaolo Bonzini break; 85353018216SPaolo Bonzini } 85453018216SPaolo Bonzini } 85553018216SPaolo Bonzini switch (offset) { 85653018216SPaolo Bonzini case 0x00: /* ACTSS */ 85753018216SPaolo Bonzini s->actss = value & 0xf; 85853018216SPaolo Bonzini break; 85953018216SPaolo Bonzini case 0x08: /* IM */ 86053018216SPaolo Bonzini s->im = value; 86153018216SPaolo Bonzini break; 86253018216SPaolo Bonzini case 0x0c: /* ISC */ 86353018216SPaolo Bonzini s->ris &= ~value; 86453018216SPaolo Bonzini break; 86553018216SPaolo Bonzini case 0x10: /* OSTAT */ 86653018216SPaolo Bonzini s->ostat &= ~value; 86753018216SPaolo Bonzini break; 86853018216SPaolo Bonzini case 0x14: /* EMUX */ 86953018216SPaolo Bonzini s->emux = value; 87053018216SPaolo Bonzini break; 87153018216SPaolo Bonzini case 0x18: /* USTAT */ 87253018216SPaolo Bonzini s->ustat &= ~value; 87353018216SPaolo Bonzini break; 87453018216SPaolo Bonzini case 0x20: /* SSPRI */ 87553018216SPaolo Bonzini s->sspri = value; 87653018216SPaolo Bonzini break; 87753018216SPaolo Bonzini case 0x28: /* PSSI */ 8789492e4b2SPhilippe Mathieu-Daudé qemu_log_mask(LOG_UNIMP, "ADC: sample initiate unimplemented\n"); 87953018216SPaolo Bonzini break; 88053018216SPaolo Bonzini case 0x30: /* SAC */ 88153018216SPaolo Bonzini s->sac = value; 88253018216SPaolo Bonzini break; 88353018216SPaolo Bonzini default: 884df3692e0SPeter Maydell qemu_log_mask(LOG_GUEST_ERROR, 885df3692e0SPeter Maydell "stellaris_adc: write at bad offset 0x%x\n", (int)offset); 88653018216SPaolo Bonzini } 88753018216SPaolo Bonzini stellaris_adc_update(s); 88853018216SPaolo Bonzini } 88953018216SPaolo Bonzini 89053018216SPaolo Bonzini static const MemoryRegionOps stellaris_adc_ops = { 89153018216SPaolo Bonzini .read = stellaris_adc_read, 89253018216SPaolo Bonzini .write = stellaris_adc_write, 89353018216SPaolo Bonzini .endianness = DEVICE_NATIVE_ENDIAN, 89453018216SPaolo Bonzini }; 89553018216SPaolo Bonzini 89653018216SPaolo Bonzini static const VMStateDescription vmstate_stellaris_adc = { 89753018216SPaolo Bonzini .name = "stellaris_adc", 89853018216SPaolo Bonzini .version_id = 1, 89953018216SPaolo Bonzini .minimum_version_id = 1, 90053018216SPaolo Bonzini .fields = (VMStateField[]) { 90153018216SPaolo Bonzini VMSTATE_UINT32(actss, stellaris_adc_state), 90253018216SPaolo Bonzini VMSTATE_UINT32(ris, stellaris_adc_state), 90353018216SPaolo Bonzini VMSTATE_UINT32(im, stellaris_adc_state), 90453018216SPaolo Bonzini VMSTATE_UINT32(emux, stellaris_adc_state), 90553018216SPaolo Bonzini VMSTATE_UINT32(ostat, stellaris_adc_state), 90653018216SPaolo Bonzini VMSTATE_UINT32(ustat, stellaris_adc_state), 90753018216SPaolo Bonzini VMSTATE_UINT32(sspri, stellaris_adc_state), 90853018216SPaolo Bonzini VMSTATE_UINT32(sac, stellaris_adc_state), 90953018216SPaolo Bonzini VMSTATE_UINT32(fifo[0].state, stellaris_adc_state), 91053018216SPaolo Bonzini VMSTATE_UINT32_ARRAY(fifo[0].data, stellaris_adc_state, 16), 91153018216SPaolo Bonzini VMSTATE_UINT32(ssmux[0], stellaris_adc_state), 91253018216SPaolo Bonzini VMSTATE_UINT32(ssctl[0], stellaris_adc_state), 91353018216SPaolo Bonzini VMSTATE_UINT32(fifo[1].state, stellaris_adc_state), 91453018216SPaolo Bonzini VMSTATE_UINT32_ARRAY(fifo[1].data, stellaris_adc_state, 16), 91553018216SPaolo Bonzini VMSTATE_UINT32(ssmux[1], stellaris_adc_state), 91653018216SPaolo Bonzini VMSTATE_UINT32(ssctl[1], stellaris_adc_state), 91753018216SPaolo Bonzini VMSTATE_UINT32(fifo[2].state, stellaris_adc_state), 91853018216SPaolo Bonzini VMSTATE_UINT32_ARRAY(fifo[2].data, stellaris_adc_state, 16), 91953018216SPaolo Bonzini VMSTATE_UINT32(ssmux[2], stellaris_adc_state), 92053018216SPaolo Bonzini VMSTATE_UINT32(ssctl[2], stellaris_adc_state), 92153018216SPaolo Bonzini VMSTATE_UINT32(fifo[3].state, stellaris_adc_state), 92253018216SPaolo Bonzini VMSTATE_UINT32_ARRAY(fifo[3].data, stellaris_adc_state, 16), 92353018216SPaolo Bonzini VMSTATE_UINT32(ssmux[3], stellaris_adc_state), 92453018216SPaolo Bonzini VMSTATE_UINT32(ssctl[3], stellaris_adc_state), 92553018216SPaolo Bonzini VMSTATE_UINT32(noise, stellaris_adc_state), 92653018216SPaolo Bonzini VMSTATE_END_OF_LIST() 92753018216SPaolo Bonzini } 92853018216SPaolo Bonzini }; 92953018216SPaolo Bonzini 93015c4fff5Sxiaoqiang.zhao static void stellaris_adc_init(Object *obj) 93153018216SPaolo Bonzini { 93215c4fff5Sxiaoqiang.zhao DeviceState *dev = DEVICE(obj); 93315c4fff5Sxiaoqiang.zhao stellaris_adc_state *s = STELLARIS_ADC(obj); 93415c4fff5Sxiaoqiang.zhao SysBusDevice *sbd = SYS_BUS_DEVICE(obj); 93553018216SPaolo Bonzini int n; 93653018216SPaolo Bonzini 93753018216SPaolo Bonzini for (n = 0; n < 4; n++) { 9387df7f67aSAndreas Färber sysbus_init_irq(sbd, &s->irq[n]); 93953018216SPaolo Bonzini } 94053018216SPaolo Bonzini 94115c4fff5Sxiaoqiang.zhao memory_region_init_io(&s->iomem, obj, &stellaris_adc_ops, s, 94253018216SPaolo Bonzini "adc", 0x1000); 9437df7f67aSAndreas Färber sysbus_init_mmio(sbd, &s->iomem); 94453018216SPaolo Bonzini stellaris_adc_reset(s); 9457df7f67aSAndreas Färber qdev_init_gpio_in(dev, stellaris_adc_trigger, 1); 94653018216SPaolo Bonzini } 94753018216SPaolo Bonzini 94853018216SPaolo Bonzini /* Board init. */ 94953018216SPaolo Bonzini static stellaris_board_info stellaris_boards[] = { 95053018216SPaolo Bonzini { "LM3S811EVB", 95153018216SPaolo Bonzini 0, 95253018216SPaolo Bonzini 0x0032000e, 95353018216SPaolo Bonzini 0x001f001f, /* dc0 */ 95453018216SPaolo Bonzini 0x001132bf, 95553018216SPaolo Bonzini 0x01071013, 95653018216SPaolo Bonzini 0x3f0f01ff, 95753018216SPaolo Bonzini 0x0000001f, 95853018216SPaolo Bonzini BP_OLED_I2C 95953018216SPaolo Bonzini }, 96053018216SPaolo Bonzini { "LM3S6965EVB", 96153018216SPaolo Bonzini 0x10010002, 96253018216SPaolo Bonzini 0x1073402e, 96353018216SPaolo Bonzini 0x00ff007f, /* dc0 */ 96453018216SPaolo Bonzini 0x001133ff, 96553018216SPaolo Bonzini 0x030f5317, 96653018216SPaolo Bonzini 0x0f0f87ff, 96753018216SPaolo Bonzini 0x5000007f, 96853018216SPaolo Bonzini BP_OLED_SSI | BP_GAMEPAD 96953018216SPaolo Bonzini } 97053018216SPaolo Bonzini }; 97153018216SPaolo Bonzini 972ba1ba5ccSIgor Mammedov static void stellaris_init(MachineState *ms, stellaris_board_info *board) 97353018216SPaolo Bonzini { 97453018216SPaolo Bonzini static const int uart_irq[] = {5, 6, 33, 34}; 97553018216SPaolo Bonzini static const int timer_irq[] = {19, 21, 23, 35}; 97653018216SPaolo Bonzini static const uint32_t gpio_addr[7] = 97753018216SPaolo Bonzini { 0x40004000, 0x40005000, 0x40006000, 0x40007000, 97853018216SPaolo Bonzini 0x40024000, 0x40025000, 0x40026000}; 97953018216SPaolo Bonzini static const int gpio_irq[7] = {0, 1, 2, 3, 4, 30, 31}; 98053018216SPaolo Bonzini 981394c8bbfSPeter Maydell /* Memory map of SoC devices, from 982394c8bbfSPeter Maydell * Stellaris LM3S6965 Microcontroller Data Sheet (rev I) 983394c8bbfSPeter Maydell * http://www.ti.com/lit/ds/symlink/lm3s6965.pdf 984394c8bbfSPeter Maydell * 985566528f8SMichel Heily * 40000000 wdtimer 986394c8bbfSPeter Maydell * 40002000 i2c (unimplemented) 987394c8bbfSPeter Maydell * 40004000 GPIO 988394c8bbfSPeter Maydell * 40005000 GPIO 989394c8bbfSPeter Maydell * 40006000 GPIO 990394c8bbfSPeter Maydell * 40007000 GPIO 991394c8bbfSPeter Maydell * 40008000 SSI 992394c8bbfSPeter Maydell * 4000c000 UART 993394c8bbfSPeter Maydell * 4000d000 UART 994394c8bbfSPeter Maydell * 4000e000 UART 995394c8bbfSPeter Maydell * 40020000 i2c 996394c8bbfSPeter Maydell * 40021000 i2c (unimplemented) 997394c8bbfSPeter Maydell * 40024000 GPIO 998394c8bbfSPeter Maydell * 40025000 GPIO 999394c8bbfSPeter Maydell * 40026000 GPIO 1000394c8bbfSPeter Maydell * 40028000 PWM (unimplemented) 1001394c8bbfSPeter Maydell * 4002c000 QEI (unimplemented) 1002394c8bbfSPeter Maydell * 4002d000 QEI (unimplemented) 1003394c8bbfSPeter Maydell * 40030000 gptimer 1004394c8bbfSPeter Maydell * 40031000 gptimer 1005394c8bbfSPeter Maydell * 40032000 gptimer 1006394c8bbfSPeter Maydell * 40033000 gptimer 1007394c8bbfSPeter Maydell * 40038000 ADC 1008394c8bbfSPeter Maydell * 4003c000 analogue comparator (unimplemented) 1009394c8bbfSPeter Maydell * 40048000 ethernet 1010394c8bbfSPeter Maydell * 400fc000 hibernation module (unimplemented) 1011394c8bbfSPeter Maydell * 400fd000 flash memory control (unimplemented) 1012394c8bbfSPeter Maydell * 400fe000 system control 1013394c8bbfSPeter Maydell */ 1014394c8bbfSPeter Maydell 101520c59c38SMichael Davidsaver DeviceState *gpio_dev[7], *nvic; 101653018216SPaolo Bonzini qemu_irq gpio_in[7][8]; 101753018216SPaolo Bonzini qemu_irq gpio_out[7][8]; 101853018216SPaolo Bonzini qemu_irq adc; 101953018216SPaolo Bonzini int sram_size; 102053018216SPaolo Bonzini int flash_size; 1021a5c82852SAndreas Färber I2CBus *i2c; 102253018216SPaolo Bonzini DeviceState *dev; 10231e31d8eeSPeter Maydell DeviceState *ssys_dev; 102453018216SPaolo Bonzini int i; 102553018216SPaolo Bonzini int j; 10268ecda75fSPeter Maydell const uint8_t *macaddr; 102753018216SPaolo Bonzini 1028fe6ac447SAlistair Francis MemoryRegion *sram = g_new(MemoryRegion, 1); 1029fe6ac447SAlistair Francis MemoryRegion *flash = g_new(MemoryRegion, 1); 1030fe6ac447SAlistair Francis MemoryRegion *system_memory = get_system_memory(); 1031fe6ac447SAlistair Francis 1032fe6ac447SAlistair Francis flash_size = (((board->dc0 & 0xffff) + 1) << 1) * 1024; 1033fe6ac447SAlistair Francis sram_size = ((board->dc0 >> 18) + 1) * 1024; 1034fe6ac447SAlistair Francis 1035fe6ac447SAlistair Francis /* Flash programming is done via the SCU, so pretend it is ROM. */ 103616260006SPhilippe Mathieu-Daudé memory_region_init_rom(flash, NULL, "stellaris.flash", flash_size, 1037f8ed85acSMarkus Armbruster &error_fatal); 1038fe6ac447SAlistair Francis memory_region_add_subregion(system_memory, 0, flash); 1039fe6ac447SAlistair Francis 104098a99ce0SPeter Maydell memory_region_init_ram(sram, NULL, "stellaris.sram", sram_size, 1041f8ed85acSMarkus Armbruster &error_fatal); 1042fe6ac447SAlistair Francis memory_region_add_subregion(system_memory, 0x20000000, sram); 1043fe6ac447SAlistair Francis 1044a861b3e9SPeter Maydell /* 1045a861b3e9SPeter Maydell * Create the system-registers object early, because we will 1046a861b3e9SPeter Maydell * need its sysclk output. 1047a861b3e9SPeter Maydell */ 1048a861b3e9SPeter Maydell ssys_dev = qdev_new(TYPE_STELLARIS_SYS); 1049a861b3e9SPeter Maydell /* Most devices come preprogrammed with a MAC address in the user data. */ 1050a861b3e9SPeter Maydell macaddr = nd_table[0].macaddr.a; 1051a861b3e9SPeter Maydell qdev_prop_set_uint32(ssys_dev, "user0", 1052a861b3e9SPeter Maydell macaddr[0] | (macaddr[1] << 8) | (macaddr[2] << 16)); 1053a861b3e9SPeter Maydell qdev_prop_set_uint32(ssys_dev, "user1", 1054a861b3e9SPeter Maydell macaddr[3] | (macaddr[4] << 8) | (macaddr[5] << 16)); 1055a861b3e9SPeter Maydell qdev_prop_set_uint32(ssys_dev, "did0", board->did0); 1056a861b3e9SPeter Maydell qdev_prop_set_uint32(ssys_dev, "did1", board->did1); 1057a861b3e9SPeter Maydell qdev_prop_set_uint32(ssys_dev, "dc0", board->dc0); 1058a861b3e9SPeter Maydell qdev_prop_set_uint32(ssys_dev, "dc1", board->dc1); 1059a861b3e9SPeter Maydell qdev_prop_set_uint32(ssys_dev, "dc2", board->dc2); 1060a861b3e9SPeter Maydell qdev_prop_set_uint32(ssys_dev, "dc3", board->dc3); 1061a861b3e9SPeter Maydell qdev_prop_set_uint32(ssys_dev, "dc4", board->dc4); 1062a861b3e9SPeter Maydell sysbus_realize_and_unref(SYS_BUS_DEVICE(ssys_dev), &error_fatal); 1063a861b3e9SPeter Maydell 10643e80f690SMarkus Armbruster nvic = qdev_new(TYPE_ARMV7M); 1065f04d4465SPeter Maydell qdev_prop_set_uint32(nvic, "num-irq", NUM_IRQ_LINES); 1066f04d4465SPeter Maydell qdev_prop_set_string(nvic, "cpu-type", ms->cpu_type); 1067a1c5a062SStefan Hajnoczi qdev_prop_set_bit(nvic, "enable-bitband", true); 10688ecda75fSPeter Maydell qdev_connect_clock_in(nvic, "cpuclk", 10698ecda75fSPeter Maydell qdev_get_clock_out(ssys_dev, "SYSCLK")); 10708ecda75fSPeter Maydell /* This SoC does not connect the systick reference clock */ 10715325cc34SMarkus Armbruster object_property_set_link(OBJECT(nvic), "memory", 10725325cc34SMarkus Armbruster OBJECT(get_system_memory()), &error_abort); 1073f04d4465SPeter Maydell /* This will exit with an error if the user passed us a bad cpu_type */ 10743c6ef471SMarkus Armbruster sysbus_realize_and_unref(SYS_BUS_DEVICE(nvic), &error_fatal); 107553018216SPaolo Bonzini 1076a861b3e9SPeter Maydell /* Now we can wire up the IRQ and MMIO of the system registers */ 1077a861b3e9SPeter Maydell sysbus_mmio_map(SYS_BUS_DEVICE(ssys_dev), 0, 0x400fe000); 1078a861b3e9SPeter Maydell sysbus_connect_irq(SYS_BUS_DEVICE(ssys_dev), 0, qdev_get_gpio_in(nvic, 28)); 1079a861b3e9SPeter Maydell 108053018216SPaolo Bonzini if (board->dc1 & (1 << 16)) { 10817df7f67aSAndreas Färber dev = sysbus_create_varargs(TYPE_STELLARIS_ADC, 0x40038000, 108220c59c38SMichael Davidsaver qdev_get_gpio_in(nvic, 14), 108320c59c38SMichael Davidsaver qdev_get_gpio_in(nvic, 15), 108420c59c38SMichael Davidsaver qdev_get_gpio_in(nvic, 16), 108520c59c38SMichael Davidsaver qdev_get_gpio_in(nvic, 17), 108620c59c38SMichael Davidsaver NULL); 108753018216SPaolo Bonzini adc = qdev_get_gpio_in(dev, 0); 108853018216SPaolo Bonzini } else { 108953018216SPaolo Bonzini adc = NULL; 109053018216SPaolo Bonzini } 109153018216SPaolo Bonzini for (i = 0; i < 4; i++) { 109253018216SPaolo Bonzini if (board->dc2 & (0x10000 << i)) { 10938ef1d394SAndreas Färber dev = sysbus_create_simple(TYPE_STELLARIS_GPTM, 109453018216SPaolo Bonzini 0x40030000 + i * 0x1000, 109520c59c38SMichael Davidsaver qdev_get_gpio_in(nvic, timer_irq[i])); 109653018216SPaolo Bonzini /* TODO: This is incorrect, but we get away with it because 109753018216SPaolo Bonzini the ADC output is only ever pulsed. */ 109853018216SPaolo Bonzini qdev_connect_gpio_out(dev, 0, adc); 109953018216SPaolo Bonzini } 110053018216SPaolo Bonzini } 110153018216SPaolo Bonzini 1102566528f8SMichel Heily if (board->dc1 & (1 << 3)) { /* watchdog present */ 11033e80f690SMarkus Armbruster dev = qdev_new(TYPE_LUMINARY_WATCHDOG); 1104566528f8SMichel Heily 11051e31d8eeSPeter Maydell qdev_connect_clock_in(dev, "WDOGCLK", 11061e31d8eeSPeter Maydell qdev_get_clock_out(ssys_dev, "SYSCLK")); 1107566528f8SMichel Heily 11083c6ef471SMarkus Armbruster sysbus_realize_and_unref(SYS_BUS_DEVICE(dev), &error_fatal); 1109566528f8SMichel Heily sysbus_mmio_map(SYS_BUS_DEVICE(dev), 1110566528f8SMichel Heily 0, 1111566528f8SMichel Heily 0x40000000u); 1112566528f8SMichel Heily sysbus_connect_irq(SYS_BUS_DEVICE(dev), 1113566528f8SMichel Heily 0, 1114566528f8SMichel Heily qdev_get_gpio_in(nvic, 18)); 1115566528f8SMichel Heily } 1116566528f8SMichel Heily 1117566528f8SMichel Heily 111853018216SPaolo Bonzini for (i = 0; i < 7; i++) { 111953018216SPaolo Bonzini if (board->dc4 & (1 << i)) { 112053018216SPaolo Bonzini gpio_dev[i] = sysbus_create_simple("pl061_luminary", gpio_addr[i], 112120c59c38SMichael Davidsaver qdev_get_gpio_in(nvic, 112220c59c38SMichael Davidsaver gpio_irq[i])); 112353018216SPaolo Bonzini for (j = 0; j < 8; j++) { 112453018216SPaolo Bonzini gpio_in[i][j] = qdev_get_gpio_in(gpio_dev[i], j); 112553018216SPaolo Bonzini gpio_out[i][j] = NULL; 112653018216SPaolo Bonzini } 112753018216SPaolo Bonzini } 112853018216SPaolo Bonzini } 112953018216SPaolo Bonzini 113053018216SPaolo Bonzini if (board->dc2 & (1 << 12)) { 113120c59c38SMichael Davidsaver dev = sysbus_create_simple(TYPE_STELLARIS_I2C, 0x40020000, 113220c59c38SMichael Davidsaver qdev_get_gpio_in(nvic, 8)); 1133a5c82852SAndreas Färber i2c = (I2CBus *)qdev_get_child_bus(dev, "i2c"); 113453018216SPaolo Bonzini if (board->peripherals & BP_OLED_I2C) { 11351373b15bSPhilippe Mathieu-Daudé i2c_slave_create_simple(i2c, "ssd0303", 0x3d); 113653018216SPaolo Bonzini } 113753018216SPaolo Bonzini } 113853018216SPaolo Bonzini 113953018216SPaolo Bonzini for (i = 0; i < 4; i++) { 114053018216SPaolo Bonzini if (board->dc2 & (1 << i)) { 1141f0d1d2c1Sxiaoqiang zhao pl011_luminary_create(0x4000c000 + i * 0x1000, 1142f0d1d2c1Sxiaoqiang zhao qdev_get_gpio_in(nvic, uart_irq[i]), 11439bca0edbSPeter Maydell serial_hd(i)); 114453018216SPaolo Bonzini } 114553018216SPaolo Bonzini } 114653018216SPaolo Bonzini if (board->dc2 & (1 << 4)) { 114720c59c38SMichael Davidsaver dev = sysbus_create_simple("pl022", 0x40008000, 114820c59c38SMichael Davidsaver qdev_get_gpio_in(nvic, 7)); 114953018216SPaolo Bonzini if (board->peripherals & BP_OLED_SSI) { 115053018216SPaolo Bonzini void *bus; 115153018216SPaolo Bonzini DeviceState *sddev; 115253018216SPaolo Bonzini DeviceState *ssddev; 115353018216SPaolo Bonzini 11545092e014SPeter Maydell /* 11555092e014SPeter Maydell * Some boards have both an OLED controller and SD card connected to 115653018216SPaolo Bonzini * the same SSI port, with the SD card chip select connected to a 115753018216SPaolo Bonzini * GPIO pin. Technically the OLED chip select is connected to the 115853018216SPaolo Bonzini * SSI Fss pin. We do not bother emulating that as both devices 115953018216SPaolo Bonzini * should never be selected simultaneously, and our OLED controller 116053018216SPaolo Bonzini * ignores stray 0xff commands that occur when deselecting the SD 116153018216SPaolo Bonzini * card. 11625092e014SPeter Maydell * 11635092e014SPeter Maydell * The h/w wiring is: 11645092e014SPeter Maydell * - GPIO pin D0 is wired to the active-low SD card chip select 11655092e014SPeter Maydell * - GPIO pin A3 is wired to the active-low OLED chip select 11665092e014SPeter Maydell * - The SoC wiring of the PL061 "auxiliary function" for A3 is 11675092e014SPeter Maydell * SSI0Fss ("frame signal"), which is an output from the SoC's 11685092e014SPeter Maydell * SSI controller. The SSI controller takes SSI0Fss low when it 11695092e014SPeter Maydell * transmits a frame, so it can work as a chip-select signal. 11705092e014SPeter Maydell * - GPIO A4 is aux-function SSI0Rx, and wired to the SD card Tx 11715092e014SPeter Maydell * (the OLED never sends data to the CPU, so no wiring needed) 11725092e014SPeter Maydell * - GPIO A5 is aux-function SSI0Tx, and wired to the SD card Rx 11735092e014SPeter Maydell * and the OLED display-data-in 11745092e014SPeter Maydell * - GPIO A2 is aux-function SSI0Clk, wired to SD card and OLED 11755092e014SPeter Maydell * serial-clock input 11765092e014SPeter Maydell * So a guest that wants to use the OLED can configure the PL061 11775092e014SPeter Maydell * to make pins A2, A3, A5 aux-function, so they are connected 11785092e014SPeter Maydell * directly to the SSI controller. When the SSI controller sends 11795092e014SPeter Maydell * data it asserts SSI0Fss which selects the OLED. 11805092e014SPeter Maydell * A guest that wants to use the SD card configures A2, A4 and A5 11815092e014SPeter Maydell * as aux-function, but leaves A3 as a software-controlled GPIO 11825092e014SPeter Maydell * line. It asserts the SD card chip-select by using the PL061 11835092e014SPeter Maydell * to control pin D0, and lets the SSI controller handle Clk, Tx 11845092e014SPeter Maydell * and Rx. (The SSI controller asserts Fss during tx cycles as 11855092e014SPeter Maydell * usual, but because A3 is not set to aux-function this is not 11865092e014SPeter Maydell * forwarded to the OLED, and so the OLED stays unselected.) 11875092e014SPeter Maydell * 11885092e014SPeter Maydell * The QEMU implementation instead is: 11895092e014SPeter Maydell * - GPIO pin D0 is wired to the active-low SD card chip select, 11905092e014SPeter Maydell * and also to the OLED chip-select which is implemented 11915092e014SPeter Maydell * as *active-high* 11925092e014SPeter Maydell * - SSI controller signals go to the devices regardless of 11935092e014SPeter Maydell * whether the guest programs A2, A4, A5 as aux-function or not 11945092e014SPeter Maydell * 11955092e014SPeter Maydell * The problem with this implementation is if the guest doesn't 11965092e014SPeter Maydell * care about the SD card and only uses the OLED. In that case it 11975092e014SPeter Maydell * may choose never to do anything with D0 (leaving it in its 11985092e014SPeter Maydell * default floating state, which reliably leaves the card disabled 11995092e014SPeter Maydell * because an SD card has a pullup on CS within the card itself), 12005092e014SPeter Maydell * and only set up A2, A3, A5. This for us would mean the OLED 12015092e014SPeter Maydell * never gets the chip-select assert it needs. We work around 12025092e014SPeter Maydell * this with a manual raise of D0 here (despite board creation 12035092e014SPeter Maydell * code being the wrong place to raise IRQ lines) to put the OLED 12045092e014SPeter Maydell * into an initially selected state. 12055092e014SPeter Maydell * 12065092e014SPeter Maydell * In theory the right way to model this would be: 12075092e014SPeter Maydell * - Implement aux-function support in the PL061, with an 12085092e014SPeter Maydell * extra set of AFIN and AFOUT GPIO lines (set up so that 12095092e014SPeter Maydell * if a GPIO line is in auxfn mode the main GPIO in and out 12105092e014SPeter Maydell * track the AFIN and AFOUT lines) 12115092e014SPeter Maydell * - Wire the AFOUT for D0 up to either a line from the 12125092e014SPeter Maydell * SSI controller that's pulled low around every transmit, 12135092e014SPeter Maydell * or at least to an always-0 line here on the board 12145092e014SPeter Maydell * - Make the ssd0323 OLED controller chipselect active-low 121553018216SPaolo Bonzini */ 121653018216SPaolo Bonzini bus = qdev_get_child_bus(dev, "ssi"); 121753018216SPaolo Bonzini 1218ec7e429bSPhilippe Mathieu-Daudé sddev = ssi_create_peripheral(bus, "ssi-sd"); 1219ec7e429bSPhilippe Mathieu-Daudé ssddev = ssi_create_peripheral(bus, "ssd0323"); 1220de77914eSPeter Crosthwaite gpio_out[GPIO_D][0] = qemu_irq_split( 1221de77914eSPeter Crosthwaite qdev_get_gpio_in_named(sddev, SSI_GPIO_CS, 0), 1222de77914eSPeter Crosthwaite qdev_get_gpio_in_named(ssddev, SSI_GPIO_CS, 0)); 1223de77914eSPeter Crosthwaite gpio_out[GPIO_C][7] = qdev_get_gpio_in(ssddev, 0); 122453018216SPaolo Bonzini 122553018216SPaolo Bonzini /* Make sure the select pin is high. */ 122653018216SPaolo Bonzini qemu_irq_raise(gpio_out[GPIO_D][0]); 122753018216SPaolo Bonzini } 122853018216SPaolo Bonzini } 122953018216SPaolo Bonzini if (board->dc4 & (1 << 28)) { 123053018216SPaolo Bonzini DeviceState *enet; 123153018216SPaolo Bonzini 123253018216SPaolo Bonzini qemu_check_nic_model(&nd_table[0], "stellaris"); 123353018216SPaolo Bonzini 12343e80f690SMarkus Armbruster enet = qdev_new("stellaris_enet"); 123553018216SPaolo Bonzini qdev_set_nic_properties(enet, &nd_table[0]); 12363c6ef471SMarkus Armbruster sysbus_realize_and_unref(SYS_BUS_DEVICE(enet), &error_fatal); 123753018216SPaolo Bonzini sysbus_mmio_map(SYS_BUS_DEVICE(enet), 0, 0x40048000); 123820c59c38SMichael Davidsaver sysbus_connect_irq(SYS_BUS_DEVICE(enet), 0, qdev_get_gpio_in(nvic, 42)); 123953018216SPaolo Bonzini } 124053018216SPaolo Bonzini if (board->peripherals & BP_GAMEPAD) { 124153018216SPaolo Bonzini qemu_irq gpad_irq[5]; 124253018216SPaolo Bonzini static const int gpad_keycode[5] = { 0xc8, 0xd0, 0xcb, 0xcd, 0x1d }; 124353018216SPaolo Bonzini 124453018216SPaolo Bonzini gpad_irq[0] = qemu_irq_invert(gpio_in[GPIO_E][0]); /* up */ 124553018216SPaolo Bonzini gpad_irq[1] = qemu_irq_invert(gpio_in[GPIO_E][1]); /* down */ 124653018216SPaolo Bonzini gpad_irq[2] = qemu_irq_invert(gpio_in[GPIO_E][2]); /* left */ 124753018216SPaolo Bonzini gpad_irq[3] = qemu_irq_invert(gpio_in[GPIO_E][3]); /* right */ 124853018216SPaolo Bonzini gpad_irq[4] = qemu_irq_invert(gpio_in[GPIO_F][1]); /* select */ 124953018216SPaolo Bonzini 125053018216SPaolo Bonzini stellaris_gamepad_init(5, gpad_irq, gpad_keycode); 125153018216SPaolo Bonzini } 125253018216SPaolo Bonzini for (i = 0; i < 7; i++) { 125353018216SPaolo Bonzini if (board->dc4 & (1 << i)) { 125453018216SPaolo Bonzini for (j = 0; j < 8; j++) { 125553018216SPaolo Bonzini if (gpio_out[i][j]) { 125653018216SPaolo Bonzini qdev_connect_gpio_out(gpio_dev[i], j, gpio_out[i][j]); 125753018216SPaolo Bonzini } 125853018216SPaolo Bonzini } 125953018216SPaolo Bonzini } 126053018216SPaolo Bonzini } 1261aecfbbc9SPeter Maydell 1262aecfbbc9SPeter Maydell /* Add dummy regions for the devices we don't implement yet, 1263aecfbbc9SPeter Maydell * so guest accesses don't cause unlogged crashes. 1264aecfbbc9SPeter Maydell */ 1265aecfbbc9SPeter Maydell create_unimplemented_device("i2c-0", 0x40002000, 0x1000); 1266aecfbbc9SPeter Maydell create_unimplemented_device("i2c-2", 0x40021000, 0x1000); 1267aecfbbc9SPeter Maydell create_unimplemented_device("PWM", 0x40028000, 0x1000); 1268aecfbbc9SPeter Maydell create_unimplemented_device("QEI-0", 0x4002c000, 0x1000); 1269aecfbbc9SPeter Maydell create_unimplemented_device("QEI-1", 0x4002d000, 0x1000); 1270aecfbbc9SPeter Maydell create_unimplemented_device("analogue-comparator", 0x4003c000, 0x1000); 1271aecfbbc9SPeter Maydell create_unimplemented_device("hibernation", 0x400fc000, 0x1000); 1272aecfbbc9SPeter Maydell create_unimplemented_device("flash-control", 0x400fd000, 0x1000); 1273f04d4465SPeter Maydell 1274f04d4465SPeter Maydell armv7m_load_kernel(ARM_CPU(first_cpu), ms->kernel_filename, flash_size); 127553018216SPaolo Bonzini } 127653018216SPaolo Bonzini 127753018216SPaolo Bonzini /* FIXME: Figure out how to generate these from stellaris_boards. */ 12783ef96221SMarcel Apfelbaum static void lm3s811evb_init(MachineState *machine) 127953018216SPaolo Bonzini { 1280ba1ba5ccSIgor Mammedov stellaris_init(machine, &stellaris_boards[0]); 128153018216SPaolo Bonzini } 128253018216SPaolo Bonzini 12833ef96221SMarcel Apfelbaum static void lm3s6965evb_init(MachineState *machine) 128453018216SPaolo Bonzini { 1285ba1ba5ccSIgor Mammedov stellaris_init(machine, &stellaris_boards[1]); 128653018216SPaolo Bonzini } 128753018216SPaolo Bonzini 12888a661aeaSAndreas Färber static void lm3s811evb_class_init(ObjectClass *oc, void *data) 128953018216SPaolo Bonzini { 12908a661aeaSAndreas Färber MachineClass *mc = MACHINE_CLASS(oc); 12918a661aeaSAndreas Färber 1292fd8f71b9SPhilippe Mathieu-Daudé mc->desc = "Stellaris LM3S811EVB (Cortex-M3)"; 1293e264d29dSEduardo Habkost mc->init = lm3s811evb_init; 12944672cbd7SPeter Maydell mc->ignore_memory_transaction_failures = true; 1295ba1ba5ccSIgor Mammedov mc->default_cpu_type = ARM_CPU_TYPE_NAME("cortex-m3"); 129653018216SPaolo Bonzini } 129753018216SPaolo Bonzini 12988a661aeaSAndreas Färber static const TypeInfo lm3s811evb_type = { 12998a661aeaSAndreas Färber .name = MACHINE_TYPE_NAME("lm3s811evb"), 13008a661aeaSAndreas Färber .parent = TYPE_MACHINE, 13018a661aeaSAndreas Färber .class_init = lm3s811evb_class_init, 13028a661aeaSAndreas Färber }; 1303e264d29dSEduardo Habkost 13048a661aeaSAndreas Färber static void lm3s6965evb_class_init(ObjectClass *oc, void *data) 1305e264d29dSEduardo Habkost { 13068a661aeaSAndreas Färber MachineClass *mc = MACHINE_CLASS(oc); 13078a661aeaSAndreas Färber 1308fd8f71b9SPhilippe Mathieu-Daudé mc->desc = "Stellaris LM3S6965EVB (Cortex-M3)"; 1309e264d29dSEduardo Habkost mc->init = lm3s6965evb_init; 13104672cbd7SPeter Maydell mc->ignore_memory_transaction_failures = true; 1311ba1ba5ccSIgor Mammedov mc->default_cpu_type = ARM_CPU_TYPE_NAME("cortex-m3"); 1312e264d29dSEduardo Habkost } 1313e264d29dSEduardo Habkost 13148a661aeaSAndreas Färber static const TypeInfo lm3s6965evb_type = { 13158a661aeaSAndreas Färber .name = MACHINE_TYPE_NAME("lm3s6965evb"), 13168a661aeaSAndreas Färber .parent = TYPE_MACHINE, 13178a661aeaSAndreas Färber .class_init = lm3s6965evb_class_init, 13188a661aeaSAndreas Färber }; 13198a661aeaSAndreas Färber 13208a661aeaSAndreas Färber static void stellaris_machine_init(void) 13218a661aeaSAndreas Färber { 13228a661aeaSAndreas Färber type_register_static(&lm3s811evb_type); 13238a661aeaSAndreas Färber type_register_static(&lm3s6965evb_type); 13248a661aeaSAndreas Färber } 13258a661aeaSAndreas Färber 13260e6aac87SEduardo Habkost type_init(stellaris_machine_init) 132753018216SPaolo Bonzini 132853018216SPaolo Bonzini static void stellaris_i2c_class_init(ObjectClass *klass, void *data) 132953018216SPaolo Bonzini { 133015c4fff5Sxiaoqiang.zhao DeviceClass *dc = DEVICE_CLASS(klass); 133153018216SPaolo Bonzini 133215c4fff5Sxiaoqiang.zhao dc->vmsd = &vmstate_stellaris_i2c; 133353018216SPaolo Bonzini } 133453018216SPaolo Bonzini 133553018216SPaolo Bonzini static const TypeInfo stellaris_i2c_info = { 1336d94a4015SAndreas Färber .name = TYPE_STELLARIS_I2C, 133753018216SPaolo Bonzini .parent = TYPE_SYS_BUS_DEVICE, 133853018216SPaolo Bonzini .instance_size = sizeof(stellaris_i2c_state), 133915c4fff5Sxiaoqiang.zhao .instance_init = stellaris_i2c_init, 134053018216SPaolo Bonzini .class_init = stellaris_i2c_class_init, 134153018216SPaolo Bonzini }; 134253018216SPaolo Bonzini 134353018216SPaolo Bonzini static void stellaris_adc_class_init(ObjectClass *klass, void *data) 134453018216SPaolo Bonzini { 134515c4fff5Sxiaoqiang.zhao DeviceClass *dc = DEVICE_CLASS(klass); 134653018216SPaolo Bonzini 134715c4fff5Sxiaoqiang.zhao dc->vmsd = &vmstate_stellaris_adc; 134853018216SPaolo Bonzini } 134953018216SPaolo Bonzini 135053018216SPaolo Bonzini static const TypeInfo stellaris_adc_info = { 13517df7f67aSAndreas Färber .name = TYPE_STELLARIS_ADC, 135253018216SPaolo Bonzini .parent = TYPE_SYS_BUS_DEVICE, 135353018216SPaolo Bonzini .instance_size = sizeof(stellaris_adc_state), 135415c4fff5Sxiaoqiang.zhao .instance_init = stellaris_adc_init, 135553018216SPaolo Bonzini .class_init = stellaris_adc_class_init, 135653018216SPaolo Bonzini }; 135753018216SPaolo Bonzini 13584bebb9adSPeter Maydell static void stellaris_sys_class_init(ObjectClass *klass, void *data) 13594bebb9adSPeter Maydell { 13604bebb9adSPeter Maydell DeviceClass *dc = DEVICE_CLASS(klass); 13614bebb9adSPeter Maydell ResettableClass *rc = RESETTABLE_CLASS(klass); 13624bebb9adSPeter Maydell 13634bebb9adSPeter Maydell dc->vmsd = &vmstate_stellaris_sys; 13644bebb9adSPeter Maydell rc->phases.enter = stellaris_sys_reset_enter; 13654bebb9adSPeter Maydell rc->phases.hold = stellaris_sys_reset_hold; 13664bebb9adSPeter Maydell rc->phases.exit = stellaris_sys_reset_exit; 13674bebb9adSPeter Maydell device_class_set_props(dc, stellaris_sys_properties); 13684bebb9adSPeter Maydell } 13694bebb9adSPeter Maydell 13704bebb9adSPeter Maydell static const TypeInfo stellaris_sys_info = { 13714bebb9adSPeter Maydell .name = TYPE_STELLARIS_SYS, 13724bebb9adSPeter Maydell .parent = TYPE_SYS_BUS_DEVICE, 13734bebb9adSPeter Maydell .instance_size = sizeof(ssys_state), 13744bebb9adSPeter Maydell .instance_init = stellaris_sys_instance_init, 13754bebb9adSPeter Maydell .class_init = stellaris_sys_class_init, 13764bebb9adSPeter Maydell }; 13774bebb9adSPeter Maydell 137853018216SPaolo Bonzini static void stellaris_register_types(void) 137953018216SPaolo Bonzini { 138053018216SPaolo Bonzini type_register_static(&stellaris_i2c_info); 138153018216SPaolo Bonzini type_register_static(&stellaris_adc_info); 13824bebb9adSPeter Maydell type_register_static(&stellaris_sys_info); 138353018216SPaolo Bonzini } 138453018216SPaolo Bonzini 138553018216SPaolo Bonzini type_init(stellaris_register_types) 1386