1 /* 2 * Luminary Micro Stellaris peripherals 3 * 4 * Copyright (c) 2006 CodeSourcery. 5 * Written by Paul Brook 6 * 7 * This code is licensed under the GPL. 8 */ 9 10 #include "qemu/osdep.h" 11 #include "hw/sysbus.h" 12 #include "hw/ssi/ssi.h" 13 #include "hw/arm/arm.h" 14 #include "hw/devices.h" 15 #include "qemu/timer.h" 16 #include "hw/i2c/i2c.h" 17 #include "net/net.h" 18 #include "hw/boards.h" 19 #include "exec/address-spaces.h" 20 #include "sysemu/sysemu.h" 21 22 #define GPIO_A 0 23 #define GPIO_B 1 24 #define GPIO_C 2 25 #define GPIO_D 3 26 #define GPIO_E 4 27 #define GPIO_F 5 28 #define GPIO_G 6 29 30 #define BP_OLED_I2C 0x01 31 #define BP_OLED_SSI 0x02 32 #define BP_GAMEPAD 0x04 33 34 #define NUM_IRQ_LINES 64 35 36 typedef const struct { 37 const char *name; 38 uint32_t did0; 39 uint32_t did1; 40 uint32_t dc0; 41 uint32_t dc1; 42 uint32_t dc2; 43 uint32_t dc3; 44 uint32_t dc4; 45 uint32_t peripherals; 46 } stellaris_board_info; 47 48 /* General purpose timer module. */ 49 50 #define TYPE_STELLARIS_GPTM "stellaris-gptm" 51 #define STELLARIS_GPTM(obj) \ 52 OBJECT_CHECK(gptm_state, (obj), TYPE_STELLARIS_GPTM) 53 54 typedef struct gptm_state { 55 SysBusDevice parent_obj; 56 57 MemoryRegion iomem; 58 uint32_t config; 59 uint32_t mode[2]; 60 uint32_t control; 61 uint32_t state; 62 uint32_t mask; 63 uint32_t load[2]; 64 uint32_t match[2]; 65 uint32_t prescale[2]; 66 uint32_t match_prescale[2]; 67 uint32_t rtc; 68 int64_t tick[2]; 69 struct gptm_state *opaque[2]; 70 QEMUTimer *timer[2]; 71 /* The timers have an alternate output used to trigger the ADC. */ 72 qemu_irq trigger; 73 qemu_irq irq; 74 } gptm_state; 75 76 static void gptm_update_irq(gptm_state *s) 77 { 78 int level; 79 level = (s->state & s->mask) != 0; 80 qemu_set_irq(s->irq, level); 81 } 82 83 static void gptm_stop(gptm_state *s, int n) 84 { 85 timer_del(s->timer[n]); 86 } 87 88 static void gptm_reload(gptm_state *s, int n, int reset) 89 { 90 int64_t tick; 91 if (reset) 92 tick = qemu_clock_get_ns(QEMU_CLOCK_VIRTUAL); 93 else 94 tick = s->tick[n]; 95 96 if (s->config == 0) { 97 /* 32-bit CountDown. */ 98 uint32_t count; 99 count = s->load[0] | (s->load[1] << 16); 100 tick += (int64_t)count * system_clock_scale; 101 } else if (s->config == 1) { 102 /* 32-bit RTC. 1Hz tick. */ 103 tick += get_ticks_per_sec(); 104 } else if (s->mode[n] == 0xa) { 105 /* PWM mode. Not implemented. */ 106 } else { 107 hw_error("TODO: 16-bit timer mode 0x%x\n", s->mode[n]); 108 } 109 s->tick[n] = tick; 110 timer_mod(s->timer[n], tick); 111 } 112 113 static void gptm_tick(void *opaque) 114 { 115 gptm_state **p = (gptm_state **)opaque; 116 gptm_state *s; 117 int n; 118 119 s = *p; 120 n = p - s->opaque; 121 if (s->config == 0) { 122 s->state |= 1; 123 if ((s->control & 0x20)) { 124 /* Output trigger. */ 125 qemu_irq_pulse(s->trigger); 126 } 127 if (s->mode[0] & 1) { 128 /* One-shot. */ 129 s->control &= ~1; 130 } else { 131 /* Periodic. */ 132 gptm_reload(s, 0, 0); 133 } 134 } else if (s->config == 1) { 135 /* RTC. */ 136 uint32_t match; 137 s->rtc++; 138 match = s->match[0] | (s->match[1] << 16); 139 if (s->rtc > match) 140 s->rtc = 0; 141 if (s->rtc == 0) { 142 s->state |= 8; 143 } 144 gptm_reload(s, 0, 0); 145 } else if (s->mode[n] == 0xa) { 146 /* PWM mode. Not implemented. */ 147 } else { 148 hw_error("TODO: 16-bit timer mode 0x%x\n", s->mode[n]); 149 } 150 gptm_update_irq(s); 151 } 152 153 static uint64_t gptm_read(void *opaque, hwaddr offset, 154 unsigned size) 155 { 156 gptm_state *s = (gptm_state *)opaque; 157 158 switch (offset) { 159 case 0x00: /* CFG */ 160 return s->config; 161 case 0x04: /* TAMR */ 162 return s->mode[0]; 163 case 0x08: /* TBMR */ 164 return s->mode[1]; 165 case 0x0c: /* CTL */ 166 return s->control; 167 case 0x18: /* IMR */ 168 return s->mask; 169 case 0x1c: /* RIS */ 170 return s->state; 171 case 0x20: /* MIS */ 172 return s->state & s->mask; 173 case 0x24: /* CR */ 174 return 0; 175 case 0x28: /* TAILR */ 176 return s->load[0] | ((s->config < 4) ? (s->load[1] << 16) : 0); 177 case 0x2c: /* TBILR */ 178 return s->load[1]; 179 case 0x30: /* TAMARCHR */ 180 return s->match[0] | ((s->config < 4) ? (s->match[1] << 16) : 0); 181 case 0x34: /* TBMATCHR */ 182 return s->match[1]; 183 case 0x38: /* TAPR */ 184 return s->prescale[0]; 185 case 0x3c: /* TBPR */ 186 return s->prescale[1]; 187 case 0x40: /* TAPMR */ 188 return s->match_prescale[0]; 189 case 0x44: /* TBPMR */ 190 return s->match_prescale[1]; 191 case 0x48: /* TAR */ 192 if (s->config == 1) { 193 return s->rtc; 194 } 195 qemu_log_mask(LOG_UNIMP, 196 "GPTM: read of TAR but timer read not supported"); 197 return 0; 198 case 0x4c: /* TBR */ 199 qemu_log_mask(LOG_UNIMP, 200 "GPTM: read of TBR but timer read not supported"); 201 return 0; 202 default: 203 qemu_log_mask(LOG_GUEST_ERROR, 204 "GPTM: read at bad offset 0x%x\n", (int)offset); 205 return 0; 206 } 207 } 208 209 static void gptm_write(void *opaque, hwaddr offset, 210 uint64_t value, unsigned size) 211 { 212 gptm_state *s = (gptm_state *)opaque; 213 uint32_t oldval; 214 215 /* The timers should be disabled before changing the configuration. 216 We take advantage of this and defer everything until the timer 217 is enabled. */ 218 switch (offset) { 219 case 0x00: /* CFG */ 220 s->config = value; 221 break; 222 case 0x04: /* TAMR */ 223 s->mode[0] = value; 224 break; 225 case 0x08: /* TBMR */ 226 s->mode[1] = value; 227 break; 228 case 0x0c: /* CTL */ 229 oldval = s->control; 230 s->control = value; 231 /* TODO: Implement pause. */ 232 if ((oldval ^ value) & 1) { 233 if (value & 1) { 234 gptm_reload(s, 0, 1); 235 } else { 236 gptm_stop(s, 0); 237 } 238 } 239 if (((oldval ^ value) & 0x100) && s->config >= 4) { 240 if (value & 0x100) { 241 gptm_reload(s, 1, 1); 242 } else { 243 gptm_stop(s, 1); 244 } 245 } 246 break; 247 case 0x18: /* IMR */ 248 s->mask = value & 0x77; 249 gptm_update_irq(s); 250 break; 251 case 0x24: /* CR */ 252 s->state &= ~value; 253 break; 254 case 0x28: /* TAILR */ 255 s->load[0] = value & 0xffff; 256 if (s->config < 4) { 257 s->load[1] = value >> 16; 258 } 259 break; 260 case 0x2c: /* TBILR */ 261 s->load[1] = value & 0xffff; 262 break; 263 case 0x30: /* TAMARCHR */ 264 s->match[0] = value & 0xffff; 265 if (s->config < 4) { 266 s->match[1] = value >> 16; 267 } 268 break; 269 case 0x34: /* TBMATCHR */ 270 s->match[1] = value >> 16; 271 break; 272 case 0x38: /* TAPR */ 273 s->prescale[0] = value; 274 break; 275 case 0x3c: /* TBPR */ 276 s->prescale[1] = value; 277 break; 278 case 0x40: /* TAPMR */ 279 s->match_prescale[0] = value; 280 break; 281 case 0x44: /* TBPMR */ 282 s->match_prescale[0] = value; 283 break; 284 default: 285 hw_error("gptm_write: Bad offset 0x%x\n", (int)offset); 286 } 287 gptm_update_irq(s); 288 } 289 290 static const MemoryRegionOps gptm_ops = { 291 .read = gptm_read, 292 .write = gptm_write, 293 .endianness = DEVICE_NATIVE_ENDIAN, 294 }; 295 296 static const VMStateDescription vmstate_stellaris_gptm = { 297 .name = "stellaris_gptm", 298 .version_id = 1, 299 .minimum_version_id = 1, 300 .fields = (VMStateField[]) { 301 VMSTATE_UINT32(config, gptm_state), 302 VMSTATE_UINT32_ARRAY(mode, gptm_state, 2), 303 VMSTATE_UINT32(control, gptm_state), 304 VMSTATE_UINT32(state, gptm_state), 305 VMSTATE_UINT32(mask, gptm_state), 306 VMSTATE_UNUSED(8), 307 VMSTATE_UINT32_ARRAY(load, gptm_state, 2), 308 VMSTATE_UINT32_ARRAY(match, gptm_state, 2), 309 VMSTATE_UINT32_ARRAY(prescale, gptm_state, 2), 310 VMSTATE_UINT32_ARRAY(match_prescale, gptm_state, 2), 311 VMSTATE_UINT32(rtc, gptm_state), 312 VMSTATE_INT64_ARRAY(tick, gptm_state, 2), 313 VMSTATE_TIMER_PTR_ARRAY(timer, gptm_state, 2), 314 VMSTATE_END_OF_LIST() 315 } 316 }; 317 318 static int stellaris_gptm_init(SysBusDevice *sbd) 319 { 320 DeviceState *dev = DEVICE(sbd); 321 gptm_state *s = STELLARIS_GPTM(dev); 322 323 sysbus_init_irq(sbd, &s->irq); 324 qdev_init_gpio_out(dev, &s->trigger, 1); 325 326 memory_region_init_io(&s->iomem, OBJECT(s), &gptm_ops, s, 327 "gptm", 0x1000); 328 sysbus_init_mmio(sbd, &s->iomem); 329 330 s->opaque[0] = s->opaque[1] = s; 331 s->timer[0] = timer_new_ns(QEMU_CLOCK_VIRTUAL, gptm_tick, &s->opaque[0]); 332 s->timer[1] = timer_new_ns(QEMU_CLOCK_VIRTUAL, gptm_tick, &s->opaque[1]); 333 vmstate_register(dev, -1, &vmstate_stellaris_gptm, s); 334 return 0; 335 } 336 337 338 /* System controller. */ 339 340 typedef struct { 341 MemoryRegion iomem; 342 uint32_t pborctl; 343 uint32_t ldopctl; 344 uint32_t int_status; 345 uint32_t int_mask; 346 uint32_t resc; 347 uint32_t rcc; 348 uint32_t rcc2; 349 uint32_t rcgc[3]; 350 uint32_t scgc[3]; 351 uint32_t dcgc[3]; 352 uint32_t clkvclr; 353 uint32_t ldoarst; 354 uint32_t user0; 355 uint32_t user1; 356 qemu_irq irq; 357 stellaris_board_info *board; 358 } ssys_state; 359 360 static void ssys_update(ssys_state *s) 361 { 362 qemu_set_irq(s->irq, (s->int_status & s->int_mask) != 0); 363 } 364 365 static uint32_t pllcfg_sandstorm[16] = { 366 0x31c0, /* 1 Mhz */ 367 0x1ae0, /* 1.8432 Mhz */ 368 0x18c0, /* 2 Mhz */ 369 0xd573, /* 2.4576 Mhz */ 370 0x37a6, /* 3.57954 Mhz */ 371 0x1ae2, /* 3.6864 Mhz */ 372 0x0c40, /* 4 Mhz */ 373 0x98bc, /* 4.906 Mhz */ 374 0x935b, /* 4.9152 Mhz */ 375 0x09c0, /* 5 Mhz */ 376 0x4dee, /* 5.12 Mhz */ 377 0x0c41, /* 6 Mhz */ 378 0x75db, /* 6.144 Mhz */ 379 0x1ae6, /* 7.3728 Mhz */ 380 0x0600, /* 8 Mhz */ 381 0x585b /* 8.192 Mhz */ 382 }; 383 384 static uint32_t pllcfg_fury[16] = { 385 0x3200, /* 1 Mhz */ 386 0x1b20, /* 1.8432 Mhz */ 387 0x1900, /* 2 Mhz */ 388 0xf42b, /* 2.4576 Mhz */ 389 0x37e3, /* 3.57954 Mhz */ 390 0x1b21, /* 3.6864 Mhz */ 391 0x0c80, /* 4 Mhz */ 392 0x98ee, /* 4.906 Mhz */ 393 0xd5b4, /* 4.9152 Mhz */ 394 0x0a00, /* 5 Mhz */ 395 0x4e27, /* 5.12 Mhz */ 396 0x1902, /* 6 Mhz */ 397 0xec1c, /* 6.144 Mhz */ 398 0x1b23, /* 7.3728 Mhz */ 399 0x0640, /* 8 Mhz */ 400 0xb11c /* 8.192 Mhz */ 401 }; 402 403 #define DID0_VER_MASK 0x70000000 404 #define DID0_VER_0 0x00000000 405 #define DID0_VER_1 0x10000000 406 407 #define DID0_CLASS_MASK 0x00FF0000 408 #define DID0_CLASS_SANDSTORM 0x00000000 409 #define DID0_CLASS_FURY 0x00010000 410 411 static int ssys_board_class(const ssys_state *s) 412 { 413 uint32_t did0 = s->board->did0; 414 switch (did0 & DID0_VER_MASK) { 415 case DID0_VER_0: 416 return DID0_CLASS_SANDSTORM; 417 case DID0_VER_1: 418 switch (did0 & DID0_CLASS_MASK) { 419 case DID0_CLASS_SANDSTORM: 420 case DID0_CLASS_FURY: 421 return did0 & DID0_CLASS_MASK; 422 } 423 /* for unknown classes, fall through */ 424 default: 425 hw_error("ssys_board_class: Unknown class 0x%08x\n", did0); 426 } 427 } 428 429 static uint64_t ssys_read(void *opaque, hwaddr offset, 430 unsigned size) 431 { 432 ssys_state *s = (ssys_state *)opaque; 433 434 switch (offset) { 435 case 0x000: /* DID0 */ 436 return s->board->did0; 437 case 0x004: /* DID1 */ 438 return s->board->did1; 439 case 0x008: /* DC0 */ 440 return s->board->dc0; 441 case 0x010: /* DC1 */ 442 return s->board->dc1; 443 case 0x014: /* DC2 */ 444 return s->board->dc2; 445 case 0x018: /* DC3 */ 446 return s->board->dc3; 447 case 0x01c: /* DC4 */ 448 return s->board->dc4; 449 case 0x030: /* PBORCTL */ 450 return s->pborctl; 451 case 0x034: /* LDOPCTL */ 452 return s->ldopctl; 453 case 0x040: /* SRCR0 */ 454 return 0; 455 case 0x044: /* SRCR1 */ 456 return 0; 457 case 0x048: /* SRCR2 */ 458 return 0; 459 case 0x050: /* RIS */ 460 return s->int_status; 461 case 0x054: /* IMC */ 462 return s->int_mask; 463 case 0x058: /* MISC */ 464 return s->int_status & s->int_mask; 465 case 0x05c: /* RESC */ 466 return s->resc; 467 case 0x060: /* RCC */ 468 return s->rcc; 469 case 0x064: /* PLLCFG */ 470 { 471 int xtal; 472 xtal = (s->rcc >> 6) & 0xf; 473 switch (ssys_board_class(s)) { 474 case DID0_CLASS_FURY: 475 return pllcfg_fury[xtal]; 476 case DID0_CLASS_SANDSTORM: 477 return pllcfg_sandstorm[xtal]; 478 default: 479 hw_error("ssys_read: Unhandled class for PLLCFG read.\n"); 480 return 0; 481 } 482 } 483 case 0x070: /* RCC2 */ 484 return s->rcc2; 485 case 0x100: /* RCGC0 */ 486 return s->rcgc[0]; 487 case 0x104: /* RCGC1 */ 488 return s->rcgc[1]; 489 case 0x108: /* RCGC2 */ 490 return s->rcgc[2]; 491 case 0x110: /* SCGC0 */ 492 return s->scgc[0]; 493 case 0x114: /* SCGC1 */ 494 return s->scgc[1]; 495 case 0x118: /* SCGC2 */ 496 return s->scgc[2]; 497 case 0x120: /* DCGC0 */ 498 return s->dcgc[0]; 499 case 0x124: /* DCGC1 */ 500 return s->dcgc[1]; 501 case 0x128: /* DCGC2 */ 502 return s->dcgc[2]; 503 case 0x150: /* CLKVCLR */ 504 return s->clkvclr; 505 case 0x160: /* LDOARST */ 506 return s->ldoarst; 507 case 0x1e0: /* USER0 */ 508 return s->user0; 509 case 0x1e4: /* USER1 */ 510 return s->user1; 511 default: 512 hw_error("ssys_read: Bad offset 0x%x\n", (int)offset); 513 return 0; 514 } 515 } 516 517 static bool ssys_use_rcc2(ssys_state *s) 518 { 519 return (s->rcc2 >> 31) & 0x1; 520 } 521 522 /* 523 * Caculate the sys. clock period in ms. 524 */ 525 static void ssys_calculate_system_clock(ssys_state *s) 526 { 527 if (ssys_use_rcc2(s)) { 528 system_clock_scale = 5 * (((s->rcc2 >> 23) & 0x3f) + 1); 529 } else { 530 system_clock_scale = 5 * (((s->rcc >> 23) & 0xf) + 1); 531 } 532 } 533 534 static void ssys_write(void *opaque, hwaddr offset, 535 uint64_t value, unsigned size) 536 { 537 ssys_state *s = (ssys_state *)opaque; 538 539 switch (offset) { 540 case 0x030: /* PBORCTL */ 541 s->pborctl = value & 0xffff; 542 break; 543 case 0x034: /* LDOPCTL */ 544 s->ldopctl = value & 0x1f; 545 break; 546 case 0x040: /* SRCR0 */ 547 case 0x044: /* SRCR1 */ 548 case 0x048: /* SRCR2 */ 549 fprintf(stderr, "Peripheral reset not implemented\n"); 550 break; 551 case 0x054: /* IMC */ 552 s->int_mask = value & 0x7f; 553 break; 554 case 0x058: /* MISC */ 555 s->int_status &= ~value; 556 break; 557 case 0x05c: /* RESC */ 558 s->resc = value & 0x3f; 559 break; 560 case 0x060: /* RCC */ 561 if ((s->rcc & (1 << 13)) != 0 && (value & (1 << 13)) == 0) { 562 /* PLL enable. */ 563 s->int_status |= (1 << 6); 564 } 565 s->rcc = value; 566 ssys_calculate_system_clock(s); 567 break; 568 case 0x070: /* RCC2 */ 569 if (ssys_board_class(s) == DID0_CLASS_SANDSTORM) { 570 break; 571 } 572 573 if ((s->rcc2 & (1 << 13)) != 0 && (value & (1 << 13)) == 0) { 574 /* PLL enable. */ 575 s->int_status |= (1 << 6); 576 } 577 s->rcc2 = value; 578 ssys_calculate_system_clock(s); 579 break; 580 case 0x100: /* RCGC0 */ 581 s->rcgc[0] = value; 582 break; 583 case 0x104: /* RCGC1 */ 584 s->rcgc[1] = value; 585 break; 586 case 0x108: /* RCGC2 */ 587 s->rcgc[2] = value; 588 break; 589 case 0x110: /* SCGC0 */ 590 s->scgc[0] = value; 591 break; 592 case 0x114: /* SCGC1 */ 593 s->scgc[1] = value; 594 break; 595 case 0x118: /* SCGC2 */ 596 s->scgc[2] = value; 597 break; 598 case 0x120: /* DCGC0 */ 599 s->dcgc[0] = value; 600 break; 601 case 0x124: /* DCGC1 */ 602 s->dcgc[1] = value; 603 break; 604 case 0x128: /* DCGC2 */ 605 s->dcgc[2] = value; 606 break; 607 case 0x150: /* CLKVCLR */ 608 s->clkvclr = value; 609 break; 610 case 0x160: /* LDOARST */ 611 s->ldoarst = value; 612 break; 613 default: 614 hw_error("ssys_write: Bad offset 0x%x\n", (int)offset); 615 } 616 ssys_update(s); 617 } 618 619 static const MemoryRegionOps ssys_ops = { 620 .read = ssys_read, 621 .write = ssys_write, 622 .endianness = DEVICE_NATIVE_ENDIAN, 623 }; 624 625 static void ssys_reset(void *opaque) 626 { 627 ssys_state *s = (ssys_state *)opaque; 628 629 s->pborctl = 0x7ffd; 630 s->rcc = 0x078e3ac0; 631 632 if (ssys_board_class(s) == DID0_CLASS_SANDSTORM) { 633 s->rcc2 = 0; 634 } else { 635 s->rcc2 = 0x07802810; 636 } 637 s->rcgc[0] = 1; 638 s->scgc[0] = 1; 639 s->dcgc[0] = 1; 640 ssys_calculate_system_clock(s); 641 } 642 643 static int stellaris_sys_post_load(void *opaque, int version_id) 644 { 645 ssys_state *s = opaque; 646 647 ssys_calculate_system_clock(s); 648 649 return 0; 650 } 651 652 static const VMStateDescription vmstate_stellaris_sys = { 653 .name = "stellaris_sys", 654 .version_id = 2, 655 .minimum_version_id = 1, 656 .post_load = stellaris_sys_post_load, 657 .fields = (VMStateField[]) { 658 VMSTATE_UINT32(pborctl, ssys_state), 659 VMSTATE_UINT32(ldopctl, ssys_state), 660 VMSTATE_UINT32(int_mask, ssys_state), 661 VMSTATE_UINT32(int_status, ssys_state), 662 VMSTATE_UINT32(resc, ssys_state), 663 VMSTATE_UINT32(rcc, ssys_state), 664 VMSTATE_UINT32_V(rcc2, ssys_state, 2), 665 VMSTATE_UINT32_ARRAY(rcgc, ssys_state, 3), 666 VMSTATE_UINT32_ARRAY(scgc, ssys_state, 3), 667 VMSTATE_UINT32_ARRAY(dcgc, ssys_state, 3), 668 VMSTATE_UINT32(clkvclr, ssys_state), 669 VMSTATE_UINT32(ldoarst, ssys_state), 670 VMSTATE_END_OF_LIST() 671 } 672 }; 673 674 static int stellaris_sys_init(uint32_t base, qemu_irq irq, 675 stellaris_board_info * board, 676 uint8_t *macaddr) 677 { 678 ssys_state *s; 679 680 s = g_new0(ssys_state, 1); 681 s->irq = irq; 682 s->board = board; 683 /* Most devices come preprogrammed with a MAC address in the user data. */ 684 s->user0 = macaddr[0] | (macaddr[1] << 8) | (macaddr[2] << 16); 685 s->user1 = macaddr[3] | (macaddr[4] << 8) | (macaddr[5] << 16); 686 687 memory_region_init_io(&s->iomem, NULL, &ssys_ops, s, "ssys", 0x00001000); 688 memory_region_add_subregion(get_system_memory(), base, &s->iomem); 689 ssys_reset(s); 690 vmstate_register(NULL, -1, &vmstate_stellaris_sys, s); 691 return 0; 692 } 693 694 695 /* I2C controller. */ 696 697 #define TYPE_STELLARIS_I2C "stellaris-i2c" 698 #define STELLARIS_I2C(obj) \ 699 OBJECT_CHECK(stellaris_i2c_state, (obj), TYPE_STELLARIS_I2C) 700 701 typedef struct { 702 SysBusDevice parent_obj; 703 704 I2CBus *bus; 705 qemu_irq irq; 706 MemoryRegion iomem; 707 uint32_t msa; 708 uint32_t mcs; 709 uint32_t mdr; 710 uint32_t mtpr; 711 uint32_t mimr; 712 uint32_t mris; 713 uint32_t mcr; 714 } stellaris_i2c_state; 715 716 #define STELLARIS_I2C_MCS_BUSY 0x01 717 #define STELLARIS_I2C_MCS_ERROR 0x02 718 #define STELLARIS_I2C_MCS_ADRACK 0x04 719 #define STELLARIS_I2C_MCS_DATACK 0x08 720 #define STELLARIS_I2C_MCS_ARBLST 0x10 721 #define STELLARIS_I2C_MCS_IDLE 0x20 722 #define STELLARIS_I2C_MCS_BUSBSY 0x40 723 724 static uint64_t stellaris_i2c_read(void *opaque, hwaddr offset, 725 unsigned size) 726 { 727 stellaris_i2c_state *s = (stellaris_i2c_state *)opaque; 728 729 switch (offset) { 730 case 0x00: /* MSA */ 731 return s->msa; 732 case 0x04: /* MCS */ 733 /* We don't emulate timing, so the controller is never busy. */ 734 return s->mcs | STELLARIS_I2C_MCS_IDLE; 735 case 0x08: /* MDR */ 736 return s->mdr; 737 case 0x0c: /* MTPR */ 738 return s->mtpr; 739 case 0x10: /* MIMR */ 740 return s->mimr; 741 case 0x14: /* MRIS */ 742 return s->mris; 743 case 0x18: /* MMIS */ 744 return s->mris & s->mimr; 745 case 0x20: /* MCR */ 746 return s->mcr; 747 default: 748 hw_error("strllaris_i2c_read: Bad offset 0x%x\n", (int)offset); 749 return 0; 750 } 751 } 752 753 static void stellaris_i2c_update(stellaris_i2c_state *s) 754 { 755 int level; 756 757 level = (s->mris & s->mimr) != 0; 758 qemu_set_irq(s->irq, level); 759 } 760 761 static void stellaris_i2c_write(void *opaque, hwaddr offset, 762 uint64_t value, unsigned size) 763 { 764 stellaris_i2c_state *s = (stellaris_i2c_state *)opaque; 765 766 switch (offset) { 767 case 0x00: /* MSA */ 768 s->msa = value & 0xff; 769 break; 770 case 0x04: /* MCS */ 771 if ((s->mcr & 0x10) == 0) { 772 /* Disabled. Do nothing. */ 773 break; 774 } 775 /* Grab the bus if this is starting a transfer. */ 776 if ((value & 2) && (s->mcs & STELLARIS_I2C_MCS_BUSBSY) == 0) { 777 if (i2c_start_transfer(s->bus, s->msa >> 1, s->msa & 1)) { 778 s->mcs |= STELLARIS_I2C_MCS_ARBLST; 779 } else { 780 s->mcs &= ~STELLARIS_I2C_MCS_ARBLST; 781 s->mcs |= STELLARIS_I2C_MCS_BUSBSY; 782 } 783 } 784 /* If we don't have the bus then indicate an error. */ 785 if (!i2c_bus_busy(s->bus) 786 || (s->mcs & STELLARIS_I2C_MCS_BUSBSY) == 0) { 787 s->mcs |= STELLARIS_I2C_MCS_ERROR; 788 break; 789 } 790 s->mcs &= ~STELLARIS_I2C_MCS_ERROR; 791 if (value & 1) { 792 /* Transfer a byte. */ 793 /* TODO: Handle errors. */ 794 if (s->msa & 1) { 795 /* Recv */ 796 s->mdr = i2c_recv(s->bus) & 0xff; 797 } else { 798 /* Send */ 799 i2c_send(s->bus, s->mdr); 800 } 801 /* Raise an interrupt. */ 802 s->mris |= 1; 803 } 804 if (value & 4) { 805 /* Finish transfer. */ 806 i2c_end_transfer(s->bus); 807 s->mcs &= ~STELLARIS_I2C_MCS_BUSBSY; 808 } 809 break; 810 case 0x08: /* MDR */ 811 s->mdr = value & 0xff; 812 break; 813 case 0x0c: /* MTPR */ 814 s->mtpr = value & 0xff; 815 break; 816 case 0x10: /* MIMR */ 817 s->mimr = 1; 818 break; 819 case 0x1c: /* MICR */ 820 s->mris &= ~value; 821 break; 822 case 0x20: /* MCR */ 823 if (value & 1) 824 hw_error( 825 "stellaris_i2c_write: Loopback not implemented\n"); 826 if (value & 0x20) 827 hw_error( 828 "stellaris_i2c_write: Slave mode not implemented\n"); 829 s->mcr = value & 0x31; 830 break; 831 default: 832 hw_error("stellaris_i2c_write: Bad offset 0x%x\n", 833 (int)offset); 834 } 835 stellaris_i2c_update(s); 836 } 837 838 static void stellaris_i2c_reset(stellaris_i2c_state *s) 839 { 840 if (s->mcs & STELLARIS_I2C_MCS_BUSBSY) 841 i2c_end_transfer(s->bus); 842 843 s->msa = 0; 844 s->mcs = 0; 845 s->mdr = 0; 846 s->mtpr = 1; 847 s->mimr = 0; 848 s->mris = 0; 849 s->mcr = 0; 850 stellaris_i2c_update(s); 851 } 852 853 static const MemoryRegionOps stellaris_i2c_ops = { 854 .read = stellaris_i2c_read, 855 .write = stellaris_i2c_write, 856 .endianness = DEVICE_NATIVE_ENDIAN, 857 }; 858 859 static const VMStateDescription vmstate_stellaris_i2c = { 860 .name = "stellaris_i2c", 861 .version_id = 1, 862 .minimum_version_id = 1, 863 .fields = (VMStateField[]) { 864 VMSTATE_UINT32(msa, stellaris_i2c_state), 865 VMSTATE_UINT32(mcs, stellaris_i2c_state), 866 VMSTATE_UINT32(mdr, stellaris_i2c_state), 867 VMSTATE_UINT32(mtpr, stellaris_i2c_state), 868 VMSTATE_UINT32(mimr, stellaris_i2c_state), 869 VMSTATE_UINT32(mris, stellaris_i2c_state), 870 VMSTATE_UINT32(mcr, stellaris_i2c_state), 871 VMSTATE_END_OF_LIST() 872 } 873 }; 874 875 static int stellaris_i2c_init(SysBusDevice *sbd) 876 { 877 DeviceState *dev = DEVICE(sbd); 878 stellaris_i2c_state *s = STELLARIS_I2C(dev); 879 I2CBus *bus; 880 881 sysbus_init_irq(sbd, &s->irq); 882 bus = i2c_init_bus(dev, "i2c"); 883 s->bus = bus; 884 885 memory_region_init_io(&s->iomem, OBJECT(s), &stellaris_i2c_ops, s, 886 "i2c", 0x1000); 887 sysbus_init_mmio(sbd, &s->iomem); 888 /* ??? For now we only implement the master interface. */ 889 stellaris_i2c_reset(s); 890 vmstate_register(dev, -1, &vmstate_stellaris_i2c, s); 891 return 0; 892 } 893 894 /* Analogue to Digital Converter. This is only partially implemented, 895 enough for applications that use a combined ADC and timer tick. */ 896 897 #define STELLARIS_ADC_EM_CONTROLLER 0 898 #define STELLARIS_ADC_EM_COMP 1 899 #define STELLARIS_ADC_EM_EXTERNAL 4 900 #define STELLARIS_ADC_EM_TIMER 5 901 #define STELLARIS_ADC_EM_PWM0 6 902 #define STELLARIS_ADC_EM_PWM1 7 903 #define STELLARIS_ADC_EM_PWM2 8 904 905 #define STELLARIS_ADC_FIFO_EMPTY 0x0100 906 #define STELLARIS_ADC_FIFO_FULL 0x1000 907 908 #define TYPE_STELLARIS_ADC "stellaris-adc" 909 #define STELLARIS_ADC(obj) \ 910 OBJECT_CHECK(stellaris_adc_state, (obj), TYPE_STELLARIS_ADC) 911 912 typedef struct StellarisADCState { 913 SysBusDevice parent_obj; 914 915 MemoryRegion iomem; 916 uint32_t actss; 917 uint32_t ris; 918 uint32_t im; 919 uint32_t emux; 920 uint32_t ostat; 921 uint32_t ustat; 922 uint32_t sspri; 923 uint32_t sac; 924 struct { 925 uint32_t state; 926 uint32_t data[16]; 927 } fifo[4]; 928 uint32_t ssmux[4]; 929 uint32_t ssctl[4]; 930 uint32_t noise; 931 qemu_irq irq[4]; 932 } stellaris_adc_state; 933 934 static uint32_t stellaris_adc_fifo_read(stellaris_adc_state *s, int n) 935 { 936 int tail; 937 938 tail = s->fifo[n].state & 0xf; 939 if (s->fifo[n].state & STELLARIS_ADC_FIFO_EMPTY) { 940 s->ustat |= 1 << n; 941 } else { 942 s->fifo[n].state = (s->fifo[n].state & ~0xf) | ((tail + 1) & 0xf); 943 s->fifo[n].state &= ~STELLARIS_ADC_FIFO_FULL; 944 if (tail + 1 == ((s->fifo[n].state >> 4) & 0xf)) 945 s->fifo[n].state |= STELLARIS_ADC_FIFO_EMPTY; 946 } 947 return s->fifo[n].data[tail]; 948 } 949 950 static void stellaris_adc_fifo_write(stellaris_adc_state *s, int n, 951 uint32_t value) 952 { 953 int head; 954 955 /* TODO: Real hardware has limited size FIFOs. We have a full 16 entry 956 FIFO fir each sequencer. */ 957 head = (s->fifo[n].state >> 4) & 0xf; 958 if (s->fifo[n].state & STELLARIS_ADC_FIFO_FULL) { 959 s->ostat |= 1 << n; 960 return; 961 } 962 s->fifo[n].data[head] = value; 963 head = (head + 1) & 0xf; 964 s->fifo[n].state &= ~STELLARIS_ADC_FIFO_EMPTY; 965 s->fifo[n].state = (s->fifo[n].state & ~0xf0) | (head << 4); 966 if ((s->fifo[n].state & 0xf) == head) 967 s->fifo[n].state |= STELLARIS_ADC_FIFO_FULL; 968 } 969 970 static void stellaris_adc_update(stellaris_adc_state *s) 971 { 972 int level; 973 int n; 974 975 for (n = 0; n < 4; n++) { 976 level = (s->ris & s->im & (1 << n)) != 0; 977 qemu_set_irq(s->irq[n], level); 978 } 979 } 980 981 static void stellaris_adc_trigger(void *opaque, int irq, int level) 982 { 983 stellaris_adc_state *s = (stellaris_adc_state *)opaque; 984 int n; 985 986 for (n = 0; n < 4; n++) { 987 if ((s->actss & (1 << n)) == 0) { 988 continue; 989 } 990 991 if (((s->emux >> (n * 4)) & 0xff) != 5) { 992 continue; 993 } 994 995 /* Some applications use the ADC as a random number source, so introduce 996 some variation into the signal. */ 997 s->noise = s->noise * 314159 + 1; 998 /* ??? actual inputs not implemented. Return an arbitrary value. */ 999 stellaris_adc_fifo_write(s, n, 0x200 + ((s->noise >> 16) & 7)); 1000 s->ris |= (1 << n); 1001 stellaris_adc_update(s); 1002 } 1003 } 1004 1005 static void stellaris_adc_reset(stellaris_adc_state *s) 1006 { 1007 int n; 1008 1009 for (n = 0; n < 4; n++) { 1010 s->ssmux[n] = 0; 1011 s->ssctl[n] = 0; 1012 s->fifo[n].state = STELLARIS_ADC_FIFO_EMPTY; 1013 } 1014 } 1015 1016 static uint64_t stellaris_adc_read(void *opaque, hwaddr offset, 1017 unsigned size) 1018 { 1019 stellaris_adc_state *s = (stellaris_adc_state *)opaque; 1020 1021 /* TODO: Implement this. */ 1022 if (offset >= 0x40 && offset < 0xc0) { 1023 int n; 1024 n = (offset - 0x40) >> 5; 1025 switch (offset & 0x1f) { 1026 case 0x00: /* SSMUX */ 1027 return s->ssmux[n]; 1028 case 0x04: /* SSCTL */ 1029 return s->ssctl[n]; 1030 case 0x08: /* SSFIFO */ 1031 return stellaris_adc_fifo_read(s, n); 1032 case 0x0c: /* SSFSTAT */ 1033 return s->fifo[n].state; 1034 default: 1035 break; 1036 } 1037 } 1038 switch (offset) { 1039 case 0x00: /* ACTSS */ 1040 return s->actss; 1041 case 0x04: /* RIS */ 1042 return s->ris; 1043 case 0x08: /* IM */ 1044 return s->im; 1045 case 0x0c: /* ISC */ 1046 return s->ris & s->im; 1047 case 0x10: /* OSTAT */ 1048 return s->ostat; 1049 case 0x14: /* EMUX */ 1050 return s->emux; 1051 case 0x18: /* USTAT */ 1052 return s->ustat; 1053 case 0x20: /* SSPRI */ 1054 return s->sspri; 1055 case 0x30: /* SAC */ 1056 return s->sac; 1057 default: 1058 hw_error("strllaris_adc_read: Bad offset 0x%x\n", 1059 (int)offset); 1060 return 0; 1061 } 1062 } 1063 1064 static void stellaris_adc_write(void *opaque, hwaddr offset, 1065 uint64_t value, unsigned size) 1066 { 1067 stellaris_adc_state *s = (stellaris_adc_state *)opaque; 1068 1069 /* TODO: Implement this. */ 1070 if (offset >= 0x40 && offset < 0xc0) { 1071 int n; 1072 n = (offset - 0x40) >> 5; 1073 switch (offset & 0x1f) { 1074 case 0x00: /* SSMUX */ 1075 s->ssmux[n] = value & 0x33333333; 1076 return; 1077 case 0x04: /* SSCTL */ 1078 if (value != 6) { 1079 hw_error("ADC: Unimplemented sequence %" PRIx64 "\n", 1080 value); 1081 } 1082 s->ssctl[n] = value; 1083 return; 1084 default: 1085 break; 1086 } 1087 } 1088 switch (offset) { 1089 case 0x00: /* ACTSS */ 1090 s->actss = value & 0xf; 1091 break; 1092 case 0x08: /* IM */ 1093 s->im = value; 1094 break; 1095 case 0x0c: /* ISC */ 1096 s->ris &= ~value; 1097 break; 1098 case 0x10: /* OSTAT */ 1099 s->ostat &= ~value; 1100 break; 1101 case 0x14: /* EMUX */ 1102 s->emux = value; 1103 break; 1104 case 0x18: /* USTAT */ 1105 s->ustat &= ~value; 1106 break; 1107 case 0x20: /* SSPRI */ 1108 s->sspri = value; 1109 break; 1110 case 0x28: /* PSSI */ 1111 hw_error("Not implemented: ADC sample initiate\n"); 1112 break; 1113 case 0x30: /* SAC */ 1114 s->sac = value; 1115 break; 1116 default: 1117 hw_error("stellaris_adc_write: Bad offset 0x%x\n", (int)offset); 1118 } 1119 stellaris_adc_update(s); 1120 } 1121 1122 static const MemoryRegionOps stellaris_adc_ops = { 1123 .read = stellaris_adc_read, 1124 .write = stellaris_adc_write, 1125 .endianness = DEVICE_NATIVE_ENDIAN, 1126 }; 1127 1128 static const VMStateDescription vmstate_stellaris_adc = { 1129 .name = "stellaris_adc", 1130 .version_id = 1, 1131 .minimum_version_id = 1, 1132 .fields = (VMStateField[]) { 1133 VMSTATE_UINT32(actss, stellaris_adc_state), 1134 VMSTATE_UINT32(ris, stellaris_adc_state), 1135 VMSTATE_UINT32(im, stellaris_adc_state), 1136 VMSTATE_UINT32(emux, stellaris_adc_state), 1137 VMSTATE_UINT32(ostat, stellaris_adc_state), 1138 VMSTATE_UINT32(ustat, stellaris_adc_state), 1139 VMSTATE_UINT32(sspri, stellaris_adc_state), 1140 VMSTATE_UINT32(sac, stellaris_adc_state), 1141 VMSTATE_UINT32(fifo[0].state, stellaris_adc_state), 1142 VMSTATE_UINT32_ARRAY(fifo[0].data, stellaris_adc_state, 16), 1143 VMSTATE_UINT32(ssmux[0], stellaris_adc_state), 1144 VMSTATE_UINT32(ssctl[0], stellaris_adc_state), 1145 VMSTATE_UINT32(fifo[1].state, stellaris_adc_state), 1146 VMSTATE_UINT32_ARRAY(fifo[1].data, stellaris_adc_state, 16), 1147 VMSTATE_UINT32(ssmux[1], stellaris_adc_state), 1148 VMSTATE_UINT32(ssctl[1], stellaris_adc_state), 1149 VMSTATE_UINT32(fifo[2].state, stellaris_adc_state), 1150 VMSTATE_UINT32_ARRAY(fifo[2].data, stellaris_adc_state, 16), 1151 VMSTATE_UINT32(ssmux[2], stellaris_adc_state), 1152 VMSTATE_UINT32(ssctl[2], stellaris_adc_state), 1153 VMSTATE_UINT32(fifo[3].state, stellaris_adc_state), 1154 VMSTATE_UINT32_ARRAY(fifo[3].data, stellaris_adc_state, 16), 1155 VMSTATE_UINT32(ssmux[3], stellaris_adc_state), 1156 VMSTATE_UINT32(ssctl[3], stellaris_adc_state), 1157 VMSTATE_UINT32(noise, stellaris_adc_state), 1158 VMSTATE_END_OF_LIST() 1159 } 1160 }; 1161 1162 static int stellaris_adc_init(SysBusDevice *sbd) 1163 { 1164 DeviceState *dev = DEVICE(sbd); 1165 stellaris_adc_state *s = STELLARIS_ADC(dev); 1166 int n; 1167 1168 for (n = 0; n < 4; n++) { 1169 sysbus_init_irq(sbd, &s->irq[n]); 1170 } 1171 1172 memory_region_init_io(&s->iomem, OBJECT(s), &stellaris_adc_ops, s, 1173 "adc", 0x1000); 1174 sysbus_init_mmio(sbd, &s->iomem); 1175 stellaris_adc_reset(s); 1176 qdev_init_gpio_in(dev, stellaris_adc_trigger, 1); 1177 vmstate_register(dev, -1, &vmstate_stellaris_adc, s); 1178 return 0; 1179 } 1180 1181 static 1182 void do_sys_reset(void *opaque, int n, int level) 1183 { 1184 if (level) { 1185 qemu_system_reset_request(); 1186 } 1187 } 1188 1189 /* Board init. */ 1190 static stellaris_board_info stellaris_boards[] = { 1191 { "LM3S811EVB", 1192 0, 1193 0x0032000e, 1194 0x001f001f, /* dc0 */ 1195 0x001132bf, 1196 0x01071013, 1197 0x3f0f01ff, 1198 0x0000001f, 1199 BP_OLED_I2C 1200 }, 1201 { "LM3S6965EVB", 1202 0x10010002, 1203 0x1073402e, 1204 0x00ff007f, /* dc0 */ 1205 0x001133ff, 1206 0x030f5317, 1207 0x0f0f87ff, 1208 0x5000007f, 1209 BP_OLED_SSI | BP_GAMEPAD 1210 } 1211 }; 1212 1213 static void stellaris_init(const char *kernel_filename, const char *cpu_model, 1214 stellaris_board_info *board) 1215 { 1216 static const int uart_irq[] = {5, 6, 33, 34}; 1217 static const int timer_irq[] = {19, 21, 23, 35}; 1218 static const uint32_t gpio_addr[7] = 1219 { 0x40004000, 0x40005000, 0x40006000, 0x40007000, 1220 0x40024000, 0x40025000, 0x40026000}; 1221 static const int gpio_irq[7] = {0, 1, 2, 3, 4, 30, 31}; 1222 1223 DeviceState *gpio_dev[7], *nvic; 1224 qemu_irq gpio_in[7][8]; 1225 qemu_irq gpio_out[7][8]; 1226 qemu_irq adc; 1227 int sram_size; 1228 int flash_size; 1229 I2CBus *i2c; 1230 DeviceState *dev; 1231 int i; 1232 int j; 1233 1234 MemoryRegion *sram = g_new(MemoryRegion, 1); 1235 MemoryRegion *flash = g_new(MemoryRegion, 1); 1236 MemoryRegion *system_memory = get_system_memory(); 1237 1238 flash_size = (((board->dc0 & 0xffff) + 1) << 1) * 1024; 1239 sram_size = ((board->dc0 >> 18) + 1) * 1024; 1240 1241 /* Flash programming is done via the SCU, so pretend it is ROM. */ 1242 memory_region_init_ram(flash, NULL, "stellaris.flash", flash_size, 1243 &error_fatal); 1244 vmstate_register_ram_global(flash); 1245 memory_region_set_readonly(flash, true); 1246 memory_region_add_subregion(system_memory, 0, flash); 1247 1248 memory_region_init_ram(sram, NULL, "stellaris.sram", sram_size, 1249 &error_fatal); 1250 vmstate_register_ram_global(sram); 1251 memory_region_add_subregion(system_memory, 0x20000000, sram); 1252 1253 nvic = armv7m_init(system_memory, flash_size, NUM_IRQ_LINES, 1254 kernel_filename, cpu_model); 1255 1256 qdev_connect_gpio_out_named(nvic, "SYSRESETREQ", 0, 1257 qemu_allocate_irq(&do_sys_reset, NULL, 0)); 1258 1259 if (board->dc1 & (1 << 16)) { 1260 dev = sysbus_create_varargs(TYPE_STELLARIS_ADC, 0x40038000, 1261 qdev_get_gpio_in(nvic, 14), 1262 qdev_get_gpio_in(nvic, 15), 1263 qdev_get_gpio_in(nvic, 16), 1264 qdev_get_gpio_in(nvic, 17), 1265 NULL); 1266 adc = qdev_get_gpio_in(dev, 0); 1267 } else { 1268 adc = NULL; 1269 } 1270 for (i = 0; i < 4; i++) { 1271 if (board->dc2 & (0x10000 << i)) { 1272 dev = sysbus_create_simple(TYPE_STELLARIS_GPTM, 1273 0x40030000 + i * 0x1000, 1274 qdev_get_gpio_in(nvic, timer_irq[i])); 1275 /* TODO: This is incorrect, but we get away with it because 1276 the ADC output is only ever pulsed. */ 1277 qdev_connect_gpio_out(dev, 0, adc); 1278 } 1279 } 1280 1281 stellaris_sys_init(0x400fe000, qdev_get_gpio_in(nvic, 28), 1282 board, nd_table[0].macaddr.a); 1283 1284 for (i = 0; i < 7; i++) { 1285 if (board->dc4 & (1 << i)) { 1286 gpio_dev[i] = sysbus_create_simple("pl061_luminary", gpio_addr[i], 1287 qdev_get_gpio_in(nvic, 1288 gpio_irq[i])); 1289 for (j = 0; j < 8; j++) { 1290 gpio_in[i][j] = qdev_get_gpio_in(gpio_dev[i], j); 1291 gpio_out[i][j] = NULL; 1292 } 1293 } 1294 } 1295 1296 if (board->dc2 & (1 << 12)) { 1297 dev = sysbus_create_simple(TYPE_STELLARIS_I2C, 0x40020000, 1298 qdev_get_gpio_in(nvic, 8)); 1299 i2c = (I2CBus *)qdev_get_child_bus(dev, "i2c"); 1300 if (board->peripherals & BP_OLED_I2C) { 1301 i2c_create_slave(i2c, "ssd0303", 0x3d); 1302 } 1303 } 1304 1305 for (i = 0; i < 4; i++) { 1306 if (board->dc2 & (1 << i)) { 1307 sysbus_create_simple("pl011_luminary", 0x4000c000 + i * 0x1000, 1308 qdev_get_gpio_in(nvic, uart_irq[i])); 1309 } 1310 } 1311 if (board->dc2 & (1 << 4)) { 1312 dev = sysbus_create_simple("pl022", 0x40008000, 1313 qdev_get_gpio_in(nvic, 7)); 1314 if (board->peripherals & BP_OLED_SSI) { 1315 void *bus; 1316 DeviceState *sddev; 1317 DeviceState *ssddev; 1318 1319 /* Some boards have both an OLED controller and SD card connected to 1320 * the same SSI port, with the SD card chip select connected to a 1321 * GPIO pin. Technically the OLED chip select is connected to the 1322 * SSI Fss pin. We do not bother emulating that as both devices 1323 * should never be selected simultaneously, and our OLED controller 1324 * ignores stray 0xff commands that occur when deselecting the SD 1325 * card. 1326 */ 1327 bus = qdev_get_child_bus(dev, "ssi"); 1328 1329 sddev = ssi_create_slave(bus, "ssi-sd"); 1330 ssddev = ssi_create_slave(bus, "ssd0323"); 1331 gpio_out[GPIO_D][0] = qemu_irq_split( 1332 qdev_get_gpio_in_named(sddev, SSI_GPIO_CS, 0), 1333 qdev_get_gpio_in_named(ssddev, SSI_GPIO_CS, 0)); 1334 gpio_out[GPIO_C][7] = qdev_get_gpio_in(ssddev, 0); 1335 1336 /* Make sure the select pin is high. */ 1337 qemu_irq_raise(gpio_out[GPIO_D][0]); 1338 } 1339 } 1340 if (board->dc4 & (1 << 28)) { 1341 DeviceState *enet; 1342 1343 qemu_check_nic_model(&nd_table[0], "stellaris"); 1344 1345 enet = qdev_create(NULL, "stellaris_enet"); 1346 qdev_set_nic_properties(enet, &nd_table[0]); 1347 qdev_init_nofail(enet); 1348 sysbus_mmio_map(SYS_BUS_DEVICE(enet), 0, 0x40048000); 1349 sysbus_connect_irq(SYS_BUS_DEVICE(enet), 0, qdev_get_gpio_in(nvic, 42)); 1350 } 1351 if (board->peripherals & BP_GAMEPAD) { 1352 qemu_irq gpad_irq[5]; 1353 static const int gpad_keycode[5] = { 0xc8, 0xd0, 0xcb, 0xcd, 0x1d }; 1354 1355 gpad_irq[0] = qemu_irq_invert(gpio_in[GPIO_E][0]); /* up */ 1356 gpad_irq[1] = qemu_irq_invert(gpio_in[GPIO_E][1]); /* down */ 1357 gpad_irq[2] = qemu_irq_invert(gpio_in[GPIO_E][2]); /* left */ 1358 gpad_irq[3] = qemu_irq_invert(gpio_in[GPIO_E][3]); /* right */ 1359 gpad_irq[4] = qemu_irq_invert(gpio_in[GPIO_F][1]); /* select */ 1360 1361 stellaris_gamepad_init(5, gpad_irq, gpad_keycode); 1362 } 1363 for (i = 0; i < 7; i++) { 1364 if (board->dc4 & (1 << i)) { 1365 for (j = 0; j < 8; j++) { 1366 if (gpio_out[i][j]) { 1367 qdev_connect_gpio_out(gpio_dev[i], j, gpio_out[i][j]); 1368 } 1369 } 1370 } 1371 } 1372 } 1373 1374 /* FIXME: Figure out how to generate these from stellaris_boards. */ 1375 static void lm3s811evb_init(MachineState *machine) 1376 { 1377 const char *cpu_model = machine->cpu_model; 1378 const char *kernel_filename = machine->kernel_filename; 1379 stellaris_init(kernel_filename, cpu_model, &stellaris_boards[0]); 1380 } 1381 1382 static void lm3s6965evb_init(MachineState *machine) 1383 { 1384 const char *cpu_model = machine->cpu_model; 1385 const char *kernel_filename = machine->kernel_filename; 1386 stellaris_init(kernel_filename, cpu_model, &stellaris_boards[1]); 1387 } 1388 1389 static void lm3s811evb_class_init(ObjectClass *oc, void *data) 1390 { 1391 MachineClass *mc = MACHINE_CLASS(oc); 1392 1393 mc->desc = "Stellaris LM3S811EVB"; 1394 mc->init = lm3s811evb_init; 1395 } 1396 1397 static const TypeInfo lm3s811evb_type = { 1398 .name = MACHINE_TYPE_NAME("lm3s811evb"), 1399 .parent = TYPE_MACHINE, 1400 .class_init = lm3s811evb_class_init, 1401 }; 1402 1403 static void lm3s6965evb_class_init(ObjectClass *oc, void *data) 1404 { 1405 MachineClass *mc = MACHINE_CLASS(oc); 1406 1407 mc->desc = "Stellaris LM3S6965EVB"; 1408 mc->init = lm3s6965evb_init; 1409 } 1410 1411 static const TypeInfo lm3s6965evb_type = { 1412 .name = MACHINE_TYPE_NAME("lm3s6965evb"), 1413 .parent = TYPE_MACHINE, 1414 .class_init = lm3s6965evb_class_init, 1415 }; 1416 1417 static void stellaris_machine_init(void) 1418 { 1419 type_register_static(&lm3s811evb_type); 1420 type_register_static(&lm3s6965evb_type); 1421 } 1422 1423 machine_init(stellaris_machine_init) 1424 1425 static void stellaris_i2c_class_init(ObjectClass *klass, void *data) 1426 { 1427 SysBusDeviceClass *sdc = SYS_BUS_DEVICE_CLASS(klass); 1428 1429 sdc->init = stellaris_i2c_init; 1430 } 1431 1432 static const TypeInfo stellaris_i2c_info = { 1433 .name = TYPE_STELLARIS_I2C, 1434 .parent = TYPE_SYS_BUS_DEVICE, 1435 .instance_size = sizeof(stellaris_i2c_state), 1436 .class_init = stellaris_i2c_class_init, 1437 }; 1438 1439 static void stellaris_gptm_class_init(ObjectClass *klass, void *data) 1440 { 1441 SysBusDeviceClass *sdc = SYS_BUS_DEVICE_CLASS(klass); 1442 1443 sdc->init = stellaris_gptm_init; 1444 } 1445 1446 static const TypeInfo stellaris_gptm_info = { 1447 .name = TYPE_STELLARIS_GPTM, 1448 .parent = TYPE_SYS_BUS_DEVICE, 1449 .instance_size = sizeof(gptm_state), 1450 .class_init = stellaris_gptm_class_init, 1451 }; 1452 1453 static void stellaris_adc_class_init(ObjectClass *klass, void *data) 1454 { 1455 SysBusDeviceClass *sdc = SYS_BUS_DEVICE_CLASS(klass); 1456 1457 sdc->init = stellaris_adc_init; 1458 } 1459 1460 static const TypeInfo stellaris_adc_info = { 1461 .name = TYPE_STELLARIS_ADC, 1462 .parent = TYPE_SYS_BUS_DEVICE, 1463 .instance_size = sizeof(stellaris_adc_state), 1464 .class_init = stellaris_adc_class_init, 1465 }; 1466 1467 static void stellaris_register_types(void) 1468 { 1469 type_register_static(&stellaris_i2c_info); 1470 type_register_static(&stellaris_gptm_info); 1471 type_register_static(&stellaris_adc_info); 1472 } 1473 1474 type_init(stellaris_register_types) 1475