1 /* 2 * Luminary Micro Stellaris peripherals 3 * 4 * Copyright (c) 2006 CodeSourcery. 5 * Written by Paul Brook 6 * 7 * This code is licensed under the GPL. 8 */ 9 10 #include "qemu/osdep.h" 11 #include "qapi/error.h" 12 #include "hw/sysbus.h" 13 #include "hw/ssi/ssi.h" 14 #include "hw/arm/arm.h" 15 #include "hw/devices.h" 16 #include "qemu/timer.h" 17 #include "hw/i2c/i2c.h" 18 #include "net/net.h" 19 #include "hw/boards.h" 20 #include "qemu/log.h" 21 #include "exec/address-spaces.h" 22 #include "sysemu/sysemu.h" 23 #include "hw/char/pl011.h" 24 25 #define GPIO_A 0 26 #define GPIO_B 1 27 #define GPIO_C 2 28 #define GPIO_D 3 29 #define GPIO_E 4 30 #define GPIO_F 5 31 #define GPIO_G 6 32 33 #define BP_OLED_I2C 0x01 34 #define BP_OLED_SSI 0x02 35 #define BP_GAMEPAD 0x04 36 37 #define NUM_IRQ_LINES 64 38 39 typedef const struct { 40 const char *name; 41 uint32_t did0; 42 uint32_t did1; 43 uint32_t dc0; 44 uint32_t dc1; 45 uint32_t dc2; 46 uint32_t dc3; 47 uint32_t dc4; 48 uint32_t peripherals; 49 } stellaris_board_info; 50 51 /* General purpose timer module. */ 52 53 #define TYPE_STELLARIS_GPTM "stellaris-gptm" 54 #define STELLARIS_GPTM(obj) \ 55 OBJECT_CHECK(gptm_state, (obj), TYPE_STELLARIS_GPTM) 56 57 typedef struct gptm_state { 58 SysBusDevice parent_obj; 59 60 MemoryRegion iomem; 61 uint32_t config; 62 uint32_t mode[2]; 63 uint32_t control; 64 uint32_t state; 65 uint32_t mask; 66 uint32_t load[2]; 67 uint32_t match[2]; 68 uint32_t prescale[2]; 69 uint32_t match_prescale[2]; 70 uint32_t rtc; 71 int64_t tick[2]; 72 struct gptm_state *opaque[2]; 73 QEMUTimer *timer[2]; 74 /* The timers have an alternate output used to trigger the ADC. */ 75 qemu_irq trigger; 76 qemu_irq irq; 77 } gptm_state; 78 79 static void gptm_update_irq(gptm_state *s) 80 { 81 int level; 82 level = (s->state & s->mask) != 0; 83 qemu_set_irq(s->irq, level); 84 } 85 86 static void gptm_stop(gptm_state *s, int n) 87 { 88 timer_del(s->timer[n]); 89 } 90 91 static void gptm_reload(gptm_state *s, int n, int reset) 92 { 93 int64_t tick; 94 if (reset) 95 tick = qemu_clock_get_ns(QEMU_CLOCK_VIRTUAL); 96 else 97 tick = s->tick[n]; 98 99 if (s->config == 0) { 100 /* 32-bit CountDown. */ 101 uint32_t count; 102 count = s->load[0] | (s->load[1] << 16); 103 tick += (int64_t)count * system_clock_scale; 104 } else if (s->config == 1) { 105 /* 32-bit RTC. 1Hz tick. */ 106 tick += NANOSECONDS_PER_SECOND; 107 } else if (s->mode[n] == 0xa) { 108 /* PWM mode. Not implemented. */ 109 } else { 110 hw_error("TODO: 16-bit timer mode 0x%x\n", s->mode[n]); 111 } 112 s->tick[n] = tick; 113 timer_mod(s->timer[n], tick); 114 } 115 116 static void gptm_tick(void *opaque) 117 { 118 gptm_state **p = (gptm_state **)opaque; 119 gptm_state *s; 120 int n; 121 122 s = *p; 123 n = p - s->opaque; 124 if (s->config == 0) { 125 s->state |= 1; 126 if ((s->control & 0x20)) { 127 /* Output trigger. */ 128 qemu_irq_pulse(s->trigger); 129 } 130 if (s->mode[0] & 1) { 131 /* One-shot. */ 132 s->control &= ~1; 133 } else { 134 /* Periodic. */ 135 gptm_reload(s, 0, 0); 136 } 137 } else if (s->config == 1) { 138 /* RTC. */ 139 uint32_t match; 140 s->rtc++; 141 match = s->match[0] | (s->match[1] << 16); 142 if (s->rtc > match) 143 s->rtc = 0; 144 if (s->rtc == 0) { 145 s->state |= 8; 146 } 147 gptm_reload(s, 0, 0); 148 } else if (s->mode[n] == 0xa) { 149 /* PWM mode. Not implemented. */ 150 } else { 151 hw_error("TODO: 16-bit timer mode 0x%x\n", s->mode[n]); 152 } 153 gptm_update_irq(s); 154 } 155 156 static uint64_t gptm_read(void *opaque, hwaddr offset, 157 unsigned size) 158 { 159 gptm_state *s = (gptm_state *)opaque; 160 161 switch (offset) { 162 case 0x00: /* CFG */ 163 return s->config; 164 case 0x04: /* TAMR */ 165 return s->mode[0]; 166 case 0x08: /* TBMR */ 167 return s->mode[1]; 168 case 0x0c: /* CTL */ 169 return s->control; 170 case 0x18: /* IMR */ 171 return s->mask; 172 case 0x1c: /* RIS */ 173 return s->state; 174 case 0x20: /* MIS */ 175 return s->state & s->mask; 176 case 0x24: /* CR */ 177 return 0; 178 case 0x28: /* TAILR */ 179 return s->load[0] | ((s->config < 4) ? (s->load[1] << 16) : 0); 180 case 0x2c: /* TBILR */ 181 return s->load[1]; 182 case 0x30: /* TAMARCHR */ 183 return s->match[0] | ((s->config < 4) ? (s->match[1] << 16) : 0); 184 case 0x34: /* TBMATCHR */ 185 return s->match[1]; 186 case 0x38: /* TAPR */ 187 return s->prescale[0]; 188 case 0x3c: /* TBPR */ 189 return s->prescale[1]; 190 case 0x40: /* TAPMR */ 191 return s->match_prescale[0]; 192 case 0x44: /* TBPMR */ 193 return s->match_prescale[1]; 194 case 0x48: /* TAR */ 195 if (s->config == 1) { 196 return s->rtc; 197 } 198 qemu_log_mask(LOG_UNIMP, 199 "GPTM: read of TAR but timer read not supported"); 200 return 0; 201 case 0x4c: /* TBR */ 202 qemu_log_mask(LOG_UNIMP, 203 "GPTM: read of TBR but timer read not supported"); 204 return 0; 205 default: 206 qemu_log_mask(LOG_GUEST_ERROR, 207 "GPTM: read at bad offset 0x%x\n", (int)offset); 208 return 0; 209 } 210 } 211 212 static void gptm_write(void *opaque, hwaddr offset, 213 uint64_t value, unsigned size) 214 { 215 gptm_state *s = (gptm_state *)opaque; 216 uint32_t oldval; 217 218 /* The timers should be disabled before changing the configuration. 219 We take advantage of this and defer everything until the timer 220 is enabled. */ 221 switch (offset) { 222 case 0x00: /* CFG */ 223 s->config = value; 224 break; 225 case 0x04: /* TAMR */ 226 s->mode[0] = value; 227 break; 228 case 0x08: /* TBMR */ 229 s->mode[1] = value; 230 break; 231 case 0x0c: /* CTL */ 232 oldval = s->control; 233 s->control = value; 234 /* TODO: Implement pause. */ 235 if ((oldval ^ value) & 1) { 236 if (value & 1) { 237 gptm_reload(s, 0, 1); 238 } else { 239 gptm_stop(s, 0); 240 } 241 } 242 if (((oldval ^ value) & 0x100) && s->config >= 4) { 243 if (value & 0x100) { 244 gptm_reload(s, 1, 1); 245 } else { 246 gptm_stop(s, 1); 247 } 248 } 249 break; 250 case 0x18: /* IMR */ 251 s->mask = value & 0x77; 252 gptm_update_irq(s); 253 break; 254 case 0x24: /* CR */ 255 s->state &= ~value; 256 break; 257 case 0x28: /* TAILR */ 258 s->load[0] = value & 0xffff; 259 if (s->config < 4) { 260 s->load[1] = value >> 16; 261 } 262 break; 263 case 0x2c: /* TBILR */ 264 s->load[1] = value & 0xffff; 265 break; 266 case 0x30: /* TAMARCHR */ 267 s->match[0] = value & 0xffff; 268 if (s->config < 4) { 269 s->match[1] = value >> 16; 270 } 271 break; 272 case 0x34: /* TBMATCHR */ 273 s->match[1] = value >> 16; 274 break; 275 case 0x38: /* TAPR */ 276 s->prescale[0] = value; 277 break; 278 case 0x3c: /* TBPR */ 279 s->prescale[1] = value; 280 break; 281 case 0x40: /* TAPMR */ 282 s->match_prescale[0] = value; 283 break; 284 case 0x44: /* TBPMR */ 285 s->match_prescale[0] = value; 286 break; 287 default: 288 hw_error("gptm_write: Bad offset 0x%x\n", (int)offset); 289 } 290 gptm_update_irq(s); 291 } 292 293 static const MemoryRegionOps gptm_ops = { 294 .read = gptm_read, 295 .write = gptm_write, 296 .endianness = DEVICE_NATIVE_ENDIAN, 297 }; 298 299 static const VMStateDescription vmstate_stellaris_gptm = { 300 .name = "stellaris_gptm", 301 .version_id = 1, 302 .minimum_version_id = 1, 303 .fields = (VMStateField[]) { 304 VMSTATE_UINT32(config, gptm_state), 305 VMSTATE_UINT32_ARRAY(mode, gptm_state, 2), 306 VMSTATE_UINT32(control, gptm_state), 307 VMSTATE_UINT32(state, gptm_state), 308 VMSTATE_UINT32(mask, gptm_state), 309 VMSTATE_UNUSED(8), 310 VMSTATE_UINT32_ARRAY(load, gptm_state, 2), 311 VMSTATE_UINT32_ARRAY(match, gptm_state, 2), 312 VMSTATE_UINT32_ARRAY(prescale, gptm_state, 2), 313 VMSTATE_UINT32_ARRAY(match_prescale, gptm_state, 2), 314 VMSTATE_UINT32(rtc, gptm_state), 315 VMSTATE_INT64_ARRAY(tick, gptm_state, 2), 316 VMSTATE_TIMER_PTR_ARRAY(timer, gptm_state, 2), 317 VMSTATE_END_OF_LIST() 318 } 319 }; 320 321 static void stellaris_gptm_init(Object *obj) 322 { 323 DeviceState *dev = DEVICE(obj); 324 gptm_state *s = STELLARIS_GPTM(obj); 325 SysBusDevice *sbd = SYS_BUS_DEVICE(obj); 326 327 sysbus_init_irq(sbd, &s->irq); 328 qdev_init_gpio_out(dev, &s->trigger, 1); 329 330 memory_region_init_io(&s->iomem, obj, &gptm_ops, s, 331 "gptm", 0x1000); 332 sysbus_init_mmio(sbd, &s->iomem); 333 334 s->opaque[0] = s->opaque[1] = s; 335 s->timer[0] = timer_new_ns(QEMU_CLOCK_VIRTUAL, gptm_tick, &s->opaque[0]); 336 s->timer[1] = timer_new_ns(QEMU_CLOCK_VIRTUAL, gptm_tick, &s->opaque[1]); 337 } 338 339 340 /* System controller. */ 341 342 typedef struct { 343 MemoryRegion iomem; 344 uint32_t pborctl; 345 uint32_t ldopctl; 346 uint32_t int_status; 347 uint32_t int_mask; 348 uint32_t resc; 349 uint32_t rcc; 350 uint32_t rcc2; 351 uint32_t rcgc[3]; 352 uint32_t scgc[3]; 353 uint32_t dcgc[3]; 354 uint32_t clkvclr; 355 uint32_t ldoarst; 356 uint32_t user0; 357 uint32_t user1; 358 qemu_irq irq; 359 stellaris_board_info *board; 360 } ssys_state; 361 362 static void ssys_update(ssys_state *s) 363 { 364 qemu_set_irq(s->irq, (s->int_status & s->int_mask) != 0); 365 } 366 367 static uint32_t pllcfg_sandstorm[16] = { 368 0x31c0, /* 1 Mhz */ 369 0x1ae0, /* 1.8432 Mhz */ 370 0x18c0, /* 2 Mhz */ 371 0xd573, /* 2.4576 Mhz */ 372 0x37a6, /* 3.57954 Mhz */ 373 0x1ae2, /* 3.6864 Mhz */ 374 0x0c40, /* 4 Mhz */ 375 0x98bc, /* 4.906 Mhz */ 376 0x935b, /* 4.9152 Mhz */ 377 0x09c0, /* 5 Mhz */ 378 0x4dee, /* 5.12 Mhz */ 379 0x0c41, /* 6 Mhz */ 380 0x75db, /* 6.144 Mhz */ 381 0x1ae6, /* 7.3728 Mhz */ 382 0x0600, /* 8 Mhz */ 383 0x585b /* 8.192 Mhz */ 384 }; 385 386 static uint32_t pllcfg_fury[16] = { 387 0x3200, /* 1 Mhz */ 388 0x1b20, /* 1.8432 Mhz */ 389 0x1900, /* 2 Mhz */ 390 0xf42b, /* 2.4576 Mhz */ 391 0x37e3, /* 3.57954 Mhz */ 392 0x1b21, /* 3.6864 Mhz */ 393 0x0c80, /* 4 Mhz */ 394 0x98ee, /* 4.906 Mhz */ 395 0xd5b4, /* 4.9152 Mhz */ 396 0x0a00, /* 5 Mhz */ 397 0x4e27, /* 5.12 Mhz */ 398 0x1902, /* 6 Mhz */ 399 0xec1c, /* 6.144 Mhz */ 400 0x1b23, /* 7.3728 Mhz */ 401 0x0640, /* 8 Mhz */ 402 0xb11c /* 8.192 Mhz */ 403 }; 404 405 #define DID0_VER_MASK 0x70000000 406 #define DID0_VER_0 0x00000000 407 #define DID0_VER_1 0x10000000 408 409 #define DID0_CLASS_MASK 0x00FF0000 410 #define DID0_CLASS_SANDSTORM 0x00000000 411 #define DID0_CLASS_FURY 0x00010000 412 413 static int ssys_board_class(const ssys_state *s) 414 { 415 uint32_t did0 = s->board->did0; 416 switch (did0 & DID0_VER_MASK) { 417 case DID0_VER_0: 418 return DID0_CLASS_SANDSTORM; 419 case DID0_VER_1: 420 switch (did0 & DID0_CLASS_MASK) { 421 case DID0_CLASS_SANDSTORM: 422 case DID0_CLASS_FURY: 423 return did0 & DID0_CLASS_MASK; 424 } 425 /* for unknown classes, fall through */ 426 default: 427 hw_error("ssys_board_class: Unknown class 0x%08x\n", did0); 428 } 429 } 430 431 static uint64_t ssys_read(void *opaque, hwaddr offset, 432 unsigned size) 433 { 434 ssys_state *s = (ssys_state *)opaque; 435 436 switch (offset) { 437 case 0x000: /* DID0 */ 438 return s->board->did0; 439 case 0x004: /* DID1 */ 440 return s->board->did1; 441 case 0x008: /* DC0 */ 442 return s->board->dc0; 443 case 0x010: /* DC1 */ 444 return s->board->dc1; 445 case 0x014: /* DC2 */ 446 return s->board->dc2; 447 case 0x018: /* DC3 */ 448 return s->board->dc3; 449 case 0x01c: /* DC4 */ 450 return s->board->dc4; 451 case 0x030: /* PBORCTL */ 452 return s->pborctl; 453 case 0x034: /* LDOPCTL */ 454 return s->ldopctl; 455 case 0x040: /* SRCR0 */ 456 return 0; 457 case 0x044: /* SRCR1 */ 458 return 0; 459 case 0x048: /* SRCR2 */ 460 return 0; 461 case 0x050: /* RIS */ 462 return s->int_status; 463 case 0x054: /* IMC */ 464 return s->int_mask; 465 case 0x058: /* MISC */ 466 return s->int_status & s->int_mask; 467 case 0x05c: /* RESC */ 468 return s->resc; 469 case 0x060: /* RCC */ 470 return s->rcc; 471 case 0x064: /* PLLCFG */ 472 { 473 int xtal; 474 xtal = (s->rcc >> 6) & 0xf; 475 switch (ssys_board_class(s)) { 476 case DID0_CLASS_FURY: 477 return pllcfg_fury[xtal]; 478 case DID0_CLASS_SANDSTORM: 479 return pllcfg_sandstorm[xtal]; 480 default: 481 hw_error("ssys_read: Unhandled class for PLLCFG read.\n"); 482 return 0; 483 } 484 } 485 case 0x070: /* RCC2 */ 486 return s->rcc2; 487 case 0x100: /* RCGC0 */ 488 return s->rcgc[0]; 489 case 0x104: /* RCGC1 */ 490 return s->rcgc[1]; 491 case 0x108: /* RCGC2 */ 492 return s->rcgc[2]; 493 case 0x110: /* SCGC0 */ 494 return s->scgc[0]; 495 case 0x114: /* SCGC1 */ 496 return s->scgc[1]; 497 case 0x118: /* SCGC2 */ 498 return s->scgc[2]; 499 case 0x120: /* DCGC0 */ 500 return s->dcgc[0]; 501 case 0x124: /* DCGC1 */ 502 return s->dcgc[1]; 503 case 0x128: /* DCGC2 */ 504 return s->dcgc[2]; 505 case 0x150: /* CLKVCLR */ 506 return s->clkvclr; 507 case 0x160: /* LDOARST */ 508 return s->ldoarst; 509 case 0x1e0: /* USER0 */ 510 return s->user0; 511 case 0x1e4: /* USER1 */ 512 return s->user1; 513 default: 514 hw_error("ssys_read: Bad offset 0x%x\n", (int)offset); 515 return 0; 516 } 517 } 518 519 static bool ssys_use_rcc2(ssys_state *s) 520 { 521 return (s->rcc2 >> 31) & 0x1; 522 } 523 524 /* 525 * Caculate the sys. clock period in ms. 526 */ 527 static void ssys_calculate_system_clock(ssys_state *s) 528 { 529 if (ssys_use_rcc2(s)) { 530 system_clock_scale = 5 * (((s->rcc2 >> 23) & 0x3f) + 1); 531 } else { 532 system_clock_scale = 5 * (((s->rcc >> 23) & 0xf) + 1); 533 } 534 } 535 536 static void ssys_write(void *opaque, hwaddr offset, 537 uint64_t value, unsigned size) 538 { 539 ssys_state *s = (ssys_state *)opaque; 540 541 switch (offset) { 542 case 0x030: /* PBORCTL */ 543 s->pborctl = value & 0xffff; 544 break; 545 case 0x034: /* LDOPCTL */ 546 s->ldopctl = value & 0x1f; 547 break; 548 case 0x040: /* SRCR0 */ 549 case 0x044: /* SRCR1 */ 550 case 0x048: /* SRCR2 */ 551 fprintf(stderr, "Peripheral reset not implemented\n"); 552 break; 553 case 0x054: /* IMC */ 554 s->int_mask = value & 0x7f; 555 break; 556 case 0x058: /* MISC */ 557 s->int_status &= ~value; 558 break; 559 case 0x05c: /* RESC */ 560 s->resc = value & 0x3f; 561 break; 562 case 0x060: /* RCC */ 563 if ((s->rcc & (1 << 13)) != 0 && (value & (1 << 13)) == 0) { 564 /* PLL enable. */ 565 s->int_status |= (1 << 6); 566 } 567 s->rcc = value; 568 ssys_calculate_system_clock(s); 569 break; 570 case 0x070: /* RCC2 */ 571 if (ssys_board_class(s) == DID0_CLASS_SANDSTORM) { 572 break; 573 } 574 575 if ((s->rcc2 & (1 << 13)) != 0 && (value & (1 << 13)) == 0) { 576 /* PLL enable. */ 577 s->int_status |= (1 << 6); 578 } 579 s->rcc2 = value; 580 ssys_calculate_system_clock(s); 581 break; 582 case 0x100: /* RCGC0 */ 583 s->rcgc[0] = value; 584 break; 585 case 0x104: /* RCGC1 */ 586 s->rcgc[1] = value; 587 break; 588 case 0x108: /* RCGC2 */ 589 s->rcgc[2] = value; 590 break; 591 case 0x110: /* SCGC0 */ 592 s->scgc[0] = value; 593 break; 594 case 0x114: /* SCGC1 */ 595 s->scgc[1] = value; 596 break; 597 case 0x118: /* SCGC2 */ 598 s->scgc[2] = value; 599 break; 600 case 0x120: /* DCGC0 */ 601 s->dcgc[0] = value; 602 break; 603 case 0x124: /* DCGC1 */ 604 s->dcgc[1] = value; 605 break; 606 case 0x128: /* DCGC2 */ 607 s->dcgc[2] = value; 608 break; 609 case 0x150: /* CLKVCLR */ 610 s->clkvclr = value; 611 break; 612 case 0x160: /* LDOARST */ 613 s->ldoarst = value; 614 break; 615 default: 616 hw_error("ssys_write: Bad offset 0x%x\n", (int)offset); 617 } 618 ssys_update(s); 619 } 620 621 static const MemoryRegionOps ssys_ops = { 622 .read = ssys_read, 623 .write = ssys_write, 624 .endianness = DEVICE_NATIVE_ENDIAN, 625 }; 626 627 static void ssys_reset(void *opaque) 628 { 629 ssys_state *s = (ssys_state *)opaque; 630 631 s->pborctl = 0x7ffd; 632 s->rcc = 0x078e3ac0; 633 634 if (ssys_board_class(s) == DID0_CLASS_SANDSTORM) { 635 s->rcc2 = 0; 636 } else { 637 s->rcc2 = 0x07802810; 638 } 639 s->rcgc[0] = 1; 640 s->scgc[0] = 1; 641 s->dcgc[0] = 1; 642 ssys_calculate_system_clock(s); 643 } 644 645 static int stellaris_sys_post_load(void *opaque, int version_id) 646 { 647 ssys_state *s = opaque; 648 649 ssys_calculate_system_clock(s); 650 651 return 0; 652 } 653 654 static const VMStateDescription vmstate_stellaris_sys = { 655 .name = "stellaris_sys", 656 .version_id = 2, 657 .minimum_version_id = 1, 658 .post_load = stellaris_sys_post_load, 659 .fields = (VMStateField[]) { 660 VMSTATE_UINT32(pborctl, ssys_state), 661 VMSTATE_UINT32(ldopctl, ssys_state), 662 VMSTATE_UINT32(int_mask, ssys_state), 663 VMSTATE_UINT32(int_status, ssys_state), 664 VMSTATE_UINT32(resc, ssys_state), 665 VMSTATE_UINT32(rcc, ssys_state), 666 VMSTATE_UINT32_V(rcc2, ssys_state, 2), 667 VMSTATE_UINT32_ARRAY(rcgc, ssys_state, 3), 668 VMSTATE_UINT32_ARRAY(scgc, ssys_state, 3), 669 VMSTATE_UINT32_ARRAY(dcgc, ssys_state, 3), 670 VMSTATE_UINT32(clkvclr, ssys_state), 671 VMSTATE_UINT32(ldoarst, ssys_state), 672 VMSTATE_END_OF_LIST() 673 } 674 }; 675 676 static int stellaris_sys_init(uint32_t base, qemu_irq irq, 677 stellaris_board_info * board, 678 uint8_t *macaddr) 679 { 680 ssys_state *s; 681 682 s = g_new0(ssys_state, 1); 683 s->irq = irq; 684 s->board = board; 685 /* Most devices come preprogrammed with a MAC address in the user data. */ 686 s->user0 = macaddr[0] | (macaddr[1] << 8) | (macaddr[2] << 16); 687 s->user1 = macaddr[3] | (macaddr[4] << 8) | (macaddr[5] << 16); 688 689 memory_region_init_io(&s->iomem, NULL, &ssys_ops, s, "ssys", 0x00001000); 690 memory_region_add_subregion(get_system_memory(), base, &s->iomem); 691 ssys_reset(s); 692 vmstate_register(NULL, -1, &vmstate_stellaris_sys, s); 693 return 0; 694 } 695 696 697 /* I2C controller. */ 698 699 #define TYPE_STELLARIS_I2C "stellaris-i2c" 700 #define STELLARIS_I2C(obj) \ 701 OBJECT_CHECK(stellaris_i2c_state, (obj), TYPE_STELLARIS_I2C) 702 703 typedef struct { 704 SysBusDevice parent_obj; 705 706 I2CBus *bus; 707 qemu_irq irq; 708 MemoryRegion iomem; 709 uint32_t msa; 710 uint32_t mcs; 711 uint32_t mdr; 712 uint32_t mtpr; 713 uint32_t mimr; 714 uint32_t mris; 715 uint32_t mcr; 716 } stellaris_i2c_state; 717 718 #define STELLARIS_I2C_MCS_BUSY 0x01 719 #define STELLARIS_I2C_MCS_ERROR 0x02 720 #define STELLARIS_I2C_MCS_ADRACK 0x04 721 #define STELLARIS_I2C_MCS_DATACK 0x08 722 #define STELLARIS_I2C_MCS_ARBLST 0x10 723 #define STELLARIS_I2C_MCS_IDLE 0x20 724 #define STELLARIS_I2C_MCS_BUSBSY 0x40 725 726 static uint64_t stellaris_i2c_read(void *opaque, hwaddr offset, 727 unsigned size) 728 { 729 stellaris_i2c_state *s = (stellaris_i2c_state *)opaque; 730 731 switch (offset) { 732 case 0x00: /* MSA */ 733 return s->msa; 734 case 0x04: /* MCS */ 735 /* We don't emulate timing, so the controller is never busy. */ 736 return s->mcs | STELLARIS_I2C_MCS_IDLE; 737 case 0x08: /* MDR */ 738 return s->mdr; 739 case 0x0c: /* MTPR */ 740 return s->mtpr; 741 case 0x10: /* MIMR */ 742 return s->mimr; 743 case 0x14: /* MRIS */ 744 return s->mris; 745 case 0x18: /* MMIS */ 746 return s->mris & s->mimr; 747 case 0x20: /* MCR */ 748 return s->mcr; 749 default: 750 hw_error("strllaris_i2c_read: Bad offset 0x%x\n", (int)offset); 751 return 0; 752 } 753 } 754 755 static void stellaris_i2c_update(stellaris_i2c_state *s) 756 { 757 int level; 758 759 level = (s->mris & s->mimr) != 0; 760 qemu_set_irq(s->irq, level); 761 } 762 763 static void stellaris_i2c_write(void *opaque, hwaddr offset, 764 uint64_t value, unsigned size) 765 { 766 stellaris_i2c_state *s = (stellaris_i2c_state *)opaque; 767 768 switch (offset) { 769 case 0x00: /* MSA */ 770 s->msa = value & 0xff; 771 break; 772 case 0x04: /* MCS */ 773 if ((s->mcr & 0x10) == 0) { 774 /* Disabled. Do nothing. */ 775 break; 776 } 777 /* Grab the bus if this is starting a transfer. */ 778 if ((value & 2) && (s->mcs & STELLARIS_I2C_MCS_BUSBSY) == 0) { 779 if (i2c_start_transfer(s->bus, s->msa >> 1, s->msa & 1)) { 780 s->mcs |= STELLARIS_I2C_MCS_ARBLST; 781 } else { 782 s->mcs &= ~STELLARIS_I2C_MCS_ARBLST; 783 s->mcs |= STELLARIS_I2C_MCS_BUSBSY; 784 } 785 } 786 /* If we don't have the bus then indicate an error. */ 787 if (!i2c_bus_busy(s->bus) 788 || (s->mcs & STELLARIS_I2C_MCS_BUSBSY) == 0) { 789 s->mcs |= STELLARIS_I2C_MCS_ERROR; 790 break; 791 } 792 s->mcs &= ~STELLARIS_I2C_MCS_ERROR; 793 if (value & 1) { 794 /* Transfer a byte. */ 795 /* TODO: Handle errors. */ 796 if (s->msa & 1) { 797 /* Recv */ 798 s->mdr = i2c_recv(s->bus) & 0xff; 799 } else { 800 /* Send */ 801 i2c_send(s->bus, s->mdr); 802 } 803 /* Raise an interrupt. */ 804 s->mris |= 1; 805 } 806 if (value & 4) { 807 /* Finish transfer. */ 808 i2c_end_transfer(s->bus); 809 s->mcs &= ~STELLARIS_I2C_MCS_BUSBSY; 810 } 811 break; 812 case 0x08: /* MDR */ 813 s->mdr = value & 0xff; 814 break; 815 case 0x0c: /* MTPR */ 816 s->mtpr = value & 0xff; 817 break; 818 case 0x10: /* MIMR */ 819 s->mimr = 1; 820 break; 821 case 0x1c: /* MICR */ 822 s->mris &= ~value; 823 break; 824 case 0x20: /* MCR */ 825 if (value & 1) 826 hw_error( 827 "stellaris_i2c_write: Loopback not implemented\n"); 828 if (value & 0x20) 829 hw_error( 830 "stellaris_i2c_write: Slave mode not implemented\n"); 831 s->mcr = value & 0x31; 832 break; 833 default: 834 hw_error("stellaris_i2c_write: Bad offset 0x%x\n", 835 (int)offset); 836 } 837 stellaris_i2c_update(s); 838 } 839 840 static void stellaris_i2c_reset(stellaris_i2c_state *s) 841 { 842 if (s->mcs & STELLARIS_I2C_MCS_BUSBSY) 843 i2c_end_transfer(s->bus); 844 845 s->msa = 0; 846 s->mcs = 0; 847 s->mdr = 0; 848 s->mtpr = 1; 849 s->mimr = 0; 850 s->mris = 0; 851 s->mcr = 0; 852 stellaris_i2c_update(s); 853 } 854 855 static const MemoryRegionOps stellaris_i2c_ops = { 856 .read = stellaris_i2c_read, 857 .write = stellaris_i2c_write, 858 .endianness = DEVICE_NATIVE_ENDIAN, 859 }; 860 861 static const VMStateDescription vmstate_stellaris_i2c = { 862 .name = "stellaris_i2c", 863 .version_id = 1, 864 .minimum_version_id = 1, 865 .fields = (VMStateField[]) { 866 VMSTATE_UINT32(msa, stellaris_i2c_state), 867 VMSTATE_UINT32(mcs, stellaris_i2c_state), 868 VMSTATE_UINT32(mdr, stellaris_i2c_state), 869 VMSTATE_UINT32(mtpr, stellaris_i2c_state), 870 VMSTATE_UINT32(mimr, stellaris_i2c_state), 871 VMSTATE_UINT32(mris, stellaris_i2c_state), 872 VMSTATE_UINT32(mcr, stellaris_i2c_state), 873 VMSTATE_END_OF_LIST() 874 } 875 }; 876 877 static void stellaris_i2c_init(Object *obj) 878 { 879 DeviceState *dev = DEVICE(obj); 880 stellaris_i2c_state *s = STELLARIS_I2C(obj); 881 SysBusDevice *sbd = SYS_BUS_DEVICE(obj); 882 I2CBus *bus; 883 884 sysbus_init_irq(sbd, &s->irq); 885 bus = i2c_init_bus(dev, "i2c"); 886 s->bus = bus; 887 888 memory_region_init_io(&s->iomem, obj, &stellaris_i2c_ops, s, 889 "i2c", 0x1000); 890 sysbus_init_mmio(sbd, &s->iomem); 891 /* ??? For now we only implement the master interface. */ 892 stellaris_i2c_reset(s); 893 } 894 895 /* Analogue to Digital Converter. This is only partially implemented, 896 enough for applications that use a combined ADC and timer tick. */ 897 898 #define STELLARIS_ADC_EM_CONTROLLER 0 899 #define STELLARIS_ADC_EM_COMP 1 900 #define STELLARIS_ADC_EM_EXTERNAL 4 901 #define STELLARIS_ADC_EM_TIMER 5 902 #define STELLARIS_ADC_EM_PWM0 6 903 #define STELLARIS_ADC_EM_PWM1 7 904 #define STELLARIS_ADC_EM_PWM2 8 905 906 #define STELLARIS_ADC_FIFO_EMPTY 0x0100 907 #define STELLARIS_ADC_FIFO_FULL 0x1000 908 909 #define TYPE_STELLARIS_ADC "stellaris-adc" 910 #define STELLARIS_ADC(obj) \ 911 OBJECT_CHECK(stellaris_adc_state, (obj), TYPE_STELLARIS_ADC) 912 913 typedef struct StellarisADCState { 914 SysBusDevice parent_obj; 915 916 MemoryRegion iomem; 917 uint32_t actss; 918 uint32_t ris; 919 uint32_t im; 920 uint32_t emux; 921 uint32_t ostat; 922 uint32_t ustat; 923 uint32_t sspri; 924 uint32_t sac; 925 struct { 926 uint32_t state; 927 uint32_t data[16]; 928 } fifo[4]; 929 uint32_t ssmux[4]; 930 uint32_t ssctl[4]; 931 uint32_t noise; 932 qemu_irq irq[4]; 933 } stellaris_adc_state; 934 935 static uint32_t stellaris_adc_fifo_read(stellaris_adc_state *s, int n) 936 { 937 int tail; 938 939 tail = s->fifo[n].state & 0xf; 940 if (s->fifo[n].state & STELLARIS_ADC_FIFO_EMPTY) { 941 s->ustat |= 1 << n; 942 } else { 943 s->fifo[n].state = (s->fifo[n].state & ~0xf) | ((tail + 1) & 0xf); 944 s->fifo[n].state &= ~STELLARIS_ADC_FIFO_FULL; 945 if (tail + 1 == ((s->fifo[n].state >> 4) & 0xf)) 946 s->fifo[n].state |= STELLARIS_ADC_FIFO_EMPTY; 947 } 948 return s->fifo[n].data[tail]; 949 } 950 951 static void stellaris_adc_fifo_write(stellaris_adc_state *s, int n, 952 uint32_t value) 953 { 954 int head; 955 956 /* TODO: Real hardware has limited size FIFOs. We have a full 16 entry 957 FIFO fir each sequencer. */ 958 head = (s->fifo[n].state >> 4) & 0xf; 959 if (s->fifo[n].state & STELLARIS_ADC_FIFO_FULL) { 960 s->ostat |= 1 << n; 961 return; 962 } 963 s->fifo[n].data[head] = value; 964 head = (head + 1) & 0xf; 965 s->fifo[n].state &= ~STELLARIS_ADC_FIFO_EMPTY; 966 s->fifo[n].state = (s->fifo[n].state & ~0xf0) | (head << 4); 967 if ((s->fifo[n].state & 0xf) == head) 968 s->fifo[n].state |= STELLARIS_ADC_FIFO_FULL; 969 } 970 971 static void stellaris_adc_update(stellaris_adc_state *s) 972 { 973 int level; 974 int n; 975 976 for (n = 0; n < 4; n++) { 977 level = (s->ris & s->im & (1 << n)) != 0; 978 qemu_set_irq(s->irq[n], level); 979 } 980 } 981 982 static void stellaris_adc_trigger(void *opaque, int irq, int level) 983 { 984 stellaris_adc_state *s = (stellaris_adc_state *)opaque; 985 int n; 986 987 for (n = 0; n < 4; n++) { 988 if ((s->actss & (1 << n)) == 0) { 989 continue; 990 } 991 992 if (((s->emux >> (n * 4)) & 0xff) != 5) { 993 continue; 994 } 995 996 /* Some applications use the ADC as a random number source, so introduce 997 some variation into the signal. */ 998 s->noise = s->noise * 314159 + 1; 999 /* ??? actual inputs not implemented. Return an arbitrary value. */ 1000 stellaris_adc_fifo_write(s, n, 0x200 + ((s->noise >> 16) & 7)); 1001 s->ris |= (1 << n); 1002 stellaris_adc_update(s); 1003 } 1004 } 1005 1006 static void stellaris_adc_reset(stellaris_adc_state *s) 1007 { 1008 int n; 1009 1010 for (n = 0; n < 4; n++) { 1011 s->ssmux[n] = 0; 1012 s->ssctl[n] = 0; 1013 s->fifo[n].state = STELLARIS_ADC_FIFO_EMPTY; 1014 } 1015 } 1016 1017 static uint64_t stellaris_adc_read(void *opaque, hwaddr offset, 1018 unsigned size) 1019 { 1020 stellaris_adc_state *s = (stellaris_adc_state *)opaque; 1021 1022 /* TODO: Implement this. */ 1023 if (offset >= 0x40 && offset < 0xc0) { 1024 int n; 1025 n = (offset - 0x40) >> 5; 1026 switch (offset & 0x1f) { 1027 case 0x00: /* SSMUX */ 1028 return s->ssmux[n]; 1029 case 0x04: /* SSCTL */ 1030 return s->ssctl[n]; 1031 case 0x08: /* SSFIFO */ 1032 return stellaris_adc_fifo_read(s, n); 1033 case 0x0c: /* SSFSTAT */ 1034 return s->fifo[n].state; 1035 default: 1036 break; 1037 } 1038 } 1039 switch (offset) { 1040 case 0x00: /* ACTSS */ 1041 return s->actss; 1042 case 0x04: /* RIS */ 1043 return s->ris; 1044 case 0x08: /* IM */ 1045 return s->im; 1046 case 0x0c: /* ISC */ 1047 return s->ris & s->im; 1048 case 0x10: /* OSTAT */ 1049 return s->ostat; 1050 case 0x14: /* EMUX */ 1051 return s->emux; 1052 case 0x18: /* USTAT */ 1053 return s->ustat; 1054 case 0x20: /* SSPRI */ 1055 return s->sspri; 1056 case 0x30: /* SAC */ 1057 return s->sac; 1058 default: 1059 hw_error("strllaris_adc_read: Bad offset 0x%x\n", 1060 (int)offset); 1061 return 0; 1062 } 1063 } 1064 1065 static void stellaris_adc_write(void *opaque, hwaddr offset, 1066 uint64_t value, unsigned size) 1067 { 1068 stellaris_adc_state *s = (stellaris_adc_state *)opaque; 1069 1070 /* TODO: Implement this. */ 1071 if (offset >= 0x40 && offset < 0xc0) { 1072 int n; 1073 n = (offset - 0x40) >> 5; 1074 switch (offset & 0x1f) { 1075 case 0x00: /* SSMUX */ 1076 s->ssmux[n] = value & 0x33333333; 1077 return; 1078 case 0x04: /* SSCTL */ 1079 if (value != 6) { 1080 hw_error("ADC: Unimplemented sequence %" PRIx64 "\n", 1081 value); 1082 } 1083 s->ssctl[n] = value; 1084 return; 1085 default: 1086 break; 1087 } 1088 } 1089 switch (offset) { 1090 case 0x00: /* ACTSS */ 1091 s->actss = value & 0xf; 1092 break; 1093 case 0x08: /* IM */ 1094 s->im = value; 1095 break; 1096 case 0x0c: /* ISC */ 1097 s->ris &= ~value; 1098 break; 1099 case 0x10: /* OSTAT */ 1100 s->ostat &= ~value; 1101 break; 1102 case 0x14: /* EMUX */ 1103 s->emux = value; 1104 break; 1105 case 0x18: /* USTAT */ 1106 s->ustat &= ~value; 1107 break; 1108 case 0x20: /* SSPRI */ 1109 s->sspri = value; 1110 break; 1111 case 0x28: /* PSSI */ 1112 hw_error("Not implemented: ADC sample initiate\n"); 1113 break; 1114 case 0x30: /* SAC */ 1115 s->sac = value; 1116 break; 1117 default: 1118 hw_error("stellaris_adc_write: Bad offset 0x%x\n", (int)offset); 1119 } 1120 stellaris_adc_update(s); 1121 } 1122 1123 static const MemoryRegionOps stellaris_adc_ops = { 1124 .read = stellaris_adc_read, 1125 .write = stellaris_adc_write, 1126 .endianness = DEVICE_NATIVE_ENDIAN, 1127 }; 1128 1129 static const VMStateDescription vmstate_stellaris_adc = { 1130 .name = "stellaris_adc", 1131 .version_id = 1, 1132 .minimum_version_id = 1, 1133 .fields = (VMStateField[]) { 1134 VMSTATE_UINT32(actss, stellaris_adc_state), 1135 VMSTATE_UINT32(ris, stellaris_adc_state), 1136 VMSTATE_UINT32(im, stellaris_adc_state), 1137 VMSTATE_UINT32(emux, stellaris_adc_state), 1138 VMSTATE_UINT32(ostat, stellaris_adc_state), 1139 VMSTATE_UINT32(ustat, stellaris_adc_state), 1140 VMSTATE_UINT32(sspri, stellaris_adc_state), 1141 VMSTATE_UINT32(sac, stellaris_adc_state), 1142 VMSTATE_UINT32(fifo[0].state, stellaris_adc_state), 1143 VMSTATE_UINT32_ARRAY(fifo[0].data, stellaris_adc_state, 16), 1144 VMSTATE_UINT32(ssmux[0], stellaris_adc_state), 1145 VMSTATE_UINT32(ssctl[0], stellaris_adc_state), 1146 VMSTATE_UINT32(fifo[1].state, stellaris_adc_state), 1147 VMSTATE_UINT32_ARRAY(fifo[1].data, stellaris_adc_state, 16), 1148 VMSTATE_UINT32(ssmux[1], stellaris_adc_state), 1149 VMSTATE_UINT32(ssctl[1], stellaris_adc_state), 1150 VMSTATE_UINT32(fifo[2].state, stellaris_adc_state), 1151 VMSTATE_UINT32_ARRAY(fifo[2].data, stellaris_adc_state, 16), 1152 VMSTATE_UINT32(ssmux[2], stellaris_adc_state), 1153 VMSTATE_UINT32(ssctl[2], stellaris_adc_state), 1154 VMSTATE_UINT32(fifo[3].state, stellaris_adc_state), 1155 VMSTATE_UINT32_ARRAY(fifo[3].data, stellaris_adc_state, 16), 1156 VMSTATE_UINT32(ssmux[3], stellaris_adc_state), 1157 VMSTATE_UINT32(ssctl[3], stellaris_adc_state), 1158 VMSTATE_UINT32(noise, stellaris_adc_state), 1159 VMSTATE_END_OF_LIST() 1160 } 1161 }; 1162 1163 static void stellaris_adc_init(Object *obj) 1164 { 1165 DeviceState *dev = DEVICE(obj); 1166 stellaris_adc_state *s = STELLARIS_ADC(obj); 1167 SysBusDevice *sbd = SYS_BUS_DEVICE(obj); 1168 int n; 1169 1170 for (n = 0; n < 4; n++) { 1171 sysbus_init_irq(sbd, &s->irq[n]); 1172 } 1173 1174 memory_region_init_io(&s->iomem, obj, &stellaris_adc_ops, s, 1175 "adc", 0x1000); 1176 sysbus_init_mmio(sbd, &s->iomem); 1177 stellaris_adc_reset(s); 1178 qdev_init_gpio_in(dev, stellaris_adc_trigger, 1); 1179 } 1180 1181 static 1182 void do_sys_reset(void *opaque, int n, int level) 1183 { 1184 if (level) { 1185 qemu_system_reset_request(); 1186 } 1187 } 1188 1189 /* Board init. */ 1190 static stellaris_board_info stellaris_boards[] = { 1191 { "LM3S811EVB", 1192 0, 1193 0x0032000e, 1194 0x001f001f, /* dc0 */ 1195 0x001132bf, 1196 0x01071013, 1197 0x3f0f01ff, 1198 0x0000001f, 1199 BP_OLED_I2C 1200 }, 1201 { "LM3S6965EVB", 1202 0x10010002, 1203 0x1073402e, 1204 0x00ff007f, /* dc0 */ 1205 0x001133ff, 1206 0x030f5317, 1207 0x0f0f87ff, 1208 0x5000007f, 1209 BP_OLED_SSI | BP_GAMEPAD 1210 } 1211 }; 1212 1213 static void stellaris_init(const char *kernel_filename, const char *cpu_model, 1214 stellaris_board_info *board) 1215 { 1216 static const int uart_irq[] = {5, 6, 33, 34}; 1217 static const int timer_irq[] = {19, 21, 23, 35}; 1218 static const uint32_t gpio_addr[7] = 1219 { 0x40004000, 0x40005000, 0x40006000, 0x40007000, 1220 0x40024000, 0x40025000, 0x40026000}; 1221 static const int gpio_irq[7] = {0, 1, 2, 3, 4, 30, 31}; 1222 1223 DeviceState *gpio_dev[7], *nvic; 1224 qemu_irq gpio_in[7][8]; 1225 qemu_irq gpio_out[7][8]; 1226 qemu_irq adc; 1227 int sram_size; 1228 int flash_size; 1229 I2CBus *i2c; 1230 DeviceState *dev; 1231 int i; 1232 int j; 1233 1234 MemoryRegion *sram = g_new(MemoryRegion, 1); 1235 MemoryRegion *flash = g_new(MemoryRegion, 1); 1236 MemoryRegion *system_memory = get_system_memory(); 1237 1238 flash_size = (((board->dc0 & 0xffff) + 1) << 1) * 1024; 1239 sram_size = ((board->dc0 >> 18) + 1) * 1024; 1240 1241 /* Flash programming is done via the SCU, so pretend it is ROM. */ 1242 memory_region_init_ram(flash, NULL, "stellaris.flash", flash_size, 1243 &error_fatal); 1244 vmstate_register_ram_global(flash); 1245 memory_region_set_readonly(flash, true); 1246 memory_region_add_subregion(system_memory, 0, flash); 1247 1248 memory_region_init_ram(sram, NULL, "stellaris.sram", sram_size, 1249 &error_fatal); 1250 vmstate_register_ram_global(sram); 1251 memory_region_add_subregion(system_memory, 0x20000000, sram); 1252 1253 nvic = armv7m_init(system_memory, flash_size, NUM_IRQ_LINES, 1254 kernel_filename, cpu_model); 1255 1256 qdev_connect_gpio_out_named(nvic, "SYSRESETREQ", 0, 1257 qemu_allocate_irq(&do_sys_reset, NULL, 0)); 1258 1259 if (board->dc1 & (1 << 16)) { 1260 dev = sysbus_create_varargs(TYPE_STELLARIS_ADC, 0x40038000, 1261 qdev_get_gpio_in(nvic, 14), 1262 qdev_get_gpio_in(nvic, 15), 1263 qdev_get_gpio_in(nvic, 16), 1264 qdev_get_gpio_in(nvic, 17), 1265 NULL); 1266 adc = qdev_get_gpio_in(dev, 0); 1267 } else { 1268 adc = NULL; 1269 } 1270 for (i = 0; i < 4; i++) { 1271 if (board->dc2 & (0x10000 << i)) { 1272 dev = sysbus_create_simple(TYPE_STELLARIS_GPTM, 1273 0x40030000 + i * 0x1000, 1274 qdev_get_gpio_in(nvic, timer_irq[i])); 1275 /* TODO: This is incorrect, but we get away with it because 1276 the ADC output is only ever pulsed. */ 1277 qdev_connect_gpio_out(dev, 0, adc); 1278 } 1279 } 1280 1281 stellaris_sys_init(0x400fe000, qdev_get_gpio_in(nvic, 28), 1282 board, nd_table[0].macaddr.a); 1283 1284 for (i = 0; i < 7; i++) { 1285 if (board->dc4 & (1 << i)) { 1286 gpio_dev[i] = sysbus_create_simple("pl061_luminary", gpio_addr[i], 1287 qdev_get_gpio_in(nvic, 1288 gpio_irq[i])); 1289 for (j = 0; j < 8; j++) { 1290 gpio_in[i][j] = qdev_get_gpio_in(gpio_dev[i], j); 1291 gpio_out[i][j] = NULL; 1292 } 1293 } 1294 } 1295 1296 if (board->dc2 & (1 << 12)) { 1297 dev = sysbus_create_simple(TYPE_STELLARIS_I2C, 0x40020000, 1298 qdev_get_gpio_in(nvic, 8)); 1299 i2c = (I2CBus *)qdev_get_child_bus(dev, "i2c"); 1300 if (board->peripherals & BP_OLED_I2C) { 1301 i2c_create_slave(i2c, "ssd0303", 0x3d); 1302 } 1303 } 1304 1305 for (i = 0; i < 4; i++) { 1306 if (board->dc2 & (1 << i)) { 1307 pl011_luminary_create(0x4000c000 + i * 0x1000, 1308 qdev_get_gpio_in(nvic, uart_irq[i]), 1309 serial_hds[i]); 1310 } 1311 } 1312 if (board->dc2 & (1 << 4)) { 1313 dev = sysbus_create_simple("pl022", 0x40008000, 1314 qdev_get_gpio_in(nvic, 7)); 1315 if (board->peripherals & BP_OLED_SSI) { 1316 void *bus; 1317 DeviceState *sddev; 1318 DeviceState *ssddev; 1319 1320 /* Some boards have both an OLED controller and SD card connected to 1321 * the same SSI port, with the SD card chip select connected to a 1322 * GPIO pin. Technically the OLED chip select is connected to the 1323 * SSI Fss pin. We do not bother emulating that as both devices 1324 * should never be selected simultaneously, and our OLED controller 1325 * ignores stray 0xff commands that occur when deselecting the SD 1326 * card. 1327 */ 1328 bus = qdev_get_child_bus(dev, "ssi"); 1329 1330 sddev = ssi_create_slave(bus, "ssi-sd"); 1331 ssddev = ssi_create_slave(bus, "ssd0323"); 1332 gpio_out[GPIO_D][0] = qemu_irq_split( 1333 qdev_get_gpio_in_named(sddev, SSI_GPIO_CS, 0), 1334 qdev_get_gpio_in_named(ssddev, SSI_GPIO_CS, 0)); 1335 gpio_out[GPIO_C][7] = qdev_get_gpio_in(ssddev, 0); 1336 1337 /* Make sure the select pin is high. */ 1338 qemu_irq_raise(gpio_out[GPIO_D][0]); 1339 } 1340 } 1341 if (board->dc4 & (1 << 28)) { 1342 DeviceState *enet; 1343 1344 qemu_check_nic_model(&nd_table[0], "stellaris"); 1345 1346 enet = qdev_create(NULL, "stellaris_enet"); 1347 qdev_set_nic_properties(enet, &nd_table[0]); 1348 qdev_init_nofail(enet); 1349 sysbus_mmio_map(SYS_BUS_DEVICE(enet), 0, 0x40048000); 1350 sysbus_connect_irq(SYS_BUS_DEVICE(enet), 0, qdev_get_gpio_in(nvic, 42)); 1351 } 1352 if (board->peripherals & BP_GAMEPAD) { 1353 qemu_irq gpad_irq[5]; 1354 static const int gpad_keycode[5] = { 0xc8, 0xd0, 0xcb, 0xcd, 0x1d }; 1355 1356 gpad_irq[0] = qemu_irq_invert(gpio_in[GPIO_E][0]); /* up */ 1357 gpad_irq[1] = qemu_irq_invert(gpio_in[GPIO_E][1]); /* down */ 1358 gpad_irq[2] = qemu_irq_invert(gpio_in[GPIO_E][2]); /* left */ 1359 gpad_irq[3] = qemu_irq_invert(gpio_in[GPIO_E][3]); /* right */ 1360 gpad_irq[4] = qemu_irq_invert(gpio_in[GPIO_F][1]); /* select */ 1361 1362 stellaris_gamepad_init(5, gpad_irq, gpad_keycode); 1363 } 1364 for (i = 0; i < 7; i++) { 1365 if (board->dc4 & (1 << i)) { 1366 for (j = 0; j < 8; j++) { 1367 if (gpio_out[i][j]) { 1368 qdev_connect_gpio_out(gpio_dev[i], j, gpio_out[i][j]); 1369 } 1370 } 1371 } 1372 } 1373 } 1374 1375 /* FIXME: Figure out how to generate these from stellaris_boards. */ 1376 static void lm3s811evb_init(MachineState *machine) 1377 { 1378 const char *cpu_model = machine->cpu_model; 1379 const char *kernel_filename = machine->kernel_filename; 1380 stellaris_init(kernel_filename, cpu_model, &stellaris_boards[0]); 1381 } 1382 1383 static void lm3s6965evb_init(MachineState *machine) 1384 { 1385 const char *cpu_model = machine->cpu_model; 1386 const char *kernel_filename = machine->kernel_filename; 1387 stellaris_init(kernel_filename, cpu_model, &stellaris_boards[1]); 1388 } 1389 1390 static void lm3s811evb_class_init(ObjectClass *oc, void *data) 1391 { 1392 MachineClass *mc = MACHINE_CLASS(oc); 1393 1394 mc->desc = "Stellaris LM3S811EVB"; 1395 mc->init = lm3s811evb_init; 1396 } 1397 1398 static const TypeInfo lm3s811evb_type = { 1399 .name = MACHINE_TYPE_NAME("lm3s811evb"), 1400 .parent = TYPE_MACHINE, 1401 .class_init = lm3s811evb_class_init, 1402 }; 1403 1404 static void lm3s6965evb_class_init(ObjectClass *oc, void *data) 1405 { 1406 MachineClass *mc = MACHINE_CLASS(oc); 1407 1408 mc->desc = "Stellaris LM3S6965EVB"; 1409 mc->init = lm3s6965evb_init; 1410 } 1411 1412 static const TypeInfo lm3s6965evb_type = { 1413 .name = MACHINE_TYPE_NAME("lm3s6965evb"), 1414 .parent = TYPE_MACHINE, 1415 .class_init = lm3s6965evb_class_init, 1416 }; 1417 1418 static void stellaris_machine_init(void) 1419 { 1420 type_register_static(&lm3s811evb_type); 1421 type_register_static(&lm3s6965evb_type); 1422 } 1423 1424 type_init(stellaris_machine_init) 1425 1426 static void stellaris_i2c_class_init(ObjectClass *klass, void *data) 1427 { 1428 DeviceClass *dc = DEVICE_CLASS(klass); 1429 1430 dc->vmsd = &vmstate_stellaris_i2c; 1431 } 1432 1433 static const TypeInfo stellaris_i2c_info = { 1434 .name = TYPE_STELLARIS_I2C, 1435 .parent = TYPE_SYS_BUS_DEVICE, 1436 .instance_size = sizeof(stellaris_i2c_state), 1437 .instance_init = stellaris_i2c_init, 1438 .class_init = stellaris_i2c_class_init, 1439 }; 1440 1441 static void stellaris_gptm_class_init(ObjectClass *klass, void *data) 1442 { 1443 DeviceClass *dc = DEVICE_CLASS(klass); 1444 1445 dc->vmsd = &vmstate_stellaris_gptm; 1446 } 1447 1448 static const TypeInfo stellaris_gptm_info = { 1449 .name = TYPE_STELLARIS_GPTM, 1450 .parent = TYPE_SYS_BUS_DEVICE, 1451 .instance_size = sizeof(gptm_state), 1452 .instance_init = stellaris_gptm_init, 1453 .class_init = stellaris_gptm_class_init, 1454 }; 1455 1456 static void stellaris_adc_class_init(ObjectClass *klass, void *data) 1457 { 1458 DeviceClass *dc = DEVICE_CLASS(klass); 1459 1460 dc->vmsd = &vmstate_stellaris_adc; 1461 } 1462 1463 static const TypeInfo stellaris_adc_info = { 1464 .name = TYPE_STELLARIS_ADC, 1465 .parent = TYPE_SYS_BUS_DEVICE, 1466 .instance_size = sizeof(stellaris_adc_state), 1467 .instance_init = stellaris_adc_init, 1468 .class_init = stellaris_adc_class_init, 1469 }; 1470 1471 static void stellaris_register_types(void) 1472 { 1473 type_register_static(&stellaris_i2c_info); 1474 type_register_static(&stellaris_gptm_info); 1475 type_register_static(&stellaris_adc_info); 1476 } 1477 1478 type_init(stellaris_register_types) 1479