1 /* 2 * Luminary Micro Stellaris peripherals 3 * 4 * Copyright (c) 2006 CodeSourcery. 5 * Written by Paul Brook 6 * 7 * This code is licensed under the GPL. 8 */ 9 10 #include "hw/sysbus.h" 11 #include "hw/ssi.h" 12 #include "hw/arm/arm.h" 13 #include "hw/devices.h" 14 #include "qemu/timer.h" 15 #include "hw/i2c/i2c.h" 16 #include "net/net.h" 17 #include "hw/boards.h" 18 #include "exec/address-spaces.h" 19 20 #define GPIO_A 0 21 #define GPIO_B 1 22 #define GPIO_C 2 23 #define GPIO_D 3 24 #define GPIO_E 4 25 #define GPIO_F 5 26 #define GPIO_G 6 27 28 #define BP_OLED_I2C 0x01 29 #define BP_OLED_SSI 0x02 30 #define BP_GAMEPAD 0x04 31 32 typedef const struct { 33 const char *name; 34 uint32_t did0; 35 uint32_t did1; 36 uint32_t dc0; 37 uint32_t dc1; 38 uint32_t dc2; 39 uint32_t dc3; 40 uint32_t dc4; 41 uint32_t peripherals; 42 } stellaris_board_info; 43 44 /* General purpose timer module. */ 45 46 #define TYPE_STELLARIS_GPTM "stellaris-gptm" 47 #define STELLARIS_GPTM(obj) \ 48 OBJECT_CHECK(gptm_state, (obj), TYPE_STELLARIS_GPTM) 49 50 typedef struct gptm_state { 51 SysBusDevice parent_obj; 52 53 MemoryRegion iomem; 54 uint32_t config; 55 uint32_t mode[2]; 56 uint32_t control; 57 uint32_t state; 58 uint32_t mask; 59 uint32_t load[2]; 60 uint32_t match[2]; 61 uint32_t prescale[2]; 62 uint32_t match_prescale[2]; 63 uint32_t rtc; 64 int64_t tick[2]; 65 struct gptm_state *opaque[2]; 66 QEMUTimer *timer[2]; 67 /* The timers have an alternate output used to trigger the ADC. */ 68 qemu_irq trigger; 69 qemu_irq irq; 70 } gptm_state; 71 72 static void gptm_update_irq(gptm_state *s) 73 { 74 int level; 75 level = (s->state & s->mask) != 0; 76 qemu_set_irq(s->irq, level); 77 } 78 79 static void gptm_stop(gptm_state *s, int n) 80 { 81 timer_del(s->timer[n]); 82 } 83 84 static void gptm_reload(gptm_state *s, int n, int reset) 85 { 86 int64_t tick; 87 if (reset) 88 tick = qemu_clock_get_ns(QEMU_CLOCK_VIRTUAL); 89 else 90 tick = s->tick[n]; 91 92 if (s->config == 0) { 93 /* 32-bit CountDown. */ 94 uint32_t count; 95 count = s->load[0] | (s->load[1] << 16); 96 tick += (int64_t)count * system_clock_scale; 97 } else if (s->config == 1) { 98 /* 32-bit RTC. 1Hz tick. */ 99 tick += get_ticks_per_sec(); 100 } else if (s->mode[n] == 0xa) { 101 /* PWM mode. Not implemented. */ 102 } else { 103 hw_error("TODO: 16-bit timer mode 0x%x\n", s->mode[n]); 104 } 105 s->tick[n] = tick; 106 timer_mod(s->timer[n], tick); 107 } 108 109 static void gptm_tick(void *opaque) 110 { 111 gptm_state **p = (gptm_state **)opaque; 112 gptm_state *s; 113 int n; 114 115 s = *p; 116 n = p - s->opaque; 117 if (s->config == 0) { 118 s->state |= 1; 119 if ((s->control & 0x20)) { 120 /* Output trigger. */ 121 qemu_irq_pulse(s->trigger); 122 } 123 if (s->mode[0] & 1) { 124 /* One-shot. */ 125 s->control &= ~1; 126 } else { 127 /* Periodic. */ 128 gptm_reload(s, 0, 0); 129 } 130 } else if (s->config == 1) { 131 /* RTC. */ 132 uint32_t match; 133 s->rtc++; 134 match = s->match[0] | (s->match[1] << 16); 135 if (s->rtc > match) 136 s->rtc = 0; 137 if (s->rtc == 0) { 138 s->state |= 8; 139 } 140 gptm_reload(s, 0, 0); 141 } else if (s->mode[n] == 0xa) { 142 /* PWM mode. Not implemented. */ 143 } else { 144 hw_error("TODO: 16-bit timer mode 0x%x\n", s->mode[n]); 145 } 146 gptm_update_irq(s); 147 } 148 149 static uint64_t gptm_read(void *opaque, hwaddr offset, 150 unsigned size) 151 { 152 gptm_state *s = (gptm_state *)opaque; 153 154 switch (offset) { 155 case 0x00: /* CFG */ 156 return s->config; 157 case 0x04: /* TAMR */ 158 return s->mode[0]; 159 case 0x08: /* TBMR */ 160 return s->mode[1]; 161 case 0x0c: /* CTL */ 162 return s->control; 163 case 0x18: /* IMR */ 164 return s->mask; 165 case 0x1c: /* RIS */ 166 return s->state; 167 case 0x20: /* MIS */ 168 return s->state & s->mask; 169 case 0x24: /* CR */ 170 return 0; 171 case 0x28: /* TAILR */ 172 return s->load[0] | ((s->config < 4) ? (s->load[1] << 16) : 0); 173 case 0x2c: /* TBILR */ 174 return s->load[1]; 175 case 0x30: /* TAMARCHR */ 176 return s->match[0] | ((s->config < 4) ? (s->match[1] << 16) : 0); 177 case 0x34: /* TBMATCHR */ 178 return s->match[1]; 179 case 0x38: /* TAPR */ 180 return s->prescale[0]; 181 case 0x3c: /* TBPR */ 182 return s->prescale[1]; 183 case 0x40: /* TAPMR */ 184 return s->match_prescale[0]; 185 case 0x44: /* TBPMR */ 186 return s->match_prescale[1]; 187 case 0x48: /* TAR */ 188 if (s->config == 1) { 189 return s->rtc; 190 } 191 qemu_log_mask(LOG_UNIMP, 192 "GPTM: read of TAR but timer read not supported"); 193 return 0; 194 case 0x4c: /* TBR */ 195 qemu_log_mask(LOG_UNIMP, 196 "GPTM: read of TBR but timer read not supported"); 197 return 0; 198 default: 199 qemu_log_mask(LOG_GUEST_ERROR, 200 "GPTM: read at bad offset 0x%x\n", (int)offset); 201 return 0; 202 } 203 } 204 205 static void gptm_write(void *opaque, hwaddr offset, 206 uint64_t value, unsigned size) 207 { 208 gptm_state *s = (gptm_state *)opaque; 209 uint32_t oldval; 210 211 /* The timers should be disabled before changing the configuration. 212 We take advantage of this and defer everything until the timer 213 is enabled. */ 214 switch (offset) { 215 case 0x00: /* CFG */ 216 s->config = value; 217 break; 218 case 0x04: /* TAMR */ 219 s->mode[0] = value; 220 break; 221 case 0x08: /* TBMR */ 222 s->mode[1] = value; 223 break; 224 case 0x0c: /* CTL */ 225 oldval = s->control; 226 s->control = value; 227 /* TODO: Implement pause. */ 228 if ((oldval ^ value) & 1) { 229 if (value & 1) { 230 gptm_reload(s, 0, 1); 231 } else { 232 gptm_stop(s, 0); 233 } 234 } 235 if (((oldval ^ value) & 0x100) && s->config >= 4) { 236 if (value & 0x100) { 237 gptm_reload(s, 1, 1); 238 } else { 239 gptm_stop(s, 1); 240 } 241 } 242 break; 243 case 0x18: /* IMR */ 244 s->mask = value & 0x77; 245 gptm_update_irq(s); 246 break; 247 case 0x24: /* CR */ 248 s->state &= ~value; 249 break; 250 case 0x28: /* TAILR */ 251 s->load[0] = value & 0xffff; 252 if (s->config < 4) { 253 s->load[1] = value >> 16; 254 } 255 break; 256 case 0x2c: /* TBILR */ 257 s->load[1] = value & 0xffff; 258 break; 259 case 0x30: /* TAMARCHR */ 260 s->match[0] = value & 0xffff; 261 if (s->config < 4) { 262 s->match[1] = value >> 16; 263 } 264 break; 265 case 0x34: /* TBMATCHR */ 266 s->match[1] = value >> 16; 267 break; 268 case 0x38: /* TAPR */ 269 s->prescale[0] = value; 270 break; 271 case 0x3c: /* TBPR */ 272 s->prescale[1] = value; 273 break; 274 case 0x40: /* TAPMR */ 275 s->match_prescale[0] = value; 276 break; 277 case 0x44: /* TBPMR */ 278 s->match_prescale[0] = value; 279 break; 280 default: 281 hw_error("gptm_write: Bad offset 0x%x\n", (int)offset); 282 } 283 gptm_update_irq(s); 284 } 285 286 static const MemoryRegionOps gptm_ops = { 287 .read = gptm_read, 288 .write = gptm_write, 289 .endianness = DEVICE_NATIVE_ENDIAN, 290 }; 291 292 static const VMStateDescription vmstate_stellaris_gptm = { 293 .name = "stellaris_gptm", 294 .version_id = 1, 295 .minimum_version_id = 1, 296 .fields = (VMStateField[]) { 297 VMSTATE_UINT32(config, gptm_state), 298 VMSTATE_UINT32_ARRAY(mode, gptm_state, 2), 299 VMSTATE_UINT32(control, gptm_state), 300 VMSTATE_UINT32(state, gptm_state), 301 VMSTATE_UINT32(mask, gptm_state), 302 VMSTATE_UNUSED(8), 303 VMSTATE_UINT32_ARRAY(load, gptm_state, 2), 304 VMSTATE_UINT32_ARRAY(match, gptm_state, 2), 305 VMSTATE_UINT32_ARRAY(prescale, gptm_state, 2), 306 VMSTATE_UINT32_ARRAY(match_prescale, gptm_state, 2), 307 VMSTATE_UINT32(rtc, gptm_state), 308 VMSTATE_INT64_ARRAY(tick, gptm_state, 2), 309 VMSTATE_TIMER_ARRAY(timer, gptm_state, 2), 310 VMSTATE_END_OF_LIST() 311 } 312 }; 313 314 static int stellaris_gptm_init(SysBusDevice *sbd) 315 { 316 DeviceState *dev = DEVICE(sbd); 317 gptm_state *s = STELLARIS_GPTM(dev); 318 319 sysbus_init_irq(sbd, &s->irq); 320 qdev_init_gpio_out(dev, &s->trigger, 1); 321 322 memory_region_init_io(&s->iomem, OBJECT(s), &gptm_ops, s, 323 "gptm", 0x1000); 324 sysbus_init_mmio(sbd, &s->iomem); 325 326 s->opaque[0] = s->opaque[1] = s; 327 s->timer[0] = timer_new_ns(QEMU_CLOCK_VIRTUAL, gptm_tick, &s->opaque[0]); 328 s->timer[1] = timer_new_ns(QEMU_CLOCK_VIRTUAL, gptm_tick, &s->opaque[1]); 329 vmstate_register(dev, -1, &vmstate_stellaris_gptm, s); 330 return 0; 331 } 332 333 334 /* System controller. */ 335 336 typedef struct { 337 MemoryRegion iomem; 338 uint32_t pborctl; 339 uint32_t ldopctl; 340 uint32_t int_status; 341 uint32_t int_mask; 342 uint32_t resc; 343 uint32_t rcc; 344 uint32_t rcc2; 345 uint32_t rcgc[3]; 346 uint32_t scgc[3]; 347 uint32_t dcgc[3]; 348 uint32_t clkvclr; 349 uint32_t ldoarst; 350 uint32_t user0; 351 uint32_t user1; 352 qemu_irq irq; 353 stellaris_board_info *board; 354 } ssys_state; 355 356 static void ssys_update(ssys_state *s) 357 { 358 qemu_set_irq(s->irq, (s->int_status & s->int_mask) != 0); 359 } 360 361 static uint32_t pllcfg_sandstorm[16] = { 362 0x31c0, /* 1 Mhz */ 363 0x1ae0, /* 1.8432 Mhz */ 364 0x18c0, /* 2 Mhz */ 365 0xd573, /* 2.4576 Mhz */ 366 0x37a6, /* 3.57954 Mhz */ 367 0x1ae2, /* 3.6864 Mhz */ 368 0x0c40, /* 4 Mhz */ 369 0x98bc, /* 4.906 Mhz */ 370 0x935b, /* 4.9152 Mhz */ 371 0x09c0, /* 5 Mhz */ 372 0x4dee, /* 5.12 Mhz */ 373 0x0c41, /* 6 Mhz */ 374 0x75db, /* 6.144 Mhz */ 375 0x1ae6, /* 7.3728 Mhz */ 376 0x0600, /* 8 Mhz */ 377 0x585b /* 8.192 Mhz */ 378 }; 379 380 static uint32_t pllcfg_fury[16] = { 381 0x3200, /* 1 Mhz */ 382 0x1b20, /* 1.8432 Mhz */ 383 0x1900, /* 2 Mhz */ 384 0xf42b, /* 2.4576 Mhz */ 385 0x37e3, /* 3.57954 Mhz */ 386 0x1b21, /* 3.6864 Mhz */ 387 0x0c80, /* 4 Mhz */ 388 0x98ee, /* 4.906 Mhz */ 389 0xd5b4, /* 4.9152 Mhz */ 390 0x0a00, /* 5 Mhz */ 391 0x4e27, /* 5.12 Mhz */ 392 0x1902, /* 6 Mhz */ 393 0xec1c, /* 6.144 Mhz */ 394 0x1b23, /* 7.3728 Mhz */ 395 0x0640, /* 8 Mhz */ 396 0xb11c /* 8.192 Mhz */ 397 }; 398 399 #define DID0_VER_MASK 0x70000000 400 #define DID0_VER_0 0x00000000 401 #define DID0_VER_1 0x10000000 402 403 #define DID0_CLASS_MASK 0x00FF0000 404 #define DID0_CLASS_SANDSTORM 0x00000000 405 #define DID0_CLASS_FURY 0x00010000 406 407 static int ssys_board_class(const ssys_state *s) 408 { 409 uint32_t did0 = s->board->did0; 410 switch (did0 & DID0_VER_MASK) { 411 case DID0_VER_0: 412 return DID0_CLASS_SANDSTORM; 413 case DID0_VER_1: 414 switch (did0 & DID0_CLASS_MASK) { 415 case DID0_CLASS_SANDSTORM: 416 case DID0_CLASS_FURY: 417 return did0 & DID0_CLASS_MASK; 418 } 419 /* for unknown classes, fall through */ 420 default: 421 hw_error("ssys_board_class: Unknown class 0x%08x\n", did0); 422 } 423 } 424 425 static uint64_t ssys_read(void *opaque, hwaddr offset, 426 unsigned size) 427 { 428 ssys_state *s = (ssys_state *)opaque; 429 430 switch (offset) { 431 case 0x000: /* DID0 */ 432 return s->board->did0; 433 case 0x004: /* DID1 */ 434 return s->board->did1; 435 case 0x008: /* DC0 */ 436 return s->board->dc0; 437 case 0x010: /* DC1 */ 438 return s->board->dc1; 439 case 0x014: /* DC2 */ 440 return s->board->dc2; 441 case 0x018: /* DC3 */ 442 return s->board->dc3; 443 case 0x01c: /* DC4 */ 444 return s->board->dc4; 445 case 0x030: /* PBORCTL */ 446 return s->pborctl; 447 case 0x034: /* LDOPCTL */ 448 return s->ldopctl; 449 case 0x040: /* SRCR0 */ 450 return 0; 451 case 0x044: /* SRCR1 */ 452 return 0; 453 case 0x048: /* SRCR2 */ 454 return 0; 455 case 0x050: /* RIS */ 456 return s->int_status; 457 case 0x054: /* IMC */ 458 return s->int_mask; 459 case 0x058: /* MISC */ 460 return s->int_status & s->int_mask; 461 case 0x05c: /* RESC */ 462 return s->resc; 463 case 0x060: /* RCC */ 464 return s->rcc; 465 case 0x064: /* PLLCFG */ 466 { 467 int xtal; 468 xtal = (s->rcc >> 6) & 0xf; 469 switch (ssys_board_class(s)) { 470 case DID0_CLASS_FURY: 471 return pllcfg_fury[xtal]; 472 case DID0_CLASS_SANDSTORM: 473 return pllcfg_sandstorm[xtal]; 474 default: 475 hw_error("ssys_read: Unhandled class for PLLCFG read.\n"); 476 return 0; 477 } 478 } 479 case 0x070: /* RCC2 */ 480 return s->rcc2; 481 case 0x100: /* RCGC0 */ 482 return s->rcgc[0]; 483 case 0x104: /* RCGC1 */ 484 return s->rcgc[1]; 485 case 0x108: /* RCGC2 */ 486 return s->rcgc[2]; 487 case 0x110: /* SCGC0 */ 488 return s->scgc[0]; 489 case 0x114: /* SCGC1 */ 490 return s->scgc[1]; 491 case 0x118: /* SCGC2 */ 492 return s->scgc[2]; 493 case 0x120: /* DCGC0 */ 494 return s->dcgc[0]; 495 case 0x124: /* DCGC1 */ 496 return s->dcgc[1]; 497 case 0x128: /* DCGC2 */ 498 return s->dcgc[2]; 499 case 0x150: /* CLKVCLR */ 500 return s->clkvclr; 501 case 0x160: /* LDOARST */ 502 return s->ldoarst; 503 case 0x1e0: /* USER0 */ 504 return s->user0; 505 case 0x1e4: /* USER1 */ 506 return s->user1; 507 default: 508 hw_error("ssys_read: Bad offset 0x%x\n", (int)offset); 509 return 0; 510 } 511 } 512 513 static bool ssys_use_rcc2(ssys_state *s) 514 { 515 return (s->rcc2 >> 31) & 0x1; 516 } 517 518 /* 519 * Caculate the sys. clock period in ms. 520 */ 521 static void ssys_calculate_system_clock(ssys_state *s) 522 { 523 if (ssys_use_rcc2(s)) { 524 system_clock_scale = 5 * (((s->rcc2 >> 23) & 0x3f) + 1); 525 } else { 526 system_clock_scale = 5 * (((s->rcc >> 23) & 0xf) + 1); 527 } 528 } 529 530 static void ssys_write(void *opaque, hwaddr offset, 531 uint64_t value, unsigned size) 532 { 533 ssys_state *s = (ssys_state *)opaque; 534 535 switch (offset) { 536 case 0x030: /* PBORCTL */ 537 s->pborctl = value & 0xffff; 538 break; 539 case 0x034: /* LDOPCTL */ 540 s->ldopctl = value & 0x1f; 541 break; 542 case 0x040: /* SRCR0 */ 543 case 0x044: /* SRCR1 */ 544 case 0x048: /* SRCR2 */ 545 fprintf(stderr, "Peripheral reset not implemented\n"); 546 break; 547 case 0x054: /* IMC */ 548 s->int_mask = value & 0x7f; 549 break; 550 case 0x058: /* MISC */ 551 s->int_status &= ~value; 552 break; 553 case 0x05c: /* RESC */ 554 s->resc = value & 0x3f; 555 break; 556 case 0x060: /* RCC */ 557 if ((s->rcc & (1 << 13)) != 0 && (value & (1 << 13)) == 0) { 558 /* PLL enable. */ 559 s->int_status |= (1 << 6); 560 } 561 s->rcc = value; 562 ssys_calculate_system_clock(s); 563 break; 564 case 0x070: /* RCC2 */ 565 if (ssys_board_class(s) == DID0_CLASS_SANDSTORM) { 566 break; 567 } 568 569 if ((s->rcc2 & (1 << 13)) != 0 && (value & (1 << 13)) == 0) { 570 /* PLL enable. */ 571 s->int_status |= (1 << 6); 572 } 573 s->rcc2 = value; 574 ssys_calculate_system_clock(s); 575 break; 576 case 0x100: /* RCGC0 */ 577 s->rcgc[0] = value; 578 break; 579 case 0x104: /* RCGC1 */ 580 s->rcgc[1] = value; 581 break; 582 case 0x108: /* RCGC2 */ 583 s->rcgc[2] = value; 584 break; 585 case 0x110: /* SCGC0 */ 586 s->scgc[0] = value; 587 break; 588 case 0x114: /* SCGC1 */ 589 s->scgc[1] = value; 590 break; 591 case 0x118: /* SCGC2 */ 592 s->scgc[2] = value; 593 break; 594 case 0x120: /* DCGC0 */ 595 s->dcgc[0] = value; 596 break; 597 case 0x124: /* DCGC1 */ 598 s->dcgc[1] = value; 599 break; 600 case 0x128: /* DCGC2 */ 601 s->dcgc[2] = value; 602 break; 603 case 0x150: /* CLKVCLR */ 604 s->clkvclr = value; 605 break; 606 case 0x160: /* LDOARST */ 607 s->ldoarst = value; 608 break; 609 default: 610 hw_error("ssys_write: Bad offset 0x%x\n", (int)offset); 611 } 612 ssys_update(s); 613 } 614 615 static const MemoryRegionOps ssys_ops = { 616 .read = ssys_read, 617 .write = ssys_write, 618 .endianness = DEVICE_NATIVE_ENDIAN, 619 }; 620 621 static void ssys_reset(void *opaque) 622 { 623 ssys_state *s = (ssys_state *)opaque; 624 625 s->pborctl = 0x7ffd; 626 s->rcc = 0x078e3ac0; 627 628 if (ssys_board_class(s) == DID0_CLASS_SANDSTORM) { 629 s->rcc2 = 0; 630 } else { 631 s->rcc2 = 0x07802810; 632 } 633 s->rcgc[0] = 1; 634 s->scgc[0] = 1; 635 s->dcgc[0] = 1; 636 ssys_calculate_system_clock(s); 637 } 638 639 static int stellaris_sys_post_load(void *opaque, int version_id) 640 { 641 ssys_state *s = opaque; 642 643 ssys_calculate_system_clock(s); 644 645 return 0; 646 } 647 648 static const VMStateDescription vmstate_stellaris_sys = { 649 .name = "stellaris_sys", 650 .version_id = 2, 651 .minimum_version_id = 1, 652 .post_load = stellaris_sys_post_load, 653 .fields = (VMStateField[]) { 654 VMSTATE_UINT32(pborctl, ssys_state), 655 VMSTATE_UINT32(ldopctl, ssys_state), 656 VMSTATE_UINT32(int_mask, ssys_state), 657 VMSTATE_UINT32(int_status, ssys_state), 658 VMSTATE_UINT32(resc, ssys_state), 659 VMSTATE_UINT32(rcc, ssys_state), 660 VMSTATE_UINT32_V(rcc2, ssys_state, 2), 661 VMSTATE_UINT32_ARRAY(rcgc, ssys_state, 3), 662 VMSTATE_UINT32_ARRAY(scgc, ssys_state, 3), 663 VMSTATE_UINT32_ARRAY(dcgc, ssys_state, 3), 664 VMSTATE_UINT32(clkvclr, ssys_state), 665 VMSTATE_UINT32(ldoarst, ssys_state), 666 VMSTATE_END_OF_LIST() 667 } 668 }; 669 670 static int stellaris_sys_init(uint32_t base, qemu_irq irq, 671 stellaris_board_info * board, 672 uint8_t *macaddr) 673 { 674 ssys_state *s; 675 676 s = (ssys_state *)g_malloc0(sizeof(ssys_state)); 677 s->irq = irq; 678 s->board = board; 679 /* Most devices come preprogrammed with a MAC address in the user data. */ 680 s->user0 = macaddr[0] | (macaddr[1] << 8) | (macaddr[2] << 16); 681 s->user1 = macaddr[3] | (macaddr[4] << 8) | (macaddr[5] << 16); 682 683 memory_region_init_io(&s->iomem, NULL, &ssys_ops, s, "ssys", 0x00001000); 684 memory_region_add_subregion(get_system_memory(), base, &s->iomem); 685 ssys_reset(s); 686 vmstate_register(NULL, -1, &vmstate_stellaris_sys, s); 687 return 0; 688 } 689 690 691 /* I2C controller. */ 692 693 #define TYPE_STELLARIS_I2C "stellaris-i2c" 694 #define STELLARIS_I2C(obj) \ 695 OBJECT_CHECK(stellaris_i2c_state, (obj), TYPE_STELLARIS_I2C) 696 697 typedef struct { 698 SysBusDevice parent_obj; 699 700 I2CBus *bus; 701 qemu_irq irq; 702 MemoryRegion iomem; 703 uint32_t msa; 704 uint32_t mcs; 705 uint32_t mdr; 706 uint32_t mtpr; 707 uint32_t mimr; 708 uint32_t mris; 709 uint32_t mcr; 710 } stellaris_i2c_state; 711 712 #define STELLARIS_I2C_MCS_BUSY 0x01 713 #define STELLARIS_I2C_MCS_ERROR 0x02 714 #define STELLARIS_I2C_MCS_ADRACK 0x04 715 #define STELLARIS_I2C_MCS_DATACK 0x08 716 #define STELLARIS_I2C_MCS_ARBLST 0x10 717 #define STELLARIS_I2C_MCS_IDLE 0x20 718 #define STELLARIS_I2C_MCS_BUSBSY 0x40 719 720 static uint64_t stellaris_i2c_read(void *opaque, hwaddr offset, 721 unsigned size) 722 { 723 stellaris_i2c_state *s = (stellaris_i2c_state *)opaque; 724 725 switch (offset) { 726 case 0x00: /* MSA */ 727 return s->msa; 728 case 0x04: /* MCS */ 729 /* We don't emulate timing, so the controller is never busy. */ 730 return s->mcs | STELLARIS_I2C_MCS_IDLE; 731 case 0x08: /* MDR */ 732 return s->mdr; 733 case 0x0c: /* MTPR */ 734 return s->mtpr; 735 case 0x10: /* MIMR */ 736 return s->mimr; 737 case 0x14: /* MRIS */ 738 return s->mris; 739 case 0x18: /* MMIS */ 740 return s->mris & s->mimr; 741 case 0x20: /* MCR */ 742 return s->mcr; 743 default: 744 hw_error("strllaris_i2c_read: Bad offset 0x%x\n", (int)offset); 745 return 0; 746 } 747 } 748 749 static void stellaris_i2c_update(stellaris_i2c_state *s) 750 { 751 int level; 752 753 level = (s->mris & s->mimr) != 0; 754 qemu_set_irq(s->irq, level); 755 } 756 757 static void stellaris_i2c_write(void *opaque, hwaddr offset, 758 uint64_t value, unsigned size) 759 { 760 stellaris_i2c_state *s = (stellaris_i2c_state *)opaque; 761 762 switch (offset) { 763 case 0x00: /* MSA */ 764 s->msa = value & 0xff; 765 break; 766 case 0x04: /* MCS */ 767 if ((s->mcr & 0x10) == 0) { 768 /* Disabled. Do nothing. */ 769 break; 770 } 771 /* Grab the bus if this is starting a transfer. */ 772 if ((value & 2) && (s->mcs & STELLARIS_I2C_MCS_BUSBSY) == 0) { 773 if (i2c_start_transfer(s->bus, s->msa >> 1, s->msa & 1)) { 774 s->mcs |= STELLARIS_I2C_MCS_ARBLST; 775 } else { 776 s->mcs &= ~STELLARIS_I2C_MCS_ARBLST; 777 s->mcs |= STELLARIS_I2C_MCS_BUSBSY; 778 } 779 } 780 /* If we don't have the bus then indicate an error. */ 781 if (!i2c_bus_busy(s->bus) 782 || (s->mcs & STELLARIS_I2C_MCS_BUSBSY) == 0) { 783 s->mcs |= STELLARIS_I2C_MCS_ERROR; 784 break; 785 } 786 s->mcs &= ~STELLARIS_I2C_MCS_ERROR; 787 if (value & 1) { 788 /* Transfer a byte. */ 789 /* TODO: Handle errors. */ 790 if (s->msa & 1) { 791 /* Recv */ 792 s->mdr = i2c_recv(s->bus) & 0xff; 793 } else { 794 /* Send */ 795 i2c_send(s->bus, s->mdr); 796 } 797 /* Raise an interrupt. */ 798 s->mris |= 1; 799 } 800 if (value & 4) { 801 /* Finish transfer. */ 802 i2c_end_transfer(s->bus); 803 s->mcs &= ~STELLARIS_I2C_MCS_BUSBSY; 804 } 805 break; 806 case 0x08: /* MDR */ 807 s->mdr = value & 0xff; 808 break; 809 case 0x0c: /* MTPR */ 810 s->mtpr = value & 0xff; 811 break; 812 case 0x10: /* MIMR */ 813 s->mimr = 1; 814 break; 815 case 0x1c: /* MICR */ 816 s->mris &= ~value; 817 break; 818 case 0x20: /* MCR */ 819 if (value & 1) 820 hw_error( 821 "stellaris_i2c_write: Loopback not implemented\n"); 822 if (value & 0x20) 823 hw_error( 824 "stellaris_i2c_write: Slave mode not implemented\n"); 825 s->mcr = value & 0x31; 826 break; 827 default: 828 hw_error("stellaris_i2c_write: Bad offset 0x%x\n", 829 (int)offset); 830 } 831 stellaris_i2c_update(s); 832 } 833 834 static void stellaris_i2c_reset(stellaris_i2c_state *s) 835 { 836 if (s->mcs & STELLARIS_I2C_MCS_BUSBSY) 837 i2c_end_transfer(s->bus); 838 839 s->msa = 0; 840 s->mcs = 0; 841 s->mdr = 0; 842 s->mtpr = 1; 843 s->mimr = 0; 844 s->mris = 0; 845 s->mcr = 0; 846 stellaris_i2c_update(s); 847 } 848 849 static const MemoryRegionOps stellaris_i2c_ops = { 850 .read = stellaris_i2c_read, 851 .write = stellaris_i2c_write, 852 .endianness = DEVICE_NATIVE_ENDIAN, 853 }; 854 855 static const VMStateDescription vmstate_stellaris_i2c = { 856 .name = "stellaris_i2c", 857 .version_id = 1, 858 .minimum_version_id = 1, 859 .fields = (VMStateField[]) { 860 VMSTATE_UINT32(msa, stellaris_i2c_state), 861 VMSTATE_UINT32(mcs, stellaris_i2c_state), 862 VMSTATE_UINT32(mdr, stellaris_i2c_state), 863 VMSTATE_UINT32(mtpr, stellaris_i2c_state), 864 VMSTATE_UINT32(mimr, stellaris_i2c_state), 865 VMSTATE_UINT32(mris, stellaris_i2c_state), 866 VMSTATE_UINT32(mcr, stellaris_i2c_state), 867 VMSTATE_END_OF_LIST() 868 } 869 }; 870 871 static int stellaris_i2c_init(SysBusDevice *sbd) 872 { 873 DeviceState *dev = DEVICE(sbd); 874 stellaris_i2c_state *s = STELLARIS_I2C(dev); 875 I2CBus *bus; 876 877 sysbus_init_irq(sbd, &s->irq); 878 bus = i2c_init_bus(dev, "i2c"); 879 s->bus = bus; 880 881 memory_region_init_io(&s->iomem, OBJECT(s), &stellaris_i2c_ops, s, 882 "i2c", 0x1000); 883 sysbus_init_mmio(sbd, &s->iomem); 884 /* ??? For now we only implement the master interface. */ 885 stellaris_i2c_reset(s); 886 vmstate_register(dev, -1, &vmstate_stellaris_i2c, s); 887 return 0; 888 } 889 890 /* Analogue to Digital Converter. This is only partially implemented, 891 enough for applications that use a combined ADC and timer tick. */ 892 893 #define STELLARIS_ADC_EM_CONTROLLER 0 894 #define STELLARIS_ADC_EM_COMP 1 895 #define STELLARIS_ADC_EM_EXTERNAL 4 896 #define STELLARIS_ADC_EM_TIMER 5 897 #define STELLARIS_ADC_EM_PWM0 6 898 #define STELLARIS_ADC_EM_PWM1 7 899 #define STELLARIS_ADC_EM_PWM2 8 900 901 #define STELLARIS_ADC_FIFO_EMPTY 0x0100 902 #define STELLARIS_ADC_FIFO_FULL 0x1000 903 904 #define TYPE_STELLARIS_ADC "stellaris-adc" 905 #define STELLARIS_ADC(obj) \ 906 OBJECT_CHECK(stellaris_adc_state, (obj), TYPE_STELLARIS_ADC) 907 908 typedef struct StellarisADCState { 909 SysBusDevice parent_obj; 910 911 MemoryRegion iomem; 912 uint32_t actss; 913 uint32_t ris; 914 uint32_t im; 915 uint32_t emux; 916 uint32_t ostat; 917 uint32_t ustat; 918 uint32_t sspri; 919 uint32_t sac; 920 struct { 921 uint32_t state; 922 uint32_t data[16]; 923 } fifo[4]; 924 uint32_t ssmux[4]; 925 uint32_t ssctl[4]; 926 uint32_t noise; 927 qemu_irq irq[4]; 928 } stellaris_adc_state; 929 930 static uint32_t stellaris_adc_fifo_read(stellaris_adc_state *s, int n) 931 { 932 int tail; 933 934 tail = s->fifo[n].state & 0xf; 935 if (s->fifo[n].state & STELLARIS_ADC_FIFO_EMPTY) { 936 s->ustat |= 1 << n; 937 } else { 938 s->fifo[n].state = (s->fifo[n].state & ~0xf) | ((tail + 1) & 0xf); 939 s->fifo[n].state &= ~STELLARIS_ADC_FIFO_FULL; 940 if (tail + 1 == ((s->fifo[n].state >> 4) & 0xf)) 941 s->fifo[n].state |= STELLARIS_ADC_FIFO_EMPTY; 942 } 943 return s->fifo[n].data[tail]; 944 } 945 946 static void stellaris_adc_fifo_write(stellaris_adc_state *s, int n, 947 uint32_t value) 948 { 949 int head; 950 951 /* TODO: Real hardware has limited size FIFOs. We have a full 16 entry 952 FIFO fir each sequencer. */ 953 head = (s->fifo[n].state >> 4) & 0xf; 954 if (s->fifo[n].state & STELLARIS_ADC_FIFO_FULL) { 955 s->ostat |= 1 << n; 956 return; 957 } 958 s->fifo[n].data[head] = value; 959 head = (head + 1) & 0xf; 960 s->fifo[n].state &= ~STELLARIS_ADC_FIFO_EMPTY; 961 s->fifo[n].state = (s->fifo[n].state & ~0xf0) | (head << 4); 962 if ((s->fifo[n].state & 0xf) == head) 963 s->fifo[n].state |= STELLARIS_ADC_FIFO_FULL; 964 } 965 966 static void stellaris_adc_update(stellaris_adc_state *s) 967 { 968 int level; 969 int n; 970 971 for (n = 0; n < 4; n++) { 972 level = (s->ris & s->im & (1 << n)) != 0; 973 qemu_set_irq(s->irq[n], level); 974 } 975 } 976 977 static void stellaris_adc_trigger(void *opaque, int irq, int level) 978 { 979 stellaris_adc_state *s = (stellaris_adc_state *)opaque; 980 int n; 981 982 for (n = 0; n < 4; n++) { 983 if ((s->actss & (1 << n)) == 0) { 984 continue; 985 } 986 987 if (((s->emux >> (n * 4)) & 0xff) != 5) { 988 continue; 989 } 990 991 /* Some applications use the ADC as a random number source, so introduce 992 some variation into the signal. */ 993 s->noise = s->noise * 314159 + 1; 994 /* ??? actual inputs not implemented. Return an arbitrary value. */ 995 stellaris_adc_fifo_write(s, n, 0x200 + ((s->noise >> 16) & 7)); 996 s->ris |= (1 << n); 997 stellaris_adc_update(s); 998 } 999 } 1000 1001 static void stellaris_adc_reset(stellaris_adc_state *s) 1002 { 1003 int n; 1004 1005 for (n = 0; n < 4; n++) { 1006 s->ssmux[n] = 0; 1007 s->ssctl[n] = 0; 1008 s->fifo[n].state = STELLARIS_ADC_FIFO_EMPTY; 1009 } 1010 } 1011 1012 static uint64_t stellaris_adc_read(void *opaque, hwaddr offset, 1013 unsigned size) 1014 { 1015 stellaris_adc_state *s = (stellaris_adc_state *)opaque; 1016 1017 /* TODO: Implement this. */ 1018 if (offset >= 0x40 && offset < 0xc0) { 1019 int n; 1020 n = (offset - 0x40) >> 5; 1021 switch (offset & 0x1f) { 1022 case 0x00: /* SSMUX */ 1023 return s->ssmux[n]; 1024 case 0x04: /* SSCTL */ 1025 return s->ssctl[n]; 1026 case 0x08: /* SSFIFO */ 1027 return stellaris_adc_fifo_read(s, n); 1028 case 0x0c: /* SSFSTAT */ 1029 return s->fifo[n].state; 1030 default: 1031 break; 1032 } 1033 } 1034 switch (offset) { 1035 case 0x00: /* ACTSS */ 1036 return s->actss; 1037 case 0x04: /* RIS */ 1038 return s->ris; 1039 case 0x08: /* IM */ 1040 return s->im; 1041 case 0x0c: /* ISC */ 1042 return s->ris & s->im; 1043 case 0x10: /* OSTAT */ 1044 return s->ostat; 1045 case 0x14: /* EMUX */ 1046 return s->emux; 1047 case 0x18: /* USTAT */ 1048 return s->ustat; 1049 case 0x20: /* SSPRI */ 1050 return s->sspri; 1051 case 0x30: /* SAC */ 1052 return s->sac; 1053 default: 1054 hw_error("strllaris_adc_read: Bad offset 0x%x\n", 1055 (int)offset); 1056 return 0; 1057 } 1058 } 1059 1060 static void stellaris_adc_write(void *opaque, hwaddr offset, 1061 uint64_t value, unsigned size) 1062 { 1063 stellaris_adc_state *s = (stellaris_adc_state *)opaque; 1064 1065 /* TODO: Implement this. */ 1066 if (offset >= 0x40 && offset < 0xc0) { 1067 int n; 1068 n = (offset - 0x40) >> 5; 1069 switch (offset & 0x1f) { 1070 case 0x00: /* SSMUX */ 1071 s->ssmux[n] = value & 0x33333333; 1072 return; 1073 case 0x04: /* SSCTL */ 1074 if (value != 6) { 1075 hw_error("ADC: Unimplemented sequence %" PRIx64 "\n", 1076 value); 1077 } 1078 s->ssctl[n] = value; 1079 return; 1080 default: 1081 break; 1082 } 1083 } 1084 switch (offset) { 1085 case 0x00: /* ACTSS */ 1086 s->actss = value & 0xf; 1087 break; 1088 case 0x08: /* IM */ 1089 s->im = value; 1090 break; 1091 case 0x0c: /* ISC */ 1092 s->ris &= ~value; 1093 break; 1094 case 0x10: /* OSTAT */ 1095 s->ostat &= ~value; 1096 break; 1097 case 0x14: /* EMUX */ 1098 s->emux = value; 1099 break; 1100 case 0x18: /* USTAT */ 1101 s->ustat &= ~value; 1102 break; 1103 case 0x20: /* SSPRI */ 1104 s->sspri = value; 1105 break; 1106 case 0x28: /* PSSI */ 1107 hw_error("Not implemented: ADC sample initiate\n"); 1108 break; 1109 case 0x30: /* SAC */ 1110 s->sac = value; 1111 break; 1112 default: 1113 hw_error("stellaris_adc_write: Bad offset 0x%x\n", (int)offset); 1114 } 1115 stellaris_adc_update(s); 1116 } 1117 1118 static const MemoryRegionOps stellaris_adc_ops = { 1119 .read = stellaris_adc_read, 1120 .write = stellaris_adc_write, 1121 .endianness = DEVICE_NATIVE_ENDIAN, 1122 }; 1123 1124 static const VMStateDescription vmstate_stellaris_adc = { 1125 .name = "stellaris_adc", 1126 .version_id = 1, 1127 .minimum_version_id = 1, 1128 .fields = (VMStateField[]) { 1129 VMSTATE_UINT32(actss, stellaris_adc_state), 1130 VMSTATE_UINT32(ris, stellaris_adc_state), 1131 VMSTATE_UINT32(im, stellaris_adc_state), 1132 VMSTATE_UINT32(emux, stellaris_adc_state), 1133 VMSTATE_UINT32(ostat, stellaris_adc_state), 1134 VMSTATE_UINT32(ustat, stellaris_adc_state), 1135 VMSTATE_UINT32(sspri, stellaris_adc_state), 1136 VMSTATE_UINT32(sac, stellaris_adc_state), 1137 VMSTATE_UINT32(fifo[0].state, stellaris_adc_state), 1138 VMSTATE_UINT32_ARRAY(fifo[0].data, stellaris_adc_state, 16), 1139 VMSTATE_UINT32(ssmux[0], stellaris_adc_state), 1140 VMSTATE_UINT32(ssctl[0], stellaris_adc_state), 1141 VMSTATE_UINT32(fifo[1].state, stellaris_adc_state), 1142 VMSTATE_UINT32_ARRAY(fifo[1].data, stellaris_adc_state, 16), 1143 VMSTATE_UINT32(ssmux[1], stellaris_adc_state), 1144 VMSTATE_UINT32(ssctl[1], stellaris_adc_state), 1145 VMSTATE_UINT32(fifo[2].state, stellaris_adc_state), 1146 VMSTATE_UINT32_ARRAY(fifo[2].data, stellaris_adc_state, 16), 1147 VMSTATE_UINT32(ssmux[2], stellaris_adc_state), 1148 VMSTATE_UINT32(ssctl[2], stellaris_adc_state), 1149 VMSTATE_UINT32(fifo[3].state, stellaris_adc_state), 1150 VMSTATE_UINT32_ARRAY(fifo[3].data, stellaris_adc_state, 16), 1151 VMSTATE_UINT32(ssmux[3], stellaris_adc_state), 1152 VMSTATE_UINT32(ssctl[3], stellaris_adc_state), 1153 VMSTATE_UINT32(noise, stellaris_adc_state), 1154 VMSTATE_END_OF_LIST() 1155 } 1156 }; 1157 1158 static int stellaris_adc_init(SysBusDevice *sbd) 1159 { 1160 DeviceState *dev = DEVICE(sbd); 1161 stellaris_adc_state *s = STELLARIS_ADC(dev); 1162 int n; 1163 1164 for (n = 0; n < 4; n++) { 1165 sysbus_init_irq(sbd, &s->irq[n]); 1166 } 1167 1168 memory_region_init_io(&s->iomem, OBJECT(s), &stellaris_adc_ops, s, 1169 "adc", 0x1000); 1170 sysbus_init_mmio(sbd, &s->iomem); 1171 stellaris_adc_reset(s); 1172 qdev_init_gpio_in(dev, stellaris_adc_trigger, 1); 1173 vmstate_register(dev, -1, &vmstate_stellaris_adc, s); 1174 return 0; 1175 } 1176 1177 /* Board init. */ 1178 static stellaris_board_info stellaris_boards[] = { 1179 { "LM3S811EVB", 1180 0, 1181 0x0032000e, 1182 0x001f001f, /* dc0 */ 1183 0x001132bf, 1184 0x01071013, 1185 0x3f0f01ff, 1186 0x0000001f, 1187 BP_OLED_I2C 1188 }, 1189 { "LM3S6965EVB", 1190 0x10010002, 1191 0x1073402e, 1192 0x00ff007f, /* dc0 */ 1193 0x001133ff, 1194 0x030f5317, 1195 0x0f0f87ff, 1196 0x5000007f, 1197 BP_OLED_SSI | BP_GAMEPAD 1198 } 1199 }; 1200 1201 static void stellaris_init(const char *kernel_filename, const char *cpu_model, 1202 stellaris_board_info *board) 1203 { 1204 static const int uart_irq[] = {5, 6, 33, 34}; 1205 static const int timer_irq[] = {19, 21, 23, 35}; 1206 static const uint32_t gpio_addr[7] = 1207 { 0x40004000, 0x40005000, 0x40006000, 0x40007000, 1208 0x40024000, 0x40025000, 0x40026000}; 1209 static const int gpio_irq[7] = {0, 1, 2, 3, 4, 30, 31}; 1210 1211 qemu_irq *pic; 1212 DeviceState *gpio_dev[7]; 1213 qemu_irq gpio_in[7][8]; 1214 qemu_irq gpio_out[7][8]; 1215 qemu_irq adc; 1216 int sram_size; 1217 int flash_size; 1218 I2CBus *i2c; 1219 DeviceState *dev; 1220 int i; 1221 int j; 1222 1223 flash_size = ((board->dc0 & 0xffff) + 1) << 1; 1224 sram_size = (board->dc0 >> 18) + 1; 1225 pic = armv7m_init(get_system_memory(), 1226 flash_size, sram_size, kernel_filename, cpu_model); 1227 1228 if (board->dc1 & (1 << 16)) { 1229 dev = sysbus_create_varargs(TYPE_STELLARIS_ADC, 0x40038000, 1230 pic[14], pic[15], pic[16], pic[17], NULL); 1231 adc = qdev_get_gpio_in(dev, 0); 1232 } else { 1233 adc = NULL; 1234 } 1235 for (i = 0; i < 4; i++) { 1236 if (board->dc2 & (0x10000 << i)) { 1237 dev = sysbus_create_simple(TYPE_STELLARIS_GPTM, 1238 0x40030000 + i * 0x1000, 1239 pic[timer_irq[i]]); 1240 /* TODO: This is incorrect, but we get away with it because 1241 the ADC output is only ever pulsed. */ 1242 qdev_connect_gpio_out(dev, 0, adc); 1243 } 1244 } 1245 1246 stellaris_sys_init(0x400fe000, pic[28], board, nd_table[0].macaddr.a); 1247 1248 for (i = 0; i < 7; i++) { 1249 if (board->dc4 & (1 << i)) { 1250 gpio_dev[i] = sysbus_create_simple("pl061_luminary", gpio_addr[i], 1251 pic[gpio_irq[i]]); 1252 for (j = 0; j < 8; j++) { 1253 gpio_in[i][j] = qdev_get_gpio_in(gpio_dev[i], j); 1254 gpio_out[i][j] = NULL; 1255 } 1256 } 1257 } 1258 1259 if (board->dc2 & (1 << 12)) { 1260 dev = sysbus_create_simple(TYPE_STELLARIS_I2C, 0x40020000, pic[8]); 1261 i2c = (I2CBus *)qdev_get_child_bus(dev, "i2c"); 1262 if (board->peripherals & BP_OLED_I2C) { 1263 i2c_create_slave(i2c, "ssd0303", 0x3d); 1264 } 1265 } 1266 1267 for (i = 0; i < 4; i++) { 1268 if (board->dc2 & (1 << i)) { 1269 sysbus_create_simple("pl011_luminary", 0x4000c000 + i * 0x1000, 1270 pic[uart_irq[i]]); 1271 } 1272 } 1273 if (board->dc2 & (1 << 4)) { 1274 dev = sysbus_create_simple("pl022", 0x40008000, pic[7]); 1275 if (board->peripherals & BP_OLED_SSI) { 1276 void *bus; 1277 DeviceState *sddev; 1278 DeviceState *ssddev; 1279 1280 /* Some boards have both an OLED controller and SD card connected to 1281 * the same SSI port, with the SD card chip select connected to a 1282 * GPIO pin. Technically the OLED chip select is connected to the 1283 * SSI Fss pin. We do not bother emulating that as both devices 1284 * should never be selected simultaneously, and our OLED controller 1285 * ignores stray 0xff commands that occur when deselecting the SD 1286 * card. 1287 */ 1288 bus = qdev_get_child_bus(dev, "ssi"); 1289 1290 sddev = ssi_create_slave(bus, "ssi-sd"); 1291 ssddev = ssi_create_slave(bus, "ssd0323"); 1292 gpio_out[GPIO_D][0] = qemu_irq_split( 1293 qdev_get_gpio_in_named(sddev, SSI_GPIO_CS, 0), 1294 qdev_get_gpio_in_named(ssddev, SSI_GPIO_CS, 0)); 1295 gpio_out[GPIO_C][7] = qdev_get_gpio_in(ssddev, 0); 1296 1297 /* Make sure the select pin is high. */ 1298 qemu_irq_raise(gpio_out[GPIO_D][0]); 1299 } 1300 } 1301 if (board->dc4 & (1 << 28)) { 1302 DeviceState *enet; 1303 1304 qemu_check_nic_model(&nd_table[0], "stellaris"); 1305 1306 enet = qdev_create(NULL, "stellaris_enet"); 1307 qdev_set_nic_properties(enet, &nd_table[0]); 1308 qdev_init_nofail(enet); 1309 sysbus_mmio_map(SYS_BUS_DEVICE(enet), 0, 0x40048000); 1310 sysbus_connect_irq(SYS_BUS_DEVICE(enet), 0, pic[42]); 1311 } 1312 if (board->peripherals & BP_GAMEPAD) { 1313 qemu_irq gpad_irq[5]; 1314 static const int gpad_keycode[5] = { 0xc8, 0xd0, 0xcb, 0xcd, 0x1d }; 1315 1316 gpad_irq[0] = qemu_irq_invert(gpio_in[GPIO_E][0]); /* up */ 1317 gpad_irq[1] = qemu_irq_invert(gpio_in[GPIO_E][1]); /* down */ 1318 gpad_irq[2] = qemu_irq_invert(gpio_in[GPIO_E][2]); /* left */ 1319 gpad_irq[3] = qemu_irq_invert(gpio_in[GPIO_E][3]); /* right */ 1320 gpad_irq[4] = qemu_irq_invert(gpio_in[GPIO_F][1]); /* select */ 1321 1322 stellaris_gamepad_init(5, gpad_irq, gpad_keycode); 1323 } 1324 for (i = 0; i < 7; i++) { 1325 if (board->dc4 & (1 << i)) { 1326 for (j = 0; j < 8; j++) { 1327 if (gpio_out[i][j]) { 1328 qdev_connect_gpio_out(gpio_dev[i], j, gpio_out[i][j]); 1329 } 1330 } 1331 } 1332 } 1333 } 1334 1335 /* FIXME: Figure out how to generate these from stellaris_boards. */ 1336 static void lm3s811evb_init(MachineState *machine) 1337 { 1338 const char *cpu_model = machine->cpu_model; 1339 const char *kernel_filename = machine->kernel_filename; 1340 stellaris_init(kernel_filename, cpu_model, &stellaris_boards[0]); 1341 } 1342 1343 static void lm3s6965evb_init(MachineState *machine) 1344 { 1345 const char *cpu_model = machine->cpu_model; 1346 const char *kernel_filename = machine->kernel_filename; 1347 stellaris_init(kernel_filename, cpu_model, &stellaris_boards[1]); 1348 } 1349 1350 static QEMUMachine lm3s811evb_machine = { 1351 .name = "lm3s811evb", 1352 .desc = "Stellaris LM3S811EVB", 1353 .init = lm3s811evb_init, 1354 }; 1355 1356 static QEMUMachine lm3s6965evb_machine = { 1357 .name = "lm3s6965evb", 1358 .desc = "Stellaris LM3S6965EVB", 1359 .init = lm3s6965evb_init, 1360 }; 1361 1362 static void stellaris_machine_init(void) 1363 { 1364 qemu_register_machine(&lm3s811evb_machine); 1365 qemu_register_machine(&lm3s6965evb_machine); 1366 } 1367 1368 machine_init(stellaris_machine_init); 1369 1370 static void stellaris_i2c_class_init(ObjectClass *klass, void *data) 1371 { 1372 SysBusDeviceClass *sdc = SYS_BUS_DEVICE_CLASS(klass); 1373 1374 sdc->init = stellaris_i2c_init; 1375 } 1376 1377 static const TypeInfo stellaris_i2c_info = { 1378 .name = TYPE_STELLARIS_I2C, 1379 .parent = TYPE_SYS_BUS_DEVICE, 1380 .instance_size = sizeof(stellaris_i2c_state), 1381 .class_init = stellaris_i2c_class_init, 1382 }; 1383 1384 static void stellaris_gptm_class_init(ObjectClass *klass, void *data) 1385 { 1386 SysBusDeviceClass *sdc = SYS_BUS_DEVICE_CLASS(klass); 1387 1388 sdc->init = stellaris_gptm_init; 1389 } 1390 1391 static const TypeInfo stellaris_gptm_info = { 1392 .name = TYPE_STELLARIS_GPTM, 1393 .parent = TYPE_SYS_BUS_DEVICE, 1394 .instance_size = sizeof(gptm_state), 1395 .class_init = stellaris_gptm_class_init, 1396 }; 1397 1398 static void stellaris_adc_class_init(ObjectClass *klass, void *data) 1399 { 1400 SysBusDeviceClass *sdc = SYS_BUS_DEVICE_CLASS(klass); 1401 1402 sdc->init = stellaris_adc_init; 1403 } 1404 1405 static const TypeInfo stellaris_adc_info = { 1406 .name = TYPE_STELLARIS_ADC, 1407 .parent = TYPE_SYS_BUS_DEVICE, 1408 .instance_size = sizeof(stellaris_adc_state), 1409 .class_init = stellaris_adc_class_init, 1410 }; 1411 1412 static void stellaris_register_types(void) 1413 { 1414 type_register_static(&stellaris_i2c_info); 1415 type_register_static(&stellaris_gptm_info); 1416 type_register_static(&stellaris_adc_info); 1417 } 1418 1419 type_init(stellaris_register_types) 1420