1 /* 2 * STM32L4x5 SoC family 3 * 4 * Copyright (c) 2023 Arnaud Minier <arnaud.minier@telecom-paris.fr> 5 * Copyright (c) 2023 Inès Varhol <ines.varhol@telecom-paris.fr> 6 * 7 * SPDX-License-Identifier: GPL-2.0-or-later 8 * 9 * This work is licensed under the terms of the GNU GPL, version 2 or later. 10 * See the COPYING file in the top-level directory. 11 * 12 * This work is heavily inspired by the stm32f405_soc by Alistair Francis. 13 * Original code is licensed under the MIT License: 14 * 15 * Copyright (c) 2014 Alistair Francis <alistair@alistair23.me> 16 */ 17 18 /* 19 * The reference used is the STMicroElectronics RM0351 Reference manual 20 * for STM32L4x5 and STM32L4x6 advanced Arm ® -based 32-bit MCUs. 21 * https://www.st.com/en/microcontrollers-microprocessors/stm32l4x5/documentation.html 22 */ 23 24 #include "qemu/osdep.h" 25 #include "qemu/units.h" 26 #include "qapi/error.h" 27 #include "exec/address-spaces.h" 28 #include "sysemu/sysemu.h" 29 #include "hw/arm/stm32l4x5_soc.h" 30 #include "hw/qdev-clock.h" 31 #include "hw/misc/unimp.h" 32 33 #define FLASH_BASE_ADDRESS 0x08000000 34 #define SRAM1_BASE_ADDRESS 0x20000000 35 #define SRAM1_SIZE (96 * KiB) 36 #define SRAM2_BASE_ADDRESS 0x10000000 37 #define SRAM2_SIZE (32 * KiB) 38 39 static void stm32l4x5_soc_initfn(Object *obj) 40 { 41 Stm32l4x5SocState *s = STM32L4X5_SOC(obj); 42 43 s->sysclk = qdev_init_clock_in(DEVICE(s), "sysclk", NULL, NULL, 0); 44 s->refclk = qdev_init_clock_in(DEVICE(s), "refclk", NULL, NULL, 0); 45 } 46 47 static void stm32l4x5_soc_realize(DeviceState *dev_soc, Error **errp) 48 { 49 ERRP_GUARD(); 50 Stm32l4x5SocState *s = STM32L4X5_SOC(dev_soc); 51 const Stm32l4x5SocClass *sc = STM32L4X5_SOC_GET_CLASS(dev_soc); 52 MemoryRegion *system_memory = get_system_memory(); 53 DeviceState *armv7m; 54 55 /* 56 * We use s->refclk internally and only define it with qdev_init_clock_in() 57 * so it is correctly parented and not leaked on an init/deinit; it is not 58 * intended as an externally exposed clock. 59 */ 60 if (clock_has_source(s->refclk)) { 61 error_setg(errp, "refclk clock must not be wired up by the board code"); 62 return; 63 } 64 65 if (!clock_has_source(s->sysclk)) { 66 error_setg(errp, "sysclk clock must be wired up by the board code"); 67 return; 68 } 69 70 /* 71 * TODO: ideally we should model the SoC RCC and its ability to 72 * change the sysclk frequency and define different sysclk sources. 73 */ 74 75 /* The refclk always runs at frequency HCLK / 8 */ 76 clock_set_mul_div(s->refclk, 8, 1); 77 clock_set_source(s->refclk, s->sysclk); 78 79 if (!memory_region_init_rom(&s->flash, OBJECT(dev_soc), "flash", 80 sc->flash_size, errp)) { 81 return; 82 } 83 memory_region_init_alias(&s->flash_alias, OBJECT(dev_soc), 84 "flash_boot_alias", &s->flash, 0, 85 sc->flash_size); 86 87 memory_region_add_subregion(system_memory, FLASH_BASE_ADDRESS, &s->flash); 88 memory_region_add_subregion(system_memory, 0, &s->flash_alias); 89 90 if (!memory_region_init_ram(&s->sram1, OBJECT(dev_soc), "SRAM1", SRAM1_SIZE, 91 errp)) { 92 return; 93 } 94 memory_region_add_subregion(system_memory, SRAM1_BASE_ADDRESS, &s->sram1); 95 96 if (!memory_region_init_ram(&s->sram2, OBJECT(dev_soc), "SRAM2", SRAM2_SIZE, 97 errp)) { 98 return; 99 } 100 memory_region_add_subregion(system_memory, SRAM2_BASE_ADDRESS, &s->sram2); 101 102 object_initialize_child(OBJECT(dev_soc), "armv7m", &s->armv7m, TYPE_ARMV7M); 103 armv7m = DEVICE(&s->armv7m); 104 qdev_prop_set_uint32(armv7m, "num-irq", 96); 105 qdev_prop_set_uint32(armv7m, "num-prio-bits", 4); 106 qdev_prop_set_string(armv7m, "cpu-type", ARM_CPU_TYPE_NAME("cortex-m4")); 107 qdev_prop_set_bit(armv7m, "enable-bitband", true); 108 qdev_connect_clock_in(armv7m, "cpuclk", s->sysclk); 109 qdev_connect_clock_in(armv7m, "refclk", s->refclk); 110 object_property_set_link(OBJECT(&s->armv7m), "memory", 111 OBJECT(system_memory), &error_abort); 112 if (!sysbus_realize(SYS_BUS_DEVICE(&s->armv7m), errp)) { 113 return; 114 } 115 116 /* APB1 BUS */ 117 create_unimplemented_device("TIM2", 0x40000000, 0x400); 118 create_unimplemented_device("TIM3", 0x40000400, 0x400); 119 create_unimplemented_device("TIM4", 0x40000800, 0x400); 120 create_unimplemented_device("TIM5", 0x40000C00, 0x400); 121 create_unimplemented_device("TIM6", 0x40001000, 0x400); 122 create_unimplemented_device("TIM7", 0x40001400, 0x400); 123 /* RESERVED: 0x40001800, 0x1000 */ 124 create_unimplemented_device("RTC", 0x40002800, 0x400); 125 create_unimplemented_device("WWDG", 0x40002C00, 0x400); 126 create_unimplemented_device("IWDG", 0x40003000, 0x400); 127 /* RESERVED: 0x40001800, 0x400 */ 128 create_unimplemented_device("SPI2", 0x40003800, 0x400); 129 create_unimplemented_device("SPI3", 0x40003C00, 0x400); 130 /* RESERVED: 0x40004000, 0x400 */ 131 create_unimplemented_device("USART2", 0x40004400, 0x400); 132 create_unimplemented_device("USART3", 0x40004800, 0x400); 133 create_unimplemented_device("UART4", 0x40004C00, 0x400); 134 create_unimplemented_device("UART5", 0x40005000, 0x400); 135 create_unimplemented_device("I2C1", 0x40005400, 0x400); 136 create_unimplemented_device("I2C2", 0x40005800, 0x400); 137 create_unimplemented_device("I2C3", 0x40005C00, 0x400); 138 /* RESERVED: 0x40006000, 0x400 */ 139 create_unimplemented_device("CAN1", 0x40006400, 0x400); 140 /* RESERVED: 0x40006800, 0x400 */ 141 create_unimplemented_device("PWR", 0x40007000, 0x400); 142 create_unimplemented_device("DAC1", 0x40007400, 0x400); 143 create_unimplemented_device("OPAMP", 0x40007800, 0x400); 144 create_unimplemented_device("LPTIM1", 0x40007C00, 0x400); 145 create_unimplemented_device("LPUART1", 0x40008000, 0x400); 146 /* RESERVED: 0x40008400, 0x400 */ 147 create_unimplemented_device("SWPMI1", 0x40008800, 0x400); 148 /* RESERVED: 0x40008C00, 0x800 */ 149 create_unimplemented_device("LPTIM2", 0x40009400, 0x400); 150 /* RESERVED: 0x40009800, 0x6800 */ 151 152 /* APB2 BUS */ 153 create_unimplemented_device("SYSCFG", 0x40010000, 0x30); 154 create_unimplemented_device("VREFBUF", 0x40010030, 0x1D0); 155 create_unimplemented_device("COMP", 0x40010200, 0x200); 156 create_unimplemented_device("EXTI", 0x40010400, 0x400); 157 /* RESERVED: 0x40010800, 0x1400 */ 158 create_unimplemented_device("FIREWALL", 0x40011C00, 0x400); 159 /* RESERVED: 0x40012000, 0x800 */ 160 create_unimplemented_device("SDMMC1", 0x40012800, 0x400); 161 create_unimplemented_device("TIM1", 0x40012C00, 0x400); 162 create_unimplemented_device("SPI1", 0x40013000, 0x400); 163 create_unimplemented_device("TIM8", 0x40013400, 0x400); 164 create_unimplemented_device("USART1", 0x40013800, 0x400); 165 /* RESERVED: 0x40013C00, 0x400 */ 166 create_unimplemented_device("TIM15", 0x40014000, 0x400); 167 create_unimplemented_device("TIM16", 0x40014400, 0x400); 168 create_unimplemented_device("TIM17", 0x40014800, 0x400); 169 /* RESERVED: 0x40014C00, 0x800 */ 170 create_unimplemented_device("SAI1", 0x40015400, 0x400); 171 create_unimplemented_device("SAI2", 0x40015800, 0x400); 172 /* RESERVED: 0x40015C00, 0x400 */ 173 create_unimplemented_device("DFSDM1", 0x40016000, 0x400); 174 /* RESERVED: 0x40016400, 0x9C00 */ 175 176 /* AHB1 BUS */ 177 create_unimplemented_device("DMA1", 0x40020000, 0x400); 178 create_unimplemented_device("DMA2", 0x40020400, 0x400); 179 /* RESERVED: 0x40020800, 0x800 */ 180 create_unimplemented_device("RCC", 0x40021000, 0x400); 181 /* RESERVED: 0x40021400, 0xC00 */ 182 create_unimplemented_device("FLASH", 0x40022000, 0x400); 183 /* RESERVED: 0x40022400, 0xC00 */ 184 create_unimplemented_device("CRC", 0x40023000, 0x400); 185 /* RESERVED: 0x40023400, 0x400 */ 186 create_unimplemented_device("TSC", 0x40024000, 0x400); 187 188 /* RESERVED: 0x40024400, 0x7FDBC00 */ 189 190 /* AHB2 BUS */ 191 create_unimplemented_device("GPIOA", 0x48000000, 0x400); 192 create_unimplemented_device("GPIOB", 0x48000400, 0x400); 193 create_unimplemented_device("GPIOC", 0x48000800, 0x400); 194 create_unimplemented_device("GPIOD", 0x48000C00, 0x400); 195 create_unimplemented_device("GPIOE", 0x48001000, 0x400); 196 create_unimplemented_device("GPIOF", 0x48001400, 0x400); 197 create_unimplemented_device("GPIOG", 0x48001800, 0x400); 198 create_unimplemented_device("GPIOH", 0x48001C00, 0x400); 199 /* RESERVED: 0x48002000, 0x7FDBC00 */ 200 create_unimplemented_device("OTG_FS", 0x50000000, 0x40000); 201 create_unimplemented_device("ADC", 0x50040000, 0x400); 202 /* RESERVED: 0x50040400, 0x20400 */ 203 create_unimplemented_device("RNG", 0x50060800, 0x400); 204 205 /* AHB3 BUS */ 206 create_unimplemented_device("FMC", 0xA0000000, 0x1000); 207 create_unimplemented_device("QUADSPI", 0xA0001000, 0x400); 208 } 209 210 static void stm32l4x5_soc_class_init(ObjectClass *klass, void *data) 211 { 212 213 DeviceClass *dc = DEVICE_CLASS(klass); 214 215 dc->realize = stm32l4x5_soc_realize; 216 /* Reason: Mapped at fixed location on the system bus */ 217 dc->user_creatable = false; 218 /* No vmstate or reset required: device has no internal state */ 219 } 220 221 static void stm32l4x5xc_soc_class_init(ObjectClass *oc, void *data) 222 { 223 Stm32l4x5SocClass *ssc = STM32L4X5_SOC_CLASS(oc); 224 225 ssc->flash_size = 256 * KiB; 226 } 227 228 static void stm32l4x5xe_soc_class_init(ObjectClass *oc, void *data) 229 { 230 Stm32l4x5SocClass *ssc = STM32L4X5_SOC_CLASS(oc); 231 232 ssc->flash_size = 512 * KiB; 233 } 234 235 static void stm32l4x5xg_soc_class_init(ObjectClass *oc, void *data) 236 { 237 Stm32l4x5SocClass *ssc = STM32L4X5_SOC_CLASS(oc); 238 239 ssc->flash_size = 1 * MiB; 240 } 241 242 static const TypeInfo stm32l4x5_soc_types[] = { 243 { 244 .name = TYPE_STM32L4X5XC_SOC, 245 .parent = TYPE_STM32L4X5_SOC, 246 .class_init = stm32l4x5xc_soc_class_init, 247 }, { 248 .name = TYPE_STM32L4X5XE_SOC, 249 .parent = TYPE_STM32L4X5_SOC, 250 .class_init = stm32l4x5xe_soc_class_init, 251 }, { 252 .name = TYPE_STM32L4X5XG_SOC, 253 .parent = TYPE_STM32L4X5_SOC, 254 .class_init = stm32l4x5xg_soc_class_init, 255 }, { 256 .name = TYPE_STM32L4X5_SOC, 257 .parent = TYPE_SYS_BUS_DEVICE, 258 .instance_size = sizeof(Stm32l4x5SocState), 259 .instance_init = stm32l4x5_soc_initfn, 260 .class_size = sizeof(Stm32l4x5SocClass), 261 .class_init = stm32l4x5_soc_class_init, 262 .abstract = true, 263 } 264 }; 265 266 DEFINE_TYPES(stm32l4x5_soc_types) 267